diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-31 02:58:24 -0700 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-31 02:58:24 -0700 |
commit | eeb85a8575d4bff6bc054bafe295e8758f2d0ded (patch) | |
tree | bf097dd61ae2c357af1d92ce44d5b845c04ee0be /src | |
parent | 8ad2b8c5596b817267fbf7a39e6ce28ffb49789c (diff) | |
download | gem5-eeb85a8575d4bff6bc054bafe295e8758f2d0ded.tar.xz |
SE/FS: Remove the last uses of FULL_SYSTEM from SPARC.
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/sparc/SConscript | 22 | ||||
-rw-r--r-- | src/arch/sparc/faults.cc | 80 | ||||
-rw-r--r-- | src/arch/sparc/isa/formats/mem/util.isa | 5 | ||||
-rw-r--r-- | src/arch/sparc/ua2005.cc | 5 |
4 files changed, 51 insertions, 61 deletions
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 974d60ddc..75a3590e7 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -36,9 +36,16 @@ if env['TARGET_ISA'] == 'sparc': Source('faults.cc') Source('interrupts.cc') Source('isa.cc') + Source('linux/linux.cc') + Source('linux/process.cc') + Source('linux/syscalls.cc') Source('nativetrace.cc') Source('pagetable.cc') + Source('process.cc') Source('remote_gdb.cc') + Source('solaris/process.cc') + Source('solaris/solaris.cc') + Source('system.cc') Source('tlb.cc') Source('ua2005.cc') Source('utility.cc') @@ -46,25 +53,12 @@ if env['TARGET_ISA'] == 'sparc': SimObject('SparcInterrupts.py') SimObject('SparcNativeTrace.py') + SimObject('SparcSystem.py') SimObject('SparcTLB.py') DebugFlag('Sparc', "Generic SPARC ISA stuff") DebugFlag('RegisterWindows', "Register window manipulation") - if env['FULL_SYSTEM']: - SimObject('SparcSystem.py') - - Source('system.cc') - else: - Source('process.cc') - - Source('linux/linux.cc') - Source('linux/process.cc') - Source('linux/syscalls.cc') - - Source('solaris/process.cc') - Source('solaris/solaris.cc') - # Add in files generated by the ISA description. isa_desc_files = env.ISADesc('isa/main.isa') # Only non-header files need to be compiled. diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 584b8299c..a737b328d 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -33,15 +33,13 @@ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" +#include "arch/sparc/process.hh" #include "arch/sparc/types.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "sim/full_system.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" -#if !FULL_SYSTEM -#include "arch/sparc/process.hh" -#endif #include "mem/page_table.hh" #include "sim/process.hh" #include "sim/full_system.hh" @@ -666,64 +664,64 @@ FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst) void SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) { -#if !FULL_SYSTEM - doNormalFault(tc, trapType(), false); + if (FullSystem) { + SparcFaultBase::invoke(tc, inst); + } else { + doNormalFault(tc, trapType(), false); - Process *p = tc->getProcessPtr(); + Process *p = tc->getProcessPtr(); - //XXX This will only work in faults from a SparcLiveProcess - SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); - assert(lp); + //XXX This will only work in faults from a SparcLiveProcess + SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); + assert(lp); - // Then adjust the PC and NPC - tc->pcState(lp->readSpillStart()); -#else - SparcFaultBase::invoke(tc, inst); -#endif + // Then adjust the PC and NPC + tc->pcState(lp->readSpillStart()); + } } void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) { -#if !FULL_SYSTEM - doNormalFault(tc, trapType(), false); + if (FullSystem) { + SparcFaultBase::invoke(tc, inst); + } else { + doNormalFault(tc, trapType(), false); - Process *p = tc->getProcessPtr(); + Process *p = tc->getProcessPtr(); - //XXX This will only work in faults from a SparcLiveProcess - SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); - assert(lp); + //XXX This will only work in faults from a SparcLiveProcess + SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); + assert(lp); - // Then adjust the PC and NPC - tc->pcState(lp->readFillStart()); -#else - SparcFaultBase::invoke(tc, inst); -#endif + // Then adjust the PC and NPC + tc->pcState(lp->readFillStart()); + } } void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) { -#if !FULL_SYSTEM - // In SE, this mechanism is how the process requests a service from the - // operating system. We'll get the process object from the thread context - // and let it service the request. + if (FullSystem) { + SparcFaultBase::invoke(tc, inst); + } else { + // In SE, this mechanism is how the process requests a service from + // the operating system. We'll get the process object from the thread + // context and let it service the request. - Process *p = tc->getProcessPtr(); + Process *p = tc->getProcessPtr(); - SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); - assert(lp); + SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); + assert(lp); - lp->handleTrap(_n, tc); + lp->handleTrap(_n, tc); - // We need to explicitly advance the pc, since that's not done for us - // on a faulting instruction - PCState pc = tc->pcState(); - pc.advance(); - tc->pcState(pc); -#else - SparcFaultBase::invoke(tc, inst); -#endif + // We need to explicitly advance the pc, since that's not done for us + // on a faulting instruction + PCState pc = tc->pcState(); + pc.advance(); + tc->pcState(pc); + } } } // namespace SparcISA diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 06206c02b..d6eee8a4d 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -326,9 +326,8 @@ let {{ ''' TruncateEA = ''' -#if !FULL_SYSTEM - EA = Pstate<3:> ? EA<31:0> : EA; -#endif + if (!FullSystem) + EA = Pstate<3:> ? EA<31:0> : EA; ''' }}; diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 70c8c18e6..e6ab64de9 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -36,6 +36,7 @@ #include "debug/Quiesce.hh" #include "debug/Timer.hh" #include "sim/system.hh" +#include "sim/full_system.hh" using namespace SparcISA; using namespace std; @@ -224,10 +225,8 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); // Time to go to sleep tc->suspend(); -#if FULL_SYSTEM - if (tc->getKernelStats()) + if (FullSystem && tc->getKernelStats()) tc->getKernelStats()->quiesce(); -#endif } break; |