diff options
| author | Gabe Black <gabeblack@google.com> | 2019-11-05 15:45:07 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-12-24 04:22:28 +0000 |
| commit | eec8ac1595320cf40650f3c03f05248015dd17ae (patch) | |
| tree | 4618f5981cc978964eacd6be7bcc3e587dfde2fc /src | |
| parent | 231dc99c840f3abff0c387287d5d5f995c209632 (diff) | |
| download | gem5-eec8ac1595320cf40650f3c03f05248015dd17ae.tar.xz | |
fastmodel: Implement readVecRegFlat for ArmThreadContext.
This just calls readVecReg after constructing a RegId.
Change-Id: Ia26b9bb874fec62f98bd5e4d3c6aa1059766c2f6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23783
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/fastmodel/iris/arm/thread_context.cc | 6 | ||||
| -rw-r--r-- | src/arch/arm/fastmodel/iris/arm/thread_context.hh | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc index 8a36ce3d3..c48ade817 100644 --- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc @@ -201,6 +201,12 @@ ArmThreadContext::readVecReg(const RegId ®_id) const return reg; } +const ArmISA::VecRegContainer & +ArmThreadContext::readVecRegFlat(RegIndex idx) const +{ + return readVecReg(RegId(VecRegClass, idx)); +} + Iris::ThreadContext::IdxNameMap ArmThreadContext::miscRegIdxNameMap({ { ArmISA::MISCREG_CPSR, "CPSR" }, { ArmISA::MISCREG_SPSR, "SPSR" }, diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.hh b/src/arch/arm/fastmodel/iris/arm/thread_context.hh index c7f26e3bd..8344f57b8 100644 --- a/src/arch/arm/fastmodel/iris/arm/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/arm/thread_context.hh @@ -83,6 +83,7 @@ class ArmThreadContext : public Iris::ThreadContext } const VecRegContainer &readVecReg(const RegId ®) const override; + const VecRegContainer &readVecRegFlat(RegIndex idx) const override; }; } // namespace Iris |