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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
| commit | fd37095fa6e07f127a1f76aaf145cd3e891f2d4d (patch) | |
| tree | 0129b2676c77d1f033b77a0653e7baa7e2b0e9d1 /src | |
| parent | 49b7088b9101dfabd236c9cf76b700fade70c265 (diff) | |
| download | gem5-fd37095fa6e07f127a1f76aaf145cd3e891f2d4d.tar.xz | |
ARM: Make MPIDR return 0 and ignore writes.
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa.hh | 3 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 6 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 9195cdfcd..1dad82397 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -155,6 +155,8 @@ namespace ArmISA mvfr1.vfpHalfPrecision = 1; miscRegs[MISCREG_MVFR1] = mvfr1; + miscRegs[MISCREG_MPIDR] = 0; + //XXX We need to initialize the rest of the state. } @@ -296,6 +298,7 @@ namespace ArmISA case MISCREG_TLBTR: case MISCREG_MVFR0: case MISCREG_MVFR1: + case MISCREG_MPIDR: return; } return setMiscRegNoEffect(misc_reg, newVal); diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 851044a35..27f12c3b2 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -128,10 +128,10 @@ namespace ArmISA MISCREG_IFSR, MISCREG_DFAR, MISCREG_IFAR, + MISCREG_MPIDR, MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_TCMTR, - MISCREG_MPIDR, MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_ID_DFR0, @@ -203,8 +203,8 @@ namespace ArmISA "itlbiall", "itlbimva", "itlbiasid", "dtlbiall", "dtlbimva", "dtlbiasid", "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa", - "dfsr", "ifsr", "dfar", "ifar", - "ctr", "tcmtr", "mpidr", + "dfsr", "ifsr", "dfar", "ifar", "mpidr", + "ctr", "tcmtr", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", |