diff options
| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-22 11:16:40 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-22 11:16:40 -0800 |
| commit | 63a25a56ccc93c24703fec87f830c833974e7060 (patch) | |
| tree | a0f12244a32eb7da2963ca974ab49a993aee2cfc /system/alpha/palcode | |
| parent | 8ea71c3907a411de9c203b45bfd6eab24e3ad849 (diff) | |
| parent | 77eed184f529c4ccbef59ad2018d18ff3fbb54af (diff) | |
| download | gem5-63a25a56ccc93c24703fec87f830c833974e7060.tar.xz | |
m5: merged in hammer fix
Diffstat (limited to 'system/alpha/palcode')
| -rw-r--r-- | system/alpha/palcode/Makefile | 92 | ||||
| -rw-r--r-- | system/alpha/palcode/osfpal.S | 4202 | ||||
| -rw-r--r-- | system/alpha/palcode/platform.S | 2337 |
3 files changed, 6631 insertions, 0 deletions
diff --git a/system/alpha/palcode/Makefile b/system/alpha/palcode/Makefile new file mode 100644 index 000000000..2f1eded33 --- /dev/null +++ b/system/alpha/palcode/Makefile @@ -0,0 +1,92 @@ +# Copyright (c) 2003, 2004 +# The Regents of The University of Michigan +# All Rights Reserved +# +# This code is part of the M5 simulator. +# +# Permission is granted to use, copy, create derivative works and +# redistribute this software and such derivative works for any purpose, +# so long as the copyright notice above, this grant of permission, and +# the disclaimer below appear in all copies made; and so long as the +# name of The University of Michigan is not used in any advertising or +# publicity pertaining to the use or distribution of this software +# without specific, written prior authorization. +# +# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE +# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT +# WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR +# IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF +# THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES, +# INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +# DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION +# WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER +# ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +# +# Authors: Nathan L. Binkert +# Ali G. Saidi + +# Makefile for palcode +# Works on alpha-linux and builds elf executable + +### If we are not compiling on an alpha, we must use cross tools ### +ifneq ($(shell uname -m), alpha) +CROSS_COMPILE?=alpha-unknown-linux-gnu- +endif +CC=$(CROSS_COMPILE)gcc +AS=$(CROSS_COMPILE)as +LD=$(CROSS_COMPILE)ld + +CFLAGS=-I . -I ../h -nostdinc -nostdinc++ -Wa,-m21164 +LDFLAGS=-Ttext 0x4000 + +TLOBJS = osfpal.o platform_tlaser.o +TLOBJS_COPY = osfpal_cache_copy.o platform_tlaser.o +TLOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_tlaser.o +TSOBJS = osfpal.o platform_tsunami.o +TSBOBJS = osfpal.o platform_bigtsunami.o +TSOBJS_COPY = osfpal_cache_copy.o platform_tsunami.o +TSOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_bigtsunami.o + +all: tlaser tsunami tsunami_b64 + +all_copy: tlaser tlaser_copy tsunami tsunami_b64 tsunami_copy + +osfpal.o: osfpal.S + $(CC) $(CFLAGS) -o $@ -c $< + +osfpal_cache_copy.o: osfpal.S + $(CC) $(CFLAGS) -DCACHE_COPY -o $@ -c $< + +osfpal_cache_copy_unaligned.o: osfpal.S + $(CC) $(CFLAGS) -DCACHE_COPY -DCACHE_COPY_UNALIGNED -o $@ -c $< + +platform_tlaser.o: platform.S + $(CC) $(CFLAGS) -DTLASER -o $@ -c $< + +platform_tsunami.o: platform.S + $(CC) $(CFLAGS) -DTSUNAMI -o $@ -c $< + +platform_bigtsunami.o: platform.S + $(CC) $(CFLAGS) -DBIG_TSUNAMI -o $@ -c $< + +tlaser: $(TLOBJS) + $(LD) $(LDFLAGS) -o tl_osfpal $(TLOBJS) + +tlaser_copy: $(TLOBJS_COPY) $(TLOBJS_COPY_UNALIGNED) + $(LD) $(LDFLAGS) -o tl_osfpal_cache $(TLOBJS_COPY) + $(LD) $(LDFLAGS) -o tl_osfpal_unalign $(TLOBJS_COPY_UNALIGNED) + +tsunami: $(TSOBJS) + $(LD) $(LDFLAGS) -o ts_osfpal $(TSOBJS) + +tsunami_b64: $(TSBOBJS) + $(LD) $(LDFLAGS) -o tsb_osfpal $(TSBOBJS) + +tsunami_copy: $(TSOBJS_COPY) $(TSOBJS_COPY_UNALIGNED) + $(LD) $(LDFLAGS) -o ts_osfpal_cache $(TSOBJS_COPY) + $(LD) $(LDFLAGS) -o ts_osfpal_unalign $(TSOBJS_COPY_UNALIGNED) + +clean: + rm -f *.o tl_osfpal tl_osfpal_cache tl_osfpal_unalign ts_osfpal \ + ts_osfpal_cache ts_osfpal_unalign tsb_osfpal diff --git a/system/alpha/palcode/osfpal.S b/system/alpha/palcode/osfpal.S new file mode 100644 index 000000000..3ec4d4011 --- /dev/null +++ b/system/alpha/palcode/osfpal.S @@ -0,0 +1,4202 @@ +/* + * Copyright (c) 2003-2006 The Regents of The University of Michigan + * Copyright (c) 1992-1995 Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali G. Saidi + * Nathan L. Binkert + */ + +// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl +// since we don't have a mechanism to expand the data structures.... pb Nov/95 +#include "ev5_defs.h" +#include "ev5_impure.h" +#include "ev5_alpha_defs.h" +#include "ev5_paldef.h" +#include "ev5_osfalpha_defs.h" +#include "fromHudsonMacros.h" +#include "fromHudsonOsf.h" +#include "dc21164FromGasSources.h" + +#define DEBUGSTORE(c) nop + +#define DEBUG_EXC_ADDR()\ + bsr r25, put_exc_addr; \ + DEBUGSTORE(13) ; \ + DEBUGSTORE(10) + +// This is the fix for the user-mode super page references causing the +// machine to crash. +#define hw_rei_spe hw_rei + +#define vmaj 1 +#define vmin 18 +#define vms_pal 1 +#define osf_pal 2 +#define pal_type osf_pal +#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0)) + + +/////////////////////////// +// PALtemp register usage +/////////////////////////// + +// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage +// for these PALtemps: +// +// pt0 local scratch +// pt1 local scratch +// pt2 entUna pt_entUna +// pt3 CPU specific impure area pointer pt_impure +// pt4 memory management temp +// pt5 memory management temp +// pt6 memory management temp +// pt7 entIF pt_entIF +// pt8 intmask pt_intmask +// pt9 entSys pt_entSys +// pt10 +// pt11 entInt pt_entInt +// pt12 entArith pt_entArith +// pt13 reserved for system specific PAL +// pt14 reserved for system specific PAL +// pt15 reserved for system specific PAL +// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, +// pt_mces +// pt17 sysval pt_sysval +// pt18 usp pt_usp +// pt19 ksp pt_ksp +// pt20 PTBR pt_ptbr +// pt21 entMM pt_entMM +// pt22 kgp pt_kgp +// pt23 PCBB pt_pcbb +// +// + + +///////////////////////////// +// PALshadow register usage +///////////////////////////// + +// +// EV5 shadows R8-R14 and R25 when in PALmode and ICSR<shadow_enable> = 1. +// This maps the OSF PAL usage of R8 - R14 and R25: +// +// r8 ITBmiss/DTBmiss scratch +// r9 ITBmiss/DTBmiss scratch +// r10 ITBmiss/DTBmiss scratch +// r11 PS +// r12 local scratch +// r13 local scratch +// r14 local scratch +// r25 local scratch +// + + + +// .sbttl "PALcode configuration options" + +// There are a number of options that may be assembled into this version of +// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit +// the following). The options that can be adjusted cause the resultant PALcode +// to reflect the desired target system. + +// multiprocessor support can be enabled for a max of n processors by +// setting the following to the number of processors on the system. +// Note that this is really the max cpuid. + +#define max_cpuid 1 +#ifndef max_cpuid +#define max_cpuid 8 +#endif + +#define osf_svmin 1 +#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0)) + +// +// RESET - Reset Trap Entry Point +// +// RESET - offset 0000 +// Entry: +// Vectored into via hardware trap on reset, or branched to +// on swppal. +// +// r0 = whami +// r1 = pal_base +// r2 = base of scratch area +// r3 = halt code +// +// +// Function: +// +// + + .text 0 + . = 0x0000 + .globl _start + .globl Pal_Base +_start: +Pal_Base: + HDW_VECTOR(PAL_RESET_ENTRY) +Trap_Reset: + nop + /* + * store into r1 + */ + br r1,sys_reset + + // Specify PAL version info as a constant + // at a known location (reset + 8). + + .long osfpal_version_l // <pal_type@16> ! <vmaj@8> ! <vmin@0> + .long osfpal_version_h // <max_cpuid@16> ! <osf_svmin@0> + .long 0 + .long 0 +pal_impure_start: + .quad 0 +pal_debug_ptr: + .quad 0 // reserved for debug pointer ; 20 + + +// +// IACCVIO - Istream Access Violation Trap Entry Point +// +// IACCVIO - offset 0080 +// Entry: +// Vectored into via hardware trap on Istream access violation or sign check error on PC. +// +// Function: +// Build stack frame +// a0 <- Faulting VA +// a1 <- MMCSR (1 for ACV) +// a2 <- -1 (for ifetch fault) +// vector via entMM +// + + HDW_VECTOR(PAL_IACCVIO_ENTRY) +Trap_Iaccvio: + DEBUGSTORE(0x42) + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS + bge r25, TRAP_IACCVIO_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +TRAP_IACCVIO_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + mfpr r14, exc_addr // get pc + + stq r16, osfsf_a0(sp) // save regs + bic r14, 3, r16 // pass pc/va as a0 + + stq r17, osfsf_a1(sp) // a1 + or r31, mmcsr_c_acv, r17 // pass mm_csr as a1 + + stq r18, osfsf_a2(sp) // a2 + mfpr r13, pt_entmm // get entry point + + stq r11, osfsf_ps(sp) // save old ps + bis r12, r31, r11 // update ps + + stq r16, osfsf_pc(sp) // save pc + stq r29, osfsf_gp(sp) // save gp + + mtpr r13, exc_addr // load exc_addr with entMM + // 1 cycle to hw_rei + mfpr r29, pt_kgp // get the kgp + + subq r31, 1, r18 // pass flag of istream, as a2 + hw_rei_spe + + +// +// INTERRUPT - Interrupt Trap Entry Point +// +// INTERRUPT - offset 0100 +// Entry: +// Vectored into via trap on hardware interrupt +// +// Function: +// check for halt interrupt +// check for passive release (current ipl geq requestor) +// if necessary, switch to kernel mode push stack frame, +// update ps (including current mode and ipl copies), sp, and gp +// pass the interrupt info to the system module +// +// + HDW_VECTOR(PAL_INTERRUPT_ENTRY) +Trap_Interrupt: + mfpr r13, ev5__intid // Fetch level of interruptor + mfpr r25, ev5__isr // Fetch interrupt summary register + + srl r25, isr_v_hlt, r9 // Get HLT bit + mfpr r14, ev5__ipl + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kern + blbs r9, sys_halt_interrupt // halt_interrupt if HLT bit set + + cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl + bne r8, sys_passive_release // Passive release is current rupt is lt or eq ipl + + and r11, osfps_m_mode, r10 // get mode bit + beq r10, TRAP_INTERRUPT_10_ // Skip stack swap in kernel + + mtpr r30, pt_usp // save user stack + mfpr r30, pt_ksp // get kern stack + +TRAP_INTERRUPT_10_: + lda sp, (0-osfsf_c_size)(sp)// allocate stack space + mfpr r14, exc_addr // get pc + + stq r11, osfsf_ps(sp) // save ps + stq r14, osfsf_pc(sp) // save pc + + stq r29, osfsf_gp(sp) // push gp + stq r16, osfsf_a0(sp) // a0 + +// pvc_violate 354 // ps is cleared anyway, if store to stack faults. + mtpr r31, ev5__ps // Set Ibox current mode to kernel + stq r17, osfsf_a1(sp) // a1 + + stq r18, osfsf_a2(sp) // a2 + subq r13, 0x11, r12 // Start to translate from EV5IPL->OSFIPL + + srl r12, 1, r8 // 1d, 1e: ipl 6. 1f: ipl 7. + subq r13, 0x1d, r9 // Check for 1d, 1e, 1f + + cmovge r9, r8, r12 // if .ge. 1d, then take shifted value + bis r12, r31, r11 // set new ps + + mfpr r12, pt_intmask + and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already) + + /* + * Lance had space problems. We don't. + */ + extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL + mfpr r29, pt_kgp // update gp + mtpr r14, ev5__ipl // load the new IPL into Ibox + br r31, sys_interrupt // Go handle interrupt + + + +// +// ITBMISS - Istream TBmiss Trap Entry Point +// +// ITBMISS - offset 0180 +// Entry: +// Vectored into via hardware trap on Istream translation buffer miss. +// +// Function: +// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid. +// Can trap into DTBMISS_DOUBLE. +// This routine can use the PALshadow registers r8, r9, and r10 +// +// + + HDW_VECTOR(PAL_ITB_MISS_ENTRY) +Trap_Itbmiss: + // Real MM mapping + nop + mfpr r8, ev5__ifault_va_form // Get virtual address of PTE. + + nop + mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss. + +pal_itb_ldq: + ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss + mtpr r10, exc_addr // Restore exc_address if there was a trap. + + mfpr r31, ev5__va // Unlock VA in case there was a double miss + nop + + and r8, osfpte_m_foe, r25 // Look for FOE set. + blbc r8, invalid_ipte_handler // PTE not valid. + + nop + bne r25, foe_ipte_handler // FOE is set + + nop + mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB. + + hw_rei_stall // + + +// +// DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point +// +// DTBMISS_SINGLE - offset 0200 +// Entry: +// Vectored into via hardware trap on Dstream single translation +// buffer miss. +// +// Function: +// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid. +// Can trap into DTBMISS_DOUBLE. +// This routine can use the PALshadow registers r8, r9, and r10 +// + + HDW_VECTOR(PAL_DTB_MISS_ENTRY) +Trap_Dtbmiss_Single: + mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0. + mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1. + +// DEBUGSTORE(0x45) +// DEBUG_EXC_ADDR() + // Real MM mapping + mfpr r9, ev5__mm_stat // Get read/write bit. E0. + mtpr r10, pt6 // Stash exc_addr away + +pal_dtb_ldq: + ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss + nop // Pad MF VA + + mfpr r10, ev5__va // Get original faulting VA for TB load. E0. + nop + + mtpr r8, ev5__dtb_pte // Write DTB PTE part. E0. + blbc r8, invalid_dpte_handler // Handle invalid PTE + + mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles. + mfpr r10, pt6 + + // Following 2 instructions take 2 cycles + mtpr r10, exc_addr // Return linkage in case we trapped. E1. + mfpr r31, pt0 // Pad the write to dtb_tag + + hw_rei // Done, return + + +// +// DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point +// +// +// DTBMISS_DOUBLE - offset 0280 +// Entry: +// Vectored into via hardware trap on Double TBmiss from single +// miss flows. +// +// r8 - faulting VA +// r9 - original MMstat +// r10 - original exc_addr (both itb,dtb miss) +// pt6 - original exc_addr (dtb miss flow only) +// VA IPR - locked with original faulting VA +// +// Function: +// Get PTE, if valid load TB and return. +// If not valid then take TNV/ACV exception. +// +// pt4 and pt5 are reserved for this flow. +// +// +// + + HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY) +Trap_Dtbmiss_double: + mtpr r8, pt4 // save r8 to do exc_addr check + mfpr r8, exc_addr + blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy! + mfpr r8, pt4 // restore r8 + nop + mtpr r22, pt5 // Get some scratch space. E1. + // Due to virtual scheme, we can skip the first lookup and go + // right to fetch of level 2 PTE + sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA + mtpr r21, pt4 // Get some scratch space. E1. + + srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 + mfpr r21, pt_ptbr // Get physical address of the page table. + + nop + addq r21, r22, r21 // Index into page table for level 2 PTE. + + sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA + ldq_p r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored) + + srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8 + blbc r21, double_pte_inv // Check for Invalid PTE. + + srl r21, 32, r21 // extract PFN from PTE + sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to <seg3>*8 + + addq r21, r22, r21 // Index into page table for level 3 PTE. + nop + + ldq_p r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored) + blbc r21, double_pte_inv // Check for invalid PTE. + + mtpr r21, ev5__dtb_pte // Write the PTE. E0. + mfpr r22, pt5 // Restore scratch register + + mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles. + mfpr r21, pt4 // Restore scratch register + + nop // Pad write to tag. + nop + + nop // Pad write to tag. + nop + + hw_rei + + + +// +// UNALIGN -- Dstream unalign trap +// +// UNALIGN - offset 0300 +// Entry: +// Vectored into via hardware trap on unaligned Dstream reference. +// +// Function: +// Build stack frame +// a0 <- Faulting VA +// a1 <- Opcode +// a2 <- src/dst register number +// vector via entUna +// + + HDW_VECTOR(PAL_UNALIGN_ENTRY) +Trap_Unalign: +/* DEBUGSTORE(0x47)*/ + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss + mfpr r14, exc_addr // get pc + + srl r8, mm_stat_v_ra, r13 // Shift Ra field to ls bits + blbs r14, pal_pal_bug_check // Bugcheck if unaligned in PAL + + blbs r8, UNALIGN_NO_DISMISS // lsb only set on store or fetch_m + // not set, must be a load + and r13, 0x1F, r8 // isolate ra + + cmpeq r8, 0x1F, r8 // check for r31/F31 + bne r8, dfault_fetch_ldr31_err // if its a load to r31 or f31 -- dismiss the fault + +UNALIGN_NO_DISMISS: + bis r11, r31, r12 // Save PS + bge r25, UNALIGN_NO_DISMISS_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +UNALIGN_NO_DISMISS_10_: + mfpr r25, ev5__va // Unlock VA + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + mtpr r25, pt0 // Stash VA + stq r18, osfsf_a2(sp) // a2 + + stq r11, osfsf_ps(sp) // save old ps + srl r13, mm_stat_v_opcode-mm_stat_v_ra, r25// Isolate opcode + + stq r29, osfsf_gp(sp) // save gp + addq r14, 4, r14 // inc PC past the ld/st + + stq r17, osfsf_a1(sp) // a1 + and r25, mm_stat_m_opcode, r17// Clean opocde for a1 + + stq r16, osfsf_a0(sp) // save regs + mfpr r16, pt0 // a0 <- va/unlock + + stq r14, osfsf_pc(sp) // save pc + mfpr r25, pt_entuna // get entry point + + + bis r12, r31, r11 // update ps + br r31, unalign_trap_cont + + +// +// DFAULT - Dstream Fault Trap Entry Point +// +// DFAULT - offset 0380 +// Entry: +// Vectored into via hardware trap on dstream fault or sign check +// error on DVA. +// +// Function: +// Ignore faults on FETCH/FETCH_M +// Check for DFAULT in PAL +// Build stack frame +// a0 <- Faulting VA +// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW) +// a2 <- R/W +// vector via entMM +// +// + HDW_VECTOR(PAL_D_FAULT_ENTRY) +Trap_Dfault: +// DEBUGSTORE(0x48) + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r13, ev5__mm_stat // Get mmstat + mfpr r8, exc_addr // get pc, preserve r14 + + srl r13, mm_stat_v_opcode, r9 // Shift opcode field to ls bits + blbs r8, dfault_in_pal + + bis r8, r31, r14 // move exc_addr to correct place + bis r11, r31, r12 // Save PS + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + and r9, mm_stat_m_opcode, r9 // Clean all but opcode + + cmpeq r9, evx_opc_sync, r9 // Is the opcode fetch/fetchm? + bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault + + //dismiss exception if load to r31/f31 + blbs r13, dfault_no_dismiss // mm_stat<0> set on store or fetchm + + // not a store or fetch, must be a load + srl r13, mm_stat_v_ra, r9 // Shift rnum to low bits + + and r9, 0x1F, r9 // isolate rnum + nop + + cmpeq r9, 0x1F, r9 // Is the rnum r31 or f31? + bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault + +dfault_no_dismiss: + and r13, 0xf, r13 // Clean extra bits in mm_stat + bge r25, dfault_trap_cont // no stack swap needed if cm=kern + + + mtpr r30, pt_usp // save user stack + bis r31, r31, r12 // Set new PS + + mfpr r30, pt_ksp + br r31, dfault_trap_cont + + +// +// MCHK - Machine Check Trap Entry Point +// +// MCHK - offset 0400 +// Entry: +// Vectored into via hardware trap on machine check. +// +// Function: +// +// + + HDW_VECTOR(PAL_MCHK_ENTRY) +Trap_Mchk: + DEBUGSTORE(0x49) + mtpr r31, ic_flush_ctl // Flush the Icache + br r31, sys_machine_check + + +// +// OPCDEC - Illegal Opcode Trap Entry Point +// +// OPCDEC - offset 0480 +// Entry: +// Vectored into via hardware trap on illegal opcode. +// +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +// + + HDW_VECTOR(PAL_OPCDEC_ENTRY) +Trap_Opcdec: + DEBUGSTORE(0x4a) +//simos DEBUG_EXC_ADDR() + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r14, exc_addr // get pc + blbs r14, pal_pal_bug_check // check opcdec in palmode + + bis r11, r31, r12 // Save PS + bge r25, TRAP_OPCDEC_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +TRAP_OPCDEC_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + addq r14, 4, r14 // inc pc + + stq r16, osfsf_a0(sp) // save regs + bis r31, osf_a0_opdec, r16 // set a0 + + stq r11, osfsf_ps(sp) // save old ps + mfpr r13, pt_entif // get entry point + + stq r18, osfsf_a2(sp) // a2 + stq r17, osfsf_a1(sp) // a1 + + stq r29, osfsf_gp(sp) // save gp + stq r14, osfsf_pc(sp) // save pc + + bis r12, r31, r11 // update ps + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei, E1 + + mfpr r29, pt_kgp // get the kgp, E1 + + hw_rei_spe // done, E1 + + +// +// ARITH - Arithmetic Exception Trap Entry Point +// +// ARITH - offset 0500 +// Entry: +// Vectored into via hardware trap on arithmetic excpetion. +// +// Function: +// Build stack frame +// a0 <- exc_sum +// a1 <- exc_mask +// a2 <- unpred +// vector via entArith +// +// + HDW_VECTOR(PAL_ARITH_ENTRY) +Trap_Arith: + DEBUGSTORE(0x4b) + and r11, osfps_m_mode, r12 // get mode bit + mfpr r31, ev5__va // unlock mbox + + bis r11, r31, r25 // save ps + mfpr r14, exc_addr // get pc + + nop + blbs r14, pal_pal_bug_check // arith trap from PAL + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + beq r12, TRAP_ARITH_10_ // if zero we are in kern now + + bis r31, r31, r25 // set the new ps + mtpr r30, pt_usp // save user stack + + nop + mfpr r30, pt_ksp // get kern stack + +TRAP_ARITH_10_: lda sp, 0-osfsf_c_size(sp) // allocate stack space + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + nop // Pad current mode write and stq + mfpr r13, ev5__exc_sum // get the exc_sum + + mfpr r12, pt_entarith + stq r14, osfsf_pc(sp) // save pc + + stq r17, osfsf_a1(sp) + mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle + + stq r11, osfsf_ps(sp) // save ps + bis r25, r31, r11 // set new ps + + stq r16, osfsf_a0(sp) // save regs + srl r13, exc_sum_v_swc, r16 // shift data to correct position + + stq r18, osfsf_a2(sp) +// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow + mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask + + stq r29, osfsf_gp(sp) + mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1 + + mfpr r29, pt_kgp // get the kern gp - E1 + hw_rei_spe // done - E1 + + +// +// FEN - Illegal Floating Point Operation Trap Entry Point +// +// FEN - offset 0580 +// Entry: +// Vectored into via hardware trap on illegal FP op. +// +// Function: +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +// + + HDW_VECTOR(PAL_FEN_ENTRY) +Trap_Fen: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r14, exc_addr // get pc + blbs r14, pal_pal_bug_check // check opcdec in palmode + + mfpr r13, ev5__icsr + nop + + bis r11, r31, r12 // Save PS + bge r25, TRAP_FEN_10_ // no stack swap needed if cm=kern + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r12 // Set new PS + mfpr r30, pt_ksp + +TRAP_FEN_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + srl r13, icsr_v_fpe, r25 // Shift FP enable to bit 0 + + + stq r16, osfsf_a0(sp) // save regs + mfpr r13, pt_entif // get entry point + + stq r18, osfsf_a2(sp) // a2 + stq r11, osfsf_ps(sp) // save old ps + + stq r29, osfsf_gp(sp) // save gp + bis r12, r31, r11 // set new ps + + stq r17, osfsf_a1(sp) // a1 + blbs r25,fen_to_opcdec // If FP is enabled, this is really OPCDEC. + + bis r31, osf_a0_fen, r16 // set a0 + stq r14, osfsf_pc(sp) // save pc + + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei -E1 + + mfpr r29, pt_kgp // get the kgp -E1 + + hw_rei_spe // done -E1 + +// FEN trap was taken, but the fault is really opcdec. + ALIGN_BRANCH +fen_to_opcdec: + addq r14, 4, r14 // save PC+4 + bis r31, osf_a0_opdec, r16 // set a0 + + stq r14, osfsf_pc(sp) // save pc + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kgp + hw_rei_spe // done + + + +////////////////////////////////////////////////////////////////////////////// +// Misc handlers - Start area for misc code. +////////////////////////////////////////////////////////////////////////////// + +// +// dfault_trap_cont +// A dfault trap has been taken. The sp has been updated if necessary. +// Push a stack frame a vector via entMM. +// +// Current state: +// r12 - new PS +// r13 - MMstat +// VA - locked +// +// + ALIGN_BLOCK +dfault_trap_cont: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + mfpr r25, ev5__va // Fetch VA/unlock + + stq r18, osfsf_a2(sp) // a2 + and r13, 1, r18 // Clean r/w bit for a2 + + stq r16, osfsf_a0(sp) // save regs + bis r25, r31, r16 // a0 <- va + + stq r17, osfsf_a1(sp) // a1 + srl r13, 1, r17 // shift fault bits to right position + + stq r11, osfsf_ps(sp) // save old ps + bis r12, r31, r11 // update ps + + stq r14, osfsf_pc(sp) // save pc + mfpr r25, pt_entmm // get entry point + + stq r29, osfsf_gp(sp) // save gp + cmovlbs r17, 1, r17 // a2. acv overrides fox. + + mtpr r25, exc_addr // load exc_addr with entMM + // 1 cycle to hw_rei + mfpr r29, pt_kgp // get the kgp + + hw_rei_spe // done + +// +//unalign_trap_cont +// An unalign trap has been taken. Just need to finish up a few things. +// +// Current state: +// r25 - entUna +// r13 - shifted MMstat +// +// + ALIGN_BLOCK +unalign_trap_cont: + mtpr r25, exc_addr // load exc_addr with entUna + // 1 cycle to hw_rei + + + mfpr r29, pt_kgp // get the kgp + and r13, mm_stat_m_ra, r18 // Clean Ra for a2 + + hw_rei_spe // done + + + +// +// dfault_in_pal +// Dfault trap was taken, exc_addr points to a PAL PC. +// r9 - mmstat<opcode> right justified +// r8 - exception address +// +// These are the cases: +// opcode was STQ -- from a stack builder, KSP not valid halt +// r14 - original exc_addr +// r11 - original PS +// opcode was STL_C -- rti or retsys clear lock_flag by stack write, +// KSP not valid halt +// r11 - original PS +// r14 - original exc_addr +// opcode was LDQ -- retsys or rti stack read, KSP not valid halt +// r11 - original PS +// r14 - original exc_addr +// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables +// r10 - original exc_addr +// r11 - original PS +// +// +// + ALIGN_BLOCK +dfault_in_pal: + DEBUGSTORE(0x50) + bic r8, 3, r8 // Clean PC + mfpr r9, pal_base + + mfpr r31, va // unlock VA + + // if not real_mm, should never get here from miss flows + + subq r9, r8, r8 // pal_base - offset + + lda r9, pal_itb_ldq-pal_base(r8) + nop + + beq r9, dfault_do_bugcheck + lda r9, pal_dtb_ldq-pal_base(r8) + + beq r9, dfault_do_bugcheck + +// +// KSP invalid halt case -- +ksp_inval_halt: + DEBUGSTORE(76) + bic r11, osfps_m_mode, r11 // set ps to kernel mode + mtpr r0, pt0 + + mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode + mtpr r31, ips + + mtpr r14, exc_addr // Set PC to instruction that caused trouble + bsr r0, pal_update_pcb // update the pcb + + lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt + br r31, sys_enter_console // enter the console + + ALIGN_BRANCH +dfault_do_bugcheck: + bis r10, r31, r14 // bugcheck expects exc_addr in r14 + br r31, pal_pal_bug_check + + +// +// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31 +// On entry - +// r14 - exc_addr +// VA is locked +// +// + ALIGN_BLOCK +dfault_fetch_ldr31_err: + mtpr r11, ev5__dtb_cm + mtpr r11, ev5__ps // Make sure ps hasn't changed + + mfpr r31, va // unlock the mbox + addq r14, 4, r14 // inc the pc to skip the fetch + + mtpr r14, exc_addr // give ibox new PC + mfpr r31, pt0 // pad exc_addr write + + hw_rei + + + + ALIGN_BLOCK +// +// sys_from_kern +// callsys from kernel mode - OS bugcheck machine check +// +// +sys_from_kern: + mfpr r14, exc_addr // PC points to call_pal + subq r14, 4, r14 + + lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code + br r31, pal_pal_mchk + + +// Continuation of long call_pal flows +// +// wrent_tbl +// Table to write *int in paltemps. +// 4 instructions/entry +// r16 has new value +// +// + ALIGN_BLOCK +wrent_tbl: +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entint + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entarith + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entmm + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entif + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entuna + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + +//orig pvc_jsr wrent, dest=1 + nop + mtpr r16, pt_entsys + + mfpr r31, pt0 // Pad for mt->mf paltemp rule + hw_rei + + ALIGN_BLOCK +// +// tbi_tbl +// Table to do tbi instructions +// 4 instructions per entry +// +tbi_tbl: + // -2 tbia +//orig pvc_jsr tbi, dest=1 + mtpr r31, ev5__dtb_ia // Flush DTB + mtpr r31, ev5__itb_ia // Flush ITB + + hw_rei_stall + + nop // Pad table + + // -1 tbiap +//orig pvc_jsr tbi, dest=1 + mtpr r31, ev5__dtb_iap // Flush DTB + mtpr r31, ev5__itb_iap // Flush ITB + + hw_rei_stall + + nop // Pad table + + + // 0 unused +//orig pvc_jsr tbi, dest=1 + hw_rei // Pad table + nop + nop + nop + + + // 1 tbisi +//orig pvc_jsr tbi, dest=1 + + nop + nop + mtpr r17, ev5__itb_is // Flush ITB + hw_rei_stall + + // 2 tbisd +//orig pvc_jsr tbi, dest=1 + mtpr r17, ev5__dtb_is // Flush DTB. + nop + + nop + hw_rei_stall + + + // 3 tbis +//orig pvc_jsr tbi, dest=1 + mtpr r17, ev5__dtb_is // Flush DTB + br r31, tbi_finish + ALIGN_BRANCH +tbi_finish: + mtpr r17, ev5__itb_is // Flush ITB + hw_rei_stall + + + + ALIGN_BLOCK +// +// bpt_bchk_common: +// Finish up the bpt/bchk instructions +// +bpt_bchk_common: + stq r18, osfsf_a2(sp) // a2 + mfpr r13, pt_entif // get entry point + + stq r12, osfsf_ps(sp) // save old ps + stq r14, osfsf_pc(sp) // save pc + + stq r29, osfsf_gp(sp) // save gp + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kgp + + + hw_rei_spe // done + + + ALIGN_BLOCK +// +// rti_to_user +// Finish up the rti instruction +// +rti_to_user: + mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles + mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei + + mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles + mtpr r25, pt_ksp // save off incase RTI to user + + mfpr r30, pt_usp + hw_rei_spe // and back + + + ALIGN_BLOCK +// +// rti_to_kern +// Finish up the rti instruction +// +rti_to_kern: + and r12, osfps_m_ipl, r11 // clean ps + mfpr r12, pt_intmask // get int mask + + extbl r12, r11, r12 // get mask for this ipl + mtpr r25, pt_ksp // save off incase RTI to user + + mtpr r12, ev5__ipl // set the new ipl. + or r25, r31, sp // sp + +// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals + hw_rei + + ALIGN_BLOCK +// +// swpctx_cont +// Finish up the swpctx instruction +// + +swpctx_cont: + + bic r25, r24, r25 // clean icsr<FPE,PMP> + sll r12, icsr_v_fpe, r12 // shift new fen to pos + + ldq_p r14, osfpcb_q_mmptr(r16)// get new mmptr + srl r22, osfpcb_v_pme, r22 // get pme down to bit 0 + + or r25, r12, r25 // icsr with new fen + srl r23, 32, r24 // move asn to low asn pos + + and r22, 1, r22 + sll r24, itb_asn_v_asn, r12 + + sll r22, icsr_v_pmp, r22 + nop + + or r25, r22, r25 // icsr with new pme + + sll r24, dtb_asn_v_asn, r24 + + subl r23, r13, r13 // gen new cc offset + mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4 + + mtpr r24, dtb_asn // Load up new ASN + mtpr r25, icsr // write the icsr + + sll r14, page_offset_size_bits, r14 // Move PTBR into internal position. + ldq_p r25, osfpcb_q_usp(r16) // get new usp + + insll r13, 4, r13 // >> 32 +// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow + mtpr r14, pt_ptbr // load the new ptbr + + mtpr r13, cc // set new offset + ldq_p r30, osfpcb_q_ksp(r16) // get new ksp + +// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow + mtpr r25, pt_usp // save usp + +no_pm_change_10_: hw_rei_stall // back we go + + ALIGN_BLOCK +// +// swppal_cont - finish up the swppal call_pal +// + +swppal_cont: + mfpr r2, pt_misc // get misc bits + sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit + or r2, r0, r2 // set the bit + mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel) + mtpr r2, pt_misc // update the chip + + or r3, r31, r4 + mfpr r3, pt_impure // pass pointer to the impure area in r3 +//orig fix_impure_ipr r3 // adjust impure pointer for ipr read +//orig restore_reg1 bc_ctl, r1, r3, ipr=1 // pass cns_bc_ctl in r1 +//orig restore_reg1 bc_config, r2, r3, ipr=1 // pass cns_bc_config in r2 +//orig unfix_impure_ipr r3 // restore impure pointer + lda r3, CNS_Q_IPR(r3) + RESTORE_SHADOW(r1,CNS_Q_BC_CTL,r3); + RESTORE_SHADOW(r1,CNS_Q_BC_CFG,r3); + lda r3, -CNS_Q_IPR(r3) + + or r31, r31, r0 // set status to success +// pvc_violate 1007 + jmp r31, (r4) // and call our friend, it's her problem now + + +swppal_fail: + addq r0, 1, r0 // set unknown pal or not loaded + hw_rei // and return + + +// .sbttl "Memory management" + + ALIGN_BLOCK +// +//foe_ipte_handler +// IFOE detected on level 3 pte, sort out FOE vs ACV +// +// on entry: +// with +// R8 = pte +// R10 = pc +// +// Function +// Determine TNV vs ACV vs FOE. Build stack and dispatch +// Will not be here if TNV. +// + +foe_ipte_handler: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS for stack write + bge r25, foe_ipte_handler_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + + srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern + nop + +foe_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0> + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack + mfpr r13, pt_entmm // get entry point + + stq r16, osfsf_a0(sp) // a0 + or r14, r31, r16 // pass pc/va as a0 + + stq r17, osfsf_a1(sp) // a1 + nop + + stq r18, osfsf_a2(sp) // a2 + lda r17, mmcsr_c_acv(r31) // assume ACV + + stq r16, osfsf_pc(sp) // save pc + cmovlbs r25, mmcsr_c_foe, r17 // otherwise FOE + + stq r12, osfsf_ps(sp) // save ps + subq r31, 1, r18 // pass flag of istream as a2 + + stq r29, osfsf_gp(sp) + mtpr r13, exc_addr // set vector address + + mfpr r29, pt_kgp // load kgp + hw_rei_spe // out to exec + + ALIGN_BLOCK +// +//invalid_ipte_handler +// TNV detected on level 3 pte, sort out TNV vs ACV +// +// on entry: +// with +// R8 = pte +// R10 = pc +// +// Function +// Determine TNV vs ACV. Build stack and dispatch. +// + +invalid_ipte_handler: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS for stack write + bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + + srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern + nop + +invalid_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0> + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + or r10, r31, r14 // Save pc/va in case TBmiss on stack + mfpr r13, pt_entmm // get entry point + + stq r16, osfsf_a0(sp) // a0 + or r14, r31, r16 // pass pc/va as a0 + + stq r17, osfsf_a1(sp) // a1 + nop + + stq r18, osfsf_a2(sp) // a2 + and r25, 1, r17 // Isolate kre + + stq r16, osfsf_pc(sp) // save pc + xor r17, 1, r17 // map to acv/tnv as a1 + + stq r12, osfsf_ps(sp) // save ps + subq r31, 1, r18 // pass flag of istream as a2 + + stq r29, osfsf_gp(sp) + mtpr r13, exc_addr // set vector address + + mfpr r29, pt_kgp // load kgp + hw_rei_spe // out to exec + + + + + ALIGN_BLOCK +// +//invalid_dpte_handler +// INVALID detected on level 3 pte, sort out TNV vs ACV +// +// on entry: +// with +// R10 = va +// R8 = pte +// R9 = mm_stat +// PT6 = pc +// +// Function +// Determine TNV vs ACV. Build stack and dispatch +// + + +invalid_dpte_handler: + mfpr r12, pt6 + blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode + + bis r12, r31, r14 // save PC in case of tbmiss or fault + srl r9, mm_stat_v_opcode, r25 // shift opc to <0> + + mtpr r11, pt0 // Save PS for stack write + and r25, mm_stat_m_opcode, r25 // isolate opcode + + cmpeq r25, evx_opc_sync, r25 // is it FETCH/FETCH_M? + blbs r25, nmiss_fetch_ldr31_err // yes + + //dismiss exception if load to r31/f31 + blbs r9, invalid_dpte_no_dismiss // mm_stat<0> set on store or fetchm + + // not a store or fetch, must be a load + srl r9, mm_stat_v_ra, r25 // Shift rnum to low bits + + and r25, 0x1F, r25 // isolate rnum + nop + + cmpeq r25, 0x1F, r25 // Is the rnum r31 or f31? + bne r25, nmiss_fetch_ldr31_err // Yes, dismiss the fault + +invalid_dpte_no_dismiss: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + bge r25, invalid_dpte_no_dismiss_10_ // no stack swap needed if cm=kern + + srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + +invalid_dpte_no_dismiss_10_: srl r8, osfpte_v_kre, r12 // get kre to <0> + lda sp, 0-osfsf_c_size(sp)// allocate stack space + + or r10, r31, r25 // Save va in case TBmiss on stack + and r9, 1, r13 // save r/w flag + + stq r16, osfsf_a0(sp) // a0 + or r25, r31, r16 // pass va as a0 + + stq r17, osfsf_a1(sp) // a1 + or r31, mmcsr_c_acv, r17 // assume acv + + srl r12, osfpte_v_kwe-osfpte_v_kre, r25 // get write enable to <0> + stq r29, osfsf_gp(sp) + + stq r18, osfsf_a2(sp) // a2 + cmovlbs r13, r25, r12 // if write access move acv based on write enable + + or r13, r31, r18 // pass flag of dstream access and read vs write + mfpr r25, pt0 // get ps + + stq r14, osfsf_pc(sp) // save pc + mfpr r13, pt_entmm // get entry point + + stq r25, osfsf_ps(sp) // save ps + mtpr r13, exc_addr // set vector address + + mfpr r29, pt_kgp // load kgp + cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv + + hw_rei_spe // out to exec + +// +// +// We come here if we are erring on a dtb_miss, and the instr is a +// fetch, fetch_m, of load to r31/f31. +// The PC is incremented, and we return to the program. +// essentially ignoring the instruction and error. +// +// + ALIGN_BLOCK +nmiss_fetch_ldr31_err: + mfpr r12, pt6 + addq r12, 4, r12 // bump pc to pc+4 + + mtpr r12, exc_addr // and set entry point + mfpr r31, pt0 // pad exc_addr write + + hw_rei // + + ALIGN_BLOCK +// +// double_pte_inv +// We had a single tbmiss which turned into a double tbmiss which found +// an invalid PTE. Return to single miss with a fake pte, and the invalid +// single miss flow will report the error. +// +// on entry: +// r21 PTE +// r22 available +// VA IPR locked with original fault VA +// pt4 saved r21 +// pt5 saved r22 +// pt6 original exc_addr +// +// on return to tbmiss flow: +// r8 fake PTE +// +// +// +double_pte_inv: + srl r21, osfpte_v_kre, r21 // get the kre bit to <0> + mfpr r22, exc_addr // get the pc + + lda r22, 4(r22) // inc the pc + lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set + + cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0 + mtpr r22, exc_addr // set for rei + + mfpr r21, pt4 // restore regs + mfpr r22, pt5 // restore regs + + hw_rei // back to tb miss + + ALIGN_BLOCK +// +//tnv_in_pal +// The only places in pal that ld or store are the +// stack builders, rti or retsys. Any of these mean we +// need to take a ksp not valid halt. +// +// +tnv_in_pal: + + + br r31, ksp_inval_halt + + +// .sbttl "Icache flush routines" + + ALIGN_BLOCK +// +// Common Icache flush routine. +// +// +// +pal_ic_flush: + nop + mtpr r31, ev5__ic_flush_ctl // Icache flush - E1 + nop + nop + +// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20) + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 10 + + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 20 + + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 30 + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop // 40 + + nop + nop + +one_cycle_and_hw_rei: + nop + nop + + hw_rei_stall + + ALIGN_BLOCK +// +//osfpal_calpal_opcdec +// Here for all opcdec CALL_PALs +// +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +// + +osfpal_calpal_opcdec: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r14, exc_addr // get pc + nop + + bis r11, r31, r12 // Save PS for stack write + bge r25, osfpal_calpal_opcdec_10_ // no stack swap needed if cm=kern + + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + +osfpal_calpal_opcdec_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + nop + + stq r16, osfsf_a0(sp) // save regs + bis r31, osf_a0_opdec, r16 // set a0 + + stq r18, osfsf_a2(sp) // a2 + mfpr r13, pt_entif // get entry point + + stq r12, osfsf_ps(sp) // save old ps + stq r17, osfsf_a1(sp) // a1 + + stq r14, osfsf_pc(sp) // save pc + nop + + stq r29, osfsf_gp(sp) // save gp + mtpr r13, exc_addr // load exc_addr with entIF + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kgp + + + hw_rei_spe // done + + + + + +// +//pal_update_pcb +// Update the PCB with the current SP, AST, and CC info +// +// r0 - return linkage +// + ALIGN_BLOCK + +pal_update_pcb: + mfpr r12, pt_pcbb // get pcbb + and r11, osfps_m_mode, r25 // get mode + beq r25, pal_update_pcb_10_ // in kern? no need to update user sp + mtpr r30, pt_usp // save user stack + stq_p r30, osfpcb_q_usp(r12) // store usp + br r31, pal_update_pcb_20_ // join common +pal_update_pcb_10_: stq_p r30, osfpcb_q_ksp(r12) // store ksp +pal_update_pcb_20_: rpcc r13 // get cyccounter + srl r13, 32, r14 // move offset + addl r13, r14, r14 // merge for new time + stl_p r14, osfpcb_l_cc(r12) // save time + +//orig pvc_jsr updpcb, bsr=1, dest=1 + ret r31, (r0) + + +// +// pal_save_state +// +// Function +// All chip state saved, all PT's, SR's FR's, IPR's +// +// +// Regs' on entry... +// +// R0 = halt code +// pt0 = r0 +// R1 = pointer to impure +// pt4 = r1 +// R3 = return addr +// pt5 = r3 +// +// register usage: +// r0 = halt_code +// r1 = addr of impure area +// r3 = return_address +// r4 = scratch +// +// + + ALIGN_BLOCK + .globl pal_save_state +pal_save_state: +// +// +// start of implementation independent save routine +// +// the impure area is larger than the addressibility of hw_ld and hw_st +// therefore, we need to play some games: The impure area +// is informally divided into the "machine independent" part and the +// "machine dependent" part. The state that will be saved in the +// "machine independent" part are gpr's, fpr's, hlt, flag, mchkflag (use (un)fix_impure_gpr macros). +// All others will be in the "machine dependent" part (use (un)fix_impure_ipr macros). +// The impure pointer will need to be adjusted by a different offset for each. The store/restore_reg +// macros will automagically adjust the offset correctly. +// + +// The distributed code is commented out and followed by corresponding SRC code. +// Beware: SAVE_IPR and RESTORE_IPR blow away r0(v0) + +//orig fix_impure_gpr r1 // adjust impure area pointer for stores to "gpr" part of impure area + lda r1, 0x200(r1) // Point to center of CPU segment +//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area flag + SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the valid flag +//orig store_reg1 hlt, r0, r1, ipr=1 + SAVE_GPR(r0,CNS_Q_HALT,r1) // Save the halt code + + mfpr r0, pt0 // get r0 back //orig +//orig store_reg1 0, r0, r1 // save r0 + SAVE_GPR(r0,CNS_Q_GPR+0x00,r1) // Save r0 + + mfpr r0, pt4 // get r1 back //orig +//orig store_reg1 1, r0, r1 // save r1 + SAVE_GPR(r0,CNS_Q_GPR+0x08,r1) // Save r1 + +//orig store_reg 2 // save r2 + SAVE_GPR(r2,CNS_Q_GPR+0x10,r1) // Save r2 + + mfpr r0, pt5 // get r3 back //orig +//orig store_reg1 3, r0, r1 // save r3 + SAVE_GPR(r0,CNS_Q_GPR+0x18,r1) // Save r3 + + // reason code has been saved + // r0 has been saved + // r1 has been saved + // r2 has been saved + // r3 has been saved + // pt0, pt4, pt5 have been lost + + // + // Get out of shadow mode + // + + mfpr r2, icsr // Get icsr + ldah r0, (1<<(icsr_v_sde-16))(r31) + bic r2, r0, r0 // ICSR with SDE clear + mtpr r0, icsr // Turn off SDE + + mfpr r31, pt0 // SDE bubble cycle 1 + mfpr r31, pt0 // SDE bubble cycle 2 + mfpr r31, pt0 // SDE bubble cycle 3 + nop + + + // save integer regs R4-r31 + SAVE_GPR(r4,CNS_Q_GPR+0x20,r1) + SAVE_GPR(r5,CNS_Q_GPR+0x28,r1) + SAVE_GPR(r6,CNS_Q_GPR+0x30,r1) + SAVE_GPR(r7,CNS_Q_GPR+0x38,r1) + SAVE_GPR(r8,CNS_Q_GPR+0x40,r1) + SAVE_GPR(r9,CNS_Q_GPR+0x48,r1) + SAVE_GPR(r10,CNS_Q_GPR+0x50,r1) + SAVE_GPR(r11,CNS_Q_GPR+0x58,r1) + SAVE_GPR(r12,CNS_Q_GPR+0x60,r1) + SAVE_GPR(r13,CNS_Q_GPR+0x68,r1) + SAVE_GPR(r14,CNS_Q_GPR+0x70,r1) + SAVE_GPR(r15,CNS_Q_GPR+0x78,r1) + SAVE_GPR(r16,CNS_Q_GPR+0x80,r1) + SAVE_GPR(r17,CNS_Q_GPR+0x88,r1) + SAVE_GPR(r18,CNS_Q_GPR+0x90,r1) + SAVE_GPR(r19,CNS_Q_GPR+0x98,r1) + SAVE_GPR(r20,CNS_Q_GPR+0xA0,r1) + SAVE_GPR(r21,CNS_Q_GPR+0xA8,r1) + SAVE_GPR(r22,CNS_Q_GPR+0xB0,r1) + SAVE_GPR(r23,CNS_Q_GPR+0xB8,r1) + SAVE_GPR(r24,CNS_Q_GPR+0xC0,r1) + SAVE_GPR(r25,CNS_Q_GPR+0xC8,r1) + SAVE_GPR(r26,CNS_Q_GPR+0xD0,r1) + SAVE_GPR(r27,CNS_Q_GPR+0xD8,r1) + SAVE_GPR(r28,CNS_Q_GPR+0xE0,r1) + SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1) + SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1) + SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1) + + // save all paltemp regs except pt0 + +//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores +//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores + + lda r1, -0x200(r1) // Restore the impure base address. + lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area. + SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle + SAVE_IPR(pt1,CNS_Q_PT+0x08,r1) + SAVE_IPR(pt2,CNS_Q_PT+0x10,r1) + SAVE_IPR(pt3,CNS_Q_PT+0x18,r1) + SAVE_IPR(pt4,CNS_Q_PT+0x20,r1) + SAVE_IPR(pt5,CNS_Q_PT+0x28,r1) + SAVE_IPR(pt6,CNS_Q_PT+0x30,r1) + SAVE_IPR(pt7,CNS_Q_PT+0x38,r1) + SAVE_IPR(pt8,CNS_Q_PT+0x40,r1) + SAVE_IPR(pt9,CNS_Q_PT+0x48,r1) + SAVE_IPR(pt10,CNS_Q_PT+0x50,r1) + SAVE_IPR(pt11,CNS_Q_PT+0x58,r1) + SAVE_IPR(pt12,CNS_Q_PT+0x60,r1) + SAVE_IPR(pt13,CNS_Q_PT+0x68,r1) + SAVE_IPR(pt14,CNS_Q_PT+0x70,r1) + SAVE_IPR(pt15,CNS_Q_PT+0x78,r1) + SAVE_IPR(pt16,CNS_Q_PT+0x80,r1) + SAVE_IPR(pt17,CNS_Q_PT+0x88,r1) + SAVE_IPR(pt18,CNS_Q_PT+0x90,r1) + SAVE_IPR(pt19,CNS_Q_PT+0x98,r1) + SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1) + SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1) + SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1) + SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1) + + // Restore shadow mode + mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) + mfpr r31, pt0 + mtpr r2, icsr // Restore original ICSR + + mfpr r31, pt0 // SDE bubble cycle 1 + mfpr r31, pt0 // SDE bubble cycle 2 + mfpr r31, pt0 // SDE bubble cycle 3 + nop + + // save all integer shadow regs + SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code + SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) + SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) + SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) + SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) + SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) + SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) + SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) + + SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) + SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1) + SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1) + SAVE_IPR(va,CNS_Q_VA,r1) + SAVE_IPR(icsr,CNS_Q_ICSR,r1) + SAVE_IPR(ipl,CNS_Q_IPL,r1) + SAVE_IPR(ips,CNS_Q_IPS,r1) + SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) + SAVE_IPR(aster,CNS_Q_ASTER,r1) + SAVE_IPR(astrr,CNS_Q_ASTRR,r1) + SAVE_IPR(sirr,CNS_Q_SIRR,r1) + SAVE_IPR(isr,CNS_Q_ISR,r1) + SAVE_IPR(iVptBr,CNS_Q_IVPTBR,r1) + SAVE_IPR(mcsr,CNS_Q_MCSR,r1) + SAVE_IPR(dcMode,CNS_Q_DC_MODE,r1) + +//orig pvc_violate 379 // mf maf_mode after a store ok (pvc doesn't distinguish ld from st) +//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for +//orig // PVC violation applies only to +pvc$osf35$379: // loads. HW_ST ok here, so ignore + SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2 + + + //the following iprs are informational only -- will not be restored + + SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1) + SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1) + SAVE_IPR(intId,CNS_Q_INT_ID,r1) + SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1) + SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1) + ldah r14, 0xFFF0(zero) + zap r14, 0xE0, r14 // Get base address of CBOX IPRs + NOP // Pad mfpr dcPerr out of shadow of + NOP // last store + NOP + SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1) + + // read cbox ipr state + + mb + ldq_p r2, scCtl(r14) + ldq_p r13, ldLock(r14) + ldq_p r4, scAddr(r14) + ldq_p r5, eiAddr(r14) + ldq_p r6, bcTagAddr(r14) + ldq_p r7, fillSyn(r14) + bis r5, r4, zero // Make sure all loads complete before + bis r7, r6, zero // reading registers that unlock them. + ldq_p r8, scStat(r14) // Unlocks scAddr. + ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn. + ldq_p zero, eiStat(r14) // Make sure it is really unlocked. + mb + + // save cbox ipr state + SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1); + SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1); + SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1); + SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1); + SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1); + SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1); + SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1); + SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1); + //bc_config? sl_rcv? + +// restore impure base +//orig unfix_impure_ipr r1 + lda r1, -CNS_Q_IPR(r1) + +// save all floating regs + mfpr r0, icsr // get icsr + or r31, 1, r2 // get a one + sll r2, icsr_v_fpe, r2 // Shift it into ICSR<FPE> position + or r2, r0, r0 // set FEN on + mtpr r0, icsr // write to icsr, enabling FEN + +// map the save area virtually + mtpr r31, dtbIa // Clear all DTB entries + srl r1, va_s_off, r0 // Clean off byte-within-page offset + sll r0, pte_v_pfn, r0 // Shift to form PFN + lda r0, pte_m_prot(r0) // Set all read/write enable bits + mtpr r0, dtbPte // Load the PTE and set valid + mtpr r1, dtbTag // Write the PTE and tag into the DTB + + +// map the next page too - in case the impure area crosses a page boundary + lda r4, (1<<va_s_off)(r1) // Generate address for next page + srl r4, va_s_off, r0 // Clean off byte-within-page offset + sll r0, pte_v_pfn, r0 // Shift to form PFN + lda r0, pte_m_prot(r0) // Set all read/write enable bits + mtpr r0, dtbPte // Load the PTE and set valid + mtpr r4, dtbTag // Write the PTE and tag into the DTB + + sll r31, 0, r31 // stall cycle 1 + sll r31, 0, r31 // stall cycle 2 + sll r31, 0, r31 // stall cycle 3 + nop + +// add offset for saving fpr regs +//orig fix_impure_gpr r1 + lda r1, 0x200(r1) // Point to center of CPU segment + +// now save the regs - F0-F31 + mf_fpcr f0 // original + + SAVE_FPR(f0,CNS_Q_FPR+0x00,r1) + SAVE_FPR(f1,CNS_Q_FPR+0x08,r1) + SAVE_FPR(f2,CNS_Q_FPR+0x10,r1) + SAVE_FPR(f3,CNS_Q_FPR+0x18,r1) + SAVE_FPR(f4,CNS_Q_FPR+0x20,r1) + SAVE_FPR(f5,CNS_Q_FPR+0x28,r1) + SAVE_FPR(f6,CNS_Q_FPR+0x30,r1) + SAVE_FPR(f7,CNS_Q_FPR+0x38,r1) + SAVE_FPR(f8,CNS_Q_FPR+0x40,r1) + SAVE_FPR(f9,CNS_Q_FPR+0x48,r1) + SAVE_FPR(f10,CNS_Q_FPR+0x50,r1) + SAVE_FPR(f11,CNS_Q_FPR+0x58,r1) + SAVE_FPR(f12,CNS_Q_FPR+0x60,r1) + SAVE_FPR(f13,CNS_Q_FPR+0x68,r1) + SAVE_FPR(f14,CNS_Q_FPR+0x70,r1) + SAVE_FPR(f15,CNS_Q_FPR+0x78,r1) + SAVE_FPR(f16,CNS_Q_FPR+0x80,r1) + SAVE_FPR(f17,CNS_Q_FPR+0x88,r1) + SAVE_FPR(f18,CNS_Q_FPR+0x90,r1) + SAVE_FPR(f19,CNS_Q_FPR+0x98,r1) + SAVE_FPR(f20,CNS_Q_FPR+0xA0,r1) + SAVE_FPR(f21,CNS_Q_FPR+0xA8,r1) + SAVE_FPR(f22,CNS_Q_FPR+0xB0,r1) + SAVE_FPR(f23,CNS_Q_FPR+0xB8,r1) + SAVE_FPR(f24,CNS_Q_FPR+0xC0,r1) + SAVE_FPR(f25,CNS_Q_FPR+0xC8,r1) + SAVE_FPR(f26,CNS_Q_FPR+0xD0,r1) + SAVE_FPR(f27,CNS_Q_FPR+0xD8,r1) + SAVE_FPR(f28,CNS_Q_FPR+0xE0,r1) + SAVE_FPR(f29,CNS_Q_FPR+0xE8,r1) + SAVE_FPR(f30,CNS_Q_FPR+0xF0,r1) + SAVE_FPR(f31,CNS_Q_FPR+0xF8,r1) + +//switch impure offset from gpr to ipr--- +//orig unfix_impure_gpr r1 +//orig fix_impure_ipr r1 +//orig store_reg1 fpcsr, f0, r1, fpcsr=1 + + SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach + lda r1, -0x200(r1) // Restore the impure base address + +// and back to gpr --- +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 + +//orig lda r0, cns_mchksize(r31) // get size of mchk area +//orig store_reg1 mchkflag, r0, r1, ipr=1 +//orig mb + + lda r1, CNS_Q_IPR(r1) // Point to base of IPR area again + // save this using the IPR base (it is closer) not the GRP base as they used...pb + lda r0, MACHINE_CHECK_SIZE(r31) // get size of mchk area + SAVE_SHADOW(r0,CNS_Q_MCHK,r1); + mb + +//orig or r31, 1, r0 // get a one +//orig store_reg1 flag, r0, r1, ipr=1 // set dump area flag +//orig mb + + lda r1, -CNS_Q_IPR(r1) // back to the base + lda r1, 0x200(r1) // Point to center of CPU segment + or r31, 1, r0 // get a one + SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag + mb + + // restore impure area base +//orig unfix_impure_gpr r1 + lda r1, -0x200(r1) // Point to center of CPU segment + + mtpr r31, dtb_ia // clear the dtb + mtpr r31, itb_ia // clear the itb + +//orig pvc_jsr savsta, bsr=1, dest=1 + ret r31, (r3) // and back we go + + + +// .sbttl "PAL_RESTORE_STATE" +// +// +// Pal_restore_state +// +// +// register usage: +// r1 = addr of impure area +// r3 = return_address +// all other regs are scratchable, as they are about to +// be reloaded from ram. +// +// Function: +// All chip state restored, all SRs, FRs, PTs, IPRs +// *** except R1, R3, PT0, PT4, PT5 *** +// +// + ALIGN_BLOCK +pal_restore_state: + +//need to restore sc_ctl,bc_ctl,bc_config??? if so, need to figure out a safe way to do so. + +// map the console io area virtually + mtpr r31, dtbIa // Clear all DTB entries + srl r1, va_s_off, r0 // Clean off byte-within-page offset + sll r0, pte_v_pfn, r0 // Shift to form PFN + lda r0, pte_m_prot(r0) // Set all read/write enable bits + mtpr r0, dtbPte // Load the PTE and set valid + mtpr r1, dtbTag // Write the PTE and tag into the DTB + + +// map the next page too, in case impure area crosses page boundary + lda r4, (1<<VA_S_OFF)(r1) // Generate address for next page + srl r4, va_s_off, r0 // Clean off byte-within-page offset + sll r0, pte_v_pfn, r0 // Shift to form PFN + lda r0, pte_m_prot(r0) // Set all read/write enable bits + mtpr r0, dtbPte // Load the PTE and set valid + mtpr r4, dtbTag // Write the PTE and tag into the DTB + +// save all floating regs + mfpr r0, icsr // Get current ICSR + bis zero, 1, r2 // Get a '1' + or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2 + sll r2, icsr_v_fpe, r2 // Shift bits into position + bis r2, r2, r0 // Set ICSR<SDE> and ICSR<FPE> + mtpr r0, icsr // Update the chip + + mfpr r31, pt0 // FPE bubble cycle 1 //orig + mfpr r31, pt0 // FPE bubble cycle 2 //orig + mfpr r31, pt0 // FPE bubble cycle 3 //orig + +//orig fix_impure_ipr r1 +//orig restore_reg1 fpcsr, f0, r1, fpcsr=1 +//orig mt_fpcr f0 +//orig +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access + lda r1, 200(r1) // Point to base of IPR area again + RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb + mt_fpcr f0 // original + + lda r1, 0x200(r1) // point to center of CPU segment + +// restore all floating regs + RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1) + RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1) + RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1) + RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1) + RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1) + RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1) + RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1) + RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1) + RESTORE_FPR(f8,CNS_Q_FPR+0x40,r1) + RESTORE_FPR(f9,CNS_Q_FPR+0x48,r1) + RESTORE_FPR(f10,CNS_Q_FPR+0x50,r1) + RESTORE_FPR(f11,CNS_Q_FPR+0x58,r1) + RESTORE_FPR(f12,CNS_Q_FPR+0x60,r1) + RESTORE_FPR(f13,CNS_Q_FPR+0x68,r1) + RESTORE_FPR(f14,CNS_Q_FPR+0x70,r1) + RESTORE_FPR(f15,CNS_Q_FPR+0x78,r1) + RESTORE_FPR(f16,CNS_Q_FPR+0x80,r1) + RESTORE_FPR(f17,CNS_Q_FPR+0x88,r1) + RESTORE_FPR(f18,CNS_Q_FPR+0x90,r1) + RESTORE_FPR(f19,CNS_Q_FPR+0x98,r1) + RESTORE_FPR(f20,CNS_Q_FPR+0xA0,r1) + RESTORE_FPR(f21,CNS_Q_FPR+0xA8,r1) + RESTORE_FPR(f22,CNS_Q_FPR+0xB0,r1) + RESTORE_FPR(f23,CNS_Q_FPR+0xB8,r1) + RESTORE_FPR(f24,CNS_Q_FPR+0xC0,r1) + RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1) + RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1) + RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1) + RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1) + RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1) + RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1) + RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1) + +// switch impure pointer from gpr to ipr area -- +//orig unfix_impure_gpr r1 +//orig fix_impure_ipr r1 + lda r1, -0x200(r1) // Restore base address of impure area. + lda r1, CNS_Q_IPR(r1) // Point to base of IPR area. + +// restore all pal regs + RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle + RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1) + RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1) + RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1) + RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1) + RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1) + RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1) + RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1) + RESTORE_IPR(pt8,CNS_Q_PT+0x40,r1) + RESTORE_IPR(pt9,CNS_Q_PT+0x48,r1) + RESTORE_IPR(pt10,CNS_Q_PT+0x50,r1) + RESTORE_IPR(pt11,CNS_Q_PT+0x58,r1) + RESTORE_IPR(pt12,CNS_Q_PT+0x60,r1) + RESTORE_IPR(pt13,CNS_Q_PT+0x68,r1) + RESTORE_IPR(pt14,CNS_Q_PT+0x70,r1) + RESTORE_IPR(pt15,CNS_Q_PT+0x78,r1) + RESTORE_IPR(pt16,CNS_Q_PT+0x80,r1) + RESTORE_IPR(pt17,CNS_Q_PT+0x88,r1) + RESTORE_IPR(pt18,CNS_Q_PT+0x90,r1) + RESTORE_IPR(pt19,CNS_Q_PT+0x98,r1) + RESTORE_IPR(pt20,CNS_Q_PT+0xA0,r1) + RESTORE_IPR(pt21,CNS_Q_PT+0xA8,r1) + RESTORE_IPR(pt22,CNS_Q_PT+0xB0,r1) + RESTORE_IPR(pt23,CNS_Q_PT+0xB8,r1) + + +//orig restore_reg exc_addr, ipr=1 // restore ipr +//orig restore_reg pal_base, ipr=1 // restore ipr +//orig restore_reg ipl, ipr=1 // restore ipr +//orig restore_reg ps, ipr=1 // restore ipr +//orig mtpr r0, dtb_cm // set current mode in mbox too +//orig restore_reg itb_asn, ipr=1 +//orig srl r0, itb_asn_v_asn, r0 +//orig sll r0, dtb_asn_v_asn, r0 +//orig mtpr r0, dtb_asn // set ASN in Mbox too +//orig restore_reg ivptbr, ipr=1 +//orig mtpr r0, mvptbr // use ivptbr value to restore mvptbr +//orig restore_reg mcsr, ipr=1 +//orig restore_reg aster, ipr=1 +//orig restore_reg astrr, ipr=1 +//orig restore_reg sirr, ipr=1 +//orig restore_reg maf_mode, ipr=1 // no mbox instruction for 3 cycles +//orig mfpr r31, pt0 // (may issue with mt maf_mode) +//orig mfpr r31, pt0 // bubble cycle 1 +//orig mfpr r31, pt0 // bubble cycle 2 +//orig mfpr r31, pt0 // bubble cycle 3 +//orig mfpr r31, pt0 // (may issue with following ld) + + // r0 gets the value of RESTORE_IPR in the macro and this code uses this side effect (gag) + RESTORE_IPR(excAddr,CNS_Q_EXC_ADDR,r1) + RESTORE_IPR(palBase,CNS_Q_PAL_BASE,r1) + RESTORE_IPR(ipl,CNS_Q_IPL,r1) + RESTORE_IPR(ips,CNS_Q_IPS,r1) + mtpr r0, dtbCm // Set Mbox current mode too. + RESTORE_IPR(itbAsn,CNS_Q_ITB_ASN,r1) + srl r0, 4, r0 + sll r0, 57, r0 + mtpr r0, dtbAsn // Set Mbox ASN too + RESTORE_IPR(iVptBr,CNS_Q_IVPTBR,r1) + mtpr r0, mVptBr // Set Mbox VptBr too + RESTORE_IPR(mcsr,CNS_Q_MCSR,r1) + RESTORE_IPR(aster,CNS_Q_ASTER,r1) + RESTORE_IPR(astrr,CNS_Q_ASTRR,r1) + RESTORE_IPR(sirr,CNS_Q_SIRR,r1) + RESTORE_IPR(mafMode,CNS_Q_MAF_MODE,r1) + STALL + STALL + STALL + STALL + STALL + + + // restore all integer shadow regs + RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code + RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1) + RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1) + RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1) + RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1) + RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1) + RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1) + RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1) + RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1) + + // + // Get out of shadow mode + // + + mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) + mfpr r31, pt0 // "" + mfpr r0, icsr // Get icsr + ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location + bic r0, r2, r2 // ICSR with SDE clear + mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles + + mfpr r31, pt0 // SDE bubble cycle 1 + mfpr r31, pt0 // SDE bubble cycle 2 + mfpr r31, pt0 // SDE bubble cycle 3 + nop + +// switch impure pointer from ipr to gpr area -- +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 + +// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ... + + lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area + lda r1, 0x200(r1) // Point to center of CPU segment + + // restore all integer regs + RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1) + RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1) + RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1) + RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1) + RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1) + RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1) + RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1) + RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1) + RESTORE_GPR(r12,CNS_Q_GPR+0x60,r1) + RESTORE_GPR(r13,CNS_Q_GPR+0x68,r1) + RESTORE_GPR(r14,CNS_Q_GPR+0x70,r1) + RESTORE_GPR(r15,CNS_Q_GPR+0x78,r1) + RESTORE_GPR(r16,CNS_Q_GPR+0x80,r1) + RESTORE_GPR(r17,CNS_Q_GPR+0x88,r1) + RESTORE_GPR(r18,CNS_Q_GPR+0x90,r1) + RESTORE_GPR(r19,CNS_Q_GPR+0x98,r1) + RESTORE_GPR(r20,CNS_Q_GPR+0xA0,r1) + RESTORE_GPR(r21,CNS_Q_GPR+0xA8,r1) + RESTORE_GPR(r22,CNS_Q_GPR+0xB0,r1) + RESTORE_GPR(r23,CNS_Q_GPR+0xB8,r1) + RESTORE_GPR(r24,CNS_Q_GPR+0xC0,r1) + RESTORE_GPR(r25,CNS_Q_GPR+0xC8,r1) + RESTORE_GPR(r26,CNS_Q_GPR+0xD0,r1) + RESTORE_GPR(r27,CNS_Q_GPR+0xD8,r1) + RESTORE_GPR(r28,CNS_Q_GPR+0xE0,r1) + RESTORE_GPR(r29,CNS_Q_GPR+0xE8,r1) + RESTORE_GPR(r30,CNS_Q_GPR+0xF0,r1) + RESTORE_GPR(r31,CNS_Q_GPR+0xF8,r1) + +//orig // switch impure pointer from gpr to ipr area -- +//orig unfix_impure_gpr r1 +//orig fix_impure_ipr r1 +//orig restore_reg icsr, ipr=1 // restore original icsr- 4 bubbles to hw_rei + + lda t0, -0x200(t0) // Restore base address of impure area. + lda t0, CNS_Q_IPR(t0) // Point to base of IPR area again. + RESTORE_IPR(icsr,CNS_Q_ICSR,r1) + +//orig // and back again -- +//orig unfix_impure_ipr r1 +//orig fix_impure_gpr r1 +//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area valid flag +//orig mb + + lda t0, -CNS_Q_IPR(t0) // Back to base of impure area again, + lda t0, 0x200(t0) // and back to center of CPU segment + SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the dump area valid flag + mb + +//orig // and back we go +//orig// restore_reg 3 +//orig restore_reg 2 +//orig// restore_reg 1 +//orig restore_reg 0 +//orig // restore impure area base +//orig unfix_impure_gpr r1 + + RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1) + RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1) + lda r1, -0x200(r1) // Restore impure base address + + mfpr r31, pt0 // stall for ldq_p above //orig + + mtpr r31, dtb_ia // clear the tb //orig + mtpr r31, itb_ia // clear the itb //orig + +//orig pvc_jsr rststa, bsr=1, dest=1 + ret r31, (r3) // back we go //orig + + +// +// pal_pal_bug_check -- code has found a bugcheck situation. +// Set things up and join common machine check flow. +// +// Input: +// r14 - exc_addr +// +// On exit: +// pt0 - saved r0 +// pt1 - saved r1 +// pt4 - saved r4 +// pt5 - saved r5 +// pt6 - saved r6 +// pt10 - saved exc_addr +// pt_misc<47:32> - mchk code +// pt_misc<31:16> - scb vector +// r14 - base of Cbox IPRs in IO space +// MCES<mchk> is set +// + + ALIGN_BLOCK + .globl pal_pal_bug_check_from_int +pal_pal_bug_check_from_int: + DEBUGSTORE(0x79) +//simos DEBUG_EXC_ADDR() + DEBUGSTORE(0x20) +//simos bsr r25, put_hex + lda r25, mchk_c_bugcheck(r31) + addq r25, 1, r25 // set flag indicating we came from interrupt and stack is already pushed + br r31, pal_pal_mchk + nop + +pal_pal_bug_check: + lda r25, mchk_c_bugcheck(r31) + +pal_pal_mchk: + sll r25, 32, r25 // Move mchk code to position + + mtpr r14, pt10 // Stash exc_addr + mtpr r14, exc_addr + + mfpr r12, pt_misc // Get MCES and scratch + zap r12, 0x3c, r12 + + or r12, r25, r12 // Combine mchk code + lda r25, scb_v_procmchk(r31) // Get SCB vector + + sll r25, 16, r25 // Move SCBv to position + or r12, r25, r25 // Combine SCBv + + mtpr r0, pt0 // Stash for scratch + bis r25, mces_m_mchk, r25 // Set MCES<MCHK> bit + + mtpr r25, pt_misc // Save mchk code!scbv!whami!mces + ldah r14, 0xfff0(r31) + + mtpr r1, pt1 // Stash for scratch + zap r14, 0xE0, r14 // Get Cbox IPR base + + mtpr r4, pt4 + mtpr r5, pt5 + + mtpr r6, pt6 + blbs r12, sys_double_machine_check // MCHK halt if double machine check + + br r31, sys_mchk_collect_iprs // Join common machine check flow + + + +// align_to_call_pal_section +// Align to address of first call_pal entry point - 2000 + +// +// HALT - PALcode for HALT instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// GO to console code +// +// + + .text 1 +// . = 0x2000 + CALL_PAL_PRIV(PAL_HALT_ENTRY) +call_pal_halt: + mfpr r31, pt0 // Pad exc_addr read + mfpr r31, pt0 + + mfpr r12, exc_addr // get PC + subq r12, 4, r12 // Point to the HALT + + mtpr r12, exc_addr + mtpr r0, pt0 + +//orig pvc_jsr updpcb, bsr=1 + bsr r0, pal_update_pcb // update the pcb + lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt + br r31, sys_enter_console // enter the console + +// +// CFLUSH - PALcode for CFLUSH instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// R16 - contains the PFN of the page to be flushed +// +// Function: +// Flush all Dstream caches of 1 entire page +// The CFLUSH routine is in the system specific module. +// +// + + CALL_PAL_PRIV(PAL_CFLUSH_ENTRY) +Call_Pal_Cflush: + br r31, sys_cflush + +// +// DRAINA - PALcode for DRAINA instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// Implicit TRAPB performed by hardware. +// +// Function: +// Stall instruction issue until all prior instructions are guaranteed to +// complete without incurring aborts. For the EV5 implementation, this +// means waiting until all pending DREADS are returned. +// +// + + CALL_PAL_PRIV(PAL_DRAINA_ENTRY) +Call_Pal_Draina: + ldah r14, 0x100(r31) // Init counter. Value? + nop + +DRAINA_LOOP: + subq r14, 1, r14 // Decrement counter + mfpr r13, ev5__maf_mode // Fetch status bit + + srl r13, maf_mode_v_dread_pending, r13 + ble r14, DRAINA_LOOP_TOO_LONG + + nop + blbs r13, DRAINA_LOOP // Wait until all DREADS clear + + hw_rei + +DRAINA_LOOP_TOO_LONG: + br r31, call_pal_halt + +// CALL_PAL OPCDECs + + CALL_PAL_PRIV(0x0003) +CallPal_OpcDec03: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0004) +CallPal_OpcDec04: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0005) +CallPal_OpcDec05: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0006) +CallPal_OpcDec06: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0007) +CallPal_OpcDec07: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0008) +CallPal_OpcDec08: + br r31, osfpal_calpal_opcdec + +// +// CSERVE - PALcode for CSERVE instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// Various functions for private use of console software +// +// option selector in r0 +// arguments in r16.... +// The CSERVE routine is in the system specific module. +// +// + + CALL_PAL_PRIV(PAL_CSERVE_ENTRY) +Call_Pal_Cserve: + br r31, sys_cserve + +// +// swppal - PALcode for swppal instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// Vectored into via hardware PALcode instruction dispatch. +// R16 contains the new PAL identifier +// R17:R21 contain implementation-specific entry parameters +// +// R0 receives status: +// 0 success (PAL was switched) +// 1 unknown PAL variant +// 2 known PAL variant, but PAL not loaded +// +// +// Function: +// Swap control to another PAL. +// + + CALL_PAL_PRIV(PAL_SWPPAL_ENTRY) +Call_Pal_Swppal: + cmpule r16, 255, r0 // see if a kibble was passed + cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59) + + or r16, r31, r3 // set r3 incase this is a address + blbc r0, swppal_cont // nope, try it as an address + + cmpeq r16, 2, r0 // is it our friend OSF? + blbc r0, swppal_fail // nope, don't know this fellow + + br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF + +// .global osfpal_hw_entry_reset +// .weak osfpal_hw_entry_reset +// .long <osfpal_hw_entry_reset-pal_start> +//orig halt // don't know how to get the address here - kludge ok, load pal at 0 + .long 0 // ?? hack upon hack...pb + +CALL_PAL_SWPPAL_10_: ldl_p r3, 0(r2) // fetch target addr +// ble r3, swppal_fail ; if OSF not linked in say not loaded. + mfpr r2, pal_base // fetch pal base + + addq r2, r3, r3 // add pal base + lda r2, 0x3FFF(r31) // get pal base checker mask + + and r3, r2, r2 // any funky bits set? + cmpeq r2, 0, r0 // + + blbc r0, swppal_fail // return unknown if bad bit set. + br r31, swppal_cont + +// .sbttl "CALL_PAL OPCDECs" + + CALL_PAL_PRIV(0x000B) +CallPal_OpcDec0B: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x000C) +CallPal_OpcDec0C: + br r31, osfpal_calpal_opcdec + +// +// wripir - PALcode for wripir instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// r16 = processor number to interrupt +// +// Function: +// IPIR <- R16 +// Handled in system-specific code +// +// Exit: +// interprocessor interrupt is recorded on the target processor +// and is initiated when the proper enabling conditions are present. +// + + CALL_PAL_PRIV(PAL_WRIPIR_ENTRY) +Call_Pal_Wrpir: + br r31, sys_wripir + +// .sbttl "CALL_PAL OPCDECs" + + CALL_PAL_PRIV(0x000E) +CallPal_OpcDec0E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x000F) +CallPal_OpcDec0F: + br r31, osfpal_calpal_opcdec + +// +// rdmces - PALcode for rdmces instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// R0 <- ZEXT(MCES) +// + + CALL_PAL_PRIV(PAL_RDMCES_ENTRY) +Call_Pal_Rdmces: + mfpr r0, pt_mces // Read from PALtemp + and r0, mces_m_all, r0 // Clear other bits + + hw_rei + +// +// wrmces - PALcode for wrmces instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK) +// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE) +// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE) +// MCES<3> <- R16<3> (DPC) +// MCES<4> <- R16<4> (DSC) +// +// + + CALL_PAL_PRIV(PAL_WRMCES_ENTRY) +Call_Pal_Wrmces: + and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE + mfpr r14, pt_mces // Get current value + + ornot r31, r13, r13 // Flip all the bits + and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17 + + and r14, r13, r1 // Update MCHK, SCE, PCE + bic r1, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r1 // Clear old DPC, DSC + + or r1, r17, r1 // Update DPC and DSC + mtpr r1, pt_mces // Write MCES back + + nop // Pad to fix PT write->read restriction + + nop + hw_rei + + + +// CALL_PAL OPCDECs + + CALL_PAL_PRIV(0x0012) +CallPal_OpcDec12: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0013) +CallPal_OpcDec13: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0014) +CallPal_OpcDec14: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0015) +CallPal_OpcDec15: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0016) +CallPal_OpcDec16: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0017) +CallPal_OpcDec17: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0018) +CallPal_OpcDec18: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0019) +CallPal_OpcDec19: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001A) +CallPal_OpcDec1A: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001B) +CallPal_OpcDec1B: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001C) +CallPal_OpcDec1C: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001D) +CallPal_OpcDec1D: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001E) +CallPal_OpcDec1E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x001F) +CallPal_OpcDec1F: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0020) +CallPal_OpcDec20: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0021) +CallPal_OpcDec21: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0022) +CallPal_OpcDec22: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0023) +CallPal_OpcDec23: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0024) +CallPal_OpcDec24: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0025) +CallPal_OpcDec25: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0026) +CallPal_OpcDec26: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0027) +CallPal_OpcDec27: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0028) +CallPal_OpcDec28: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x0029) +CallPal_OpcDec29: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x002A) +CallPal_OpcDec2A: + br r31, osfpal_calpal_opcdec + +// +// wrfen - PALcode for wrfen instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// a0<0> -> ICSR<FPE> +// Store new FEN in PCB +// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) +// are UNPREDICTABLE +// +// Issue: What about pending FP loads when FEN goes from on->off???? +// + + CALL_PAL_PRIV(PAL_WRFEN_ENTRY) +Call_Pal_Wrfen: + or r31, 1, r13 // Get a one + mfpr r1, ev5__icsr // Get current FPE + + sll r13, icsr_v_fpe, r13 // shift 1 to icsr<fpe> spot, e0 + and r16, 1, r16 // clean new fen + + sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position + bic r1, r13, r1 // zero icsr<fpe> + + or r1, r12, r1 // Or new FEN into ICSR + mfpr r12, pt_pcbb // Get PCBB - E1 + + mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI + stl_p r16, osfpcb_q_fen(r12) // Store FEN in PCB. + + mfpr r31, pt0 // Pad ICSR<FPE> write. + mfpr r31, pt0 + + mfpr r31, pt0 +// pvc_violate 225 // cuz PVC can't distinguish which bits changed + hw_rei + + + CALL_PAL_PRIV(0x002C) +CallPal_OpcDec2C: + br r31, osfpal_calpal_opcdec + +// +// wrvptpr - PALcode for wrvptpr instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// vptptr <- a0 (r16) +// + + CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY) +Call_Pal_Wrvptptr: + mtpr r16, ev5__mvptbr // Load Mbox copy + mtpr r16, ev5__ivptbr // Load Ibox copy + nop // Pad IPR write + nop + hw_rei + + CALL_PAL_PRIV(0x002E) +CallPal_OpcDec2E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_PRIV(0x002F) +CallPal_OpcDec2F: + br r31, osfpal_calpal_opcdec + + +// +// swpctx - PALcode for swpctx instruction +// +// Entry: +// hardware dispatch via callPal instruction +// R16 -> new pcb +// +// Function: +// dynamic state moved to old pcb +// new state loaded from new pcb +// pcbb pointer set +// old pcbb returned in R0 +// +// Note: need to add perf monitor stuff +// + + CALL_PAL_PRIV(PAL_SWPCTX_ENTRY) +Call_Pal_Swpctx: + rpcc r13 // get cyccounter + mfpr r0, pt_pcbb // get pcbb + + ldq_p r22, osfpcb_q_fen(r16) // get new fen/pme + ldq_p r23, osfpcb_l_cc(r16) // get new asn + + srl r13, 32, r25 // move offset + mfpr r24, pt_usp // get usp + + stq_p r30, osfpcb_q_ksp(r0) // store old ksp +// pvc_violate 379 // stq_p can't trap except replay. only problem if mf same ipr in same shadow. + mtpr r16, pt_pcbb // set new pcbb + + stq_p r24, osfpcb_q_usp(r0) // store usp + addl r13, r25, r25 // merge for new time + + stl_p r25, osfpcb_l_cc(r0) // save time + ldah r24, (1<<(icsr_v_fpe-16))(r31) + + and r22, 1, r12 // isolate fen + mfpr r25, icsr // get current icsr + + lda r24, (1<<icsr_v_pmp)(r24) + br r31, swpctx_cont + +// +// wrval - PALcode for wrval instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// sysvalue <- a0 (r16) +// + + CALL_PAL_PRIV(PAL_WRVAL_ENTRY) +Call_Pal_Wrval: + nop + mtpr r16, pt_sysval // Pad paltemp write + nop + nop + hw_rei + +// +// rdval - PALcode for rdval instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- sysvalue +// + + CALL_PAL_PRIV(PAL_RDVAL_ENTRY) +Call_Pal_Rdval: + nop + mfpr r0, pt_sysval + nop + hw_rei + +// +// tbi - PALcode for tbi instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// TB invalidate +// r16/a0 = TBI type +// r17/a1 = Va for TBISx instructions +// + + CALL_PAL_PRIV(PAL_TBI_ENTRY) +Call_Pal_Tbi: + addq r16, 2, r16 // change range to 0-2 + br r23, CALL_PAL_tbi_10_ // get our address + +CALL_PAL_tbi_10_: cmpult r16, 6, r22 // see if in range + lda r23, tbi_tbl-CALL_PAL_tbi_10_(r23) // set base to start of table + sll r16, 4, r16 // * 16 + blbc r22, CALL_PAL_tbi_30_ // go rei, if not + + addq r23, r16, r23 // addr of our code +//orig pvc_jsr tbi + jmp r31, (r23) // and go do it + +CALL_PAL_tbi_30_: + hw_rei + nop + +// +// wrent - PALcode for wrent instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// Update ent* in paltemps +// r16/a0 = Address of entry routine +// r17/a1 = Entry Number 0..5 +// +// r22, r23 trashed +// + + CALL_PAL_PRIV(PAL_WRENT_ENTRY) +Call_Pal_Wrent: + cmpult r17, 6, r22 // see if in range + br r23, CALL_PAL_wrent_10_ // get our address + +CALL_PAL_wrent_10_: bic r16, 3, r16 // clean pc + blbc r22, CALL_PAL_wrent_30_ // go rei, if not in range + + lda r23, wrent_tbl-CALL_PAL_wrent_10_(r23) // set base to start of table + sll r17, 4, r17 // *16 + + addq r17, r23, r23 // Get address in table +//orig pvc_jsr wrent + jmp r31, (r23) // and go do it + +CALL_PAL_wrent_30_: + hw_rei // out of range, just return + +// +// swpipl - PALcode for swpipl instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- PS<IPL> +// PS<IPL> <- a0<2:0> (r16) +// +// t8 (r22) is scratch +// + + CALL_PAL_PRIV(PAL_SWPIPL_ENTRY) +Call_Pal_Swpipl: + and r16, osfps_m_ipl, r16 // clean New ipl + mfpr r22, pt_intmask // get int mask + + extbl r22, r16, r22 // get mask for this ipl + bis r11, r31, r0 // return old ipl + + bis r16, r31, r11 // set new ps + mtpr r22, ev5__ipl // set new mask + + mfpr r31, pt0 // pad ipl write + mfpr r31, pt0 // pad ipl write + + hw_rei // back + +// +// rdps - PALcode for rdps instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- ps +// + + CALL_PAL_PRIV(PAL_RDPS_ENTRY) +Call_Pal_Rdps: + bis r11, r31, r0 // Fetch PALshadow PS + nop // Must be 2 cycles long + hw_rei + +// +// wrkgp - PALcode for wrkgp instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// kgp <- a0 (r16) +// + + CALL_PAL_PRIV(PAL_WRKGP_ENTRY) +Call_Pal_Wrkgp: + nop + mtpr r16, pt_kgp + nop // Pad for pt write->read restriction + nop + hw_rei + +// +// wrusp - PALcode for wrusp instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// usp <- a0 (r16) +// + + CALL_PAL_PRIV(PAL_WRUSP_ENTRY) +Call_Pal_Wrusp: + nop + mtpr r16, pt_usp + nop // Pad possible pt write->read restriction + nop + hw_rei + +// +// wrperfmon - PALcode for wrperfmon instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// +// Function: +// Various control functions for the onchip performance counters +// +// option selector in r16 +// option argument in r17 +// returned status in r0 +// +// +// r16 = 0 Disable performance monitoring for one or more cpu's +// r17 = 0 disable no counters +// r17 = bitmask disable counters specified in bit mask (1=disable) +// +// r16 = 1 Enable performance monitoring for one or more cpu's +// r17 = 0 enable no counters +// r17 = bitmask enable counters specified in bit mask (1=enable) +// +// r16 = 2 Mux select for one or more cpu's +// r17 = Mux selection (cpu specific) +// <24:19> bc_ctl<pm_mux_sel> field (see spec) +// <31>,<7:4>,<3:0> pmctr <sel0>,<sel1>,<sel2> fields (see spec) +// +// r16 = 3 Options +// r17 = (cpu specific) +// <0> = 0 log all processes +// <0> = 1 log only selected processes +// <30,9,8> mode select - ku,kp,kk +// +// r16 = 4 Interrupt frequency select +// r17 = (cpu specific) indicates interrupt frequencies desired for each +// counter, with "zero interrupts" being an option +// frequency info in r17 bits as defined by PMCTR_CTL<FRQx> below +// +// r16 = 5 Read Counters +// r17 = na +// r0 = value (same format as ev5 pmctr) +// <0> = 0 Read failed +// <0> = 1 Read succeeded +// +// r16 = 6 Write Counters +// r17 = value (same format as ev5 pmctr; all counters written simultaneously) +// +// r16 = 7 Enable performance monitoring for one or more cpu's and reset counter to 0 +// r17 = 0 enable no counters +// r17 = bitmask enable & clear counters specified in bit mask (1=enable & clear) +// +//============================================================================= +//Assumptions: +//PMCTR_CTL: +// +// <15:14> CTL0 -- encoded frequency select and enable - CTR0 +// <13:12> CTL1 -- " - CTR1 +// <11:10> CTL2 -- " - CTR2 +// +// <9:8> FRQ0 -- frequency select for CTR0 (no enable info) +// <7:6> FRQ1 -- frequency select for CTR1 +// <5:4> FRQ2 -- frequency select for CTR2 +// +// <0> all vs. select processes (0=all,1=select) +// +// where +// FRQx<1:0> +// 0 1 disable interrupt +// 1 0 frequency = 65536 (16384 for ctr2) +// 1 1 frequency = 256 +// note: FRQx<1:0> = 00 will keep counters from ever being enabled. +// +//============================================================================= +// + CALL_PAL_PRIV(0x0039) +// unsupported in Hudson code .. pboyle Nov/95 +CALL_PAL_Wrperfmon: + // "real" performance monitoring code + cmpeq r16, 1, r0 // check for enable + bne r0, perfmon_en // br if requested to enable + + cmpeq r16, 2, r0 // check for mux ctl + bne r0, perfmon_muxctl // br if request to set mux controls + + cmpeq r16, 3, r0 // check for options + bne r0, perfmon_ctl // br if request to set options + + cmpeq r16, 4, r0 // check for interrupt frequency select + bne r0, perfmon_freq // br if request to change frequency select + + cmpeq r16, 5, r0 // check for counter read request + bne r0, perfmon_rd // br if request to read counters + + cmpeq r16, 6, r0 // check for counter write request + bne r0, perfmon_wr // br if request to write counters + + cmpeq r16, 7, r0 // check for counter clear/enable request + bne r0, perfmon_enclr // br if request to clear/enable counters + + beq r16, perfmon_dis // br if requested to disable (r16=0) + br r31, perfmon_unknown // br if unknown request + +// +// rdusp - PALcode for rdusp instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- usp +// + + CALL_PAL_PRIV(PAL_RDUSP_ENTRY) +Call_Pal_Rdusp: + nop + mfpr r0, pt_usp + hw_rei + + + CALL_PAL_PRIV(0x003B) +CallPal_OpcDec3B: + br r31, osfpal_calpal_opcdec + +// +// whami - PALcode for whami instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- whami +// + CALL_PAL_PRIV(PAL_WHAMI_ENTRY) +Call_Pal_Whami: + nop + mfpr r0, pt_whami // Get Whami + extbl r0, 1, r0 // Isolate just whami bits + hw_rei + +// +// retsys - PALcode for retsys instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// 00(sp) contains return pc +// 08(sp) contains r29 +// +// Function: +// Return from system call. +// mode switched from kern to user. +// stacks swapped, ugp, upc restored. +// r23, r25 junked +// + + CALL_PAL_PRIV(PAL_RETSYS_ENTRY) +Call_Pal_Retsys: + lda r25, osfsf_c_size(sp) // pop stack + bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr + + mfpr r14, exc_addr // save exc_addr in case of fault + ldq r23, osfsf_pc(sp) // get pc + + ldq r29, osfsf_gp(sp) // get gp + stl_c r31, -4(sp) // clear lock_flag + + lda r11, 1<<osfps_v_mode(r31)// new PS:mode=user + mfpr r30, pt_usp // get users stack + + bic r23, 3, r23 // clean return pc + mtpr r31, ev5__ipl // zero ibox IPL - 2 bubbles to hw_rei + + mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles + mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei + + mtpr r23, exc_addr // set return address - 1 bubble to hw_rei + mtpr r25, pt_ksp // save kern stack + + rc r31 // clear inter_flag +// pvc_violate 248 // possible hidden mt->mf pt violation ok in callpal + hw_rei_spe // and back + + + CALL_PAL_PRIV(0x003E) +CallPal_OpcDec3E: + br r31, osfpal_calpal_opcdec + +// +// rti - PALcode for rti instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// 00(sp) -> ps +// 08(sp) -> pc +// 16(sp) -> r29 (gp) +// 24(sp) -> r16 (a0) +// 32(sp) -> r17 (a1) +// 40(sp) -> r18 (a3) +// + + CALL_PAL_PRIV(PAL_RTI_ENTRY) + /* called once by platform_tlaser */ + .globl Call_Pal_Rti +Call_Pal_Rti: + lda r25, osfsf_c_size(sp) // get updated sp + bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr + + mfpr r14, exc_addr // save PC in case of fault + rc r31 // clear intr_flag + + ldq r12, -6*8(r25) // get ps + ldq r13, -5*8(r25) // pc + + ldq r18, -1*8(r25) // a2 + ldq r17, -2*8(r25) // a1 + + ldq r16, -3*8(r25) // a0 + ldq r29, -4*8(r25) // gp + + bic r13, 3, r13 // clean return pc + stl_c r31, -4(r25) // clear lock_flag + + and r12, osfps_m_mode, r11 // get mode + mtpr r13, exc_addr // set return address + + beq r11, rti_to_kern // br if rti to Kern + br r31, rti_to_user // out of call_pal space + + +/////////////////////////////////////////////////// +// Start the Unprivileged CALL_PAL Entry Points +/////////////////////////////////////////////////// + +// +// bpt - PALcode for bpt instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +// +// + .text 1 +// . = 0x3000 + CALL_PAL_UNPRIV(PAL_BPT_ENTRY) +Call_Pal_Bpt: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS for stack write + bge r25, CALL_PAL_bpt_10_ // no stack swap needed if cm=kern + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + +CALL_PAL_bpt_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + mfpr r14, exc_addr // get pc + + stq r16, osfsf_a0(sp) // save regs + bis r31, osf_a0_bpt, r16 // set a0 + + stq r17, osfsf_a1(sp) // a1 + br r31, bpt_bchk_common // out of call_pal space + + +// +// bugchk - PALcode for bugchk instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +// +// + CALL_PAL_UNPRIV(PAL_BUGCHK_ENTRY) +Call_Pal_Bugchk: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS for stack write + bge r25, CALL_PAL_bugchk_10_ // no stack swap needed if cm=kern + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + +CALL_PAL_bugchk_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + mfpr r14, exc_addr // get pc + + stq r16, osfsf_a0(sp) // save regs + bis r31, osf_a0_bugchk, r16 // set a0 + + stq r17, osfsf_a1(sp) // a1 + br r31, bpt_bchk_common // out of call_pal space + + + CALL_PAL_UNPRIV(0x0082) +CallPal_OpcDec82: + br r31, osfpal_calpal_opcdec + +// +// callsys - PALcode for callsys instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// Switch mode to kernel and build a callsys stack frame. +// sp = ksp +// gp = kgp +// t8 - t10 (r22-r24) trashed +// +// +// + CALL_PAL_UNPRIV(PAL_CALLSYS_ENTRY) +Call_Pal_Callsys: + + and r11, osfps_m_mode, r24 // get mode + mfpr r22, pt_ksp // get ksp + + beq r24, sys_from_kern // sysCall from kern is not allowed + mfpr r12, pt_entsys // get address of callSys routine + +// +// from here on we know we are in user going to Kern +// + mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles + mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei + + bis r31, r31, r11 // PS=0 (mode=kern) + mfpr r23, exc_addr // get pc + + mtpr r30, pt_usp // save usp + lda sp, 0-osfsf_c_size(r22)// set new sp + + stq r29, osfsf_gp(sp) // save user gp/r29 + stq r24, osfsf_ps(sp) // save ps + + stq r23, osfsf_pc(sp) // save pc + mtpr r12, exc_addr // set address + // 1 cycle to hw_rei + + mfpr r29, pt_kgp // get the kern gp/r29 + + hw_rei_spe // and off we go! + + + CALL_PAL_UNPRIV(0x0084) +CallPal_OpcDec84: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0085) +CallPal_OpcDec85: + br r31, osfpal_calpal_opcdec + +// +// imb - PALcode for imb instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// Flush the writebuffer and flush the Icache +// +// +// + CALL_PAL_UNPRIV(PAL_IMB_ENTRY) +Call_Pal_Imb: + mb // Clear the writebuffer + mfpr r31, ev5__mcsr // Sync with clear + nop + nop + br r31, pal_ic_flush // Flush Icache + + +// CALL_PAL OPCDECs + + CALL_PAL_UNPRIV(0x0087) +CallPal_OpcDec87: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0088) +CallPal_OpcDec88: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0089) +CallPal_OpcDec89: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x008A) +CallPal_OpcDec8A: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x008B) +CallPal_OpcDec8B: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x008C) +CallPal_OpcDec8C: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x008D) +CallPal_OpcDec8D: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x008E) +CallPal_OpcDec8E: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x008F) +CallPal_OpcDec8F: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0090) +CallPal_OpcDec90: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0091) +CallPal_OpcDec91: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0092) +CallPal_OpcDec92: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0093) +CallPal_OpcDec93: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0094) +CallPal_OpcDec94: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0095) +CallPal_OpcDec95: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0096) +CallPal_OpcDec96: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0097) +CallPal_OpcDec97: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0098) +CallPal_OpcDec98: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x0099) +CallPal_OpcDec99: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x009A) +CallPal_OpcDec9A: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x009B) +CallPal_OpcDec9B: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x009C) +CallPal_OpcDec9C: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x009D) +CallPal_OpcDec9D: + br r31, osfpal_calpal_opcdec + +// +// rdunique - PALcode for rdunique instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// v0 (r0) <- unique +// +// +// + CALL_PAL_UNPRIV(PAL_RDUNIQUE_ENTRY) +CALL_PALrdunique_: + mfpr r0, pt_pcbb // get pcb pointer + ldq_p r0, osfpcb_q_unique(r0) // get new value + + hw_rei + +// +// wrunique - PALcode for wrunique instruction +// +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// unique <- a0 (r16) +// +// +// +CALL_PAL_UNPRIV(PAL_WRUNIQUE_ENTRY) +CALL_PAL_Wrunique: + nop + mfpr r12, pt_pcbb // get pcb pointer + stq_p r16, osfpcb_q_unique(r12)// get new value + nop // Pad palshadow write + hw_rei // back + +// CALL_PAL OPCDECs + + CALL_PAL_UNPRIV(0x00A0) +CallPal_OpcDecA0: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00A1) +CallPal_OpcDecA1: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00A2) +CallPal_OpcDecA2: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00A3) +CallPal_OpcDecA3: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00A4) +CallPal_OpcDecA4: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00A5) +CallPal_OpcDecA5: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00A6) +CallPal_OpcDecA6: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00A7) +CallPal_OpcDecA7: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00A8) +CallPal_OpcDecA8: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00A9) +CallPal_OpcDecA9: + br r31, osfpal_calpal_opcdec + + +// +// gentrap - PALcode for gentrap instruction +// +// CALL_PAL_gentrap: +// Entry: +// Vectored into via hardware PALcode instruction dispatch. +// +// Function: +// Build stack frame +// a0 <- code +// a1 <- unpred +// a2 <- unpred +// vector via entIF +// +// + + CALL_PAL_UNPRIV(0x00AA) +// unsupported in Hudson code .. pboyle Nov/95 +CALL_PAL_gentrap: + sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + bis r11, r31, r12 // Save PS for stack write + bge r25, CALL_PAL_gentrap_10_ // no stack swap needed if cm=kern + + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel - + // no virt ref for next 2 cycles + mtpr r30, pt_usp // save user stack + + bis r31, r31, r11 // Set new PS + mfpr r30, pt_ksp + +CALL_PAL_gentrap_10_: + lda sp, 0-osfsf_c_size(sp)// allocate stack space + mfpr r14, exc_addr // get pc + + stq r16, osfsf_a0(sp) // save regs + bis r31, osf_a0_gentrap, r16// set a0 + + stq r17, osfsf_a1(sp) // a1 + br r31, bpt_bchk_common // out of call_pal space + + +// CALL_PAL OPCDECs + + CALL_PAL_UNPRIV(0x00AB) +CallPal_OpcDecAB: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00AC) +CallPal_OpcDecAC: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00AD) +CallPal_OpcDecAD: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00AE) +CallPal_OpcDecAE: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00AF) +CallPal_OpcDecAF: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B0) +CallPal_OpcDecB0: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B1) +CallPal_OpcDecB1: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B2) +CallPal_OpcDecB2: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B3) +CallPal_OpcDecB3: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B4) +CallPal_OpcDecB4: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B5) +CallPal_OpcDecB5: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B6) +CallPal_OpcDecB6: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B7) +CallPal_OpcDecB7: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B8) +CallPal_OpcDecB8: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00B9) +CallPal_OpcDecB9: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00BA) +CallPal_OpcDecBA: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00BB) +CallPal_OpcDecBB: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00BC) +CallPal_OpcDecBC: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00BD) +CallPal_OpcDecBD: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00BE) +CallPal_OpcDecBE: + br r31, osfpal_calpal_opcdec + + CALL_PAL_UNPRIV(0x00BF) +CallPal_OpcDecBF: + // MODIFIED BY EGH 2/25/04 + br r31, copypal_impl + + +/*======================================================================*/ +/* OSF/1 CALL_PAL CONTINUATION AREA */ +/*======================================================================*/ + + .text 2 + + . = 0x4000 + + +// Continuation of MTPR_PERFMON + ALIGN_BLOCK + // "real" performance monitoring code +// mux ctl +perfmon_muxctl: + lda r8, 1(r31) // get a 1 + sll r8, pmctr_v_sel0, r8 // move to sel0 position + or r8, ((0xf<<pmctr_v_sel1) | (0xf<<pmctr_v_sel2)), r8 // build mux select mask + and r17, r8, r25 // isolate pmctr mux select bits + mfpr r0, ev5__pmctr + bic r0, r8, r0 // clear old mux select bits + or r0,r25, r25 // or in new mux select bits + mtpr r25, ev5__pmctr + + // ok, now tackle cbox mux selects + ldah r14, 0xfff0(r31) + zap r14, 0xE0, r14 // Get Cbox IPR base +//orig get_bc_ctl_shadow r16 // bc_ctl returned in lower longword +// adapted from ev5_pal_macros.mar + mfpr r16, pt_impure + lda r16, CNS_Q_IPR(r16) + RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16); + + lda r8, 0x3F(r31) // build mux select mask + sll r8, bc_ctl_v_pm_mux_sel, r8 + + and r17, r8, r25 // isolate bc_ctl mux select bits + bic r16, r8, r16 // isolate old mux select bits + or r16, r25, r25 // create new bc_ctl + mb // clear out cbox for future ipr write + stq_p r25, ev5__bc_ctl(r14) // store to cbox ipr + mb // clear out cbox for future ipr write + +//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr +// adapted from ev5_pal_macros.mar + mfpr r16, pt_impure + lda r16, CNS_Q_IPR(r16) + SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16); + + br r31, perfmon_success + + +// requested to disable perf monitoring +perfmon_dis: + mfpr r14, ev5__pmctr // read ibox pmctr ipr +perfmon_dis_ctr0: // and begin with ctr0 + blbc r17, perfmon_dis_ctr1 // do not disable ctr0 + lda r8, 3(r31) + sll r8, pmctr_v_ctl0, r8 + bic r14, r8, r14 // disable ctr0 +perfmon_dis_ctr1: + srl r17, 1, r17 + blbc r17, perfmon_dis_ctr2 // do not disable ctr1 + lda r8, 3(r31) + sll r8, pmctr_v_ctl1, r8 + bic r14, r8, r14 // disable ctr1 +perfmon_dis_ctr2: + srl r17, 1, r17 + blbc r17, perfmon_dis_update // do not disable ctr2 + lda r8, 3(r31) + sll r8, pmctr_v_ctl2, r8 + bic r14, r8, r14 // disable ctr2 +perfmon_dis_update: + mtpr r14, ev5__pmctr // update pmctr ipr +//;the following code is not needed for ev5 pass2 and later, but doesn't hurt anything to leave in +// adapted from ev5_pal_macros.mar +//orig get_pmctr_ctl r8, r25 // pmctr_ctl bit in r8. adjusted impure pointer in r25 + mfpr r25, pt_impure + lda r25, CNS_Q_IPR(r25) + RESTORE_SHADOW(r8,CNS_Q_PM_CTL,r25); + + lda r17, 0x3F(r31) // build mask + sll r17, pmctr_v_ctl2, r17 // shift mask to correct position + and r14, r17, r14 // isolate ctl bits + bic r8, r17, r8 // clear out old ctl bits + or r14, r8, r14 // create shadow ctl bits +//orig store_reg1 pmctr_ctl, r14, r25, ipr=1 // update pmctr_ctl register +//adjusted impure pointer still in r25 + SAVE_SHADOW(r14,CNS_Q_PM_CTL,r25); + + br r31, perfmon_success + + +// requested to enable perf monitoring +//;the following code can be greatly simplified for pass2, but should work fine as is. + + +perfmon_enclr: + lda r9, 1(r31) // set enclr flag + br perfmon_en_cont + +perfmon_en: + bis r31, r31, r9 // clear enclr flag + +perfmon_en_cont: + mfpr r8, pt_pcbb // get PCB base +//orig get_pmctr_ctl r25, r25 + mfpr r25, pt_impure + lda r25, CNS_Q_IPR(r25) + RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r25); + + ldq_p r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword + mfpr r14, ev5__pmctr // read ibox pmctr ipr + srl r16, osfpcb_v_pme, r16 // get pme bit + mfpr r13, icsr + and r16, 1, r16 // isolate pme bit + + // this code only needed in pass2 and later + lda r12, 1<<icsr_v_pmp(r31) // pb + bic r13, r12, r13 // clear pmp bit + sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position + or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear + mtpr r13, icsr // update icsr + + bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable) + + sll r25, 6, r25 // shift frequency bits into pmctr_v_ctl positions + bis r14, r31, r13 // copy pmctr + +perfmon_en_ctr0: // and begin with ctr0 + blbc r17, perfmon_en_ctr1 // do not enable ctr0 + + blbc r9, perfmon_en_noclr0 // enclr flag set, clear ctr0 field + lda r8, 0xffff(r31) + zapnot r8, 3, r8 // ctr0<15:0> mask + sll r8, pmctr_v_ctr0, r8 + bic r14, r8, r14 // clear ctr bits + bic r13, r8, r13 // clear ctr bits + +perfmon_en_noclr0: +//orig get_addr r8, 3<<pmctr_v_ctl0, r31 + LDLI(r8, (3<<pmctr_v_ctl0)) + and r25, r8, r12 //isolate frequency select bits for ctr0 + bic r14, r8, r14 // clear ctl0 bits in preparation for enabling + or r14,r12,r14 // or in new ctl0 bits + +perfmon_en_ctr1: // enable ctr1 + srl r17, 1, r17 // get ctr1 enable + blbc r17, perfmon_en_ctr2 // do not enable ctr1 + + blbc r9, perfmon_en_noclr1 // if enclr flag set, clear ctr1 field + lda r8, 0xffff(r31) + zapnot r8, 3, r8 // ctr1<15:0> mask + sll r8, pmctr_v_ctr1, r8 + bic r14, r8, r14 // clear ctr bits + bic r13, r8, r13 // clear ctr bits + +perfmon_en_noclr1: +//orig get_addr r8, 3<<pmctr_v_ctl1, r31 + LDLI(r8, (3<<pmctr_v_ctl1)) + and r25, r8, r12 //isolate frequency select bits for ctr1 + bic r14, r8, r14 // clear ctl1 bits in preparation for enabling + or r14,r12,r14 // or in new ctl1 bits + +perfmon_en_ctr2: // enable ctr2 + srl r17, 1, r17 // get ctr2 enable + blbc r17, perfmon_en_return // do not enable ctr2 - return + + blbc r9, perfmon_en_noclr2 // if enclr flag set, clear ctr2 field + lda r8, 0x3FFF(r31) // ctr2<13:0> mask + sll r8, pmctr_v_ctr2, r8 + bic r14, r8, r14 // clear ctr bits + bic r13, r8, r13 // clear ctr bits + +perfmon_en_noclr2: +//orig get_addr r8, 3<<pmctr_v_ctl2, r31 + LDLI(r8, (3<<pmctr_v_ctl2)) + and r25, r8, r12 //isolate frequency select bits for ctr2 + bic r14, r8, r14 // clear ctl2 bits in preparation for enabling + or r14,r12,r14 // or in new ctl2 bits + +perfmon_en_return: + cmovlbs r16, r14, r13 // if pme enabled, move enables into pmctr + // else only do the counter clears + mtpr r13, ev5__pmctr // update pmctr ipr + +//;this code not needed for pass2 and later, but does not hurt to leave it in + lda r8, 0x3F(r31) +//orig get_pmctr_ctl r25, r12 // read pmctr ctl; r12=adjusted impure pointer + mfpr r12, pt_impure + lda r12, CNS_Q_IPR(r12) + RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r12); + + sll r8, pmctr_v_ctl2, r8 // build ctl mask + and r8, r14, r14 // isolate new ctl bits + bic r25, r8, r25 // clear out old ctl value + or r25, r14, r14 // create new pmctr_ctl +//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 + SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr + + br r31, perfmon_success + + +// options... +perfmon_ctl: + +// set mode +//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer + mfpr r12, pt_impure + lda r12, CNS_Q_IPR(r12) + RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); + + // build mode mask for pmctr register + LDLI(r8, ((1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk))) + mfpr r0, ev5__pmctr + and r17, r8, r25 // isolate pmctr mode bits + bic r0, r8, r0 // clear old mode bits + or r0, r25, r25 // or in new mode bits + mtpr r25, ev5__pmctr + + // the following code will only be used in pass2, but should + // not hurt anything if run in pass1. + mfpr r8, icsr + lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0 + bic r8, r25, r8 // clear old pma bit + cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1 + or r8, r25, r8 + mtpr r8, icsr // 4 bubbles to hw_rei + mfpr r31, pt0 // pad icsr write + mfpr r31, pt0 // pad icsr write + + // the following code not needed for pass2 and later, but + // should work anyway. + bis r14, 1, r14 // set for select processes + blbs r17, perfmon_sp // branch if select processes + bic r14, 1, r14 // all processes +perfmon_sp: +//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register + SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr + br r31, perfmon_success + +// counter frequency select +perfmon_freq: +//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer + mfpr r12, pt_impure + lda r12, CNS_Q_IPR(r12) + RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12); + + lda r8, 0x3F(r31) +//orig sll r8, pmctr_ctl_v_frq2, r8 // build mask for frequency select field +// I guess this should be a shift of 4 bits from the above control register structure +#define pmctr_ctl_v_frq2_SHIFT 4 + sll r8, pmctr_ctl_v_frq2_SHIFT, r8 // build mask for frequency select field + + and r8, r17, r17 + bic r14, r8, r14 // clear out old frequency select bits + + or r17, r14, r14 // or in new frequency select info +//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register + SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr + + br r31, perfmon_success + +// read counters +perfmon_rd: + mfpr r0, ev5__pmctr + or r0, 1, r0 // or in return status + hw_rei // back to user + +// write counters +perfmon_wr: + mfpr r14, ev5__pmctr + lda r8, 0x3FFF(r31) // ctr2<13:0> mask + sll r8, pmctr_v_ctr2, r8 + + LDLI(r9, (0xFFFFFFFF)) // ctr2<15:0>,ctr1<15:0> mask + sll r9, pmctr_v_ctr1, r9 + or r8, r9, r8 // or ctr2, ctr1, ctr0 mask + bic r14, r8, r14 // clear ctr fields + and r17, r8, r25 // clear all but ctr fields + or r25, r14, r14 // write ctr fields + mtpr r14, ev5__pmctr // update pmctr ipr + + mfpr r31, pt0 // pad pmctr write (needed only to keep PVC happy) + +perfmon_success: + or r31, 1, r0 // set success + hw_rei // back to user + +perfmon_unknown: + or r31, r31, r0 // set fail + hw_rei // back to user + + +////////////////////////////////////////////////////////// +// Copy code +////////////////////////////////////////////////////////// + +copypal_impl: + mov r16, r0 +#ifdef CACHE_COPY +#ifndef CACHE_COPY_UNALIGNED + and r16, 63, r8 + and r17, 63, r9 + bis r8, r9, r8 + bne r8, cache_copy_done +#endif + bic r18, 63, r8 + and r18, 63, r18 + beq r8, cache_copy_done +cache_loop: + ldf f17, 0(r16) + stf f17, 0(r16) + addq r17, 64, r17 + addq r16, 64, r16 + subq r8, 64, r8 + bne r8, cache_loop +cache_copy_done: +#endif + ble r18, finished // if len <=0 we are finished + ldq_u r8, 0(r17) + xor r17, r16, r9 + and r9, 7, r9 + and r16, 7, r10 + bne r9, unaligned + beq r10, aligned + ldq_u r9, 0(r16) + addq r18, r10, r18 + mskqh r8, r17, r8 + mskql r9, r17, r9 + bis r8, r9, r8 +aligned: + subq r18, 1, r10 + bic r10, 7, r10 + and r18, 7, r18 + beq r10, aligned_done +loop: + stq_u r8, 0(r16) + ldq_u r8, 8(r17) + subq r10, 8, r10 + lda r16,8(r16) + lda r17,8(r17) + bne r10, loop +aligned_done: + bne r18, few_left + stq_u r8, 0(r16) + br r31, finished + few_left: + mskql r8, r18, r10 + ldq_u r9, 0(r16) + mskqh r9, r18, r9 + bis r10, r9, r10 + stq_u r10, 0(r16) + br r31, finished +unaligned: + addq r17, r18, r25 + cmpule r18, 8, r9 + bne r9, unaligned_few_left + beq r10, unaligned_dest_aligned + and r16, 7, r10 + subq r31, r10, r10 + addq r10, 8, r10 + ldq_u r9, 7(r17) + extql r8, r17, r8 + extqh r9, r17, r9 + bis r8, r9, r12 + insql r12, r16, r12 + ldq_u r13, 0(r16) + mskql r13, r16, r13 + bis r12, r13, r12 + stq_u r12, 0(r16) + addq r16, r10, r16 + addq r17, r10, r17 + subq r18, r10, r18 + ldq_u r8, 0(r17) +unaligned_dest_aligned: + subq r18, 1, r10 + bic r10, 7, r10 + and r18, 7, r18 + beq r10, unaligned_partial_left +unaligned_loop: + ldq_u r9, 7(r17) + lda r17, 8(r17) + extql r8, r17, r12 + extqh r9, r17, r13 + subq r10, 8, r10 + bis r12, r13, r13 + stq r13, 0(r16) + lda r16, 8(r16) + beq r10, unaligned_second_partial_left + ldq_u r8, 7(r17) + lda r17, 8(r17) + extql r9, r17, r12 + extqh r8, r17, r13 + bis r12, r13, r13 + subq r10, 8, r10 + stq r13, 0(r16) + lda r16, 8(r16) + bne r10, unaligned_loop +unaligned_partial_left: + mov r8, r9 +unaligned_second_partial_left: + ldq_u r8, -1(r25) + extql r9, r17, r9 + extqh r8, r17, r8 + bis r8, r9, r8 + bne r18, few_left + stq_u r8, 0(r16) + br r31, finished +unaligned_few_left: + ldq_u r9, -1(r25) + extql r8, r17, r8 + extqh r9, r17, r9 + bis r8, r9, r8 + insqh r8, r16, r9 + insql r8, r16, r8 + lda r12, -1(r31) + mskql r12, r18, r13 + cmovne r13, r13, r12 + insqh r12, r16, r13 + insql r12, r16, r12 + addq r16, r18, r10 + ldq_u r14, 0(r16) + ldq_u r25, -1(r10) + bic r14, r12, r14 + bic r25, r13, r25 + and r8, r12, r8 + and r9, r13, r9 + bis r8, r14, r8 + bis r9, r25, r9 + stq_u r9, -1(r10) + stq_u r8, 0(r16) +finished: + hw_rei diff --git a/system/alpha/palcode/platform.S b/system/alpha/palcode/platform.S new file mode 100644 index 000000000..da3f466c1 --- /dev/null +++ b/system/alpha/palcode/platform.S @@ -0,0 +1,2337 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * Copyright (c) 1993 Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali G. Saidi + * Nathan L. Binkert + */ + +#define max_cpuid 1 +#define hw_rei_spe hw_rei + +#include "ev5_defs.h" +#include "ev5_impure.h" +#include "ev5_alpha_defs.h" +#include "ev5_paldef.h" +#include "ev5_osfalpha_defs.h" +#include "fromHudsonMacros.h" +#include "fromHudsonOsf.h" +#include "dc21164FromGasSources.h" +#include "cserve.h" +#include "tlaser.h" + +#define pt_entInt pt_entint +#define pt_entArith pt_entarith +#define mchk_size ((mchk_cpu_base + 7 + 8) &0xfff8) +#define mchk_flag CNS_Q_FLAG +#define mchk_sys_base 56 +#define mchk_cpu_base (CNS_Q_LD_LOCK + 8) +#define mchk_offsets CNS_Q_EXC_ADDR +#define mchk_mchk_code 8 +#define mchk_ic_perr_stat CNS_Q_ICPERR_STAT +#define mchk_dc_perr_stat CNS_Q_DCPERR_STAT +#define mchk_sc_addr CNS_Q_SC_ADDR +#define mchk_sc_stat CNS_Q_SC_STAT +#define mchk_ei_addr CNS_Q_EI_ADDR +#define mchk_bc_tag_addr CNS_Q_BC_TAG_ADDR +#define mchk_fill_syn CNS_Q_FILL_SYN +#define mchk_ei_stat CNS_Q_EI_STAT +#define mchk_exc_addr CNS_Q_EXC_ADDR +#define mchk_ld_lock CNS_Q_LD_LOCK +#define osfpcb_q_Ksp pcb_q_ksp +#define pal_impure_common_size ((0x200 + 7) & 0xfff8) + +#if defined(BIG_TSUNAMI) +#define MAXPROC 0x3f +#define IPIQ_addr 0x800 +#define IPIQ_shift 0 +#define IPIR_addr 0x840 +#define IPIR_shift 0 +#define RTC_addr 0x880 +#define RTC_shift 0 +#define DIR_addr 0xa2 +#elif defined(TSUNAMI) +#define MAXPROC 0x3 +#define IPIQ_addr 0x080 +#define IPIQ_shift 12 +#define IPIR_addr 0x080 +#define IPIR_shift 8 +#define RTC_addr 0x080 +#define RTC_shift 4 +#define DIR_addr 0xa0 +#elif defined(TLASER) +#define MAXPROC 0xf +#else +#error Must define BIG_TSUNAMI, TSUNAMI, or TLASER +#endif + +#define ALIGN_BLOCK \ + .align 5 + +#define ALIGN_BRANCH \ + .align 3 + +#define EXPORT(_x) \ + .align 5; \ + .globl _x; \ +_x: + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// XXX the following is 'made up' +// XXX bugnion + +// XXX bugnion not sure how to align 'quad' +#define ALIGN_QUAD \ + .align 3 + +#define ALIGN_128 \ + .align 7 + + +#define GET_IMPURE(_r) mfpr _r,pt_impure +#define GET_ADDR(_r1,_off,_r2) lda _r1,_off(_r2) + + +#define BIT(_x) (1<<(_x)) + + +// System specific code - beh model version +// +// +// Entry points +// SYS_CFLUSH - Cache flush +// SYS_CSERVE - Console service +// SYS_WRIPIR - interprocessor interrupts +// SYS_HALT_INTERRUPT - Halt interrupt +// SYS_PASSIVE_RELEASE - Interrupt, passive release +// SYS_INTERRUPT - Interrupt +// SYS_RESET - Reset +// SYS_ENTER_CONSOLE +// +// +// Macro to read TLINTRSUMx +// +// Based on the CPU_NUMBER, read either the TLINTRSUM0 or TLINTRSUM1 register +// +// Assumed register usage: +// rsum TLINTRSUMx contents +// raddr node space address +// scratch scratch register +// +#define Read_TLINTRSUMx(_rsum, _raddr, _scratch) \ + nop; \ + mfpr _scratch, pt_whami; /* Get our whami (VID) */ \ + extbl _scratch, 1, _scratch; /* shift down to bit 0 */ \ + lda _raddr, 0xff88(zero); /* Get base node space address bits */ \ + sll _raddr, 24, _raddr; /* Shift up to proper position */ \ + srl _scratch, 1, _rsum; /* Shift off the cpu number */ \ + sll _rsum, 22, _rsum; /* Get our node offset */ \ + addq _raddr, _rsum, _raddr; /* Get our base node space address */ \ + blbs _scratch, 1f; \ + lda _raddr, 0x1180(_raddr); \ + br r31, 2f; \ +1: lda _raddr, 0x11c0(_raddr); \ +2: ldl_p _rsum, 0(_raddr) /* read the right tlintrsum reg */ + +// +// Macro to write TLINTRSUMx +// +// Based on the CPU_NUMBER, write either the TLINTRSUM0 or TLINTRSUM1 register +// +// Assumed register usage: +// rsum TLINTRSUMx write data +// raddr node space address +// scratch scratch register +// +#define Write_TLINTRSUMx(_rsum,_raddr,_whami) \ + nop; \ + mfpr _whami, pt_whami; /* Get our whami (VID) */ \ + extbl _whami, 1, _whami; /* shift down to bit 0 */ \ + lda _raddr, 0xff88(zero); /* Get base node space address bits */ \ + sll _raddr, 24, _raddr; /* Shift up to proper position */ \ + blbs _whami, 1f; \ + lda _raddr, 0x1180(_raddr); \ + br zero, 2f; \ +1: lda _raddr, 0x11c0(_raddr); \ +2: srl _whami, 1, _whami; /* Get our node offset */ \ + addq _raddr, _whami, _raddr; /* Get our base node space address */ \ + mb; \ + stq_p _rsum, 0(_raddr); /* write the right tlintrsum reg */ \ + ldq_p _rsum, 0(_raddr); /* dummy read to tlintrsum */ \ + bis _rsum, _rsum, _rsum /* needed to complete the ldqp above */ + + +// +// Macro to determine highest priority TIOP Node ID from interrupt pending mask +// +// Assumed register usage: +// rmask - TLINTRSUMx contents, shifted to isolate IOx bits +// rid - TLSB Node ID of highest TIOP +// +#define Intr_Find_TIOP(_rmask,_rid) \ + srl _rmask,3,_rid; /* check IOP8 */ \ + blbc _rid,1f; /* not IOP8 */ \ + lda _rid,8(zero); /* IOP8 */ \ + br zero,6f; \ +1: srl _rmask,3,_rid; /* check IOP7 */ \ + blbc _rid, 2f; /* not IOP7 */ \ + lda _rid, 7(r31); /* IOP7 */ \ + br r31, 6f; \ +2: srl _rmask, 2, _rid; /* check IOP6 */ \ + blbc _rid, 3f; /* not IOP6 */ \ + lda _rid, 6(r31); /* IOP6 */ \ + br r31, 6f; \ +3: srl _rmask, 1, _rid; /* check IOP5 */ \ + blbc _rid, 4f; /* not IOP5 */ \ + lda _rid, 5(r31); /* IOP5 */ \ + br r31, 6f; \ +4: srl _rmask, 0, _rid; /* check IOP4 */ \ + blbc _rid, 5f; /* not IOP4 */ \ + lda r14, 4(r31); /* IOP4 */ \ + br r31, 6f; \ +5: lda r14, 0(r31); /* passive release */ \ +6: + +// +// Macro to calculate base node space address for given node id +// +// Assumed register usage: +// rid - TLSB node id +// raddr - base node space address +#define Get_TLSB_Node_Address(_rid,_raddr) \ + sll _rid, 22, _rid; \ + lda _raddr, 0xff88(zero); \ + sll _raddr, 24, _raddr; \ + addq _raddr, _rid, _raddr + + +#define OSFmchk_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ + lda _rs1, tlep_##_tlepreg(zero); \ + or _rs1, _nodebase, _rs1; \ + ldl_p _rs1, 0(_rs1); \ + stl_p _rs, mchk_##_tlepreg(_rlog) /* store in frame */ + +#define OSFmchk_TLEPstore(_tlepreg) \ + OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg) + +#define OSFcrd_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ + lda _rs1, tlep_##_tlepreg(zero); \ + or _rs1, _nodebase, _rs1; \ + ldl_p _rs1, 0(_rs1); \ + stl_p _rs, mchk_crd_##_tlepreg(_rlog) + +#define OSFcrd_TLEPstore_tlsb_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ + lda _rs1, tlsb_##_tlepreg(zero); \ + or _rs1, _nodebase, _rs1; \ + ldl_p _rs1, 0(_rs1); \ + stl_p _rs,mchk_crd_##_tlepreg(_rlog) + +#define OSFcrd_TLEPstore_tlsb_clr_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \ + lda _rs1,tlsb_##_tlepreg(zero); \ + or _rs1, _nodebase,_rs1; \ + ldl_p _rs1, 0(_rs1); \ + stl_p _rs, mchk_crd_##_tlepreg(_rlog); \ + stl_p _rs, 0(_rs1) + +#define OSFcrd_TLEPstore(_tlepreg) \ + OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg) +#define OSFcrd_TLEPstore_tlsb(_tlepreg) \ + OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg) +#define OSFcrd_TLEPstore_tlsb_clr(_tlepreg) \ + OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg) + + +#define save_pcia_intr(_irq) \ + and r13, 0xf, r25; /* isolate low 4 bits */ \ + addq r14, 4, r14; /* format the TIOP Node id field */ \ + sll r14, 4, r14; /* shift the TIOP Node id */ \ + or r14, r25, r10; /* merge Node id/hose/HPC */ \ + mfpr r14, pt14; /* get saved value */ \ + extbl r14, _irq, r25; /* confirm none outstanding */ \ + bne r25, sys_machine_check_while_in_pal; \ + insbl r10, _irq, r10; /* align new info */ \ + or r14, r10, r14; /* merge info */ \ + mtpr r14, pt14; /* save it */ \ + bic r13, 0xf, r13 /* clear low 4 bits of vector */ + + +// wripir - PALcode for wripir instruction +// R16 has the processor number. +// + ALIGN_BLOCK +EXPORT(sys_wripir) + // + // Convert the processor number to a CPU mask + // + and r16, MAXPROC, r14 // mask the top stuff: MAXPROC+1 CPUs supported + bis r31, 0x1, r16 // get a one + sll r16, r14, r14 // shift the bit to the right place +#if defined(TSUNAMI) || defined(BIG_TSUNAMI) + sll r14,IPIQ_shift,r14 +#endif + + + // + // Build the Broadcast Space base address + // +#if defined(TSUNAMI) || defined(BIG_TSUNAMI) + lda r16,0xf01(r31) + sll r16,32,r16 + ldah r13,0xa0(r31) + sll r13,8,r13 + bis r16,r13,r16 + lda r16,IPIQ_addr(r16) +#elif defined(TLASER) + lda r13, 0xff8e(r31) // Load the upper address bits + sll r13, 24, r13 // shift them to the top +#endif + + // + // Send out the IP Intr + // +#if defined(TSUNAMI) || defined(BIG_TSUNAMI) + stq_p r14, 0(r16) // Tsunami MISC Register +#elif defined(TLASER) + stq_p r14, 0x40(r13) // Write to TLIPINTR reg +#endif + wmb // Push out the store + hw_rei + + +// cflush - PALcode for CFLUSH instruction +// +// SYS_CFLUSH +// Entry: +// R16 - contains the PFN of the page to be flushed +// +// Function: +// Flush all Dstream caches of 1 entire page +// +// + ALIGN_BLOCK +EXPORT(sys_cflush) + +// #convert pfn to addr, and clean off <63:20> +// #sll r16, <page_offset_size_bits>+<63-20>>, r12 + sll r16, page_offset_size_bits+(63-20),r12 + +// #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16> +// # stolen from srcmax code. XXX bugnion + lda r13, 0x10(r31) // assume 16Mbytes of cache + sll r13, 20, r13 // convert to bytes + + + srl r12, 63-20, r12 // shift back to normal position + xor r12, r13, r12 // xor addr<18> + + or r31, 8192/(32*8), r13 // get count of loads + nop + +cflush_loop: + subq r13, 1, r13 // decr counter + mfpr r25, ev5__intid // Fetch level of interruptor + + ldq_p r31, 32*0(r12) // do a load + ldq_p r31, 32*1(r12) // do next load + + ldq_p r31, 32*2(r12) // do next load + ldq_p r31, 32*3(r12) // do next load + + ldq_p r31, 32*4(r12) // do next load + ldq_p r31, 32*5(r12) // do next load + + ldq_p r31, 32*6(r12) // do next load + ldq_p r31, 32*7(r12) // do next load + + mfpr r14, ev5__ipl // Fetch current level + lda r12, (32*8)(r12) // skip to next cache block addr + + cmple r25, r14, r25 // R25 = 1 if intid .less than or eql ipl + beq r25, 1f // if any int's pending, re-queue CFLUSH -- need to check for hlt interrupt??? + + bne r13, cflush_loop // loop till done + hw_rei // back to user + + ALIGN_BRANCH +1: // Here if interrupted + mfpr r12, exc_addr + subq r12, 4, r12 // Backup PC to point to CFLUSH + + mtpr r12, exc_addr + nop + + mfpr r31, pt0 // Pad exc_addr write + hw_rei + + + ALIGN_BLOCK +// +// sys_cserve - PALcode for CSERVE instruction +// +// Function: +// Various functions for private use of console software +// +// option selector in r0 +// arguments in r16.... +// +// +// r0 = 0 unknown +// +// r0 = 1 ldq_p +// r0 = 2 stq_p +// args, are as for normal STQ_P/LDQ_P in VMS PAL +// +// r0 = 3 dump_tb's +// r16 = detination PA to dump tb's to. +// +// r0<0> = 1, success +// r0<0> = 0, failure, or option not supported +// r0<63:1> = (generally 0, but may be function dependent) +// r0 - load data on ldq_p +// +// +EXPORT(sys_cserve) + + /* taken from scrmax */ + cmpeq r18, CSERVE_K_RD_IMPURE, r0 + bne r0, Sys_Cserve_Rd_Impure + + cmpeq r18, CSERVE_K_JTOPAL, r0 + bne r0, Sys_Cserve_Jtopal + call_pal 0 + + or r31, r31, r0 + hw_rei // and back we go + +Sys_Cserve_Rd_Impure: + mfpr r0, pt_impure // Get base of impure scratch area. + hw_rei + + ALIGN_BRANCH + +Sys_Cserve_Jtopal: + bic a0, 3, t8 // Clear out low 2 bits of address + bis t8, 1, t8 // Or in PAL mode bit + mtpr t8,exc_addr + hw_rei + + // ldq_p + ALIGN_QUAD +1: + ldq_p r0,0(r17) // get the data + nop // pad palshadow write + + hw_rei // and back we go + + + // stq_p + ALIGN_QUAD +2: + stq_p r18, 0(r17) // store the data + lda r0,17(r31) // bogus + hw_rei // and back we go + + + ALIGN_QUAD +csrv_callback: + ldq r16, 0(r17) // restore r16 + ldq r17, 8(r17) // restore r17 + lda r0, hlt_c_callback(r31) + br r31, sys_enter_console + + +csrv_identify: + mfpr r0, pal_base + ldq_p r0, 8(r0) + hw_rei + + +// dump tb's + ALIGN_QUAD +0: + // DTB PTEs - 64 entries + addq r31, 64, r0 // initialize loop counter + nop + +1: mfpr r12, ev5__dtb_pte_temp // read out next pte to temp + mfpr r12, ev5__dtb_pte // read out next pte to reg file + + subq r0, 1, r0 // decrement loop counter + nop // Pad - no Mbox instr in cycle after mfpr + + stq_p r12, 0(r16) // store out PTE + addq r16, 8 ,r16 // increment pointer + + bne r0, 1b + + ALIGN_BRANCH + // ITB PTEs - 48 entries + addq r31, 48, r0 // initialize loop counter + nop + +2: mfpr r12, ev5__itb_pte_temp // read out next pte to temp + mfpr r12, ev5__itb_pte // read out next pte to reg file + + subq r0, 1, r0 // decrement loop counter + nop // + + stq_p r12, 0(r16) // store out PTE + addq r16, 8 ,r16 // increment pointer + + bne r0, 2b + or r31, 1, r0 // set success + + hw_rei // and back we go + + +// +// SYS_INTERRUPT - Interrupt processing code +// +// Current state: +// Stack is pushed +// ps, sp and gp are updated +// r12, r14 - available +// r13 - INTID (new EV5 IPL) +// r25 - ISR +// r16, r17, r18 - available +// +// +EXPORT(sys_interrupt) + cmpeq r13, 31, r12 // Check for level 31 interrupt + bne r12, sys_int_mchk_or_crd // machine check or crd + + cmpeq r13, 30, r12 // Check for level 30 interrupt + bne r12, sys_int_powerfail // powerfail + + cmpeq r13, 29, r12 // Check for level 29 interrupt + bne r12, sys_int_perf_cnt // performance counters + + cmpeq r13, 23, r12 // Check for level 23 interrupt + bne r12, sys_int_23 // IPI in Tsunami + + cmpeq r13, 22, r12 // Check for level 22 interrupt + bne r12, sys_int_22 // timer interrupt + + cmpeq r13, 21, r12 // Check for level 21 interrupt + bne r12, sys_int_21 // I/O + + cmpeq r13, 20, r12 // Check for level 20 interrupt + bne r12, sys_int_20 // system error interrupt + // (might be corrected) + + mfpr r14, exc_addr // ooops, something is wrong + br r31, pal_pal_bug_check_from_int + + +// +//sys_int_2* +// Routines to handle device interrupts at IPL 23-20. +// System specific method to ack/clear the interrupt, detect passive +// release, detect interprocessor (22), interval clock (22), corrected +// system error (20) +// +// Current state: +// Stack is pushed +// ps, sp and gp are updated +// r12, r14 - available +// r13 - INTID (new EV5 IPL) +// r25 - ISR +// +// On exit: +// Interrupt has been ack'd/cleared +// a0/r16 - signals IO device interrupt +// a1/r17 - contains interrupt vector +// exit to ent_int address +// +// + +#if defined(TSUNAMI) || defined(BIG_TSUNAMI) + ALIGN_BRANCH +sys_int_23: + or r31,0,r16 // IPI interrupt A0 = 0 + lda r12,0xf01(r31) // build up an address for the MISC register + sll r12,16,r12 + lda r12,0xa000(r12) + sll r12,16,r12 + lda r12,IPIR_addr(r12) + + mfpr r10, pt_whami // get CPU ID + extbl r10, 1, r10 // Isolate just whami bits + or r31,0x1,r14 // load r14 with bit to clear + sll r14,r10,r14 // left shift by CPU ID + sll r14,IPIR_shift,r14 + stq_p r14, 0(r12) // clear the ipi interrupt + + br r31, pal_post_interrupt // Notify the OS + + + ALIGN_BRANCH +sys_int_22: + or r31,1,r16 // a0 means it is a clock interrupt + lda r12,0xf01(r31) // build up an address for the MISC register + sll r12,16,r12 + lda r12,0xa000(r12) + sll r12,16,r12 + lda r12,RTC_addr(r12) + + mfpr r10, pt_whami // get CPU ID + extbl r10, 1, r10 // Isolate just whami bits + or r31,0x1,r14 // load r14 with bit to clear + sll r14,r10,r14 // left shift by CPU ID + sll r14,RTC_shift,r14 // put the bits in the right position + stq_p r14, 0(r12) // clear the rtc interrupt + + br r31, pal_post_interrupt // Tell the OS + + + ALIGN_BRANCH +sys_int_20: + Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx + srl r13, 12, r13 // shift down to examine IPL15 + + Intr_Find_TIOP(r13,r14) + beq r14, 1f + + Get_TLSB_Node_Address(r14,r10) + lda r10, 0xa40(r10) // Get base TLILID address + + ldl_p r13, 0(r10) // Read the TLILID register + bne r13, pal_post_dev_interrupt + beq r13, 1f + + and r13, 0x3, r10 // check for PCIA bits + beq r10, pal_post_dev_interrupt // done if nothing set + save_pcia_intr(1) + br r31, pal_post_dev_interrupt // + +1: lda r16, osfint_c_passrel(r31) // passive release + br r31, pal_post_interrupt // + + + ALIGN_BRANCH +sys_int_21: + + lda r12,0xf01(r31) // calculate DIRn address + sll r12,32,r12 + ldah r13,DIR_addr(r31) + sll r13,8,r13 + bis r12,r13,r12 + + mfpr r13, pt_whami // get CPU ID + extbl r13, 1, r13 // Isolate just whami bits + +#ifdef BIG_TSUNAMI + sll r13,4,r13 + or r12,r13,r12 +#else + lda r12,0x0080(r12) + and r13,0x1,r14 // grab LSB and shift left 6 + sll r14,6,r14 + and r13,0x2,r10 // grabl LSB+1 and shift left 9 + sll r10,9,r10 + + mskbl r12,0,r12 // calculate DIRn address + lda r13,0x280(r31) + bis r12,r13,r12 + or r12,r14,r12 + or r12,r10,r12 +#endif + + ldq_p r13, 0(r12) // read DIRn + + or r31,1,r14 // set bit 55 (ISA Interrupt) + sll r14,55,r14 + + and r13, r14, r14 // check if bit 55 is set + lda r16,0x900(r31) // load offset for normal into r13 + beq r14, normal_int // if not compute the vector normally + + lda r16,0x800(r31) // replace with offset for pic + lda r12,0xf01(r31) // build an addr to access PIC + sll r12,32,r12 // at f01fc000000 + ldah r13,0xfc(r31) + sll r13,8,r13 + bis r12,r13,r12 + ldq_p r13,0x0020(r12) // read PIC1 ISR for interrupting dev + +normal_int: + //ctlz r13,r14 // count the number of leading zeros + // EV5 doesn't have ctlz, but we do, so lets use it + .byte 0x4e + .byte 0x06 + .byte 0xed + .byte 0x73 + lda r10,63(r31) + subq r10,r14,r17 // subtract from + + lda r13,0x10(r31) + mulq r17,r13,r17 // compute 0x900 + (0x10 * Highest DIRn-bit) + addq r17,r16,r17 + + or r31,3,r16 // a0 means it is a I/O interrupt + + br r31, pal_post_interrupt + +#elif defined(TLASER) + ALIGN_BRANCH +sys_int_23: + Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx + srl r13, 22, r13 // shift down to examine IPL17 + + Intr_Find_TIOP(r13,r14) + beq r14, 1f + + Get_TLSB_Node_Address(r14,r10) + lda r10, 0xac0(r10) // Get base TLILID address + + ldl_p r13, 0(r10) // Read the TLILID register + bne r13, pal_post_dev_interrupt + +1: lda r16, osfint_c_passrel(r31) // passive release + br r31, pal_post_interrupt // + + + ALIGN_BRANCH +sys_int_22: + Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx + srl r13, 6, r14 // check the Intim bit + + blbs r14, tlep_intim // go service Intim + srl r13, 5, r14 // check the IP Int bit + + blbs r14, tlep_ipint // go service IP Int + srl r13, 17, r13 // shift down to examine IPL16 + + Intr_Find_TIOP(r13,r14) + beq r14, 1f + + Get_TLSB_Node_Address(r14,r10) + lda r10, 0xa80(r10) // Get base TLILID address + + ldl_p r13, 0(r10) // Read the TLILID register + bne r13, pal_post_dev_interrupt + beq r13, 1f + + and r13, 0x3, r10 // check for PCIA bits + beq r10, pal_post_dev_interrupt // done if nothing set + save_pcia_intr(2) + br r31, pal_post_dev_interrupt // + +1: lda r16, osfint_c_passrel(r31) // passive release + br r31, pal_post_interrupt // + + + ALIGN_BRANCH +sys_int_21: + Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx + srl r13, 12, r13 // shift down to examine IPL15 + + Intr_Find_TIOP(r13,r14) + beq r14, 1f + + Get_TLSB_Node_Address(r14,r10) + lda r10, 0xa40(r10) // Get base TLILID address + + ldl_p r13, 0(r10) // Read the TLILID register + bne r13, pal_post_dev_interrupt + beq r13, 1f + + and r13, 0x3, r10 // check for PCIA bits + beq r10, pal_post_dev_interrupt // done if nothing set + save_pcia_intr(1) + br r31, pal_post_dev_interrupt // + +1: lda r16, osfint_c_passrel(r31) // passive release + br r31, pal_post_interrupt // + + + ALIGN_BRANCH +sys_int_20: + lda r13, 1(r31) // Duart0 bit + Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit + + Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx + blbs r13, tlep_uart0 // go service UART int + + srl r13, 7, r13 // shift down to examine IPL14 + Intr_Find_TIOP(r13,r14) + + beq r14, tlep_ecc // Branch if not IPL14 + Get_TLSB_Node_Address(r14,r10) + + lda r10, 0xa00(r10) // Get base TLILID0 address + ldl_p r13, 0(r10) // Read the TLILID register + + bne r13, pal_post_dev_interrupt + beq r13, 1f + + and r13, 0x3, r10 // check for PCIA bits + beq r10, pal_post_dev_interrupt // done if nothing set + save_pcia_intr(0) + br r31, pal_post_dev_interrupt // +1: lda r16, osfint_c_passrel(r31) // passive release + br r31, pal_post_interrupt // + + + ALIGN_BRANCH +tlep_intim: + lda r13, 0xffb(r31) // get upper GBUS address bits + sll r13, 28, r13 // shift up to top + + lda r13, (0x300)(r13) // full CSRC address (tlep watch csrc offset) + ldq_p r13, 0(r13) // read CSRC + + lda r13, 0x40(r31) // load Intim bit + Write_TLINTRSUMx(r13,r10,r14) // clear the Intim bit + + lda r16, osfint_c_clk(r31) // passive release + br r31, pal_post_interrupt // Build the stack frame + + + ALIGN_BRANCH +tlep_ipint: + lda r13, 0x20(r31) // load IP Int bit + Write_TLINTRSUMx(r13,r10,r14) // clear the IP Int bit + + lda r16, osfint_c_ip(r31) // passive release + br r31, pal_post_interrupt // Build the stack frame + + + ALIGN_BRANCH +tlep_uart0: + lda r13, 0xffa(r31) // get upper GBUS address bits + sll r13, 28, r13 // shift up to top + + ldl_p r14, 0x80(r13) // zero pointer register + lda r14, 3(r31) // index to RR3 + + stl_p r14, 0x80(r13) // write pointer register + mb + + mb + ldl_p r14, 0x80(r13) // read RR3 + + srl r14, 5, r10 // is it Channel A RX? + blbs r10, uart0_rx + + srl r14, 4, r10 // is it Channel A TX? + blbs r10, uart0_tx + + srl r14, 2, r10 // is it Channel B RX? + blbs r10, uart1_rx + + srl r14, 1, r10 // is it Channel B TX? + blbs r10, uart1_tx + + lda r8, 0(r31) // passive release + br r31, clear_duart0_int // clear tlintrsum and post + + + ALIGN_BRANCH +uart0_rx: + lda r8, 0x680(r31) // UART0 RX vector + br r31, clear_duart0_int // clear tlintrsum and post + + + ALIGN_BRANCH +uart0_tx: + lda r14, 0x28(r31) // Reset TX Int Pending code + mb + stl_p r14, 0x80(r13) // write Channel A WR0 + mb + + lda r8, 0x6c0(r31) // UART0 TX vector + br r31, clear_duart0_int // clear tlintrsum and post + + + ALIGN_BRANCH +uart1_rx: + lda r8, 0x690(r31) // UART1 RX vector + br r31, clear_duart0_int // clear tlintrsum and post + + + ALIGN_BRANCH +uart1_tx: + lda r14, 0x28(r31) // Reset TX Int Pending code + stl_p r14, 0(r13) // write Channel B WR0 + + lda r8, 0x6d0(r31) // UART1 TX vector + br r31, clear_duart0_int // clear tlintrsum and post + + + ALIGN_BRANCH +clear_duart0_int: + lda r13, 1(r31) // load duart0 bit + Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit + + beq r8, 1f + or r8, r31, r13 // move vector to r13 + br r31, pal_post_dev_interrupt // Build the stack frame +1: nop + nop + hw_rei +// lda r16, osfint_c_passrel(r31) // passive release +// br r31, pal_post_interrupt // + + + ALIGN_BRANCH +tlep_ecc: + mfpr r14, pt_whami // get our node id + extbl r14, 1, r14 // shift to bit 0 + + srl r14, 1, r14 // shift off cpu number + Get_TLSB_Node_Address(r14,r10) // compute our nodespace address + + ldl_p r13, 0x40(r10) // read our TLBER WAS tlsb_tlber_offset + srl r13, 17, r13 // shift down the CWDE/CRDE bits + + and r13, 3, r13 // mask the CWDE/CRDE bits + beq r13, 1f + + ornot r31, r31, r12 // set flag + lda r9, mchk_c_sys_ecc(r31) // System Correctable error MCHK code + br r31, sys_merge_sys_corr // jump to CRD logout frame code + +1: lda r16, osfint_c_passrel(r31) // passive release + +#endif // if TSUNAMI || BIG_TSUNAMI elif TLASER + + ALIGN_BRANCH +pal_post_dev_interrupt: + or r13, r31, r17 // move vector to a1 + or r31, osfint_c_dev, r16 // a0 signals IO device interrupt + +pal_post_interrupt: + mfpr r12, pt_entint + + mtpr r12, exc_addr + + nop + nop + + hw_rei_spe + + +// +// sys_passive_release +// Just pretend the interrupt never occurred. +// + +EXPORT(sys_passive_release) + mtpr r11, ev5__dtb_cm // Restore Mbox current mode for ps + nop + + mfpr r31, pt0 // Pad write to dtb_cm + hw_rei + +// +// sys_int_powerfail +// A powerfail interrupt has been detected. The stack has been pushed. +// IPL and PS are updated as well. +// +// I'm not sure what to do here, I'm treating it as an IO device interrupt +// +// + + ALIGN_BLOCK +sys_int_powerfail: + lda r12, 0xffc4(r31) // get GBUS_MISCR address bits + sll r12, 24, r12 // shift to proper position + ldq_p r12, 0(r12) // read GBUS_MISCR + srl r12, 5, r12 // isolate bit <5> + blbc r12, 1f // if clear, no missed mchk + + // Missed a CFAIL mchk + lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits + sll r13, 24, r13 // shift to proper position + lda r14, 0x40(r31) // get bit <6> mask + ldq_p r12, 0(r13) // read GBUS$SERNUM + or r12, r14, r14 // set bit <6> + stq_p r14, 0(r13) // clear GBUS$SERNUM<6> + mb + mb + +1: br r31, sys_int_mchk // do a machine check + + lda r17, scb_v_pwrfail(r31) // a1 to interrupt vector + mfpr r25, pt_entint + + lda r16, osfint_c_dev(r31) // a0 to device code + mtpr r25, exc_addr + + nop // pad exc_addr write + nop + + hw_rei_spe + +// +// sys_halt_interrupt +// A halt interrupt has been detected. Pass control to the console. +// +// +// + EXPORT(sys_halt_interrupt) + + ldah r13, 0x1800(r31) // load Halt/^PHalt bits + Write_TLINTRSUMx(r13,r10,r14) // clear the ^PHalt bits + + mtpr r11, dtb_cm // Restore Mbox current mode + nop + nop + mtpr r0, pt0 + lda r0, hlt_c_hw_halt(r31) // set halt code to hw halt + br r31, sys_enter_console // enter the console + + + +// +// sys_int_mchk_or_crd +// +// Current state: +// Stack is pushed +// ps, sp and gp are updated +// r12 +// r13 - INTID (new EV5 IPL) +// r14 - exc_addr +// r25 - ISR +// r16, r17, r18 - available +// +// + ALIGN_BLOCK +sys_int_mchk_or_crd: + srl r25, isr_v_mck, r12 + blbs r12, sys_int_mchk + // + // Not a Machine check interrupt, so must be an Internal CRD interrupt + // + + mb //Clear out Cbox prior to reading IPRs + srl r25, isr_v_crd, r13 //Check for CRD + blbc r13, pal_pal_bug_check_from_int //If CRD not set, shouldn't be here!!! + + lda r9, 1(r31) + sll r9, hwint_clr_v_crdc, r9 // get ack bit for crd + mtpr r9, ev5__hwint_clr // ack the crd interrupt + + or r31, r31, r12 // clear flag + lda r9, mchk_c_ecc_c(r31) // Correctable error MCHK code + +sys_merge_sys_corr: + ldah r14, 0xfff0(r31) + mtpr r0, pt0 // save r0 for scratch + zap r14, 0xE0, r14 // Get Cbox IPR base + mtpr r1, pt1 // save r0 for scratch + + ldq_p r0, ei_addr(r14) // EI_ADDR IPR + ldq_p r10, fill_syn(r14) // FILL_SYN IPR + bis r0, r10, r31 // Touch lds to make sure they complete before doing scrub + + blbs r12, 1f // no scrubbing for IRQ0 case +// XXX bugnion pvc_jsr crd_scrub_mem, bsr=1 + bsr r13, sys_crd_scrub_mem // and go scrub + + // ld/st pair in scrub routine will have finished due + // to ibox stall of stx_c. Don't need another mb. + ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN + or r8, r31, r12 // Must only be executed once in this flow, and must + br r31, 2f // be after the scrub routine. + +1: ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN + // For IRQ0 CRD case only - meaningless data. + +2: mfpr r13, pt_mces // Get MCES + srl r12, ei_stat_v_ei_es, r14 // Isolate EI_STAT:EI_ES + blbc r14, 6f // branch if 630 + srl r13, mces_v_dsc, r14 // check if 620 reporting disabled + blbc r14, 5f // branch if enabled + or r13, r31, r14 // don't set SCE if disabled + br r31, 8f // continue +5: bis r13, BIT(mces_v_sce), r14 // Set MCES<SCE> bit + br r31, 8f + +6: srl r13, mces_v_dpc, r14 // check if 630 reporting disabled + blbc r14, 7f // branch if enabled + or r13, r31, r14 // don't set PCE if disabled + br r31, 8f // continue +7: bis r13, BIT(mces_v_pce), r14 // Set MCES<PCE> bit + + // Setup SCB if dpc is not set +8: mtpr r14, pt_mces // Store updated MCES + srl r13, mces_v_sce, r1 // Get SCE + srl r13, mces_v_pce, r14 // Get PCE + or r1, r14, r1 // SCE OR PCE, since they share + // the CRD logout frame + // Get base of the logout area. + GET_IMPURE(r14) // addr of per-cpu impure area + GET_ADDR(r14,(pal_logout_area+mchk_crd_base),r14) + + blbc r1, sys_crd_write_logout_frame // If pce/sce not set, build the frame + + // Set the 2nd error flag in the logout area: + + lda r1, 3(r31) // Set retry and 2nd error flags + sll r1, 30, r1 // Move to bits 31:30 of logout frame flag longword + stl_p r1, mchk_crd_flag+4(r14) // store flag longword + br sys_crd_ack + +sys_crd_write_logout_frame: + // should only be here if neither the pce or sce bits are set + + // + // Write the mchk code to the logout area + // + stq_p r9, mchk_crd_mchk_code(r14) + + + // + // Write the first 2 quadwords of the logout area: + // + lda r1, 1(r31) // Set retry flag + sll r1, 63, r9 // Move retry flag to bit 63 + lda r1, mchk_crd_size(r9) // Combine retry flag and frame size + stq_p r1, mchk_crd_flag(r14) // store flag/frame size + + // + // Write error IPRs already fetched to the logout area + // + stq_p r0, mchk_crd_ei_addr(r14) + stq_p r10, mchk_crd_fill_syn(r14) + stq_p r8, mchk_crd_ei_stat(r14) + stq_p r25, mchk_crd_isr(r14) + // + // Log system specific info here + // +crd_storeTLEP_: + lda r1, 0xffc4(r31) // Get GBUS$MISCR address + sll r1, 24, r1 + ldq_p r1, 0(r1) // Read GBUS$MISCR + sll r1, 16, r1 // shift up to proper field + mfpr r10, pt_whami // get our node id + extbl r10, 1, r10 // shift to bit 0 + or r1, r10, r1 // merge MISCR and WHAMI + stl_p r1, mchk_crd_whami(r14) // write to crd logout area + srl r10, 1, r10 // shift off cpu number + + Get_TLSB_Node_Address(r10,r0) // compute our nodespace address + + OSFcrd_TLEPstore_tlsb(tldev) + OSFcrd_TLEPstore_tlsb_clr(tlber) + OSFcrd_TLEPstore_tlsb_clr(tlesr0) + OSFcrd_TLEPstore_tlsb_clr(tlesr1) + OSFcrd_TLEPstore_tlsb_clr(tlesr2) + OSFcrd_TLEPstore_tlsb_clr(tlesr3) + +sys_crd_ack: + mfpr r0, pt0 // restore r0 + mfpr r1, pt1 // restore r1 + + srl r12, ei_stat_v_ei_es, r12 + blbc r12, 5f + srl r13, mces_v_dsc, r10 // logging enabled? + br r31, 6f +5: srl r13, mces_v_dpc, r10 // logging enabled? +6: blbc r10, sys_crd_post_interrupt // logging enabled -- report it + + // logging not enabled + // Get base of the logout area. + GET_IMPURE(r13) // addr of per-cpu impure area + GET_ADDR(r13,(pal_logout_area+mchk_crd_base),r13) + ldl_p r10, mchk_crd_rsvd(r13) // bump counter + addl r10, 1, r10 + stl_p r10, mchk_crd_rsvd(r13) + mb + br r31, sys_crd_dismiss_interrupt // just return + + // + // The stack is pushed. Load up a0,a1,a2 and vector via entInt + // + // + + ALIGN_BRANCH +sys_crd_post_interrupt: + lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0 + lda r17, scb_v_proc_corr_err(r31) // a1 <- interrupt vector + + blbc r12, 1f + lda r17, scb_v_sys_corr_err(r31) // a1 <- interrupt vector + +1: subq r31, 1, r18 // get a -1 + mfpr r25, pt_entInt + + srl r18, 42, r18 // shift off low bits of kseg addr + mtpr r25, exc_addr // load interrupt vector + + sll r18, 42, r18 // shift back into position + or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address + + hw_rei_spe // done + + + // + // The stack is pushed. Need to back out of it all. + // + +sys_crd_dismiss_interrupt: + br r31, Call_Pal_Rti + + +// sys_crd_scrub_mem +// +// r0 = addr of cache block +// + ALIGN_BLOCK // align for branch target +sys_crd_scrub_mem: + // now find error in memory, and attempt to scrub that cache block + // This routine just scrubs the failing octaword + // Only need to "touch" one quadword per octaword to accomplish the scrub + srl r0, 39, r8 // get high bit of bad pa + blbs r8, 1f // don't attempt fixup on IO space addrs + nop // needed to align the ldq_pl to octaword boundary + nop // " + + ldq_p r8, 0(r0) // attempt to read the bad memory + // location + // (Note bits 63:40,3:0 of ei_addr + // are set to 1, but as long as + // we are doing a phys ref, should + // be ok) + nop // Needed to keep the Ibox from swapping the ldq_p into E1 + + stq_p r8, 0(r0) // Store it back if it is still there. + // If store fails, location already + // scrubbed by someone else + + nop // needed to align the ldq_p to octaword boundary + + lda r8, 0x20(r31) // flip bit 5 to touch next hexaword + xor r8, r0, r0 + nop // needed to align the ldq_p to octaword boundary + nop // " + + ldq_p r8, 0(r0) // attempt to read the bad memory + // location + // (Note bits 63:40,3:0 of ei_addr + // are set to 1, but as long as + // we are doing a phys ref, should + // be ok) + nop // Needed to keep the Ibox from swapping the ldq_p into E1 + + stq_p r8, 0(r0) // Store it back if it is still there. + // If store fails, location already + // scrubbed by someone else + + lda r8, 0x20(r31) // restore r0 to original address + xor r8, r0, r0 + + //at this point, ei_stat could be locked due to a new corr error on the ld, + //so read ei_stat to unlock AFTER this routine. + +// XXX bugnion pvc$jsr crd_scrub_mem, bsr=1, dest=1 +1: ret r31, (r13) // and back we go + + +// +// sys_int_mchk - MCHK Interrupt code +// +// Machine check interrupt from the system. Setup and join the +// regular machine check flow. +// On exit: +// pt0 - saved r0 +// pt1 - saved r1 +// pt4 - saved r4 +// pt5 - saved r5 +// pt6 - saved r6 +// pt10 - saved exc_addr +// pt_misc<47:32> - mchk code +// pt_misc<31:16> - scb vector +// r14 - base of Cbox IPRs in IO space +// MCES<mchk> is set +// + ALIGN_BLOCK +sys_int_mchk: + lda r14, mchk_c_sys_hrd_error(r31) + mfpr r12, exc_addr + + addq r14, 1, r14 // Flag as interrupt + nop + + sll r14, 32, r14 // Move mchk code to position + mtpr r12, pt10 // Stash exc_addr + + mfpr r12, pt_misc // Get MCES and scratch + mtpr r0, pt0 // Stash for scratch + + zap r12, 0x3c, r12 // Clear scratch + blbs r12, sys_double_machine_check // MCHK halt if double machine check + + or r12, r14, r12 // Combine mchk code + lda r14, scb_v_sysmchk(r31) // Get SCB vector + + sll r14, 16, r14 // Move SCBv to position + or r12, r14, r14 // Combine SCBv + + bis r14, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit + mtpr r14, pt_misc // Save mchk code!scbv!whami!mces + + ldah r14, 0xfff0(r31) + mtpr r1, pt1 // Stash for scratch + + zap r14, 0xE0, r14 // Get Cbox IPR base + mtpr r4, pt4 + + mtpr r5, pt5 + + mtpr r6, pt6 + br r31, sys_mchk_collect_iprs // Join common machine check flow + + +// +// sys_int_perf_cnt - Performance counter interrupt code +// +// A performance counter interrupt has been detected. The stack +// has been pushed. IPL and PS are updated as well. +// +// on exit to interrupt entry point ENTINT:: +// a0 = osfint$c_perf +// a1 = scb$v_perfmon (650) +// a2 = 0 if performance counter 0 fired +// a2 = 1 if performance counter 1 fired +// a2 = 2 if performance counter 2 fired +// (if more than one counter overflowed, an interrupt will be +// generated for each counter that overflows) +// +// +// + ALIGN_BLOCK +sys_int_perf_cnt: // Performance counter interrupt + lda r17, scb_v_perfmon(r31) // a1 to interrupt vector + mfpr r25, pt_entint + + lda r16, osfint_c_perf(r31) // a0 to perf counter code + mtpr r25, exc_addr + + //isolate which perf ctr fired, load code in a2, and ack + mfpr r25, isr + or r31, r31, r18 // assume interrupt was pc0 + + srl r25, isr_v_pc1, r25 // isolate + cmovlbs r25, 1, r18 // if pc1 set, load 1 into r14 + + srl r25, 1, r25 // get pc2 + cmovlbs r25, 2, r18 // if pc2 set, load 2 into r14 + + lda r25, 1(r31) // get a one + sll r25, r18, r25 + + sll r25, hwint_clr_v_pc0c, r25 // ack only the perf counter that generated the interrupt + mtpr r25, hwint_clr + + hw_rei_spe + + + +// +// sys_reset - System specific RESET code +// On entry: +// r1 = pal_base +8 +// +// Entry state on trap: +// r0 = whami +// r2 = base of scratch area +// r3 = halt code +// and the following 3 if init_cbox is enabled: +// r5 = sc_ctl +// r6 = bc_ctl +// r7 = bc_cnfg +// +// Entry state on switch: +// r17 - new PC +// r18 - new PCBB +// r19 - new VPTB +// + + ALIGN_BLOCK + .globl sys_reset +sys_reset: +// mtpr r31, ic_flush_ctl // do not flush the icache - done by hardware before SROM load + mtpr r31, itb_ia // clear the ITB + mtpr r31, dtb_ia // clear the DTB + + lda r1, -8(r1) // point to start of code + mtpr r1, pal_base // initialize PAL_BASE + + // Interrupts + mtpr r31, astrr // stop ASTs + mtpr r31, aster // stop ASTs + mtpr r31, sirr // clear software interrupts + + mtpr r0, pt1 // r0 is whami (unless we entered via swp) + + ldah r1,(BIT(icsr_v_sde-16)|BIT(icsr_v_fpe-16)|BIT(icsr_v_spe-16+1))(zero) + + bis r31, 1, r0 + sll r0, icsr_v_crde, r0 // A 1 in iscr<corr_read_enable> + or r0, r1, r1 // Set the bit + + mtpr r1, icsr // ICSR - Shadows enabled, Floating point enable, + // super page enabled, correct read per assembly option + + // Mbox/Dcache init + lda r1,BIT(mcsr_v_sp1)(zero) + + mtpr r1, mcsr // MCSR - Super page enabled + lda r1, BIT(dc_mode_v_dc_ena)(r31) + ALIGN_BRANCH +// mtpr r1, dc_mode // turn Dcache on + nop + + mfpr r31, pt0 // No Mbox instr in 1,2,3,4 + mfpr r31, pt0 + mfpr r31, pt0 + mfpr r31, pt0 + mtpr r31, dc_flush // flush Dcache + + // build PS (IPL=7,CM=K,VMM=0,SW=0) + lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7 + lda r1, 0x1F(r31) + mtpr r1, ipl // set internal <ipl>=1F + mtpr r31, ev5__ps // set new ps<cm>=0, Ibox copy + mtpr r31, dtb_cm // set new ps<cm>=0, Mbox copy + + // Create the PALtemp pt_intmask + // MAP: + // OSF IPL EV5 internal IPL(hex) note + // 0 0 + // 1 1 + // 2 2 + // 3 14 device + // 4 15 device + // 5 16 device + // 6 1E device,performance counter, powerfail + // 7 1F + // + + ldah r1, 0x1f1E(r31) // Create upper lw of int_mask + lda r1, 0x1615(r1) + + sll r1, 32, r1 + ldah r1, 0x1402(r1) // Create lower lw of int_mask + + lda r1, 0x0100(r1) + mtpr r1, pt_intmask // Stash in PALtemp + + // Unlock a bunch of chip internal IPRs + mtpr r31, exc_sum // clear out exeception summary and exc_mask + mfpr r31, va // unlock va, mmstat + lda r8,(BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(zero) + + mtpr r8, icperr_stat // Clear Icache parity error & timeout status + lda r8,(BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31) + + mtpr r8, dcperr_stat // Clear Dcache parity error status + + rc r0 // clear intr_flag + mtpr r31, pt_trap + + mfpr r0, pt_misc + srl r0, pt_misc_v_switch, r1 + blbs r1, sys_reset_switch // see if we got here from swppal + + // Rest of the "real" reset flow + // ASN + mtpr r31, dtb_asn + mtpr r31, itb_asn + + lda r1, 0x67(r31) + sll r1, hwint_clr_v_pc0c, r1 + mtpr r1, hwint_clr // Clear hardware interrupt requests + + lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error + mfpr r0, pt1 // get whami + insbl r0, 1, r0 // isolate whami in correct pt_misc position + or r0, r1, r1 // combine whami and mces + mtpr r1, pt_misc // store whami and mces, swap bit clear + + zapnot r3, 1, r0 // isolate halt code + mtpr r0, pt0 // save entry type + + // Cycle counter + or r31, 1, r9 // get a one + sll r9, 32, r9 // shift to <32> + mtpr r31, cc // clear Cycle Counter + mtpr r9, cc_ctl // clear and enable the Cycle Counter + mtpr r31, pt_scc // clear System Cycle Counter + + + // Misc PALtemps + mtpr r31, maf_mode // no mbox instructions for 3 cycles + or r31, 1, r1 // get bogus scbb value + mtpr r1, pt_scbb // load scbb + mtpr r31, pt_prbr // clear out prbr +#if defined(TSUNAMI) || defined(BIG_TSUNAMI) + // yes, this is ugly, but you figure out a better + // way to get the address of the kludge_initial_pcbb + // in r1 with an uncooperative assembler --ali + br r1, kludge_getpcb_addr + br r31, kludge_initial_pcbb +kludge_getpcb_addr: + ldq_p r19, 0(r1) + sll r19, 44, r19 + srl r19, 44, r19 + mulq r19,4,r19 + addq r19, r1, r1 + addq r1,4,r1 +#elif defined(TLASER) + // or zero,kludge_initial_pcbb,r1 + GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1) +#endif + mtpr r1, pt_pcbb // load pcbb + lda r1, 2(r31) // get a two + sll r1, 32, r1 // gen up upper bits + mtpr r1, mvptbr + mtpr r1, ivptbr + mtpr r31, pt_ptbr + // Performance counters + mtpr r31, pmctr + + // Clear pmctr_ctl in impure area + + + ldah r14, 0xfff0(r31) + zap r14, 0xE0, r14 // Get Cbox IPR base + GET_IMPURE(r13) + stq_p r31, 0(r13) // Clear lock_flag + + mfpr r0, pt0 // get entry type + br r31, sys_enter_console // enter the cosole + + + // swppal entry + // r0 - pt_misc + // r17 - new PC + // r18 - new PCBB + // r19 - new VPTB +sys_reset_switch: + or r31, 1, r9 + sll r9, pt_misc_v_switch, r9 + bic r0, r9, r0 // clear switch bit + mtpr r0, pt_misc + + rpcc r1 // get cyccounter + + ldq_p r22, osfpcb_q_fen(r18) // get new fen/pme + ldl_p r23, osfpcb_l_cc(r18) // get cycle counter + ldl_p r24, osfpcb_l_asn(r18) // get new asn + + + ldq_p r25, osfpcb_q_Mmptr(r18)// get new mmptr + sll r25, page_offset_size_bits, r25 // convert pfn to pa + mtpr r25, pt_ptbr // load the new mmptr + mtpr r18, pt_pcbb // set new pcbb + + bic r17, 3, r17 // clean use pc + mtpr r17, exc_addr // set new pc + mtpr r19, mvptbr + mtpr r19, ivptbr + + ldq_p r30, osfpcb_q_Usp(r18) // get new usp + mtpr r30, pt_usp // save usp + + sll r24, dtb_asn_v_asn, r8 + mtpr r8, dtb_asn + sll r24, itb_asn_v_asn, r24 + mtpr r24, itb_asn + + mfpr r25, icsr // get current icsr + lda r24, 1(r31) + sll r24, icsr_v_fpe, r24 // 1 in icsr<fpe> position + bic r25, r24, r25 // clean out old fpe + and r22, 1, r22 // isolate new fen bit + sll r22, icsr_v_fpe, r22 + or r22, r25, r25 // or in new fpe + mtpr r25, icsr // update ibox ipr + + subl r23, r1, r1 // gen new cc offset + insll r1, 4, r1 // << 32 + mtpr r1, cc // set new offset + + or r31, r31, r0 // set success + ldq_p r30, osfpcb_q_Ksp(r18) // get new ksp + mfpr r31, pt0 // stall + hw_rei_stall + +// +//sys_machine_check - Machine check PAL +// A machine_check trap has occurred. The Icache has been flushed. +// +// + + ALIGN_BLOCK +EXPORT(sys_machine_check) + // Need to fill up the refill buffer (32 instructions) and + // then flush the Icache again. + // Also, due to possible 2nd Cbox register file write for + // uncorrectable errors, no register file read or write for 7 cycles. + + //nop + .long 0x4000054 // call M5 Panic + mtpr r0, pt0 // Stash for scratch -- OK if Cbox overwrites + // r0 later + nop + nop + + nop + nop + + nop + nop + + nop + nop + // 10 instructions// 5 cycles + + nop + nop + + nop + nop + + // Register file can now be written + lda r0, scb_v_procmchk(r31) // SCB vector + mfpr r13, pt_mces // Get MCES + sll r0, 16, r0 // Move SCBv to correct position + bis r13, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit + + + zap r14, 0x3C, r14 // Clear mchk_code word and SCBv word + mtpr r14, pt_mces + // 20 instructions + + nop + or r14, r0, r14 // Insert new SCB vector + lda r0, mchk_c_proc_hrd_error(r31) // MCHK code + mfpr r12, exc_addr + + sll r0, 32, r0 // Move MCHK code to correct position + mtpr r4, pt4 + or r14, r0, r14 // Insert new MCHK code + mtpr r14, pt_misc // Store updated MCES, MCHK code, and SCBv + + ldah r14, 0xfff0(r31) + mtpr r1, pt1 // Stash for scratch - 30 instructions + + zap r14, 0xE0, r14 // Get Cbox IPR base + mtpr r12, pt10 // Stash exc_addr + + + + mtpr r31, ic_flush_ctl // Second Icache flush, now it is really flushed. + blbs r13, sys_double_machine_check // MCHK halt if double machine check + + mtpr r6, pt6 + mtpr r5, pt5 + + // Look for the powerfail cases here.... + mfpr r4, isr + srl r4, isr_v_pfl, r4 + blbc r4, sys_mchk_collect_iprs // skip if no powerfail interrupt pending + lda r4, 0xffc4(r31) // get GBUS$MISCR address bits + sll r4, 24, r4 // shift to proper position + ldq_p r4, 0(r4) // read GBUS$MISCR + srl r4, 5, r4 // isolate bit <5> + blbc r4, sys_mchk_collect_iprs // skip if already cleared + // No missed CFAIL mchk + lda r5, 0xffc7(r31) // get GBUS$SERNUM address bits + sll r5, 24, r5 // shift to proper position + lda r6, 0x40(r31) // get bit <6> mask + ldq_p r4, 0(r5) // read GBUS$SERNUM + or r4, r6, r6 // set bit <6> + stq_p r6, 0(r5) // clear GBUS$SERNUM<6> + mb + mb + + + // + // Start to collect the IPRs. Common entry point for mchk flows. + // + // Current state: + // pt0 - saved r0 + // pt1 - saved r1 + // pt4 - saved r4 + // pt5 - saved r5 + // pt6 - saved r6 + // pt10 - saved exc_addr + // pt_misc<47:32> - mchk code + // pt_misc<31:16> - scb vector + // r14 - base of Cbox IPRs in IO space + // r0, r1, r4, r5, r6, r12, r13, r25 - available + // r8, r9, r10 - available as all loads are physical + // MCES<mchk> is set + // + // + +EXPORT(sys_mchk_collect_iprs) + .long 0x4000054 // call M5 Panic + //mb // MB before reading Scache IPRs + mfpr r1, icperr_stat + + mfpr r8, dcperr_stat + mtpr r31, dc_flush // Flush the Dcache + + mfpr r31, pt0 // Pad Mbox instructions from dc_flush + mfpr r31, pt0 + nop + nop + + ldq_p r9, sc_addr(r14) // SC_ADDR IPR + bis r9, r31, r31 // Touch ld to make sure it completes before + // read of SC_STAT + ldq_p r10, sc_stat(r14) // SC_STAT, also unlocks SC_ADDR + + ldq_p r12, ei_addr(r14) // EI_ADDR IPR + ldq_p r13, bc_tag_addr(r14) // BC_TAG_ADDR IPR + ldq_p r0, fill_syn(r14) // FILL_SYN IPR + bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT + bis r0, r0, r31 // Touch lds to make sure they complete before reading EI_STAT + ldq_p r25, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN + ldq_p r31, ei_stat(r14) // Read again to insure it is unlocked + + + + + // + // Look for nonretryable cases + // In this segment: + // r5<0> = 1 means retryable + // r4, r6, and r14 are available for scratch + // + // + + + bis r31, r31, r5 // Clear local retryable flag + srl r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits to low bits + + lda r4, 1(r31) + sll r4, icperr_stat_v_tmr, r4 + and r1, r4, r4 // Timeout reset + bne r4, sys_cpu_mchk_not_retryable + + and r8, BIT(dcperr_stat_v_lock), r4 // DCache parity error locked + bne r4, sys_cpu_mchk_not_retryable + + lda r4, 1(r31) + sll r4, sc_stat_v_sc_scnd_err, r4 + and r10, r4, r4 // 2nd Scache error occurred + bne r4, sys_cpu_mchk_not_retryable + + + bis r31, 0xa3, r4 // EI_STAT Bcache Tag Parity Error, Bcache Tag Control + // Parity Error, Interface Parity Error, 2nd Error + + and r25, r4, r4 + bne r4, sys_cpu_mchk_not_retryable + +// bis r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4 + bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4 + and r25, r4, r4 // Isolate the Uncorrectable Error Bit +// bis r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6 + bis r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit + cmovne r6, 0, r4 // r4 = 0 if IRD or if No Uncorrectable Error + bne r4, sys_cpu_mchk_not_retryable + + lda r4, 7(r31) + and r10, r4, r4 // Isolate the Scache Tag Parity Error bits + bne r4, sys_cpu_mchk_not_retryable // All Scache Tag PEs are not retryable + + + lda r4, 0x7f8(r31) + and r10, r4, r4 // Isolate the Scache Data Parity Error bits + srl r10, sc_stat_v_cbox_cmd, r6 + and r6, 0x1f, r6 // Isolate Scache Command field + subq r6, 1, r6 // Scache Iread command = 1 + cmoveq r6, 0, r4 // r4 = 0 if IRD or if No Parity Error + bne r4, sys_cpu_mchk_not_retryable + + // Look for the system unretryable cases here.... + + mfpr r4, isr // mchk_interrupt pin asserted + srl r4, isr_v_mck, r4 + blbs r4, sys_cpu_mchk_not_retryable + + + + // + // Look for retryable cases + // In this segment: + // r5<0> = 1 means retryable + // r6 - holds the mchk code + // r4 and r14 are available for scratch + // + // + + + // Within the chip, the retryable cases are Istream errors + lda r4, 3(r31) + sll r4, icperr_stat_v_dpe, r4 + and r1, r4, r4 + cmovne r4, 1, r5 // Retryable if just Icache parity error + + + lda r4, 0x7f8(r31) + and r10, r4, r4 // Isolate the Scache Data Parity Error bits + srl r10, sc_stat_v_cbox_cmd, r14 + and r14, 0x1f, r14 // Isolate Scache Command field + subq r14, 1, r14 // Scache Iread command = 1 + cmovne r4, 1, r4 // r4 = 1 if Scache data parity error bit set + cmovne r14, 0, r4 // r4 = 1 if Scache PE and Iread + bis r4, r5, r5 // Accumulate + + + bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4 + and r25, r4, r4 // Isolate the Uncorrectable Error Bit + and r25, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r14 // Isolate the Iread bit + cmovne r4, 1, r4 // r4 = 1 if uncorr error + cmoveq r14, 0, r4 // r4 = 1 if uncorr and Iread + bis r4, r5, r5 // Accumulate + + mfpr r6, pt_misc + extwl r6, 4, r6 // Fetch mchk code + bic r6, 1, r6 // Clear flag from interrupt flow + cmovne r5, mchk_c_retryable_ird, r6 // Set mchk code + + + // + // Write the logout frame + // + // Current state: + // r0 - fill_syn + // r1 - icperr_stat + // r4 - available + // r5<0> - retry flag + // r6 - mchk code + // r8 - dcperr_stat + // r9 - sc_addr + // r10 - sc_stat + // r12 - ei_addr + // r13 - bc_tag_addr + // r14 - available + // r25 - ei_stat (shifted) + // pt0 - saved r0 + // pt1 - saved r1 + // pt4 - saved r4 + // pt5 - saved r5 + // pt6 - saved r6 + // pt10 - saved exc_addr + // + // + +sys_mchk_write_logout_frame: + // Get base of the logout area. + GET_IMPURE(r14) // addr of per-cpu impure area + GET_ADDR(r14,pal_logout_area+mchk_mchk_base,r14) + + // Write the first 2 quadwords of the logout area: + + sll r5, 63, r5 // Move retry flag to bit 63 + lda r4, mchk_size(r5) // Combine retry flag and frame size + stq_p r4, mchk_flag(r14) // store flag/frame size + lda r4, mchk_sys_base(r31) // sys offset + sll r4, 32, r4 + lda r4, mchk_cpu_base(r4) // cpu offset + stq_p r4, mchk_offsets(r14) // store sys offset/cpu offset into logout frame + + // + // Write the mchk code to the logout area + // Write error IPRs already fetched to the logout area + // Restore some GPRs from PALtemps + // + + mfpr r5, pt5 + stq_p r6, mchk_mchk_code(r14) + mfpr r4, pt4 + stq_p r1, mchk_ic_perr_stat(r14) + mfpr r6, pt6 + stq_p r8, mchk_dc_perr_stat(r14) + mfpr r1, pt1 + stq_p r9, mchk_sc_addr(r14) + stq_p r10, mchk_sc_stat(r14) + stq_p r12, mchk_ei_addr(r14) + stq_p r13, mchk_bc_tag_addr(r14) + stq_p r0, mchk_fill_syn(r14) + mfpr r0, pt0 + sll r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits back to expected position + // retrieve lower 28 bits again from ei_stat and restore before storing to logout frame + ldah r13, 0xfff0(r31) + zapnot r13, 0x1f, r13 + ldq_p r13, ei_stat(r13) + sll r13, 64-ei_stat_v_bc_tperr, r13 + srl r13, 64-ei_stat_v_bc_tperr, r13 + or r25, r13, r25 + stq_p r25, mchk_ei_stat(r14) + + + + + // + // complete the CPU-specific part of the logout frame + // + + ldah r13, 0xfff0(r31) + zap r13, 0xE0, r13 // Get Cbox IPR base + ldq_p r13, ld_lock(r13) // Get ld_lock IPR + stq_p r13, mchk_ld_lock(r14) // and stash it in the frame + + // Unlock IPRs + lda r8, (BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31) + mtpr r8, dcperr_stat // Clear Dcache parity error status + + lda r8, (BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(r31) + mtpr r8, icperr_stat // Clear Icache parity error & timeout status + +1: ldq_p r8, mchk_ic_perr_stat(r14) // get ICPERR_STAT value + GET_ADDR(r0,0x1800,r31) // get ICPERR_STAT value + and r0, r8, r0 // compare + beq r0, 2f // check next case if nothing set + lda r0, mchk_c_retryable_ird(r31) // set new MCHK code + br r31, do_670 // setup new vector + +2: ldq_p r8, mchk_dc_perr_stat(r14) // get DCPERR_STAT value + GET_ADDR(r0,0x3f,r31) // get DCPERR_STAT value + and r0, r8, r0 // compare + beq r0, 3f // check next case if nothing set + lda r0, mchk_c_dcperr(r31) // set new MCHK code + br r31, do_670 // setup new vector + +3: ldq_p r8, mchk_sc_stat(r14) // get SC_STAT value + GET_ADDR(r0,0x107ff,r31) // get SC_STAT value + and r0, r8, r0 // compare + beq r0, 4f // check next case if nothing set + lda r0, mchk_c_scperr(r31) // set new MCHK code + br r31, do_670 // setup new vector + +4: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value + GET_ADDR(r0,0x30000000,r31) // get EI_STAT value + and r0, r8, r0 // compare + beq r0, 5f // check next case if nothing set + lda r0, mchk_c_bcperr(r31) // set new MCHK code + br r31, do_670 // setup new vector + +5: ldl_p r8, mchk_tlber(r14) // get TLBER value + GET_ADDR(r0,0xfe01,r31) // get high TLBER mask value + sll r0, 16, r0 // shift into proper position + GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value + or r0, r1, r0 // merge mask values + and r0, r8, r0 // compare + beq r0, 6f // check next case if nothing set + GET_ADDR(r0, 0xfff0, r31) // set new MCHK code + br r31, do_660 // setup new vector + +6: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value + GET_ADDR(r0,0xff7f,r31) // get TLEPAERR mask value + and r0, r8, r0 // compare + beq r0, 7f // check next case if nothing set + GET_ADDR(r0, 0xfffa, r31) // set new MCHK code + br r31, do_660 // setup new vector + +7: ldl_p r8, mchk_tlepderr(r14) // get TLEPDERR value + GET_ADDR(r0,0x7,r31) // get TLEPDERR mask value + and r0, r8, r0 // compare + beq r0, 8f // check next case if nothing set + GET_ADDR(r0, 0xfffb, r31) // set new MCHK code + br r31, do_660 // setup new vector + +8: ldl_p r8, mchk_tlepmerr(r14) // get TLEPMERR value + GET_ADDR(r0,0x3f,r31) // get TLEPMERR mask value + and r0, r8, r0 // compare + beq r0, 9f // check next case if nothing set + GET_ADDR(r0, 0xfffc, r31) // set new MCHK code + br r31, do_660 // setup new vector + +9: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value + GET_ADDR(r0,0xb,r31) // get EI_STAT mask value + sll r0, 32, r0 // shift to upper lw + and r0, r8, r0 // compare + beq r0, 1f // check next case if nothing set + GET_ADDR(r0,0xfffd,r31) // set new MCHK code + br r31, do_660 // setup new vector + +1: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value + GET_ADDR(r0,0x80,r31) // get TLEPAERR mask value + and r0, r8, r0 // compare + beq r0, cont_logout_frame // check next case if nothing set + GET_ADDR(r0, 0xfffe, r31) // set new MCHK code + br r31, do_660 // setup new vector + +do_670: lda r8, scb_v_procmchk(r31) // SCB vector + br r31, do_6x0_cont +do_660: lda r8, scb_v_sysmchk(r31) // SCB vector +do_6x0_cont: + sll r8, 16, r8 // shift to proper position + mfpr r1, pt_misc // fetch current pt_misc + GET_ADDR(r4,0xffff, r31) // mask for vector field + sll r4, 16, r4 // shift to proper position + bic r1, r4, r1 // clear out old vector field + or r1, r8, r1 // merge in new vector + mtpr r1, pt_misc // save new vector field + stl_p r0, mchk_mchk_code(r14) // save new mchk code + +cont_logout_frame: + // Restore some GPRs from PALtemps + mfpr r0, pt0 + mfpr r1, pt1 + mfpr r4, pt4 + + mfpr r12, pt10 // fetch original PC + blbs r12, sys_machine_check_while_in_pal // MCHK halt if machine check in pal + +//XXXbugnion pvc_jsr armc, bsr=1 + bsr r12, sys_arith_and_mchk // go check for and deal with arith trap + + mtpr r31, exc_sum // Clear Exception Summary + + mfpr r25, pt10 // write exc_addr after arith_and_mchk to pickup new pc + stq_p r25, mchk_exc_addr(r14) + + // + // Set up the km trap + // + + +sys_post_mchk_trap: + mfpr r25, pt_misc // Check for flag from mchk interrupt + extwl r25, 4, r25 + blbs r25, sys_mchk_stack_done // Stack from already pushed if from interrupt flow + + bis r14, r31, r12 // stash pointer to logout area + mfpr r14, pt10 // get exc_addr + + sll r11, 63-3, r25 // get mode to msb + bge r25, 3f + + mtpr r31, dtb_cm + mtpr r31, ev5__ps + + mtpr r30, pt_usp // save user stack + mfpr r30, pt_ksp + +3: + lda sp, 0-osfsf_c_size(sp) // allocate stack space + nop + + stq r18, osfsf_a2(sp) // a2 + stq r11, osfsf_ps(sp) // save ps + + stq r14, osfsf_pc(sp) // save pc + mfpr r25, pt_entint // get the VA of the interrupt routine + + stq r16, osfsf_a0(sp) // a0 + lda r16, osfint_c_mchk(r31) // flag as mchk in a0 + + stq r17, osfsf_a1(sp) // a1 + mfpr r17, pt_misc // get vector + + stq r29, osfsf_gp(sp) // old gp + mtpr r25, exc_addr // + + or r31, 7, r11 // get new ps (km, high ipl) + subq r31, 1, r18 // get a -1 + + extwl r17, 2, r17 // a1 <- interrupt vector + bis r31, ipl_machine_check, r25 + + mtpr r25, ipl // Set internal ipl + srl r18, 42, r18 // shift off low bits of kseg addr + + sll r18, 42, r18 // shift back into position + mfpr r29, pt_kgp // get the kern r29 + + or r12, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address + hw_rei_spe // out to interrupt dispatch routine + + + // + // The stack is pushed. Load up a0,a1,a2 and vector via entInt + // + // + ALIGN_BRANCH +sys_mchk_stack_done: + lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0 + lda r17, scb_v_sysmchk(r31) // a1 <- interrupt vector + + subq r31, 1, r18 // get a -1 + mfpr r25, pt_entInt + + srl r18, 42, r18 // shift off low bits of kseg addr + mtpr r25, exc_addr // load interrupt vector + + sll r18, 42, r18 // shift back into position + or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address + + hw_rei_spe // done + + + ALIGN_BRANCH +sys_cpu_mchk_not_retryable: + mfpr r6, pt_misc + extwl r6, 4, r6 // Fetch mchk code + br r31, sys_mchk_write_logout_frame // + + + +// +//sys_double_machine_check - a machine check was started, but MCES<MCHK> was +// already set. We will now double machine check halt. +// +// pt0 - old R0 +// +// + +EXPORT(sys_double_machine_check) + lda r0, hlt_c_dbl_mchk(r31) + br r31, sys_enter_console + +// +// sys_machine_check_while_in_pal - a machine check was started, +// exc_addr points to a PAL PC. We will now machine check halt. +// +// pt0 - old R0 +// +// +sys_machine_check_while_in_pal: + stq_p r12, mchk_exc_addr(r14) // exc_addr has not yet been written + lda r0, hlt_c_mchk_from_pal(r31) + br r31, sys_enter_console + + +//ARITH and MCHK +// Check for arithmetic errors and build trap frame, +// but don't post the trap. +// on entry: +// pt10 - exc_addr +// r12 - return address +// r14 - logout frame pointer +// r13 - available +// r8,r9,r10 - available except across stq's +// pt0,1,6 - available +// +// on exit: +// pt10 - new exc_addr +// r17 = exc_mask +// r16 = exc_sum +// r14 - logout frame pointer +// + ALIGN_BRANCH +sys_arith_and_mchk: + mfpr r13, ev5__exc_sum + srl r13, exc_sum_v_swc, r13 + bne r13, handle_arith_and_mchk + +// XXX bugnion pvc$jsr armc, bsr=1, dest=1 + ret r31, (r12) // return if no outstanding arithmetic error + +handle_arith_and_mchk: + mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel + // no virt ref for next 2 cycles + mtpr r14, pt0 + + mtpr r1, pt1 // get a scratch reg + and r11, osfps_m_mode, r1 // get mode bit + + bis r11, r31, r25 // save ps + beq r1, 1f // if zero we are in kern now + + bis r31, r31, r25 // set the new ps + mtpr r30, pt_usp // save user stack + + mfpr r30, pt_ksp // get kern stack +1: + mfpr r14, exc_addr // get pc into r14 in case stack writes fault + + lda sp, 0-osfsf_c_size(sp) // allocate stack space + mtpr r31, ev5__ps // Set Ibox current mode to kernel + + mfpr r1, pt_entArith + stq r14, osfsf_pc(sp) // save pc + + stq r17, osfsf_a1(sp) + mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle + + stq r29, osfsf_gp(sp) + stq r16, osfsf_a0(sp) // save regs + + bis r13, r31, r16 // move exc_sum to r16 + stq r18, osfsf_a2(sp) + + stq r11, osfsf_ps(sp) // save ps + mfpr r29, pt_kgp // get the kern gp + + mfpr r14, pt0 // restore logout frame pointer from pt0 + bis r25, r31, r11 // set new ps + + mtpr r1, pt10 // Set new PC + mfpr r1, pt1 + +// XXX bugnion pvc$jsr armc, bsr=1, dest=1 + ret r31, (r12) // return if no outstanding arithmetic error + + + +// sys_enter_console - Common PALcode for ENTERING console +// +// Entry: +// Entered when PAL wants to enter the console. +// usually as the result of a HALT instruction or button, +// or catastrophic error. +// +// Regs on entry... +// +// R0 = halt code +// pt0 <- r0 +// +// Function: +// +// Save all readable machine state, and "call" the console +// +// Returns: +// +// +// Notes: +// +// In these routines, once the save state routine has been executed, +// the remainder of the registers become scratchable, as the only +// "valid" copy of them is the "saved" copy. +// +// Any registers or PTs that are modified before calling the save +// routine will have there data lost. The code below will save all +// state, but will loose pt 0,4,5. +// +// + + ALIGN_BLOCK +EXPORT(sys_enter_console) + mtpr r1, pt4 + mtpr r3, pt5 + subq r31, 1, r1 + sll r1, 42, r1 + ldah r1, 1(r1) + + /* taken from scrmax, seems like the obvious thing to do */ + mtpr r1, exc_addr + mfpr r1, pt4 + mfpr r3, pt5 + STALL + STALL + hw_rei_stall + + +// +// sys_exit_console - Common PALcode for ENTERING console +// +// Entry: +// Entered when console wants to reenter PAL. +// usually as the result of a CONTINUE. +// +// +// Regs' on entry... +// +// +// Function: +// +// Restore all readable machine state, and return to user code. +// +// +// +// + ALIGN_BLOCK +sys_exit_console: + + GET_IMPURE(r1) + + // clear lock and intr_flags prior to leaving console + rc r31 // clear intr_flag + // lock flag cleared by restore_state + // TB's have been flushed + + ldq_p r3, (cns_gpr+(8*3))(r1) // restore r3 + ldq_p r1, (cns_gpr+8)(r1) // restore r1 + hw_rei_stall // back to user + + +// kludge_initial_pcbb - PCB for Boot use only + + ALIGN_128 +.globl kludge_initial_pcbb +kludge_initial_pcbb: // PCB is 128 bytes long + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop + nop + nop + + nop + nop + nop + nop + + +// SET_SC_BC_CTL subroutine +// +// Subroutine to set the SC_CTL, BC_CONFIG, and BC_CTL registers and +// flush the Scache +// There must be no outstanding memory references -- istream or +// dstream -- when these registers are written. EV5 prefetcher is +// difficult to turn off. So, this routine needs to be exactly 32 +// instructions long// the final jmp must be in the last octaword of a +// page (prefetcher doesn't go across page) +// +// +// Register expecations: +// r0 base address of CBOX iprs +// r5 value to set sc_ctl to (flush bit is added in) +// r6 value to set bc_ctl to +// r7 value to set bc_config to +// r10 return address +// r19 old sc_ctl value +// r20 old value of bc_ctl +// r21 old value of bc_config +// r23 flush scache flag +// Register usage: +// r17 sc_ctl with flush bit cleared +// r22 loop address +// +// +set_sc_bc_ctl: + ret r31, (r10) // return to where we came from |