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author | Akash Bagdia <akash.bagdia@arm.com> | 2013-06-27 05:49:49 -0400 |
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committer | Akash Bagdia <akash.bagdia@arm.com> | 2013-06-27 05:49:49 -0400 |
commit | 7d7ab738622e7969a7db85ff970e406c950b2576 (patch) | |
tree | 805e31d199b63e10eeb2017e880699ae3953f4e5 /tests/configs/base_config.py | |
parent | 4de3205afaac1fd11876b33675aa6f49c9632764 (diff) | |
download | gem5-7d7ab738622e7969a7db85ff970e406c950b2576.tar.xz |
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).
The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.
Diffstat (limited to 'tests/configs/base_config.py')
-rw-r--r-- | tests/configs/base_config.py | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py index 0cafacdda..16620c4dd 100644 --- a/tests/configs/base_config.py +++ b/tests/configs/base_config.py @@ -74,9 +74,10 @@ class BaseSystem(object): self.num_cpus = num_cpus self.checker = checker - def create_cpus(self): + def create_cpus(self, cpu_clk_domain): """Return a list of CPU objects to add to a system.""" - cpus = [ self.cpu_class(cpu_id=i, clock='2GHz') + cpus = [ self.cpu_class(clk_domain = cpu_clk_domain, + cpu_id=i) for i in range(self.num_cpus) ] if self.checker: for c in cpus: @@ -101,8 +102,9 @@ class BaseSystem(object): Returns: A bus that CPUs should use to connect to the shared cache. """ - system.toL2Bus = CoherentBus(clock='2GHz') - system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8) + system.toL2Bus = CoherentBus(clk_domain=system.cpu_clk_domain) + system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, + size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave return system.toL2Bus @@ -134,8 +136,8 @@ class BaseSystem(object): Arguments: system -- System to initialize. """ - system.clock = '1GHz' - system.cpu = self.create_cpus() + self.create_clk_src(system) + system.cpu = self.create_cpus(system.cpu_clk_domain) if _have_kvm_support and \ any([isinstance(c, BaseKvmCPU) for c in system.cpu]): @@ -145,6 +147,16 @@ class BaseSystem(object): for cpu in system.cpu: self.init_cpu(system, cpu, sha_bus) + def create_clk_src(self,system): + # Create system clock domain. This provides clock value to every + # clocked object that lies beneath it unless explicitly overwritten + # by a different clock domain. + system.clk_domain = SrcClockDomain(clock = '1GHz') + + # Create a seperate clock domain for components that should + # run at CPUs frequency + system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') + @abstractmethod def create_system(self): """Create an return an initialized system.""" @@ -244,8 +256,10 @@ class BaseFSSwitcheroo(BaseFSSystem): BaseFSSystem.__init__(self, **kwargs) self.cpu_classes = tuple(cpu_classes) - def create_cpus(self): - cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True) + def create_cpus(self, cpu_clk_domain): + cpus = [ cclass(clk_domain = cpu_clk_domain, + cpu_id=0, + switched_out=True) for cclass in self.cpu_classes ] cpus[0].switched_out = False return cpus |