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| author | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-09-25 11:49:41 -0500 |
|---|---|---|
| committer | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-09-25 11:49:41 -0500 |
| commit | 6fc0094337bc0356c55232c3850fb5fd2dab1f0c (patch) | |
| tree | f23261eb3f3a7e91b08505e68015941b1d04ba7c /tests/configs/memtest.py | |
| parent | 74ab69c7eafc2f0d187ce3ba7d6b9a59ba291b9f (diff) | |
| download | gem5-6fc0094337bc0356c55232c3850fb5fd2dab1f0c.tar.xz | |
Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.
Diffstat (limited to 'tests/configs/memtest.py')
| -rw-r--r-- | tests/configs/memtest.py | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index 57f45b1d4..f91a7eb78 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -34,7 +34,8 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = '1ns' + hit_latency = '1ns' + response_latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -46,7 +47,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = '10ns' + hit_latency = '10ns' + response_latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 |