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| author | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-09-25 11:49:41 -0500 |
|---|---|---|
| committer | Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> | 2012-09-25 11:49:41 -0500 |
| commit | 6fc0094337bc0356c55232c3850fb5fd2dab1f0c (patch) | |
| tree | f23261eb3f3a7e91b08505e68015941b1d04ba7c /tests/configs/pc-o3-timing.py | |
| parent | 74ab69c7eafc2f0d187ce3ba7d6b9a59ba291b9f (diff) | |
| download | gem5-6fc0094337bc0356c55232c3850fb5fd2dab1f0c.tar.xz | |
Cache: add a response latency to the caches
In the current caches the hit latency is paid twice on a miss. This patch lets
a configurable response latency be set of the cache for the backward path.
Diffstat (limited to 'tests/configs/pc-o3-timing.py')
| -rw-r--r-- | tests/configs/pc-o3-timing.py | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py index 2d3019daf..c3e705705 100644 --- a/tests/configs/pc-o3-timing.py +++ b/tests/configs/pc-o3-timing.py @@ -39,7 +39,8 @@ mem_size = '128MB' # ==================== class L1(BaseCache): - latency = '1ns' + hit_latency = '1ns' + response_latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 20 @@ -51,7 +52,8 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = '10ns' + hit_latency = '10ns' + response_latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -62,7 +64,8 @@ class L2(BaseCache): class PageTableWalkerCache(BaseCache): assoc = 2 block_size = 64 - latency = '1ns' + hit_latency = '1ns' + response_latency = '1ns' mshrs = 10 size = '1kB' tgts_per_mshr = 12 @@ -73,7 +76,8 @@ class PageTableWalkerCache(BaseCache): class IOCache(BaseCache): assoc = 8 block_size = 64 - latency = '50ns' + hit_latency = '50ns' + response_latency = '50ns' mshrs = 20 size = '1kB' tgts_per_mshr = 12 |