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author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-08-18 00:16:23 -0400 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-08-18 00:16:23 -0400 |
commit | 4e3164617ad709cb6d4b0f8fbbdfd596f4d6f236 (patch) | |
tree | 9d1e42532d876c646fb91d18b0f70803bb62fd9f /tests/configs/simple-timing.py | |
parent | 2b70b74c9bc575005a26fd727be26e11ac6db032 (diff) | |
download | gem5-4e3164617ad709cb6d4b0f8fbbdfd596f4d6f236.tar.xz |
Add caches in, fix cpu.mem param
--HG--
extra : convert_revision : 486283d83786807c72bb4601e4b9613b55d8802c
Diffstat (limited to 'tests/configs/simple-timing.py')
-rw-r--r-- | tests/configs/simple-timing.py | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 8be0c0b3b..9a5b20e88 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -37,8 +37,9 @@ class MyCache(BaseCache): tgts_per_mshr = 5 cpu = TimingSimpleCPU() -#cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), -# MyCache(size = '2MB')) +cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), + MyCache(size = '2MB')) +cpu.mem = cpu.dcache system = System(cpu = cpu, physmem = PhysicalMemory(), |