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authorKevin Lim <ktlim@umich.edu>2006-11-05 20:42:05 -0500
committerKevin Lim <ktlim@umich.edu>2006-11-05 20:42:05 -0500
commit257e09d62622676b84b5166854850024a5f72bcc (patch)
tree3a9adc891c83ae90e8fc00cbdf947d67d97d7b98 /tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
parent067c9c5531cb591aa7a2472ebbe366683fcfeb0d (diff)
downloadgem5-257e09d62622676b84b5166854850024a5f72bcc.tar.xz
Update refs.
--HG-- extra : convert_revision : 61d298fb0d9a66a76209a6bfcdb7c14f2efca947
Diffstat (limited to 'tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini')
-rw-r--r--tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini6
1 files changed, 2 insertions, 4 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
index f8e1f1bb0..d8fc14e8d 100644
--- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -64,7 +64,6 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.cpu.dcache
progress_interval=0
system=system
workload=system.cpu.workload
@@ -78,7 +77,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -118,7 +116,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -158,7 +155,6 @@ assoc=2
block_size=64
compressed_bus=false
compression_latency=0
-do_copy=false
hash_delay=1
hit_latency=1
latency=1
@@ -195,6 +191,7 @@ mem_side=system.membus.port[1]
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
@@ -217,6 +214,7 @@ uid=100
type=Bus
bus_id=0
clock=1000
+responder_set=false
width=64
port=system.physmem.port system.cpu.l2cache.mem_side