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authorGabe Black <gblack@eecs.umich.edu>2011-10-08 23:24:34 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-10-08 23:24:34 -0700
commit020e923ba7f027b7b3b18ccf8ac208c576d75b95 (patch)
tree1380a476d993ddf9895442114f03449ac88863b6 /tests
parentbfec60ad3a24a0977e9da2b052614c273918bd5d (diff)
downloadgem5-020e923ba7f027b7b3b18ccf8ac208c576d75b95.tar.xz
Configs: Use connectAllPorts to connect ports for simple-timing-ruby.
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/simple-timing-ruby.py3
1 files changed, 1 insertions, 2 deletions
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 1d67f6f97..d03b86068 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -82,8 +82,7 @@ assert(len(system.ruby._cpu_ruby_ports) == 1)
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
-cpu.icache_port = system.ruby._cpu_ruby_ports[0].port
-cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port
+cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
# -----------------------
# run simulation