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authorNilay Vaish <nilay@cs.wisc.edu>2014-02-23 19:16:16 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-02-23 19:16:16 -0600
commit7e27860ef4e5016f5a3c907fbe4c7858f83c8100 (patch)
tree24dddb6be57a6e5e959e91fc79eeac6a5c576703 /tests
parent5755fff99811a334874026c465ccebb9b0627230 (diff)
downloadgem5-7e27860ef4e5016f5a3c907fbe4c7858f83c8100.tar.xz
ruby: route all packets through ruby port
Currently, the interrupt controller in x86 is connected to the io bus directly. Therefore the packets between the io devices and the interrupt controller do not go through ruby. This patch changes ruby port so that these packets arrive at the ruby port first, which then routes them to their destination. Note that the patch does not make these packets go through the ruby network. That would happen in a subsequent patch.
Diffstat (limited to 'tests')
-rw-r--r--tests/configs/pc-simple-timing-ruby.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 57f9b6679..81ec2fa9b 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -82,9 +82,9 @@ for (i, cpu) in enumerate(system.cpu):
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
- cpu.interrupts.pio = system.piobus.master
- cpu.interrupts.int_master = system.piobus.slave
- cpu.interrupts.int_slave = system.piobus.master
+ cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master
+ cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave
+ cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master
# Set access_phys_mem to True for ruby port
system.ruby._cpu_ruby_ports[i].access_phys_mem = True