diff options
| -rw-r--r-- | src/arch/x86/isa/includes.isa | 1 | ||||
| -rw-r--r-- | src/arch/x86/isa/operands.isa | 15 |
2 files changed, 10 insertions, 6 deletions
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 58aef7b1d..f9e1e971c 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -111,6 +111,7 @@ output header {{ output decoder {{ #include "arch/x86/faults.hh" +#include "arch/x86/floatregs.hh" #include "arch/x86/miscregs.hh" #include "arch/x86/segmentregs.hh" #include "base/cprintf.hh" diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 3a557169f..347322752 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -92,7 +92,6 @@ def operand_types {{ 'uqw' : ('unsigned int', 64), 'sf' : ('float', 32), 'df' : ('float', 64), - 'qf' : ('float', 128) }}; def operands {{ @@ -103,10 +102,14 @@ def operands {{ 'DestReg': ('IntReg', 'uqw', '(((dest & 0x1C) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5), 'Data': ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6), 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7), - 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), - 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 11), - 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12), - 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20), - 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50), + 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20), + 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21), + 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22), + 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23), + 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), + 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), + 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), + 'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 60), + 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; |