diff options
155 files changed, 4974 insertions, 4223 deletions
diff --git a/SConstruct b/SConstruct index 06e1c3f16..89761a4f1 100755 --- a/SConstruct +++ b/SConstruct @@ -487,6 +487,7 @@ if main['GCC']: # Note CCVERSION doesn't work here because it is run with the CC # before we override it from the command line gcc_version = readCommand([main['CXX'], '-dumpversion'], exception=False) + main['GCC_VERSION'] = gcc_version if not compareVersions(gcc_version, '4.4.1') or \ not compareVersions(gcc_version, '4.4.2'): print 'Info: Tree vectorizer in GCC 4.4.1 & 4.4.2 is buggy, disabling.' diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 83e4cae5d..967570265 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -253,7 +253,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): self.flags_addr = self.realview.realview_io.pio_addr + 0x30 if mdesc.disk().count('android'): - boot_flags += "init=/init " + boot_flags += " init=/init " self.boot_osflags = boot_flags self.physmem.port = self.membus.port diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py index ba4671d6e..e6ac5f8c8 100644 --- a/configs/example/ruby_fs.py +++ b/configs/example/ruby_fs.py @@ -30,18 +30,18 @@ # Full system configuraiton for ruby # -import os import optparse +import os import sys from os.path import join as joinpath import m5 from m5.defines import buildEnv from m5.objects import * -from m5.util import addToPath, panic +from m5.util import addToPath, fatal if not buildEnv['FULL_SYSTEM']: - panic("This script requires full-system mode (*_FS).") + fatal("This script requires full-system mode (*_FS).") addToPath('../common') addToPath('../ruby') @@ -60,7 +60,9 @@ config_root = os.path.dirname(config_path) m5_root = os.path.dirname(config_root) parser = optparse.OptionParser() - +# System options +parser.add_option("--kernel", action="store", type="string") +parser.add_option("--script", action="store", type="string") # Benchmark options parser.add_option("-b", "--benchmark", action="store", type="string", dest="benchmark", @@ -117,9 +119,15 @@ elif buildEnv['TARGET_ISA'] == "x86": else: fatal("incapable of building non-alpha or non-x86 full system!") -Ruby.create_system(options, system, system.piobus, system._dma_devices) +if options.kernel is not None: + system.kernel = binary(options.kernel) + +if options.script is not None: + system.readfile = options.script system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)] +Ruby.create_system(options, system, system.piobus, system._dma_devices) + for (i, cpu) in enumerate(system.cpu): # diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index 9174709b4..e83e7f23f 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -40,6 +40,8 @@ def define_options(parser): help="the number of rows in the mesh topology") parser.add_option("--garnet-network", type="string", default=None, help="'fixed'|'flexible'") + parser.add_option("--network-fault-model", action="store_true", default=False, + help="enable network fault model: see src/mem/ruby/network/fault_model/") # ruby mapping options parser.add_option("--numa-high-bit", type="int", default=0, @@ -109,7 +111,13 @@ def create_system(options, system, piobus = None, dma_devices = []): print "Error: could not create topology %s" % options.topology raise - network = NetworkClass(ruby_system = ruby, topology = net_topology) + if options.network_fault_model: + assert(options.garnet_network == "fixed") + fault_model = FaultModel() + network = NetworkClass(ruby_system = ruby, topology = net_topology,\ + enable_fault_model=True, fault_model = fault_model) + else: + network = NetworkClass(ruby_system = ruby, topology = net_topology) # # Loop through the directory controlers. diff --git a/src/SConscript b/src/SConscript index 117f21394..0a4bb57f4 100755 --- a/src/SConscript +++ b/src/SConscript @@ -51,7 +51,7 @@ Export('env') build_env = [(opt, env[opt]) for opt in export_vars] -from m5.util import code_formatter +from m5.util import code_formatter, compareVersions ######################################################################## # Code for adding source files of various types @@ -449,7 +449,13 @@ sys.meta_path.remove(importer) sim_objects = m5.SimObject.allClasses all_enums = m5.params.allEnums -all_params = {} +# Find param types that need to be explicitly wrapped with swig. +# These will be recognized because the ParamDesc will have a +# swig_decl() method. Most param types are based on types that don't +# need this, either because they're based on native types (like Int) +# or because they're SimObjects (which get swigged independently). +# For now the only things handled here are VectorParam types. +params_to_swig = {} for name,obj in sorted(sim_objects.iteritems()): for param in obj._params.local.values(): # load the ptype attribute now because it depends on the @@ -461,8 +467,8 @@ for name,obj in sorted(sim_objects.iteritems()): if not hasattr(param, 'swig_decl'): continue pname = param.ptype_str - if pname not in all_params: - all_params[pname] = param + if pname not in params_to_swig: + params_to_swig[pname] = param ######################################################################## # @@ -523,24 +529,23 @@ PySource('m5', 'python/m5/info.py') # Create all of the SimObject param headers and enum headers # -def createSimObjectParam(target, source, env): +def createSimObjectParamStruct(target, source, env): assert len(target) == 1 and len(source) == 1 name = str(source[0].get_contents()) obj = sim_objects[name] code = code_formatter() - obj.cxx_decl(code) + obj.cxx_param_decl(code) code.write(target[0].abspath) -def createSwigParam(target, source, env): +def createParamSwigWrapper(target, source, env): assert len(target) == 1 and len(source) == 1 name = str(source[0].get_contents()) - param = all_params[name] + param = params_to_swig[name] code = code_formatter() - code('%module(package="m5.internal") $0_${name}', param.file_ext) param.swig_decl(code) code.write(target[0].abspath) @@ -554,7 +559,7 @@ def createEnumStrings(target, source, env): obj.cxx_def(code) code.write(target[0].abspath) -def createEnumParam(target, source, env): +def createEnumDecls(target, source, env): assert len(target) == 1 and len(source) == 1 name = str(source[0].get_contents()) @@ -564,25 +569,25 @@ def createEnumParam(target, source, env): obj.cxx_decl(code) code.write(target[0].abspath) -def createEnumSwig(target, source, env): +def createEnumSwigWrapper(target, source, env): assert len(target) == 1 and len(source) == 1 name = str(source[0].get_contents()) obj = all_enums[name] code = code_formatter() - code('''\ -%module(package="m5.internal") enum_$name + obj.swig_decl(code) + code.write(target[0].abspath) -%{ -#include "enums/$name.hh" -%} +def createSimObjectSwigWrapper(target, source, env): + name = source[0].get_contents() + obj = sim_objects[name] -%include "enums/$name.hh" -''') + code = code_formatter() + obj.swig_decl(code) code.write(target[0].abspath) -# Generate all of the SimObject param struct header files +# Generate all of the SimObject param C++ struct header files params_hh_files = [] for name,simobj in sorted(sim_objects.iteritems()): py_source = PySource.modules[simobj.__module__] @@ -591,16 +596,16 @@ for name,simobj in sorted(sim_objects.iteritems()): hh_file = File('params/%s.hh' % name) params_hh_files.append(hh_file) env.Command(hh_file, Value(name), - MakeAction(createSimObjectParam, Transform("SO PARAM"))) + MakeAction(createSimObjectParamStruct, Transform("SO PARAM"))) env.Depends(hh_file, depends + extra_deps) -# Generate any parameter header files needed +# Generate any needed param SWIG wrapper files params_i_files = [] -for name,param in all_params.iteritems(): - i_file = File('python/m5/internal/%s_%s.i' % (param.file_ext, name)) +for name,param in params_to_swig.iteritems(): + i_file = File('python/m5/internal/%s.i' % (param.swig_module_name())) params_i_files.append(i_file) env.Command(i_file, Value(name), - MakeAction(createSwigParam, Transform("SW PARAM"))) + MakeAction(createParamSwigWrapper, Transform("SW PARAM"))) env.Depends(i_file, depends) SwigSource('m5.internal', i_file) @@ -617,54 +622,22 @@ for name,enum in sorted(all_enums.iteritems()): hh_file = File('enums/%s.hh' % name) env.Command(hh_file, Value(name), - MakeAction(createEnumParam, Transform("EN PARAM"))) + MakeAction(createEnumDecls, Transform("ENUMDECL"))) env.Depends(hh_file, depends + extra_deps) i_file = File('python/m5/internal/enum_%s.i' % name) env.Command(i_file, Value(name), - MakeAction(createEnumSwig, Transform("ENUMSWIG"))) + MakeAction(createEnumSwigWrapper, Transform("ENUMSWIG"))) env.Depends(i_file, depends + extra_deps) SwigSource('m5.internal', i_file) -def buildParam(target, source, env): - name = source[0].get_contents() - obj = sim_objects[name] - class_path = obj.cxx_class.split('::') - classname = class_path[-1] - namespaces = class_path[:-1] - params = obj._params.local.values() - - code = code_formatter() - - code('%module(package="m5.internal") param_$name') - code() - code('%{') - code('#include "params/$obj.hh"') - for param in params: - param.cxx_predecls(code) - code('%}') - code() - - for param in params: - param.swig_predecls(code) - - code() - if obj._base: - code('%import "python/m5/internal/param_${{obj._base}}.i"') - code() - obj.swig_objdecls(code) - code() - - code('%include "params/$obj.hh"') - - code.write(target[0].abspath) - +# Generate SimObject SWIG wrapper files for name in sim_objects.iterkeys(): - params_file = File('python/m5/internal/param_%s.i' % name) - env.Command(params_file, Value(name), - MakeAction(buildParam, Transform("BLDPARAM"))) - env.Depends(params_file, depends) - SwigSource('m5.internal', params_file) + i_file = File('python/m5/internal/param_%s.i' % name) + env.Command(i_file, Value(name), + MakeAction(createSimObjectSwigWrapper, Transform("SO SWIG"))) + env.Depends(i_file, depends) + SwigSource('m5.internal', i_file) # Generate the main swig init file def makeEmbeddedSwigInit(target, source, env): @@ -687,7 +660,7 @@ for swig in SwigSource.all: MakeAction('$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' '-o ${TARGETS[0]} $SOURCES', Transform("SWIG"))) cc_file = str(swig.tnode) - init_file = '%s/init_%s.cc' % (dirname(cc_file), basename(cc_file)) + init_file = '%s/%s_init.cc' % (dirname(cc_file), basename(cc_file)) env.Command(init_file, Value(swig.module), MakeAction(makeEmbeddedSwigInit, Transform("EMBED SW"))) Source(init_file, **swig.guards) @@ -878,6 +851,9 @@ def makeEnv(label, objsfx, strip = False, **kwargs): swig_env.Append(CCFLAGS='-Wno-uninitialized') swig_env.Append(CCFLAGS='-Wno-sign-compare') swig_env.Append(CCFLAGS='-Wno-parentheses') + if compareVersions(env['GCC_VERSION'], '4.6.0') != -1: + swig_env.Append(CCFLAGS='-Wno-unused-label') + swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable') werror_env = new_env.Clone() werror_env.Append(CCFLAGS='-Werror') @@ -904,9 +880,10 @@ def makeEnv(label, objsfx, strip = False, **kwargs): return obj - sources = Source.get(main=False, skip_lib=False) - static_objs = [ make_obj(s, True) for s in sources ] - shared_objs = [ make_obj(s, False) for s in sources ] + static_objs = \ + [ make_obj(s, True) for s in Source.get(main=False, skip_lib=False) ] + shared_objs = \ + [ make_obj(s, False) for s in Source.get(main=False, skip_lib=False) ] static_date = make_obj(date_source, static=True, extra_deps=static_objs) static_objs.append(static_date) diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 9863a7370..4dcc58ffe 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -202,8 +202,6 @@ int break_ipl = -1; void ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) { - uint64_t old; - if (tc->misspeculating()) return; @@ -255,10 +253,9 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) case IPR_PALtemp23: // write entire quad w/ no side-effect - old = ipr[idx]; - ipr[idx] = val; if (tc->getKernelStats()) - tc->getKernelStats()->context(old, val, tc); + tc->getKernelStats()->context(ipr[idx], val, tc); + ipr[idx] = val; break; case IPR_DTB_PTE: diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index ed5128204..f286be91c 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -388,7 +388,7 @@ def template MiscExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Addr EA; + Addr EA M5_VAR_USED; Fault fault = NoFault; %(fp_enable_check)s; diff --git a/src/arch/alpha/linux/linux.hh b/src/arch/alpha/linux/linux.hh index c728ce1fb..3304816c3 100644 --- a/src/arch/alpha/linux/linux.hh +++ b/src/arch/alpha/linux/linux.hh @@ -69,6 +69,7 @@ class AlphaLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x10; + static const unsigned TGT_MAP_FIXED = 0x100; //@{ /// For getsysinfo(). diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index 637fbe065..4a3079264 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -126,7 +126,7 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize) stack_min = roundDown(stack_min, pageSize); stack_size = stack_base - stack_min; // map memory - pTable->allocate(stack_min, roundUp(stack_size, pageSize)); + allocateMem(stack_min, roundUp(stack_size, pageSize)); // map out initial stack contents Addr argv_array_base = stack_min + intSize; // room for argc diff --git a/src/arch/alpha/tru64/tru64.hh b/src/arch/alpha/tru64/tru64.hh index 0ee12973c..f0cad8289 100644 --- a/src/arch/alpha/tru64/tru64.hh +++ b/src/arch/alpha/tru64/tru64.hh @@ -64,6 +64,7 @@ class AlphaTru64 : public Tru64 /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x10; + static const unsigned TGT_MAP_FIXED = 0x100; //@{ /// For getsysinfo(). diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 812338c30..0cb27d7f1 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -561,20 +561,22 @@ let {{ } } case 0xa: + if (q) + return new Unknown(machInst); if (b) { - return decodeNeonUSThreeReg<VpminD, VpminQ>( - q, u, size, machInst, vd, vn, vm); + return decodeNeonUSThreeUSReg<VpminD>( + u, size, machInst, vd, vn, vm); } else { - return decodeNeonUSThreeReg<VpmaxD, VpmaxQ>( - q, u, size, machInst, vd, vn, vm); + return decodeNeonUSThreeUSReg<VpmaxD>( + u, size, machInst, vd, vn, vm); } case 0xb: if (b) { - if (u) { + if (u || q) { return new Unknown(machInst); } else { - return decodeNeonUThreeReg<NVpaddD, NVpaddQ>( - q, size, machInst, vd, vn, vm); + return decodeNeonUThreeUSReg<NVpaddD>( + size, machInst, vd, vn, vm); } } else { if (u) { @@ -1542,7 +1544,7 @@ let {{ else return new NVswpD<uint64_t>(machInst, vd, vm); case 0x1: - return decodeNeonUTwoMiscReg<NVtrnD, NVtrnQ>( + return decodeNeonUTwoMiscSReg<NVtrnD, NVtrnQ>( q, size, machInst, vd, vm); case 0x2: return decodeNeonUTwoMiscReg<NVuzpD, NVuzpQ>( diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index f82858bbd..b701995f4 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -447,7 +447,7 @@ let {{ exec_output = "" singleSimpleCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = (FPSCR) FpscrExc; + FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; FpDest = %(op)s; ''' singleCode = singleSimpleCode + ''' @@ -457,7 +457,7 @@ let {{ "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" doubleCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = (FPSCR) FpscrExc; + FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; double dest = %(op)s; FpDestP0_uw = dblLow(dest); FpDestP1_uw = dblHi(dest); diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 815d4c258..db36a3fff 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -563,15 +563,16 @@ let {{ let {{ exec_output = '' - for type in ('uint8_t', 'uint16_t', 'uint32_t'): + for typeSize in (8, 16, 32): for sRegs in 1, 2: - for dRegs in range(sRegs, 5): + for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, 5)): for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop", "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop", "MicroPackNeon%(dRegs)dto%(sRegs)dUop"): Name = format % { "sRegs" : sRegs * 2, "dRegs" : dRegs * 2 } - substDict = { "class_name" : Name, "targs" : type } + substDict = { "class_name" : Name, + "targs" : "uint%d_t" % typeSize } exec_output += MicroNeonExecDeclare.subst(substDict) }}; diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index 9565ee14a..b1ad1eeb3 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1616,10 +1616,8 @@ let {{ threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode) threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode) - threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes, + threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes, 2, vaddCode, pairwise=True) - threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes, - 4, vaddCode, pairwise=True) vaddlwCode = ''' destElem = (BigElement)srcElem1 + (BigElement)srcElem2; ''' @@ -2110,11 +2108,9 @@ let {{ ''' threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode) - threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True) - threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True) + threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True) - threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True) - threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True) + threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True) vqdmulhCode = ''' FPSCR fpscr = (FPSCR) FpscrQc; @@ -3137,8 +3133,10 @@ let {{ destReg.elements[i + 1] = mid; } ''' - twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode) - twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode) + twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", + smallUnsignedTypes, 2, vtrnCode) + twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", + smallUnsignedTypes, 4, vtrnCode) vuzpCode = ''' Element mid[eCount]; diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index a00114409..a4a740f89 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -1112,7 +1112,7 @@ def template LoadRegConstructor {{ (IntRegIndex)_index) { %(constructor)s; - bool conditional = false; + bool conditional M5_VAR_USED = false; if (!(condCode == COND_AL || condCode == COND_UC)) { conditional = true; for (int x = 0; x < _numDestRegs; x++) { @@ -1166,7 +1166,7 @@ def template LoadImmConstructor {{ (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) { %(constructor)s; - bool conditional = false; + bool conditional M5_VAR_USED = false; if (!(condCode == COND_AL || condCode == COND_UC)) { conditional = true; for (int x = 0; x < _numDestRegs; x++) { diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh index 33e48fc93..40d586aaf 100644 --- a/src/arch/arm/linux/linux.hh +++ b/src/arch/arm/linux/linux.hh @@ -91,6 +91,7 @@ class ArmLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// For getrusage(). diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc index f17749252..c65962d00 100644 --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -503,7 +503,7 @@ void ArmLinuxProcess::initState() { ArmLiveProcess::initState(); - pTable->allocate(commPage, PageBytes); + allocateMem(commPage, PageBytes); ThreadContext *tc = system->getThreadContext(contextIds[0]); uint8_t swiNeg1[] = { diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index c3b02744e..aa5d7dfce 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -251,8 +251,7 @@ ArmLiveProcess::argsInit(int intSize, int pageSize) stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents uint32_t sentry_base = stack_base - sentry_size; diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 25b470972..193f050de 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -497,8 +497,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + FP_Base_DepTag); - data = insertBits(data, top_bit, - bottom_bit, Rt); + data = insertBits(data, MT_H ? 63 : 31, + MT_H ? 32 : 0, Rt); xc->setRegOtherThread(RD + FP_Base_DepTag, data); }}); @@ -532,7 +532,7 @@ decode OPCODE_HI default Unknown::unknown() { panic("FP Control Value (%d) " "Not Available. Ignoring " "Access to Floating Control " - "Status Register", FS); + "S""tatus Register", FS); } xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); }}); @@ -776,7 +776,6 @@ decode OPCODE_HI default Unknown::unknown() { bits(pageGrain, pageGrain.esp) == 1) { SP = 1; } - IndexReg index = Index; Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); }}); 0x06: tlbwr({{ @@ -842,7 +841,6 @@ decode OPCODE_HI default Unknown::unknown() { bits(pageGrain, pageGrain.esp) == 1) { SP = 1; } - IndexReg index = Index; Ptr->insertAt(newEntry, Random, SP); }}); diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 1944d69d3..41f94e129 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -107,7 +107,7 @@ def template ThreadRegisterExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - int64_t data; + int64_t data M5_VAR_USED; %(op_decl)s; %(op_rd)s; @@ -126,17 +126,6 @@ def template ThreadRegisterExecute {{ } else if (vpeControl.targTC > mvpConf0.ptc) { data = -1; } else { - int top_bit = 0; - int bottom_bit = 0; - - if (MT_H == 1) { - top_bit = 63; - bottom_bit = 32; - } else { - top_bit = 31; - bottom_bit = 0; - } - %(code)s; } } else { @@ -203,10 +192,11 @@ def format MT_MFTR(code, *flags) {{ flags += ('IsNonSpeculative', ) # code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code - code += 'if (MT_H == 1) {\n' - code += 'data = bits(data, top_bit, bottom_bit);\n' - code += '}\n' - code += 'Rd = data;\n' + code += ''' + if (MT_H) + data = bits(data, 63, 32); + Rd = data; + ''' iop = InstObjParams(name, Name, 'MTOp', code, flags) header_output = BasicDeclare.subst(iop) diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa index 944254d90..d2e9c797e 100644 --- a/src/arch/mips/isa/includes.isa +++ b/src/arch/mips/isa/includes.isa @@ -52,7 +52,9 @@ output decoder {{ #include "arch/mips/faults.hh" #include "arch/mips/isa_traits.hh" #include "arch/mips/mt_constants.hh" +#include "arch/mips/pagetable.hh" #include "arch/mips/pra_constants.hh" +#include "arch/mips/tlb.hh" #include "arch/mips/utility.hh" #include "base/loader/symtab.hh" #include "base/cprintf.hh" diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh index a2418cfb6..949cce8aa 100644 --- a/src/arch/mips/linux/linux.hh +++ b/src/arch/mips/linux/linux.hh @@ -65,6 +65,7 @@ class MipsLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x800; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// For getsysinfo(). diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index c62b60b98..5643ff18a 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -136,7 +136,7 @@ MipsLiveProcess::argsInit(int pageSize) stack_min = roundDown(stack_min, pageSize); stack_size = stack_base - stack_min; // map memory - pTable->allocate(stack_min, roundUp(stack_size, pageSize)); + allocateMem(stack_min, roundUp(stack_size, pageSize)); // map out initial stack contents IntType argv_array_base = stack_min + intSize; // room for argc diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index 52e13dfc3..057fb5e76 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -129,7 +129,6 @@ int TLB::probeEntry(Addr vpn, uint8_t asn) const { // assume not found... - PTE *retval = NULL; int Ind = -1; PageTable::const_iterator i = lookupTable.find(vpn); if (i != lookupTable.end()) { @@ -144,7 +143,6 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const if (((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid))) { // We have a VPN + ASID Match - retval = pte; Ind = index; break; } diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index 0361ee998..a409eefac 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -123,7 +123,7 @@ def template LoadCompleteAcc {{ %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Addr EA; + Addr M5_VAR_USED EA; Fault fault = NoFault; %(op_decl)s; diff --git a/src/arch/power/linux/linux.hh b/src/arch/power/linux/linux.hh index 1bfc9cbd8..45ca048a0 100644 --- a/src/arch/power/linux/linux.hh +++ b/src/arch/power/linux/linux.hh @@ -127,6 +127,7 @@ class PowerLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// ioctl() command codes. diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc index d12e3eab6..788c7cc0c 100644 --- a/src/arch/power/process.cc +++ b/src/arch/power/process.cc @@ -187,8 +187,7 @@ PowerLiveProcess::argsInit(int intSize, int pageSize) stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents uint32_t sentry_base = stack_base - sentry_size; diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc index d9be7fa69..2148e875a 100644 --- a/src/arch/power/tlb.cc +++ b/src/arch/power/tlb.cc @@ -119,7 +119,6 @@ int TLB::probeEntry(Addr vpn,uint8_t asn) const { // assume not found... - PowerISA::PTE *retval = NULL; int Ind = -1; PageTable::const_iterator i = lookupTable.find(vpn); if (i != lookupTable.end()) { @@ -133,7 +132,6 @@ TLB::probeEntry(Addr vpn,uint8_t asn) const && (pte->G || (asn == pte->asid))) { // We have a VPN + ASID Match - retval = pte; Ind = index; break; } diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index d6eee8a4d..a77059181 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -326,8 +326,8 @@ let {{ ''' TruncateEA = ''' - if (!FullSystem) - EA = Pstate<3:> ? EA<31:0> : EA; + if (!FullSystem) + EA = Pstate<3:> ? EA<31:0> : EA; ''' }}; diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh index 1f7567d43..8ac408812 100644 --- a/src/arch/sparc/linux/linux.hh +++ b/src/arch/sparc/linux/linux.hh @@ -77,6 +77,7 @@ class SparcLinux : public Linux static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; typedef struct { int64_t uptime; /* Seconds since boot */ diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 3eee3d137..5c594dcbc 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -316,8 +316,7 @@ SparcLiveProcess::argsInit(int pageSize) stack_size = stack_base - stack_min; // Allocate space for the stack - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents IntType sentry_base = stack_base - sentry_size; diff --git a/src/arch/sparc/solaris/solaris.hh b/src/arch/sparc/solaris/solaris.hh index df2565027..8222addab 100644 --- a/src/arch/sparc/solaris/solaris.hh +++ b/src/arch/sparc/solaris/solaris.hh @@ -59,6 +59,7 @@ class SparcSolaris : public Solaris static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x100; + static const unsigned TGT_MAP_FIXED = 0x10; }; #endif diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py index 9fc3e9035..68031c76c 100644 --- a/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py @@ -67,18 +67,22 @@ def macroop ADD_P_I def macroop ADD_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop ADD_LOCKED_P_I { rdip t7 limm t2, imm + mfence ldstl t1, seg, riprel, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADD_M_R @@ -98,17 +102,21 @@ def macroop ADD_P_R def macroop ADD_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop ADD_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADD_R_M @@ -168,18 +176,22 @@ def macroop SUB_P_I def macroop SUB_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop SUB_LOCKED_P_I { rdip t7 limm t2, imm + mfence ldstl t1, seg, riprel, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop SUB_M_R @@ -199,17 +211,21 @@ def macroop SUB_P_R def macroop SUB_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop SUB_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADC_R_R @@ -243,18 +259,22 @@ def macroop ADC_P_I def macroop ADC_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop ADC_LOCKED_P_I { rdip t7 limm t2, imm + mfence ldstl t1, seg, riprel, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADC_M_R @@ -274,17 +294,21 @@ def macroop ADC_P_R def macroop ADC_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop ADC_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop ADC_R_M @@ -344,18 +368,22 @@ def macroop SBB_P_I def macroop SBB_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop SBB_LOCKED_P_I { rdip t7 limm t2, imm + mfence ldstl t1, seg, riprel, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop SBB_M_R @@ -375,17 +403,21 @@ def macroop SBB_P_R def macroop SBB_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop SBB_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop NEG_R @@ -410,16 +442,20 @@ def macroop NEG_P def macroop NEG_LOCKED_M { + mfence ldstl t1, seg, sib, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) stul t1, seg, sib, disp + mfence }; def macroop NEG_LOCKED_P { rdip t7 + mfence ldstl t1, seg, riprel, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) stul t1, seg, riprel, disp + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py index f27cd7008..515082d64 100644 --- a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py @@ -58,17 +58,21 @@ def macroop INC_P def macroop INC_LOCKED_M { + mfence ldstl t1, seg, sib, disp addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) stul t1, seg, sib, disp + mfence }; def macroop INC_LOCKED_P { rdip t7 + mfence ldstl t1, seg, riprel, disp addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) stul t1, seg, riprel, disp + mfence }; def macroop DEC_R @@ -93,16 +97,20 @@ def macroop DEC_P def macroop DEC_LOCKED_M { + mfence ldstl t1, seg, sib, disp subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) stul t1, seg, sib, disp + mfence }; def macroop DEC_LOCKED_P { rdip t7 + mfence ldstl t1, seg, riprel, disp subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) stul t1, seg, riprel, disp + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py index 66eb0f8a2..f69e1dc48 100644 --- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py @@ -114,10 +114,12 @@ def macroop BTC_LOCKED_M_I { limm t1, imm, dataSize=asz limm t4, 1 roli t4, t4, imm + mfence ldstl t1, seg, sib, disp sexti t0, t1, imm, flags=(CF,) xor t1, t1, t4 stul t1, seg, sib, disp + mfence }; def macroop BTC_LOCKED_P_I { @@ -125,10 +127,12 @@ def macroop BTC_LOCKED_P_I { limm t1, imm, dataSize=asz limm t4, 1 roli t4, t4, imm + mfence ldstl t1, seg, riprel, disp sexti t0, t1, imm, flags=(CF,) xor t1, t1, t4 stul t1, seg, riprel, disp + mfence }; def macroop BTC_R_R { @@ -168,10 +172,12 @@ def macroop BTC_LOCKED_M_R { lea t3, flatseg, [dsz, t3, base], dataSize=asz limm t4, 1 rol t4, t4, reg + mfence ldstl t1, seg, [scale, index, t3], disp sext t0, t1, reg, flags=(CF,) xor t1, t1, t4 stul t1, seg, [scale, index, t3], disp + mfence }; def macroop BTC_LOCKED_P_R { @@ -180,10 +186,12 @@ def macroop BTC_LOCKED_P_R { srai t3, t2, ldsz, dataSize=asz limm t4, 1 rol t4, t4, reg + mfence ldstl t1, seg, [dsz, t3, t7], disp sext t0, t1, reg, flags=(CF,) xor t1, t1, t4 stul t1, seg, [dsz, t3, t7], disp + mfence }; def macroop BTR_R_I { @@ -218,10 +226,12 @@ def macroop BTR_LOCKED_M_I { limm t1, imm, dataSize=asz limm t4, "(uint64_t(-(2ULL)))" roli t4, t4, imm + mfence ldstl t1, seg, sib, disp sexti t0, t1, imm, flags=(CF,) and t1, t1, t4 stul t1, seg, sib, disp + mfence }; def macroop BTR_LOCKED_P_I { @@ -229,10 +239,12 @@ def macroop BTR_LOCKED_P_I { limm t1, imm, dataSize=asz limm t4, "(uint64_t(-(2ULL)))" roli t4, t4, imm + mfence ldstl t1, seg, riprel, disp sexti t0, t1, imm, flags=(CF,) and t1, t1, t4 stul t1, seg, riprel, disp + mfence }; def macroop BTR_R_R { @@ -272,10 +284,12 @@ def macroop BTR_LOCKED_M_R { lea t3, flatseg, [dsz, t3, base], dataSize=asz limm t4, "(uint64_t(-(2ULL)))" rol t4, t4, reg + mfence ldstl t1, seg, [scale, index, t3], disp sext t0, t1, reg, flags=(CF,) and t1, t1, t4 stul t1, seg, [scale, index, t3], disp + mfence }; def macroop BTR_LOCKED_P_R { @@ -284,10 +298,12 @@ def macroop BTR_LOCKED_P_R { srai t3, t2, ldsz, dataSize=asz limm t4, "(uint64_t(-(2ULL)))" rol t4, t4, reg + mfence ldstl t1, seg, [dsz, t3, t7], disp sext t0, t1, reg, flags=(CF,) and t1, t1, t4 stul t1, seg, [dsz, t3, t7], disp + mfence }; def macroop BTS_R_I { @@ -322,10 +338,12 @@ def macroop BTS_LOCKED_M_I { limm t1, imm, dataSize=asz limm t4, 1 roli t4, t4, imm + mfence ldstl t1, seg, sib, disp sexti t0, t1, imm, flags=(CF,) or t1, t1, t4 stul t1, seg, sib, disp + mfence }; def macroop BTS_LOCKED_P_I { @@ -333,10 +351,12 @@ def macroop BTS_LOCKED_P_I { limm t1, imm, dataSize=asz limm t4, 1 roli t4, t4, imm + mfence ldstl t1, seg, riprel, disp sexti t0, t1, imm, flags=(CF,) or t1, t1, t4 stul t1, seg, riprel, disp + mfence }; def macroop BTS_R_R { @@ -377,10 +397,12 @@ def macroop BTS_LOCKED_M_R { lea t3, flatseg, [dsz, t3, base], dataSize=asz limm t4, 1 rol t4, t4, reg + mfence ldstl t1, seg, [scale, index, t3], disp sext t0, t1, reg, flags=(CF,) or t1, t1, t4 stul t1, seg, [scale, index, t3], disp + mfence }; def macroop BTS_LOCKED_P_R { @@ -390,9 +412,11 @@ def macroop BTS_LOCKED_P_R { lea t3, flatseg, [dsz, t3, base], dataSize=asz limm t4, 1 rol t4, t4, reg + mfence ldstl t1, seg, [1, t3, t7], disp sext t0, t1, reg, flags=(CF,) or t1, t1, t4 stul t1, seg, [1, t3, t7], disp + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py index 6504b5ab4..1518ce5e0 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py @@ -50,46 +50,58 @@ def macroop XCHG_R_R def macroop XCHG_R_M { + mfence ldstl t1, seg, sib, disp stul reg, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XCHG_R_P { rdip t7 + mfence ldstl t1, seg, riprel, disp stul reg, seg, riprel, disp + mfence mov reg, reg, t1 }; def macroop XCHG_M_R { + mfence ldstl t1, seg, sib, disp stul reg, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XCHG_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp stul reg, seg, riprel, disp + mfence mov reg, reg, t1 }; def macroop XCHG_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp stul reg, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XCHG_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp stul reg, seg, riprel, disp + mfence mov reg, reg, t1 }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/logical.py b/src/arch/x86/isa/insts/general_purpose/logical.py index b8d442a02..49dea86e5 100644 --- a/src/arch/x86/isa/insts/general_purpose/logical.py +++ b/src/arch/x86/isa/insts/general_purpose/logical.py @@ -61,18 +61,22 @@ def macroop OR_P_I def macroop OR_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop OR_LOCKED_P_I { limm t2, imm rdip t7 + mfence ldstl t1, seg, riprel, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop OR_M_R @@ -92,17 +96,21 @@ def macroop OR_P_R def macroop OR_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop OR_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop OR_R_M @@ -155,18 +163,22 @@ def macroop XOR_P_I def macroop XOR_LOCKED_M_I { limm t2, imm + mfence ldstl t1, seg, sib, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop XOR_LOCKED_P_I { limm t2, imm rdip t7 + mfence ldstl t1, seg, riprel, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop XOR_M_R @@ -186,17 +198,21 @@ def macroop XOR_P_R def macroop XOR_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop XOR_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop XOR_R_M @@ -255,19 +271,23 @@ def macroop AND_P_I def macroop AND_LOCKED_M_I { + mfence ldstl t2, seg, sib, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) stul t2, seg, sib, disp + mfence }; def macroop AND_LOCKED_P_I { rdip t7 + mfence ldstl t2, seg, riprel, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) stul t2, seg, riprel, disp + mfence }; def macroop AND_M_R @@ -287,17 +307,21 @@ def macroop AND_P_R def macroop AND_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, sib, disp + mfence }; def macroop AND_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) stul t1, seg, riprel, disp + mfence }; def macroop NOT_R @@ -326,17 +350,21 @@ def macroop NOT_P def macroop NOT_LOCKED_M { limm t1, -1 + mfence ldstl t2, seg, sib, disp xor t2, t2, t1 stul t2, seg, sib, disp + mfence }; def macroop NOT_LOCKED_P { limm t1, -1 rdip t7 + mfence ldstl t2, seg, riprel, disp xor t2, t2, t1 stul t2, seg, riprel, disp + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/semaphores.py b/src/arch/x86/isa/insts/general_purpose/semaphores.py index 072e28de6..17bee7fb7 100644 --- a/src/arch/x86/isa/insts/general_purpose/semaphores.py +++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py @@ -62,21 +62,25 @@ def macroop CMPXCHG_P_R { }; def macroop CMPXCHG_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) mov t1, t1, reg, flags=(CZF,) stul t1, seg, sib, disp + mfence mov rax, rax, t1, flags=(nCZF,) }; def macroop CMPXCHG_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) mov t1, t1, reg, flags=(CZF,) stul t1, seg, riprel, disp + mfence mov rax, rax, t1, flags=(nCZF,) }; @@ -96,17 +100,21 @@ def macroop XADD_P_R { }; def macroop XADD_LOCKED_M_R { + mfence ldstl t1, seg, sib, disp add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t2, seg, sib, disp + mfence mov reg, reg, t1 }; def macroop XADD_LOCKED_P_R { rdip t7 + mfence ldstl t1, seg, riprel, disp add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) stul t2, seg, riprel, disp + mfence mov reg, reg, t1 }; diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index 664f91860..5798ac4b0 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -59,7 +59,8 @@ let {{ ''' + generatorNameTemplate + '''(StaticInstPtr curMacroop) { static const char *macrocodeBlock = romMnemonic; - static const ExtMachInst dummyExtMachInst; + static const ExtMachInst dummyExtMachInst = \ + X86ISA::NoopMachInst; static const EmulEnv dummyEmulEnv(0, 0, 1, 1, 1); Macroop * macroop = dynamic_cast<Macroop *>(curMacroop.get()); diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 52420f175..5c242e2c9 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -1,4 +1,5 @@ // Copyright (c) 2007-2008 The Hewlett-Packard Development Company +// Copyright (c) 2011 Mark D. Hill and David A. Wood // All rights reserved. // // The license below extends only to copyright in the software and shall @@ -203,3 +204,55 @@ let {{ microopClasses["halt"] = Halt }}; + +def template MicroFenceOpDeclare {{ + class %(class_name)s : public X86ISA::X86MicroopBase + { + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + uint64_t setFlags); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroFenceOpConstructor {{ + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, uint64_t setFlags) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + setFlags, %(op_class)s) + { + %(constructor)s; + } +}}; + +let {{ + class MfenceOp(X86Microop): + def __init__(self): + self.className = "Mfence" + self.mnemonic = "mfence" + self.instFlags = "| (1ULL << StaticInst::IsMemBarrier)" + + def getAllocator(self, microFlags): + allocString = ''' + (StaticInstPtr)(new %(class_name)s(machInst, + macrocodeBlock, %(flags)s)) + ''' + allocator = allocString % { + "class_name" : self.className, + "mnemonic" : self.mnemonic, + "flags" : self.microFlagsText(microFlags) + self.instFlags} + return allocator + + microopClasses["mfence"] = MfenceOp +}}; + +let {{ + # Build up the all register version of this micro op + iop = InstObjParams("mfence", "Mfence", 'X86MicroopBase', + {"code" : ""}) + header_output += MicroFenceOpDeclare.subst(iop) + decoder_output += MicroFenceOpConstructor.subst(iop) + exec_output += BasicExecute.subst(iop) +}}; diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh index 99b09f405..4e5d43d45 100644 --- a/src/arch/x86/linux/linux.hh +++ b/src/arch/x86/linux/linux.hh @@ -88,6 +88,7 @@ class X86Linux64 : public Linux static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; typedef struct { uint64_t iov_base; // void * @@ -158,6 +159,7 @@ class X86Linux32 : public Linux static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; typedef struct { int32_t uptime; /* Seconds since boot */ diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 79a140776..f5ba787c9 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -167,7 +167,7 @@ X86_64LiveProcess::initState() argsInit(sizeof(uint64_t), VMPageSize); // Set up the vsyscall page for this process. - pTable->allocate(vsyscallPage.base, vsyscallPage.size); + allocateMem(vsyscallPage.base, vsyscallPage.size); uint8_t vtimeBlob[] = { 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax 0x0f,0x05, // syscall @@ -265,7 +265,7 @@ I386LiveProcess::initState() * Set up a GDT for this process. The whole GDT wouldn't really be for * this process, but the only parts we care about are. */ - pTable->allocate(_gdtStart, _gdtSize); + allocateMem(_gdtStart, _gdtSize); uint64_t zero = 0; assert(_gdtSize % sizeof(zero) == 0); for (Addr gdtCurrent = _gdtStart; @@ -274,7 +274,7 @@ I386LiveProcess::initState() } // Set up the vsyscall page for this process. - pTable->allocate(vsyscallPage.base, vsyscallPage.size); + allocateMem(vsyscallPage.base, vsyscallPage.size); uint8_t vsyscallBlob[] = { 0x51, // push %ecx 0x52, // push %edp @@ -577,8 +577,7 @@ X86LiveProcess::argsInit(int pageSize, stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents IntType sentry_base = stack_base - sentry_size; diff --git a/src/base/inet.cc b/src/base/inet.cc index 0fb864dab..7d7eb3f5a 100644 --- a/src/base/inet.cc +++ b/src/base/inet.cc @@ -30,6 +30,7 @@ * Gabe Black */ +#include <cstddef> #include <cstdio> #include <sstream> #include <string> diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 8a755a4bf..6e2de0baf 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -234,8 +234,7 @@ BaseCPU::startup() if (params()->progress_interval) { Tick num_ticks = ticks(params()->progress_interval); - Event *event; - event = new CPUProgressEvent(this, num_ticks); + new CPUProgressEvent(this, num_ticks); } } diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 9d6ecc7e1..010bdb512 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -206,7 +206,6 @@ InOrderCPU::InOrderCPU(Params *params) lastRunningCycle(0), instsPerSwitch(0) { - ThreadID active_threads; cpu_params = params; resPool = new ResourcePool(this, params); @@ -214,6 +213,7 @@ InOrderCPU::InOrderCPU(Params *params) // Resize for Multithreading CPUs thread.resize(numThreads); + ThreadID active_threads = params->workload.size(); if (FullSystem) { active_threads = 1; } else { @@ -1110,7 +1110,6 @@ InOrderCPU::updateThreadPriority() //DEFAULT TO ROUND ROBIN SCHEME //e.g. Move highest priority to end of thread list list<ThreadID>::iterator list_begin = activeThreads.begin(); - list<ThreadID>::iterator list_end = activeThreads.end(); unsigned high_thread = *list_begin; diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc index 5e4c978a6..75d30c894 100644 --- a/src/cpu/legiontrace.cc +++ b/src/cpu/legiontrace.cc @@ -158,7 +158,7 @@ Trace::LegionTraceRecord::dump() bool diffTnpc = false; bool diffTstate = false; bool diffTt = false; - bool diffTba = false; + bool diffTba M5_VAR_USED = false; bool diffHpstate = false; bool diffHtstate = false; bool diffHtba = false; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 16e78f8ec..bb5ccc17e 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1639,7 +1639,6 @@ FullO3CPU<Impl>::updateThreadPriority() //DEFAULT TO ROUND ROBIN SCHEME //e.g. Move highest priority to end of thread list list<ThreadID>::iterator list_begin = activeThreads.begin(); - list<ThreadID>::iterator list_end = activeThreads.end(); unsigned high_thread = *list_begin; diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 6dbafb56c..4106bbef9 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -1214,24 +1214,16 @@ template <class Impl> void DefaultRename<Impl>::readFreeEntries(ThreadID tid) { - bool updated = false; - if (fromIEW->iewInfo[tid].usedIQ) { - freeEntries[tid].iqEntries = - fromIEW->iewInfo[tid].freeIQEntries; - updated = true; - } + if (fromIEW->iewInfo[tid].usedIQ) + freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; - if (fromIEW->iewInfo[tid].usedLSQ) { - freeEntries[tid].lsqEntries = - fromIEW->iewInfo[tid].freeLSQEntries; - updated = true; - } + if (fromIEW->iewInfo[tid].usedLSQ) + freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; if (fromCommit->commitInfo[tid].usedROB) { freeEntries[tid].robEntries = fromCommit->commitInfo[tid].freeROBEntries; emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; - updated = true; } DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", diff --git a/src/cpu/testers/rubytest/Check.hh b/src/cpu/testers/rubytest/Check.hh index 6861a74d3..db1485548 100644 --- a/src/cpu/testers/rubytest/Check.hh +++ b/src/cpu/testers/rubytest/Check.hh @@ -37,7 +37,6 @@ #include "mem/protocol/TesterStatus.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" class SubBlock; diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index 3c64e2717..62e4a9c37 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -75,6 +75,18 @@ PioDevice::init() pioPort->sendStatusChange(Port::RangeChange); } +Port * +PioDevice::getPort(const std::string &if_name, int idx) +{ + if (if_name == "pio") { + if (pioPort != NULL) + fatal("%s: pio port already connected to %s", + name(), pioPort->getPeer()->name()); + pioPort = new PioPort(this, sys); + return pioPort; + } + return NULL; +} unsigned int PioDevice::drain(Event *de) @@ -349,3 +361,19 @@ DmaDevice::~DmaDevice() if (dmaPort) delete dmaPort; } + + +Port * +DmaDevice::getPort(const std::string &if_name, int idx) +{ + if (if_name == "dma") { + if (dmaPort != NULL) + fatal("%s: dma port already connected to %s", + name(), dmaPort->getPeer()->name()); + dmaPort = new DmaPort(this, sys, params()->min_backoff_delay, + params()->max_backoff_delay); + return dmaPort; + } + return PioDevice::getPort(if_name, idx); +} + diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index bdafc34a0..a92402bfe 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -209,17 +209,8 @@ class PioDevice : public MemObject virtual unsigned int drain(Event *de); - virtual Port *getPort(const std::string &if_name, int idx = -1) - { - if (if_name == "pio") { - if (pioPort != NULL) - fatal("%s: pio port already connected to %s", - name(), pioPort->getPeer()->name()); - pioPort = new PioPort(this, sys); - return pioPort; - } else - return NULL; - } + virtual Port *getPort(const std::string &if_name, int idx = -1); + friend class PioPort; }; @@ -285,24 +276,7 @@ class DmaDevice : public PioDevice unsigned cacheBlockSize() const { return dmaPort->cacheBlockSize(); } - virtual Port *getPort(const std::string &if_name, int idx = -1) - { - if (if_name == "pio") { - if (pioPort != NULL) - fatal("%s: pio port already connected to %s", - name(), pioPort->getPeer()->name()); - pioPort = new PioPort(this, sys); - return pioPort; - } else if (if_name == "dma") { - if (dmaPort != NULL) - fatal("%s: dma port already connected to %s", - name(), dmaPort->getPeer()->name()); - dmaPort = new DmaPort(this, sys, params()->min_backoff_delay, - params()->max_backoff_delay); - return dmaPort; - } else - return NULL; - } + virtual Port *getPort(const std::string &if_name, int idx = -1); friend class DmaPort; }; diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc index 9397a599b..b0aaf6e64 100644 --- a/src/dev/mc146818.cc +++ b/src/dev/mc146818.cc @@ -217,7 +217,7 @@ MC146818::serialize(const string &base, ostream &os) // Tick rtcTimerInterruptTickOffset = event.when() - curTick(); SERIALIZE_SCALAR(rtcTimerInterruptTickOffset); - Tick rtcClockTickOffset = event.when() - curTick(); + Tick rtcClockTickOffset = tickEvent.when() - curTick(); SERIALIZE_SCALAR(rtcClockTickOffset); } diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh index d56b32cf0..8b8091f0d 100644 --- a/src/kern/tru64/tru64.hh +++ b/src/kern/tru64/tru64.hh @@ -557,7 +557,7 @@ class Tru64 : public OperatingSystem stack_base, stack_size); // map memory - process->pTable->allocate(rounded_stack_base, rounded_stack_size); + process->allocateMem(rounded_stack_base, rounded_stack_size); argp->address = gtoh(rounded_stack_base); argp.copyOut(tc->getMemPort()); @@ -676,7 +676,7 @@ class Tru64 : public OperatingSystem // Register this as a valid address range with the process base_addr = roundDown(base_addr, VMPageSize); int size = cur_addr - base_addr; - process->pTable->allocate(base_addr, roundUp(size, VMPageSize)); + process->allocateMem(base_addr, roundUp(size, VMPageSize)); config.copyOut(tc->getMemPort()); slot_state.copyOut(tc->getMemPort()); diff --git a/src/mem/SConscript b/src/mem/SConscript index da37edb57..2aa7d0323 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -65,10 +65,11 @@ DebugFlag('RubyMemory') DebugFlag('RubyNetwork') DebugFlag('RubyPort') DebugFlag('RubyQueue') +DebugFlag('RubySequencer') DebugFlag('RubySlicc') DebugFlag('RubyStorebuffer') DebugFlag('RubyTester') CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester', - 'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache', - 'RubyMemory', 'RubyDma', 'RubyPort']) + 'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache', + 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer']) diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index 113ad8b4d..71c3ba48c 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -393,10 +393,8 @@ IIC::freeReplacementBlock(PacketList & writebacks) unsigned long IIC::getFreeDataBlock(PacketList & writebacks) { - struct IICTag *tag_ptr; unsigned long data_ptr; - tag_ptr = NULL; /* find data block */ while (blkFreelist.empty()) { freeReplacementBlock(writebacks); diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index c260ba2d4..0ec2dbc07 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -45,16 +45,14 @@ #include "debug/MMU.hh" #include "mem/page_table.hh" #include "sim/faults.hh" -#include "sim/process.hh" #include "sim/sim_object.hh" -#include "sim/system.hh" using namespace std; using namespace TheISA; -PageTable::PageTable(Process *_process, Addr _pageSize) +PageTable::PageTable(const std::string &__name, uint64_t _pid, Addr _pageSize) : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))), - process(_process) + pid(_pid), _name(__name) { assert(isPowerOf2(pageSize)); pTableCache[0].vaddr = 0; @@ -67,24 +65,20 @@ PageTable::~PageTable() } void -PageTable::allocate(Addr vaddr, int64_t size) +PageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber) { // starting address must be page aligned assert(pageOffset(vaddr) == 0); DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); - for (; size > 0; size -= pageSize, vaddr += pageSize) { - PTableItr iter = pTable.find(vaddr); - - if (iter != pTable.end()) { + for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) { + if (!clobber && (pTable.find(vaddr) != pTable.end())) { // already mapped - fatal("PageTable::allocate: address 0x%x already mapped", - vaddr); + fatal("PageTable::allocate: address 0x%x already mapped", vaddr); } - pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr, - process->system->new_page()); + pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr); updateCache(vaddr, pTable[vaddr]); } } @@ -111,11 +105,11 @@ PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) } void -PageTable::deallocate(Addr vaddr, int64_t size) +PageTable::unmap(Addr vaddr, int64_t size) { assert(pageOffset(vaddr) == 0); - DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size); + DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size); for (; size > 0; size -= pageSize, vaddr += pageSize) { PTableItr iter = pTable.find(vaddr); @@ -128,6 +122,21 @@ PageTable::deallocate(Addr vaddr, int64_t size) } bool +PageTable::isUnmapped(Addr vaddr, int64_t size) +{ + // starting address must be page aligned + assert(pageOffset(vaddr) == 0); + + for (; size > 0; size -= pageSize, vaddr += pageSize) { + if (pTable.find(vaddr) != pTable.end()) { + return false; + } + } + + return true; +} + +bool PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry) { Addr page_addr = pageAlign(vaddr); @@ -196,7 +205,7 @@ PageTable::serialize(std::ostream &os) PTableItr iter = pTable.begin(); PTableItr end = pTable.end(); while (iter != end) { - os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n"; + os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n"; paramOut(os, "vaddr", iter->first); iter->second.serialize(os); @@ -219,9 +228,9 @@ PageTable::unserialize(Checkpoint *cp, const std::string §ion) TheISA::TlbEntry *entry; Addr vaddr; - paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr); + paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr); entry = new TheISA::TlbEntry(); - entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i)); + entry->unserialize(cp, csprintf("%s.Entry%d", name(), i)); pTable[vaddr] = *entry; ++i; } diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index 61da5f322..b1b5227be 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -46,8 +46,6 @@ #include "mem/request.hh" #include "sim/serialize.hh" -class Process; - /** * Page Table Declaration. */ @@ -68,20 +66,33 @@ class PageTable const Addr pageSize; const Addr offsetMask; - Process *process; + const uint64_t pid; + const std::string _name; public: - PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize); + PageTable(const std::string &__name, uint64_t _pid, + Addr _pageSize = TheISA::VMPageSize); ~PageTable(); + // for DPRINTF compatibility + const std::string name() const { return _name; } + Addr pageAlign(Addr a) { return (a & ~offsetMask); } Addr pageOffset(Addr a) { return (a & offsetMask); } - void allocate(Addr vaddr, int64_t size); + void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false); void remap(Addr vaddr, int64_t size, Addr new_vaddr); - void deallocate(Addr vaddr, int64_t size); + void unmap(Addr vaddr, int64_t size); + + /** + * Check if any pages in a region are already allocated + * @param vaddr The starting virtual address of the region. + * @param size The length of the region. + * @return True if no pages in the region are mapped. + */ + bool isUnmapped(Addr vaddr, int64_t size); /** * Lookup function diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index b2ba0872e..f0be1fd34 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -679,6 +679,17 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") mandatoryQueue_in.recycle(); } + action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") { + peek(mandatoryQueue_in, RubyRequest) { + L1IcacheMemory.profileMiss(in_msg); + } + } + + action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") { + peek(mandatoryQueue_in, RubyRequest) { + L1DcacheMemory.profileMiss(in_msg); + } + } //***************************************************** // TRANSITIONS @@ -698,6 +709,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") oo_allocateL1DCacheBlock; i_allocateTBE; a_issueGETS; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -705,6 +717,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") pp_allocateL1ICacheBlock; i_allocateTBE; ai_issueGETINSTR; + uu_profileInstMiss; k_popMandatoryQueue; } @@ -712,6 +725,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") oo_allocateL1DCacheBlock; i_allocateTBE; b_issueGETX; + uu_profileDataMiss; k_popMandatoryQueue; } @@ -729,6 +743,7 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") transition(S, Store, SM) { i_allocateTBE; c_issueUPGRADE; + uu_profileDataMiss; k_popMandatoryQueue; } diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm index a8fcb07d1..2d8ae4ca8 100644 --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm @@ -716,9 +716,25 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } } + GenericRequestType convertToGenericType(CoherenceRequestType type) { + if(type == CoherenceRequestType:GETS) { + return GenericRequestType:GETS; + } else if(type == CoherenceRequestType:GETX) { + return GenericRequestType:GETX; + } else if(type == CoherenceRequestType:GET_INSTR) { + return GenericRequestType:GET_INSTR; + } else if(type == CoherenceRequestType:UPGRADE) { + return GenericRequestType:UPGRADE; + } else { + DPRINTF(RubySlicc, "%s\n", type); + error("Invalid CoherenceRequestType\n"); + } + } + action(uu_profileMiss, "\u", desc="Profile the demand miss") { peek(L1RequestIntraChipL2Network_in, RequestMsg) { - //profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, L1CacheMachIDToProcessorNum(in_msg.Requestor)); + L2cacheMemory.profileGenericRequest(convertToGenericType(in_msg.Type), + in_msg.AccessMode, in_msg.Prefetch); } } diff --git a/src/mem/protocol/MESI_CMP_directory.slicc b/src/mem/protocol/MESI_CMP_directory.slicc index 07b55620b..37ac0a424 100644 --- a/src/mem/protocol/MESI_CMP_directory.slicc +++ b/src/mem/protocol/MESI_CMP_directory.slicc @@ -5,4 +5,3 @@ include "MESI_CMP_directory-L1cache.sm"; include "MESI_CMP_directory-L2cache.sm"; include "MESI_CMP_directory-dir.sm"; include "MESI_CMP_directory-dma.sm"; -include "standard_CMP-protocol.sm"; diff --git a/src/mem/protocol/MI_example.slicc b/src/mem/protocol/MI_example.slicc index 00508673b..70614787a 100644 --- a/src/mem/protocol/MI_example.slicc +++ b/src/mem/protocol/MI_example.slicc @@ -4,4 +4,3 @@ include "MI_example-msg.sm"; include "MI_example-cache.sm"; include "MI_example-dir.sm"; include "MI_example-dma.sm"; -include "standard_1level_CMP-protocol.sm"; diff --git a/src/mem/protocol/MOESI_CMP_directory.slicc b/src/mem/protocol/MOESI_CMP_directory.slicc index 199ea174d..0bba349b5 100644 --- a/src/mem/protocol/MOESI_CMP_directory.slicc +++ b/src/mem/protocol/MOESI_CMP_directory.slicc @@ -5,4 +5,3 @@ include "MOESI_CMP_directory-L2cache.sm"; include "MOESI_CMP_directory-L1cache.sm"; include "MOESI_CMP_directory-dma.sm"; include "MOESI_CMP_directory-dir.sm"; -include "standard_CMP-protocol.sm"; diff --git a/src/mem/protocol/MOESI_CMP_token.slicc b/src/mem/protocol/MOESI_CMP_token.slicc index 9818561d6..5bc3a5700 100644 --- a/src/mem/protocol/MOESI_CMP_token.slicc +++ b/src/mem/protocol/MOESI_CMP_token.slicc @@ -5,4 +5,3 @@ include "MOESI_CMP_token-L1cache.sm"; include "MOESI_CMP_token-L2cache.sm"; include "MOESI_CMP_token-dir.sm"; include "MOESI_CMP_token-dma.sm"; -include "standard_CMP-protocol.sm"; diff --git a/src/mem/protocol/MOESI_hammer.slicc b/src/mem/protocol/MOESI_hammer.slicc index 66d217c9c..ab8eb730a 100644 --- a/src/mem/protocol/MOESI_hammer.slicc +++ b/src/mem/protocol/MOESI_hammer.slicc @@ -4,4 +4,3 @@ include "MOESI_hammer-msg.sm"; include "MOESI_hammer-cache.sm"; include "MOESI_hammer-dir.sm"; include "MOESI_hammer-dma.sm"; -include "standard_1level_CMP-protocol.sm"; diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm index 3c777e965..4f6f0e3d1 100644 --- a/src/mem/protocol/RubySlicc_ComponentMapping.sm +++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm @@ -30,34 +30,12 @@ // Mapping functions int machineCount(MachineType machType); - -// NodeID map_address_to_node(Address addr); MachineID mapAddressToRange(Address addr, MachineType type, int low, int high); NetDest broadcast(MachineType type); MachineID map_Address_to_DMA(Address addr); MachineID map_Address_to_Directory(Address addr); NodeID map_Address_to_DirectoryNode(Address addr); - - -MachineID getL1MachineID(NodeID L1RubyNode); -NodeID getChipID(MachineID L2machID); -MachineID getCollectorDest(MachineID L1machID); -MachineID getCollectorL1Cache(MachineID colID); -NetDest getMultiStaticL2BankNetDest(Address addr, Set sharers); -bool isL1OnChip(MachineID L1machID, NodeID L2NodeID); -bool isL2OnChip(MachineID L2machID, NodeID L2NodeID); - -int getNumBanksInBankSet(); NodeID machineIDToNodeID(MachineID machID); NodeID machineIDToVersion(MachineID machID); MachineType machineIDToMachineType(MachineID machID); -NodeID L1CacheMachIDToProcessorNum(MachineID machID); -NodeID L2CacheMachIDToChipID(MachineID machID); -Set getOtherLocalL1IDs(MachineID L1); -Set getLocalL1IDs(MachineID L1); -Set getExternalL1IDs(MachineID L1); -NetDest getAllPertinentL2Banks(Address addr); -bool isLocalProcessor(MachineID thisId, MachineID tarId); - GenericMachineType ConvertMachToGenericMach(MachineType machType); - diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index a2f8abfaa..cc404394d 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -48,7 +48,7 @@ structure(InPort, external = "yes", primitive="yes") { bool isEmpty(); } -external_type(NodeID, default="0"); +external_type(NodeID, default="0", primitive="yes"); external_type(MachineID); MessageBuffer getMandatoryQueue(int core_id); diff --git a/src/mem/protocol/standard_1level_CMP-protocol.sm b/src/mem/protocol/standard_1level_CMP-protocol.sm deleted file mode 100644 index 34da6201f..000000000 --- a/src/mem/protocol/standard_1level_CMP-protocol.sm +++ /dev/null @@ -1,40 +0,0 @@ - -/* - * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * $Id$ - */ - -// global protocol features -global(Protocol, desc="Global properties of this protocol", - interface = "AbstractProtocol") { - bool TwoLevelCache := false; - bool CMP := true; -} - diff --git a/src/mem/protocol/standard_CMP-protocol.sm b/src/mem/protocol/standard_CMP-protocol.sm deleted file mode 100644 index dbd7e4ef5..000000000 --- a/src/mem/protocol/standard_CMP-protocol.sm +++ /dev/null @@ -1,36 +0,0 @@ - -/* - * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -// global protocol features -global(Protocol, desc="Global properties of this protocol", - interface = "AbstractProtocol") { - bool TwoLevelCache := true; - bool CMP := true; -} - diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript index 64dd83bb0..06f6abd9f 100644 --- a/src/mem/ruby/SConscript +++ b/src/mem/ruby/SConscript @@ -109,7 +109,6 @@ MakeInclude('system/DirectoryMemory.hh') MakeInclude('system/MachineID.hh') MakeInclude('system/MemoryControl.hh') MakeInclude('system/WireBuffer.hh') -MakeInclude('system/NodeID.hh') MakeInclude('system/PerfectCacheMemory.hh') MakeInclude('system/PersistentTable.hh') MakeInclude('system/Sequencer.hh') diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh index 4a9a3adb2..7ab3d1251 100644 --- a/src/mem/ruby/common/Address.hh +++ b/src/mem/ruby/common/Address.hh @@ -33,8 +33,7 @@ #include <iomanip> #include "base/hashmap.hh" -#include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" +#include "mem/ruby/common/TypeDefines.hh" const int ADDRESS_WIDTH = 64; // address width in bytes diff --git a/src/mem/ruby/common/DataBlock.hh b/src/mem/ruby/common/DataBlock.hh index 1d6abcfee..7bd92710d 100644 --- a/src/mem/ruby/common/DataBlock.hh +++ b/src/mem/ruby/common/DataBlock.hh @@ -32,7 +32,7 @@ #include <iomanip> #include <iostream> -#include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/TypeDefines.hh" class DataBlock { diff --git a/src/mem/ruby/common/Driver.hh b/src/mem/ruby/common/Driver.hh index 8d687ef4f..477b90927 100644 --- a/src/mem/ruby/common/Driver.hh +++ b/src/mem/ruby/common/Driver.hh @@ -34,7 +34,6 @@ #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Consumer.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" class Driver { diff --git a/src/mem/ruby/common/Global.hh b/src/mem/ruby/common/Global.hh index 357825465..cae7cb16b 100644 --- a/src/mem/ruby/common/Global.hh +++ b/src/mem/ruby/common/Global.hh @@ -29,16 +29,7 @@ #ifndef __MEM_RUBY_COMMON_GLOBAL_HH__ #define __MEM_RUBY_COMMON_GLOBAL_HH__ -// external includes for all classes -#include "mem/ruby/common/TypeDefines.hh" - -// simple type declarations -typedef Time LogicalTime; -typedef int64 Index; // what the address bit ripper returns -typedef int word; // one word of a cache line -typedef unsigned int uint; -typedef int SwitchID; -typedef int LinkID; +#include "base/str.hh" class RubyEventQueue; extern RubyEventQueue* g_eventQueue_ptr; diff --git a/src/mem/ruby/common/Histogram.hh b/src/mem/ruby/common/Histogram.hh index 81cfbd477..bfc0e4293 100644 --- a/src/mem/ruby/common/Histogram.hh +++ b/src/mem/ruby/common/Histogram.hh @@ -32,7 +32,7 @@ #include <iostream> #include <vector> -#include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/TypeDefines.hh" class Histogram { diff --git a/src/mem/ruby/common/NetDest.hh b/src/mem/ruby/common/NetDest.hh index 8006045d8..5ad1b6100 100644 --- a/src/mem/ruby/common/NetDest.hh +++ b/src/mem/ruby/common/NetDest.hh @@ -42,7 +42,6 @@ #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Set.hh" #include "mem/ruby/system/MachineID.hh" -#include "mem/ruby/system/NodeID.hh" class NetDest { diff --git a/src/mem/ruby/common/Set.hh b/src/mem/ruby/common/Set.hh index b76c3409d..ea10b83f1 100644 --- a/src/mem/ruby/common/Set.hh +++ b/src/mem/ruby/common/Set.hh @@ -36,7 +36,6 @@ #include <limits> #include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/System.hh" class Set diff --git a/src/mem/ruby/common/TypeDefines.hh b/src/mem/ruby/common/TypeDefines.hh index 2e8d308e2..233c9146a 100644 --- a/src/mem/ruby/common/TypeDefines.hh +++ b/src/mem/ruby/common/TypeDefines.hh @@ -44,4 +44,9 @@ typedef long long integer_t; typedef int64 Time; typedef uint64 physical_address_t; +typedef int64 Index; // what the address bit ripper returns +typedef int LinkID; +typedef int NodeID; +typedef int SwitchID; + #endif diff --git a/src/mem/ruby/eventqueue/RubyEventQueue.hh b/src/mem/ruby/eventqueue/RubyEventQueue.hh index 3e2bc3f89..20b44362a 100644 --- a/src/mem/ruby/eventqueue/RubyEventQueue.hh +++ b/src/mem/ruby/eventqueue/RubyEventQueue.hh @@ -59,7 +59,7 @@ #include <iostream> #include "config/no_vector_bounds_checks.hh" -#include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/TypeDefines.hh" #include "sim/eventq.hh" class Consumer; diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh index 309560921..157849149 100644 --- a/src/mem/ruby/network/Network.hh +++ b/src/mem/ruby/network/Network.hh @@ -47,7 +47,6 @@ #include "mem/protocol/LinkDirection.hh" #include "mem/protocol/MessageSizeType.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/System.hh" #include "params/RubyNetwork.hh" #include "sim/sim_object.hh" diff --git a/src/mem/ruby/network/Topology.hh b/src/mem/ruby/network/Topology.hh index 7b7439686..e8510f810 100644 --- a/src/mem/ruby/network/Topology.hh +++ b/src/mem/ruby/network/Topology.hh @@ -45,8 +45,7 @@ #include <vector> #include "mem/protocol/LinkDirection.hh" -#include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" +#include "mem/ruby/common/TypeDefines.hh" #include "params/Topology.hh" #include "sim/sim_object.hh" diff --git a/src/mem/ruby/network/fault_model/FaultModel.cc b/src/mem/ruby/network/fault_model/FaultModel.cc new file mode 100644 index 000000000..195f7c66c --- /dev/null +++ b/src/mem/ruby/network/fault_model/FaultModel.cc @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2011 Massachusetts Institute of Technology + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Konstantinos Aisopos + */ + +/* + * Official Tool Website: www.mit.edu/~kaisopos/FaultModel + * + * If you use our tool for academic research, we request that you cite: + * Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling + * System-Level Modeling of Variation-Induced Faults in Networks-on-Chip. + * Proceedings of the 48th Design Automation Conference (DAC'11) + */ + +// C includes +#include <assert.h> +#include <stdio.h> + +// C++ includes +#include <fstream> +#include <iostream> +#include <vector> + +// GEM5 includes +#include "FaultModel.hh" +#include "base/misc.hh" + +#define MAX(a,b) ((a > b) ? (a) : (b)) + + +FaultModel::FaultModel(const Params *p) : SimObject(p) +{ + // read configurations into "configurations" vector + // format: <buff/vc> <vcs> <10 fault types> + bool more_records = true; + for (int i = 0; more_records; i += (fields_per_conf_record)){ + system_conf configuration; + configuration.buff_per_vc = + p->baseline_fault_vector_database[i + conf_record_buff_per_vc]; + configuration.vcs = + p->baseline_fault_vector_database[i + conf_record_vcs]; + for (int fault_index = 0; fault_index < number_of_fault_types; + fault_index++){ + configuration.fault_type[fault_index] = + p->baseline_fault_vector_database[i + + conf_record_first_fault_type + fault_index] / 100; + } + configurations.push_back(configuration); + if (p->baseline_fault_vector_database[i+fields_per_conf_record] < 0){ + more_records = false; + } + } + + // read temperature weights into "temperature_weights" vector + // format: <temperature> <weight> + more_records = true; + for (int i = 0; more_records; i += (fields_per_temperature_record)){ + int record_temperature = + p->temperature_weights_database[i + temperature_record_temp]; + int record_weight = + p->temperature_weights_database[i + temperature_record_weight]; + static int first_record = true; + if (first_record){ + for (int temperature = 0; temperature < record_temperature; + temperature++){ + temperature_weights.push_back(0); + } + first_record = false; + } + assert(record_temperature == temperature_weights.size()); + temperature_weights.push_back(record_weight); + if (p->temperature_weights_database[i + + fields_per_temperature_record] < 0){ + more_records = false; + } + } +} + +string +FaultModel::fault_type_to_string(int ft) +{ + if (ft == data_corruption__few_bits){ + return "data_corruption__few_bits"; + } else if (ft == data_corruption__all_bits){ + return "data_corruption__all_bits"; + } else if (ft == flit_conservation__flit_duplication){ + return "flit_conservation__flit_duplication"; + } else if (ft == flit_conservation__flit_loss_or_split){ + return "flit_conservation__flit_loss_or_split"; + } else if (ft == misrouting){ + return "misrouting"; + } else if (ft == credit_conservation__credit_generation){ + return "credit_conservation__credit_generation"; + } else if (ft == credit_conservation__credit_loss){ + return "credit_conservation__credit_loss"; + } else if (ft == erroneous_allocation__VC){ + return "erroneous_allocation__VC"; + } else if (ft == erroneous_allocation__switch){ + return "erroneous_allocation__switch"; + } else if (ft == unfair_arbitration){ + return "unfair_arbitration"; + } else if (ft == number_of_fault_types){ + return "none"; + } else { + return "none"; + } +} + + +int +FaultModel::declare_router(int number_of_inputs, + int number_of_outputs, + int number_of_vcs_per_input, + int number_of_buff_per_data_vc, + int number_of_buff_per_ctrl_vc) +{ + // check inputs (are they legal?) + if (number_of_inputs <= 0 || number_of_outputs <= 0 || + number_of_vcs_per_input <= 0 || number_of_buff_per_data_vc <= 0 || + number_of_buff_per_ctrl_vc <= 0){ + fatal("Fault Model: ERROR in argument of FaultModel_declare_router!"); + } + int number_of_buffers_per_vc = MAX(number_of_buff_per_data_vc, + number_of_buff_per_ctrl_vc); + int total_vcs = number_of_inputs * number_of_vcs_per_input; + if (total_vcs > MAX_VCs){ + fatal("Fault Model: ERROR! Number inputs*VCs (MAX_VCs) unsupported"); + } + if (number_of_buffers_per_vc > MAX_BUFFERS_per_VC){ + fatal("Fault Model: ERROR! buffers/VC (MAX_BUFFERS_per_VC) too high"); + } + + // link the router to a DB record + int record_hit = -1; + for (int record = 0; record < configurations.size(); record++){ + if ((configurations[record].buff_per_vc == number_of_buffers_per_vc)&& + (configurations[record].vcs == total_vcs)){ + record_hit = record; + } + } + if (record_hit == -1){ + panic("Fault Model: ERROR! configuration not found in DB. BUG?"); + } + + // remember the router and return its ID + routers.push_back(configurations[record_hit]); + static int router_index = 0; + return router_index++; +} + +bool +FaultModel::fault_vector(int routerID, + int temperature_input, + float fault_vector[]) +{ + bool ok = true; + + // is the routerID recorded? + if (routerID < 0 || routerID >= ((int) routers.size())){ + warn("Fault Model: ERROR! unknown router ID argument."); + fatal("Fault Model: Did you enable the fault model flag)?"); + } + + // is the temperature too high/too low? + int temperature = temperature_input; + if (temperature_input >= ((int) temperature_weights.size())){ + ok = false; + warn_once("Fault Model: Temperature exceeded simulated upper bound."); + warn_once("Fault Model: The fault model is not accurate any more."); + temperature = (temperature_weights.size() - 1); + } else if (temperature_input < 0){ + ok = false; + warn_once("Fault Model: Temperature exceeded simulated lower bound."); + warn_once("Fault Model: The fault model is not accurate any more."); + temperature = 0; + } + + // recover the router record and return its fault vector + for (int i = 0; i < number_of_fault_types; i++){ + fault_vector[i] = routers[routerID].fault_type[i] * + ((float)temperature_weights[temperature]); + } + return ok; +} + +bool +FaultModel::fault_prob(int routerID, + int temperature_input, + float *aggregate_fault_prob) +{ + *aggregate_fault_prob = 1.0; + bool ok = true; + + // is the routerID recorded? + if (routerID < 0 || routerID >= ((int) routers.size())){ + warn("Fault Model: ERROR! unknown router ID argument."); + fatal("Fault Model: Did you enable the fault model flag)?"); + } + + // is the temperature too high/too low? + int temperature = temperature_input; + if (temperature_input >= ((int) temperature_weights.size()) ){ + ok = false; + warn_once("Fault Model: Temperature exceeded simulated upper bound."); + warn_once("Fault Model: The fault model is not accurate any more."); + temperature = (temperature_weights.size()-1); + } else if (temperature_input < 0){ + ok = false; + warn_once("Fault Model: Temperature exceeded simulated lower bound."); + warn_once("Fault Model: The fault model is not accurate any more."); + temperature = 0; + } + + // recover the router record and return its aggregate fault probability + for (int i = 0; i < number_of_fault_types; i++){ + *aggregate_fault_prob= *aggregate_fault_prob * + ( 1.0 - (routers[routerID].fault_type[i] * + ((float)temperature_weights[temperature])) ); + } + *aggregate_fault_prob = 1.0 - *aggregate_fault_prob; + return ok; +} + +// this function is used only for debugging purposes +void +FaultModel::print(void) +{ + cout << "--- PRINTING configurations ---\n"; + for (int record = 0; record < configurations.size(); record++){ + cout << "(" << record << ") "; + cout << "VCs=" << configurations[record].vcs << " "; + cout << "Buff/VC=" << configurations[record].buff_per_vc << " ["; + for (int fault_type_num = 0; + fault_type_num < number_of_fault_types; + fault_type_num++){ + cout << (100 * configurations[record].fault_type[fault_type_num]); + cout << "% "; + } + cout << "]\n"; + } + cout << "--- PRINTING temperature weights ---\n"; + for (int record = 0; record < temperature_weights.size(); record++){ + cout << "temperature=" << record << " => "; + cout << "weight=" << temperature_weights[record]; + cout << "\n"; + } +} + +FaultModel * +FaultModelParams::create() +{ + return new FaultModel(this); +} diff --git a/src/mem/ruby/network/fault_model/FaultModel.hh b/src/mem/ruby/network/fault_model/FaultModel.hh new file mode 100644 index 000000000..12a3f3844 --- /dev/null +++ b/src/mem/ruby/network/fault_model/FaultModel.hh @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2011 Massachusetts Institute of Technology + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Konstantinos Aisopos + */ + +/* + * Official Tool Website: www.mit.edu/~kaisopos/FaultModel + * + * If you use our tool for academic research, we request that you cite: + * Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling + * System-Level Modeling of Variation-Induced Faults in Networks-on-Chip. + * Proceedings of the 48th Design Automation Conference (DAC'11) + */ + +#ifndef __MEM_RUBY_NETWORK_FAULT_MODEL_HH__ +#define __MEM_RUBY_NETWORK_FAULT_MODEL_HH__ + +// tool limitations and fixed inputs +#define MAX_VCs 40 +#define MAX_BUFFERS_per_VC 5 +#define BASELINE_TEMPERATURE_CELCIUS 71 + +// C++ includes +#include <string> +using namespace std; + +// GEM5 includes +#include "params/FaultModel.hh" +#include "sim/sim_object.hh" + +class FaultModel : public SimObject +{ + public: + typedef FaultModelParams Params; + FaultModel(const Params *p); + const Params *params() const { return (const Params *)_params; } + + /************************************************************************/ + /********** THE FAULT TYPES SUPPORTED BY THE FAULT MODEL ***************/ + /************************************************************************/ + + enum fault_type + { + data_corruption__few_bits, + data_corruption__all_bits, + flit_conservation__flit_duplication, + flit_conservation__flit_loss_or_split, + misrouting, + credit_conservation__credit_generation, + credit_conservation__credit_loss, + erroneous_allocation__VC, + erroneous_allocation__switch, + unfair_arbitration, + number_of_fault_types + }; + + /************************************************************************/ + /******************** INTERFACE OF THE FAULT MODEL *********************/ + /************************************************************************/ + + enum conf_record_format + { + conf_record_buff_per_vc, + conf_record_vcs, + conf_record_first_fault_type, + conf_record_last_fault_type = conf_record_first_fault_type + number_of_fault_types - 1, + fields_per_conf_record + }; + + enum temperature_record_format + { + temperature_record_temp, + temperature_record_weight, + fields_per_temperature_record + }; + + struct system_conf + { + int vcs; + int buff_per_vc; + float fault_type[number_of_fault_types]; + }; + + int declare_router(int number_of_inputs, + int number_of_outputs, + int number_of_vcs_per_vnet, + int number_of_buff_per_data_vc, + int number_of_buff_per_ctrl_vc); + + string fault_type_to_string(int fault_type_index); + + // the following 2 functions are called at runtime, to get the probability + // of each fault type (fault_vector) or the aggregate fault probability + // (fault_prob). Note: the probability values are provided by reference + // (in the variables fault_vector[] & aggregate_fault_prob respectively). + // Both functions also return a success flag (which is always true if + // temperature ranges from 0C to 125C) + + bool fault_vector(int routerID, + int temperature, + float fault_vector[]); + + bool fault_prob(int routerID, + int temperature, + float *aggregate_fault_prob); + + // for debugging purposes + + void print(void); + + private: + vector <system_conf> configurations; + vector <system_conf> routers; + vector <int> temperature_weights; +}; + +#endif // __MEM_RUBY_NETWORK_FAULT_MODEL_HH__ diff --git a/src/mem/ruby/network/fault_model/FaultModel.py b/src/mem/ruby/network/fault_model/FaultModel.py new file mode 100644 index 000000000..5117491f2 --- /dev/null +++ b/src/mem/ruby/network/fault_model/FaultModel.py @@ -0,0 +1,302 @@ +# Copyright (c) 2011 Massachusetts Institute of Technology +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Konstantinos Aisopos + +# Official Tool Website: www.mit.edu/~kaisopos/FaultModel +# +# If you use our tool for academic research, we request that you cite: +# Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling +# System-Level Modeling of Variation-Induced Faults in Networks-on-Chip. +# Proceedings of the 48th Design Automation Conference (DAC'11) + +from m5.params import * +from m5.SimObject import SimObject + +class FaultModel(SimObject): + type = 'FaultModel' + cxx_class = 'FaultModel' + + baseline_fault_vector_database = VectorParam.Float([ + 5, 40, 0.080892, 0.109175, 0.018864, 0.130408, 0.059724, 0.077571, 0.034830, 0.083430, 0.067500, 0.121500, + 5, 39, 0.062640, 0.089100, 0.016821, 0.109620, 0.051462, 0.060210, 0.029700, 0.076140, 0.062100, 0.116100, + 5, 38, 0.050490, 0.076950, 0.015782, 0.091530, 0.044550, 0.046170, 0.025920, 0.070200, 0.057294, 0.110700, + 5, 37, 0.042120, 0.067770, 0.014191, 0.082890, 0.040986, 0.037800, 0.023760, 0.065880, 0.053568, 0.104490, + 5, 36, 0.035910, 0.061020, 0.013211, 0.075600, 0.035100, 0.030240, 0.021060, 0.061560, 0.049815, 0.100710, + 5, 35, 0.032130, 0.054810, 0.011964, 0.071550, 0.031860, 0.026730, 0.019710, 0.057510, 0.047169, 0.094230, + 5, 34, 0.028890, 0.051030, 0.011054, 0.067500, 0.030510, 0.023450, 0.018630, 0.054000, 0.045900, 0.088290, + 5, 33, 0.026460, 0.047250, 0.010160, 0.062640, 0.028971, 0.021600, 0.017280, 0.049410, 0.042903, 0.082080, + 5, 32, 0.024300, 0.042930, 0.009312, 0.057780, 0.027000, 0.019710, 0.016470, 0.045360, 0.041310, 0.075600, + 5, 31, 0.022410, 0.037260, 0.008910, 0.054540, 0.024732, 0.018171, 0.015660, 0.043470, 0.039447, 0.070740, + 5, 30, 0.021870, 0.032130, 0.008162, 0.050220, 0.023625, 0.016762, 0.013770, 0.039150, 0.037557, 0.065880, + 5, 29, 0.020790, 0.028080, 0.007657, 0.042660, 0.020061, 0.016043, 0.012690, 0.036720, 0.035451, 0.062370, + 5, 28, 0.019440, 0.025650, 0.007123, 0.037800, 0.018900, 0.015363, 0.011880, 0.033480, 0.032400, 0.057780, + 5, 27, 0.018473, 0.023760, 0.006737, 0.034830, 0.018036, 0.014153, 0.011232, 0.030240, 0.030645, 0.055890, + 5, 26, 0.017550, 0.021330, 0.006440, 0.032130, 0.016497, 0.013511, 0.010031, 0.027621, 0.028242, 0.051030, + 5, 25, 0.016462, 0.020520, 0.006210, 0.028890, 0.015822, 0.013095, 0.009442, 0.021600, 0.026379, 0.046170, + 5, 24, 0.015930, 0.018360, 0.005940, 0.026730, 0.015047, 0.012377, 0.008918, 0.018360, 0.023193, 0.037800, + 5, 23, 0.015390, 0.017931, 0.005594, 0.025488, 0.013365, 0.012037, 0.008775, 0.015120, 0.018657, 0.031590, + 5, 22, 0.014804, 0.017167, 0.005338, 0.023976, 0.012258, 0.011734, 0.008087, 0.013500, 0.015444, 0.026190, + 5, 21, 0.014180, 0.016548, 0.004995, 0.022194, 0.011807, 0.011073, 0.007236, 0.011070, 0.013500, 0.021870, + 5, 20, 0.013743, 0.016176, 0.004613, 0.020414, 0.011070, 0.010415, 0.006220, 0.010415, 0.010800, 0.019077, + 5, 19, 0.011877, 0.015412, 0.003861, 0.016659, 0.008235, 0.008640, 0.005400, 0.009720, 0.008532, 0.013770, + 5, 18, 0.011097, 0.014310, 0.003483, 0.014526, 0.006912, 0.007560, 0.003780, 0.008640, 0.006885, 0.010260, + 5, 17, 0.010419, 0.011939, 0.002700, 0.011394, 0.005400, 0.006318, 0.003038, 0.008100, 0.005400, 0.009450, + 5, 16, 0.009887, 0.009720, 0.002395, 0.010152, 0.004023, 0.005400, 0.002743, 0.007020, 0.004590, 0.008370, + 5, 15, 0.009617, 0.007825, 0.002079, 0.008289, 0.003780, 0.004806, 0.002236, 0.006480, 0.003996, 0.008127, + 5, 14, 0.008710, 0.006820, 0.001817, 0.007749, 0.003240, 0.004185, 0.001760, 0.005400, 0.002538, 0.006615, + 5, 13, 0.008116, 0.006566, 0.001566, 0.006426, 0.002741, 0.003564, 0.001299, 0.004590, 0.001917, 0.005994, + 5, 12, 0.007908, 0.006151, 0.001350, 0.005400, 0.002471, 0.003132, 0.000794, 0.004050, 0.001323, 0.005940, + 5, 11, 0.007690, 0.005627, 0.001094, 0.005076, 0.002363, 0.002052, 0.000567, 0.003510, 0.001188, 0.004860, + 5, 10, 0.007560, 0.005038, 0.000805, 0.004536, 0.001985, 0.000540, 0.000000, 0.002430, 0.000999, 0.003240, + 5, 9, 0.007314, 0.004193, 0.000540, 0.003834, 0.001715, 0.000000, 0.000000, 0.002160, 0.000945, 0.002700, + 5, 8, 0.006750, 0.003240, 0.000000, 0.003240, 0.001323, 0.000000, 0.000000, 0.001350, 0.000837, 0.002646, + 5, 7, 0.006461, 0.002700, 0.000000, 0.002700, 0.001215, 0.000000, 0.000000, 0.000000, 0.000810, 0.001809, + 5, 6, 0.006240, 0.001796, 0.000000, 0.002052, 0.001013, 0.000000, 0.000000, 0.000000, 0.000756, 0.001620, + 5, 5, 0.005430, 0.000675, 0.000000, 0.000864, 0.000864, 0.000000, 0.000000, 0.000000, 0.000729, 0.001593, + 5, 4, 0.003780, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.001080, + 5, 3, 0.001350, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000540, + 5, 2, 0.000540, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000270, + 5, 1, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, + 4, 40, 0.079484, 0.106785, 0.018198, 0.122699, 0.057538, 0.076974, 0.034813, 0.079276, 0.061426, 0.112509, + 4, 39, 0.062146, 0.088671, 0.016205, 0.108082, 0.050454, 0.059905, 0.029600, 0.075465, 0.057362, 0.106596, + 4, 38, 0.050047, 0.076478, 0.014924, 0.090994, 0.043475, 0.045808, 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0.015568, 0.007962, 0.007444, 0.005192, 0.004836, 0.005670, 0.008289, + 1, 19, 0.008640, 0.011740, 0.001161, 0.012596, 0.006842, 0.006275, 0.002700, 0.003834, 0.003186, 0.005751, + 1, 18, 0.008262, 0.010171, 0.000783, 0.010622, 0.004965, 0.005273, 0.002071, 0.003251, 0.001728, 0.005157, + 1, 17, 0.007420, 0.008640, 0.000340, 0.008211, 0.003791, 0.004271, 0.001836, 0.002835, 0.000918, 0.002943, + 1, 16, 0.007136, 0.007020, 0.000000, 0.006672, 0.003213, 0.003213, 0.001080, 0.002419, 0.000189, 0.001917, + 1, 15, 0.006939, 0.004590, 0.000000, 0.005589, 0.002012, 0.002722, 0.000000, 0.001871, 0.000108, 0.001215, + 1, 14, 0.006753, 0.003083, 0.000000, 0.003888, 0.001229, 0.001966, 0.000000, 0.001285, 0.000189, 0.001161, + 1, 13, 0.006534, 0.002279, 0.000000, 0.003075, 0.000878, 0.001455, 0.000000, 0.001002, 0.000000, 0.000756, + 1, 12, 0.006251, 0.001647, 0.000000, 0.002700, 0.000837, 0.001134, 0.000000, 0.000756, 0.000000, 0.000891, + 1, 11, 0.006013, 0.001045, 0.000000, 0.002376, 0.000716, 0.000491, 0.000000, 0.000246, 0.000000, 0.000648, + 1, 10, 0.005732, 0.000845, 0.000000, 0.001836, 0.000648, 0.000189, 0.000000, 0.000000, 0.000000, 0.000540, + 1, 9, 0.005076, 0.000697, 0.000000, 0.001134, 0.000473, 0.000038, 0.000000, 0.000000, 0.000000, 0.000000, + 1, 8, 0.004523, 0.000540, 0.000000, 0.000662, 0.000446, 0.000076, 0.000000, 0.000000, 0.000000, 0.000000, + 1, 7, 0.003972, 0.000294, 0.000000, 0.000429, 0.000378, 0.000019, 0.000000, 0.000000, 0.000000, 0.000000, + 1, 6, 0.003564, 0.000254, 0.000000, 0.000208, 0.000270, 0.000038, 0.000000, 0.000000, 0.000000, 0.000000, + 1, 5, 0.003210, 0.000122, 0.000000, 0.000230, 0.000311, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, + 1, 4, 0.000489, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, + 1, 3, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, + 1, 2, 0.000022, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, + 1, 1, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, 0.000000, + -1], ""); + + temperature_weights_database = VectorParam.Int([ + 71, 1, + 72, 2, + 73, 3, + 74, 4, + 75, 5, + 76, 5, + 77, 6, + 78, 7, + 79, 8, + 80, 10, + 81, 11, + 82, 12, + 83, 12, + 84, 13, + 85, 14, + 86, 16, + 87, 17, + 88, 18, + 89, 19, + 90, 20, + 91, 22, + 92, 24, + 93, 26, + 94, 27, + 95, 29, + 96, 30, + 97, 32, + 98, 35, + 99, 37, + 100, 39, + 101, 42, + 102, 45, + 103, 47, + 104, 50, + 105, 53, + 106, 56, + 107, 61, + 108, 65, + 109, 70, + 110, 74, + 111, 78, + 112, 82, + 113, 89, + 114, 95, + 115, 100, + 116, 106, + 117, 115, + 118, 122, + 119, 130, + 120, 139, + 121, 147, + 122, 156, + 123, 169, + 124, 178, + 125, 190, + -1], ""); diff --git a/src/mem/ruby/network/fault_model/SConscript b/src/mem/ruby/network/fault_model/SConscript new file mode 100644 index 000000000..ade3eca64 --- /dev/null +++ b/src/mem/ruby/network/fault_model/SConscript @@ -0,0 +1,43 @@ +# Copyright (c) 2011 Massachusetts Institute of Technology +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Konstantinos Aisopos + +# Official Tool Website: www.mit.edu/~kaisopos/FaultModel +# +# If you use our tool for academic research, we request that you cite: +# Konstantinos Aisopos, Chia-Hsin Owen Chen, and Li-Shiuan Peh. Enabling +# System-Level Modeling of Variation-Induced Faults in Networks-on-Chip. +# Proceedings of the 48th Design Automation Conference (DAC'11) + +Import('*') + +if env['PROTOCOL'] == 'None': + Return() + +SimObject('FaultModel.py') +Source('FaultModel.cc') + diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc b/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc index e3eb73b0a..cd4ca0af1 100644 --- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc +++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc @@ -38,6 +38,9 @@ BaseGarnetNetwork::BaseGarnetNetwork(const Params *p) { m_ni_flit_size = p->ni_flit_size; m_vcs_per_vnet = p->vcs_per_vnet; + m_enable_fault_model = p->enable_fault_model; + if (m_enable_fault_model) + fault_model = p->fault_model; m_ruby_start = 0; m_flits_received = 0; diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh b/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh index 95d4c5f5c..52079d8f6 100644 --- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh +++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh @@ -38,6 +38,7 @@ #include "mem/ruby/network/garnet/NetworkHeader.hh" #include "mem/ruby/network/Network.hh" +#include "mem/ruby/network/fault_model/FaultModel.hh" #include "params/BaseGarnetNetwork.hh" #include "math.h" @@ -50,10 +51,13 @@ class BaseGarnetNetwork : public Network void init(); int getNiFlitSize() {return m_ni_flit_size; } int getVCsPerVnet() {return m_vcs_per_vnet; } + bool isFaultModelEnabled() {return m_enable_fault_model;} + FaultModel* fault_model; protected: int m_ni_flit_size; int m_vcs_per_vnet; + bool m_enable_fault_model; int m_flits_received; int m_flits_injected; diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py index 8073131f4..2431db203 100644 --- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py +++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py @@ -36,3 +36,5 @@ class BaseGarnetNetwork(RubyNetwork): abstract = True ni_flit_size = Param.Int(16, "network interface flit size in bytes") vcs_per_vnet = Param.Int(4, "virtual channels per virtual network"); + enable_fault_model = Param.Bool(False, "enable network fault model"); + fault_model = Param.FaultModel(NULL, "network fault model"); diff --git a/src/mem/ruby/network/garnet/NetworkHeader.hh b/src/mem/ruby/network/garnet/NetworkHeader.hh index 713c49439..eccb4b31c 100644 --- a/src/mem/ruby/network/garnet/NetworkHeader.hh +++ b/src/mem/ruby/network/garnet/NetworkHeader.hh @@ -31,9 +31,6 @@ #ifndef __MEM_RUBY_NETWORK_GARNET_NETWORKHEADER_HH__ #define __MEM_RUBY_NETWORK_GARNET_NETWORKHEADER_HH__ -#include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" - enum flit_type {HEAD_, BODY_, TAIL_, HEAD_TAIL_, NUM_FLIT_TYPE_}; enum VC_state_type {IDLE_, VC_AB_, ACTIVE_, NUM_VC_STATE_TYPE_}; enum VNET_type {CTRL_VNET_, DATA_VNET_, NULL_VNET_, NUM_VNET_TYPE_}; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc index be9a92305..fccd73ee2 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc @@ -97,6 +97,23 @@ GarnetNetwork_d::init() NetworkLink_d* net_link = safe_cast<NetworkLink_d*>(*i); net_link->init_net_ptr(this); } + + // FaultModel: declare each router to the fault model + if(isFaultModelEnabled()){ + for (vector<Router_d*>::const_iterator i= m_router_ptr_vector.begin(); + i != m_router_ptr_vector.end(); ++i) { + Router_d* router = safe_cast<Router_d*>(*i); + int router_id=fault_model->declare_router(router->get_num_inports(), + router->get_num_outports(), + router->get_vc_per_vnet(), + getBuffersPerDataVC(), + getBuffersPerCtrlVC()); + assert(router_id == router->get_id()); + router->printAggregateFaultProbability(cout); + router->printFaultVector(cout); + } + } + } GarnetNetwork_d::~GarnetNetwork_d() diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh index 2030bb4f0..a7fe05a64 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh @@ -39,6 +39,7 @@ #include "mem/ruby/network/Network.hh" #include "params/GarnetNetwork_d.hh" +class FaultModel; class NetworkInterface_d; class MessageBuffer; class Router_d; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc index 62ab5ce07..b638c9aca 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc @@ -189,6 +189,35 @@ Router_d::printConfig(ostream& out) out << "]" << endl; } +void +Router_d::printFaultVector(ostream& out) +{ + int temperature_celcius = BASELINE_TEMPERATURE_CELCIUS; + int num_fault_types = m_network_ptr->fault_model->number_of_fault_types; + float fault_vector[num_fault_types]; + get_fault_vector(temperature_celcius, fault_vector); + out << "Router-" << m_id << " fault vector: " << endl; + for (int fault_type_index = 0; fault_type_index < num_fault_types; + fault_type_index++){ + out << " - probability of ("; + out << + m_network_ptr->fault_model->fault_type_to_string(fault_type_index); + out << ") = "; + out << fault_vector[fault_type_index] << endl; + } +} + +void +Router_d::printAggregateFaultProbability(std::ostream& out) +{ + int temperature_celcius = BASELINE_TEMPERATURE_CELCIUS; + float aggregate_fault_prob; + get_aggregate_fault_probability(temperature_celcius, + &aggregate_fault_prob); + out << "Router-" << m_id << " fault probability: "; + out << aggregate_fault_prob << endl; +} + Router_d * GarnetRouter_dParams::create() { diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh index e5a3a0ce2..babc0d443 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh @@ -50,6 +50,7 @@ class RoutingUnit_d; class VCallocator_d; class SWallocator_d; class Switch_d; +class FaultModel; class Router_d : public BasicRouter { @@ -86,6 +87,8 @@ class Router_d : public BasicRouter void vcarb_req(); void swarb_req(); void printConfig(std::ostream& out); + void printFaultVector(std::ostream& out); + void printAggregateFaultProbability(std::ostream& out); double calculate_power(); void calculate_performance_numbers(); @@ -93,6 +96,15 @@ class Router_d : public BasicRouter double get_dynamic_power(){return m_power_dyn;} double get_static_power(){return m_power_sta;} double get_clk_power(){return m_clk_power;} + bool get_fault_vector(int temperature, float fault_vector[]){ + return m_network_ptr->fault_model->fault_vector(m_id, temperature, + fault_vector); + } + bool get_aggregate_fault_probability(int temperature, + float *aggregate_fault_prob){ + return m_network_ptr->fault_model->fault_prob(m_id, temperature, + aggregate_fault_prob); + } private: int m_virtual_networks, m_num_vcs, m_vc_per_vnet; diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh b/src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh index 829509f64..e98bf3f7b 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh @@ -31,6 +31,7 @@ #ifndef __MEM_RUBY_NETWORK_GARNET_FLEXIBLE_PIPELINE_IN_VC_STATE_HH__ #define __MEM_RUBY_NETWORK_GARNET_FLEXIBLE_PIPELINE_IN_VC_STATE_HH__ +#include "mem/ruby/common/TypeDefines.hh" #include "mem/ruby/network/garnet/NetworkHeader.hh" class InVcState diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh b/src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh index 17fa9141e..03ea14076 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh @@ -31,6 +31,7 @@ #ifndef __MEM_RUBY_NETWORK_GARNET_FLEXIBLE_PIPELINE_OUT_VC_STATE_HH__ #define __MEM_RUBY_NETWORK_GARNET_FLEXIBLE_PIPELINE_OUT_VC_STATE_HH__ +#include "mem/ruby/common/TypeDefines.hh" #include "mem/ruby/network/garnet/NetworkHeader.hh" class OutVcState diff --git a/src/mem/ruby/network/orion/Clock.cc b/src/mem/ruby/network/orion/Clock.cc index 500d6580b..fda18cd64 100644 --- a/src/mem/ruby/network/orion/Clock.cc +++ b/src/mem/ruby/network/orion/Clock.cc @@ -137,13 +137,10 @@ void Clock::init() double router_diagonal = m_orion_cfg_ptr->get<double>("ROUTER_DIAGONAL"); double Clockwire = m_tech_param_ptr->get_ClockCap(); - double Reswire = m_tech_param_ptr->get_Reswire(); double htree_clockcap; - double htree_res; int k; double h; - double cap_clock_buf = 0; double BufferNMOSOffCurrent = m_tech_param_ptr->get_BufferNMOSOffCurrent(); double BufferPMOSOffCurrent = m_tech_param_ptr->get_BufferPMOSOffCurrent(); @@ -151,7 +148,6 @@ void Clock::init() if (m_tech_param_ptr->is_trans_type_hvt() || m_tech_param_ptr->is_trans_type_nvt()) { htree_clockcap = (4+4+2+2)*(router_diagonal*1e-6)*Clockwire; - htree_res = (4+4+2+2)*(router_diagonal*1e-6)*Reswire; wire.calc_opt_buffering(&k, &h, ((4+4+2+2)*router_diagonal*1e-6)); i_static_nmos = BufferNMOSOffCurrent*h*k*15; @@ -160,15 +156,12 @@ void Clock::init() else { htree_clockcap = (8+4+4+4+4)*(router_diagonal*1e-6)*Clockwire; - htree_res = (8+4+4+4+4)*(router_diagonal*1e-6)*Reswire; wire.calc_opt_buffering(&k, &h, ((4+4+2+2)*router_diagonal*1e-6)); i_static_nmos = BufferNMOSOffCurrent*h*k*29; i_static_pmos = BufferPMOSOffCurrent*h*k*15; } - cap_clock_buf = ((double)k)*cap_clock*h; - m_e_htree = (htree_clockcap+cap_clock)*e_factor; } else diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc index 06c4ace91..f8b08d551 100644 --- a/src/mem/ruby/network/simple/PerfectSwitch.cc +++ b/src/mem/ruby/network/simple/PerfectSwitch.cc @@ -71,8 +71,7 @@ PerfectSwitch::addInPort(const vector<MessageBuffer*>& in) for (int j = 0; j < m_virtual_networks; j++) { m_in[port][j]->setConsumer(this); string desc = csprintf("[Queue from port %s %s %s to PerfectSwitch]", - NodeIDToString(m_switch_id), NodeIDToString(port), - NodeIDToString(j)); + to_string(m_switch_id), to_string(port), to_string(j)); m_in[port][j]->setDescription(desc); m_in[port][j]->setIncomingLink(port); m_in[port][j]->setVnet(j); diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh b/src/mem/ruby/network/simple/PerfectSwitch.hh index 15abec020..d761c398d 100644 --- a/src/mem/ruby/network/simple/PerfectSwitch.hh +++ b/src/mem/ruby/network/simple/PerfectSwitch.hh @@ -42,7 +42,6 @@ #include "mem/ruby/common/Consumer.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" class MessageBuffer; class NetDest; diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh b/src/mem/ruby/network/simple/SimpleNetwork.hh index fb5481b46..54e1ee36e 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.hh +++ b/src/mem/ruby/network/simple/SimpleNetwork.hh @@ -34,7 +34,6 @@ #include "mem/ruby/common/Global.hh" #include "mem/ruby/network/Network.hh" -#include "mem/ruby/system/NodeID.hh" #include "params/SimpleNetwork.hh" #include "sim/sim_object.hh" diff --git a/src/mem/ruby/network/simple/Throttle.cc b/src/mem/ruby/network/simple/Throttle.cc index 822989204..b248c6c6c 100644 --- a/src/mem/ruby/network/simple/Throttle.cc +++ b/src/mem/ruby/network/simple/Throttle.cc @@ -113,8 +113,8 @@ Throttle::addVirtualNetwork(MessageBuffer* in_ptr, MessageBuffer* out_ptr) // Set consumer and description m_in[m_vnets]->setConsumer(this); - string desc = "[Queue to Throttle " + NodeIDToString(m_sID) + " " + - NodeIDToString(m_node) + "]"; + string desc = "[Queue to Throttle " + to_string(m_sID) + " " + + to_string(m_node) + "]"; m_in[m_vnets]->setDescription(desc); m_vnets++; } diff --git a/src/mem/ruby/network/simple/Throttle.hh b/src/mem/ruby/network/simple/Throttle.hh index 09eac79a8..28fe046b4 100644 --- a/src/mem/ruby/network/simple/Throttle.hh +++ b/src/mem/ruby/network/simple/Throttle.hh @@ -45,7 +45,6 @@ #include "mem/ruby/common/Consumer.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/network/Network.hh" -#include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/System.hh" class MessageBuffer; diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.hh b/src/mem/ruby/profiler/AccessTraceForAddress.hh index 228ebcade..289b83a3a 100644 --- a/src/mem/ruby/profiler/AccessTraceForAddress.hh +++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh @@ -36,7 +36,6 @@ #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Set.hh" -#include "mem/ruby/system/NodeID.hh" class Histogram; diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh index e525a792f..5bce34bbb 100644 --- a/src/mem/ruby/profiler/AddressProfiler.hh +++ b/src/mem/ruby/profiler/AddressProfiler.hh @@ -38,7 +38,6 @@ #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Histogram.hh" #include "mem/ruby/profiler/AccessTraceForAddress.hh" -#include "mem/ruby/system/NodeID.hh" class Set; diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh index 33cb45e85..c53db7ea8 100644 --- a/src/mem/ruby/profiler/CacheProfiler.hh +++ b/src/mem/ruby/profiler/CacheProfiler.hh @@ -39,7 +39,6 @@ #include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Histogram.hh" -#include "mem/ruby/system/NodeID.hh" class CacheProfiler { diff --git a/src/mem/ruby/profiler/MemCntrlProfiler.hh b/src/mem/ruby/profiler/MemCntrlProfiler.hh index e6d64a2b5..a594e0d96 100644 --- a/src/mem/ruby/profiler/MemCntrlProfiler.hh +++ b/src/mem/ruby/profiler/MemCntrlProfiler.hh @@ -33,7 +33,7 @@ #include <string> #include <vector> -#include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/TypeDefines.hh" class MemCntrlProfiler { diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh index 9efaf4be1..258fc6f98 100644 --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -64,7 +64,6 @@ #include "mem/ruby/common/Set.hh" #include "mem/ruby/system/MachineID.hh" #include "mem/ruby/system/MemoryControl.hh" -#include "mem/ruby/system/NodeID.hh" #include "params/RubyProfiler.hh" #include "sim/sim_object.hh" diff --git a/src/mem/ruby/recorder/CacheRecorder.hh b/src/mem/ruby/recorder/CacheRecorder.hh index 97a20af28..9f96f4fa0 100644 --- a/src/mem/ruby/recorder/CacheRecorder.hh +++ b/src/mem/ruby/recorder/CacheRecorder.hh @@ -41,7 +41,6 @@ #include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/recorder/TraceRecord.hh" -#include "mem/ruby/system/NodeID.hh" class Address; class TraceRecord; diff --git a/src/mem/ruby/recorder/TraceRecord.cc b/src/mem/ruby/recorder/TraceRecord.cc index aa54ee53c..79186d33b 100644 --- a/src/mem/ruby/recorder/TraceRecord.cc +++ b/src/mem/ruby/recorder/TraceRecord.cc @@ -73,17 +73,15 @@ void TraceRecord::issueRequest() const { assert(m_sequencer_ptr != NULL); - - RubyRequest request(m_data_address.getAddress(), NULL, - RubySystem::getBlockSizeBytes(), m_pc_address.getAddress(), - m_type, RubyAccessMode_User, NULL); + Request req(m_data_address.getAddress(), 0, 0); + Packet *pkt = new Packet(&req, MemCmd(MemCmd::InvalidCmd), -1); // Clear out the sequencer while (!m_sequencer_ptr->empty()) { g_eventQueue_ptr->triggerEvents(g_eventQueue_ptr->getTime() + 100); } - m_sequencer_ptr->makeRequest(request); + m_sequencer_ptr->makeRequest(pkt); // Clear out the sequencer while (!m_sequencer_ptr->empty()) { diff --git a/src/mem/ruby/recorder/TraceRecord.hh b/src/mem/ruby/recorder/TraceRecord.hh index 9ec2bdb99..42f213564 100644 --- a/src/mem/ruby/recorder/TraceRecord.hh +++ b/src/mem/ruby/recorder/TraceRecord.hh @@ -38,7 +38,6 @@ #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/Sequencer.hh" class CacheMsg; diff --git a/src/mem/ruby/recorder/Tracer.hh b/src/mem/ruby/recorder/Tracer.hh index e050b3812..cad47b28c 100644 --- a/src/mem/ruby/recorder/Tracer.hh +++ b/src/mem/ruby/recorder/Tracer.hh @@ -39,7 +39,6 @@ #include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" #include "params/RubyTracer.hh" #include "sim/sim_object.hh" #include "gzstream.hh" diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh index 7fcfabe9c..c57857adb 100644 --- a/src/mem/ruby/slicc_interface/Message.hh +++ b/src/mem/ruby/slicc_interface/Message.hh @@ -33,6 +33,7 @@ #include "base/refcnt.hh" #include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/TypeDefines.hh" #include "mem/ruby/eventqueue/RubyEventQueue.hh" class Message; diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh index 18e7ad6fc..cb9830446 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh @@ -29,38 +29,12 @@ #ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__ #define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__ -#include "mem/protocol/GenericMachineType.hh" #include "mem/protocol/MachineType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/NetDest.hh" #include "mem/ruby/system/DirectoryMemory.hh" #include "mem/ruby/system/MachineID.hh" -#include "mem/ruby/system/NodeID.hh" - -#ifdef MACHINETYPE_L1Cache -#define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache -#else -#define MACHINETYPE_L1CACHE_ENUM MachineType_NUM -#endif - -#ifdef MACHINETYPE_L2Cache -#define MACHINETYPE_L2CACHE_ENUM MachineType_L2Cache -#else -#define MACHINETYPE_L2CACHE_ENUM MachineType_NUM -#endif - -#ifdef MACHINETYPE_L3Cache -#define MACHINETYPE_L3CACHE_ENUM MachineType_L3Cache -#else -#define MACHINETYPE_L3CACHE_ENUM MachineType_NUM -#endif - -#ifdef MACHINETYPE_DMA -#define MACHINETYPE_DMA_ENUM MachineType_DMA -#else -#define MACHINETYPE_DMA_ENUM MachineType_NUM -#endif // used to determine the home directory // returns a value between 0 and total_directories_within_the_system @@ -80,13 +54,6 @@ map_Address_to_Directory(const Address &addr) return mach; } -inline MachineID -map_Address_to_DMA(const Address & addr) -{ - MachineID dma = {MACHINETYPE_DMA_ENUM, 0}; - return dma; -} - inline NetDest broadcast(MachineType type) { @@ -121,41 +88,6 @@ machineIDToMachineType(MachineID machID) return machID.type; } -inline NodeID -L1CacheMachIDToProcessorNum(MachineID machID) -{ - assert(machID.type == MACHINETYPE_L1CACHE_ENUM); - return machID.num; -} - -inline MachineID -getL1MachineID(NodeID L1RubyNode) -{ - MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode}; - return mach; -} - -inline GenericMachineType -ConvertMachToGenericMach(MachineType machType) -{ - if (machType == MACHINETYPE_L1CACHE_ENUM) - return GenericMachineType_L1Cache; - - if (machType == MACHINETYPE_L2CACHE_ENUM) - return GenericMachineType_L2Cache; - - if (machType == MACHINETYPE_L3CACHE_ENUM) - return GenericMachineType_L3Cache; - - if (machType == MachineType_Directory) - return GenericMachineType_Directory; - - if (machType == MACHINETYPE_DMA_ENUM) - return GenericMachineType_DMA; - - panic("cannot convert to a GenericMachineType"); -} - inline int machineCount(MachineType machType) { diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh index b2e612bd4..bed42018b 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh @@ -39,7 +39,6 @@ #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/profiler/Profiler.hh" -#include "mem/ruby/system/NodeID.hh" class Set; diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh index 9b284dab4..d535ba7cd 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh @@ -45,7 +45,6 @@ #include "mem/ruby/network/Network.hh" #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" #include "mem/ruby/system/MachineID.hh" -#include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/System.hh" class Set; diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index f8e4cf810..0e82ba3eb 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -48,27 +48,16 @@ DMASequencer::init() } RequestStatus -DMASequencer::makeRequest(const RubyRequest &request) +DMASequencer::makeRequest(PacketPtr pkt) { if (m_is_busy) { return RequestStatus_BufferFull; } - uint64_t paddr = request.m_PhysicalAddress.getAddress(); - uint8_t* data = request.data; - int len = request.m_Size; - bool write = false; - switch(request.m_Type) { - case RubyRequestType_LD: - write = false; - break; - case RubyRequestType_ST: - write = true; - break; - default: - panic("DMASequencer::makeRequest does not support RubyRequestType"); - return RequestStatus_NULL; - } + uint64_t paddr = pkt->getAddr(); + uint8_t* data = pkt->getPtr<uint8_t>(true); + int len = pkt->getSize(); + bool write = pkt->isWrite(); assert(!m_is_busy); // only support one outstanding DMA request m_is_busy = true; @@ -79,7 +68,7 @@ DMASequencer::makeRequest(const RubyRequest &request) active_request.len = len; active_request.bytes_completed = 0; active_request.bytes_issued = 0; - active_request.pkt = request.pkt; + active_request.pkt = pkt; SequencerMsg *msg = new SequencerMsg; msg->getPhysicalAddress() = Address(paddr); diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh index 61d7ef1c6..5f6b9f100 100644 --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -53,7 +53,7 @@ class DMASequencer : public RubyPort DMASequencer(const Params *); void init(); /* external interface */ - RequestStatus makeRequest(const RubyRequest & request); + RequestStatus makeRequest(PacketPtr pkt); bool busy() { return m_is_busy;} /* SLICC callback */ diff --git a/src/mem/ruby/system/MachineID.hh b/src/mem/ruby/system/MachineID.hh index 567d1f004..18beac5d8 100644 --- a/src/mem/ruby/system/MachineID.hh +++ b/src/mem/ruby/system/MachineID.hh @@ -34,7 +34,6 @@ #include "base/cprintf.hh" #include "mem/protocol/MachineType.hh" -#include "mem/ruby/common/Global.hh" struct MachineID { diff --git a/src/mem/ruby/system/NodeID.hh b/src/mem/ruby/system/NodeID.hh deleted file mode 100644 index ed3486aaf..000000000 --- a/src/mem/ruby/system/NodeID.hh +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __MEM_RUBY_SYSTEM_NODEID_HH__ -#define __MEM_RUBY_SYSTEM_NODEID_HH__ - -#include <string> - -#include "base/str.hh" -#include "mem/ruby/common/Global.hh" - -typedef int NodeID; - -inline std::string -NodeIDToString(NodeID node) -{ - return to_string(node); -} - -#endif // __MEM_RUBY_SYSTEM_NODEID_HH__ diff --git a/src/mem/ruby/system/PersistentTable.hh b/src/mem/ruby/system/PersistentTable.hh index 356406cbd..d2f58b0db 100644 --- a/src/mem/ruby/system/PersistentTable.hh +++ b/src/mem/ruby/system/PersistentTable.hh @@ -41,6 +41,7 @@ class PersistentTableEntry { public: + PersistentTableEntry() {} void print(std::ostream& out) const {} NetDest m_starving; diff --git a/src/mem/ruby/system/PseudoLRUPolicy.hh b/src/mem/ruby/system/PseudoLRUPolicy.hh index 1e1e68188..3cc2a5dfe 100644 --- a/src/mem/ruby/system/PseudoLRUPolicy.hh +++ b/src/mem/ruby/system/PseudoLRUPolicy.hh @@ -64,8 +64,6 @@ inline PseudoLRUPolicy::PseudoLRUPolicy(Index num_sets, Index assoc) : AbstractReplacementPolicy(num_sets, assoc) { - int num_tree_nodes; - // associativity cannot exceed capacity of tree representation assert(num_sets > 0 && assoc > 1 && assoc <= (Index) sizeof(uint64)*4); @@ -84,7 +82,6 @@ PseudoLRUPolicy::PseudoLRUPolicy(Index num_sets, Index assoc) m_num_levels++; } assert(m_num_levels < sizeof(unsigned int)*4); - num_tree_nodes = (1 << m_num_levels) - 1; m_trees = new uint64[m_num_sets]; for (unsigned i = 0; i < m_num_sets; i++) { m_trees[i] = 0; diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index c2661bcf2..f7bde739e 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -26,10 +26,6 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "config/the_isa.hh" -#if THE_ISA == X86_ISA -#include "arch/x86/insts/microldstop.hh" -#endif // X86_ISA #include "cpu/testers/rubytest/RubyTester.hh" #include "debug/Ruby.hh" #include "mem/protocol/AccessPermission.hh" @@ -199,73 +195,11 @@ RubyPort::M5Port::recvTiming(PacketPtr pkt) return ruby_port->pio_port->sendTiming(pkt); } - // For DMA and CPU requests, translate them to ruby requests before - // sending them to our assigned ruby port. - RubyRequestType type = RubyRequestType_NULL; - - // If valid, copy the pc to the ruby request - Addr pc = 0; - if (pkt->req->hasPC()) { - pc = pkt->req->getPC(); - } - - if (pkt->isLLSC()) { - if (pkt->isWrite()) { - DPRINTF(RubyPort, "Issuing SC\n"); - type = RubyRequestType_Store_Conditional; - } else { - DPRINTF(RubyPort, "Issuing LL\n"); - assert(pkt->isRead()); - type = RubyRequestType_Load_Linked; - } - } else if (pkt->req->isLocked()) { - if (pkt->isWrite()) { - DPRINTF(RubyPort, "Issuing Locked RMW Write\n"); - type = RubyRequestType_Locked_RMW_Write; - } else { - DPRINTF(RubyPort, "Issuing Locked RMW Read\n"); - assert(pkt->isRead()); - type = RubyRequestType_Locked_RMW_Read; - } - } else { - if (pkt->isRead()) { - if (pkt->req->isInstFetch()) { - type = RubyRequestType_IFETCH; - } else { -#if THE_ISA == X86_ISA - uint32_t flags = pkt->req->getFlags(); - bool storeCheck = flags & - (TheISA::StoreCheck << TheISA::FlagShift); -#else - bool storeCheck = false; -#endif // X86_ISA - if (storeCheck) { - type = RubyRequestType_RMW_Read; - } else { - type = RubyRequestType_LD; - } - } - } else if (pkt->isWrite()) { - // - // Note: M5 packets do not differentiate ST from RMW_Write - // - type = RubyRequestType_ST; - } else if (pkt->isFlush()) { - type = RubyRequestType_FLUSH; - } else { - panic("Unsupported ruby packet type\n"); - } - } - - RubyRequest ruby_request(pkt->getAddr(), pkt->getPtr<uint8_t>(true), - pkt->getSize(), pc, type, - RubyAccessMode_Supervisor, pkt); - - assert(ruby_request.m_PhysicalAddress.getOffset() + ruby_request.m_Size <= - RubySystem::getBlockSizeBytes()); + assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= + RubySystem::getBlockSizeBytes()); // Submit the ruby request - RequestStatus requestStatus = ruby_port->makeRequest(ruby_request); + RequestStatus requestStatus = ruby_port->makeRequest(pkt); // If the request successfully issued then we should return true. // Otherwise, we need to delete the senderStatus we just created and return diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index e1ba2f7d1..88e865766 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -114,7 +114,7 @@ class RubyPort : public MemObject Port *getPort(const std::string &if_name, int idx); - virtual RequestStatus makeRequest(const RubyRequest & request) = 0; + virtual RequestStatus makeRequest(PacketPtr pkt) = 0; // // Called by the controller to give the sequencer a pointer. diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 711ef12ed..9010178be 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -28,15 +28,21 @@ #include "base/misc.hh" #include "base/str.hh" +#include "config/the_isa.hh" +#if THE_ISA == X86_ISA +#include "arch/x86/insts/microldstop.hh" +#endif // X86_ISA #include "cpu/testers/rubytest/RubyTester.hh" #include "debug/MemoryAccess.hh" #include "debug/ProtocolTrace.hh" +#include "debug/RubySequencer.hh" +#include "mem/protocol/PrefetchBit.hh" +#include "mem/protocol/RubyAccessMode.hh" #include "mem/ruby/buffers/MessageBuffer.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/SubBlock.hh" #include "mem/ruby/profiler/Profiler.hh" #include "mem/ruby/recorder/Tracer.hh" -#include "mem/ruby/slicc_interface/AbstractController.hh" #include "mem/ruby/slicc_interface/RubyRequest.hh" #include "mem/ruby/system/CacheMemory.hh" #include "mem/ruby/system/Sequencer.hh" @@ -62,7 +68,6 @@ Sequencer::Sequencer(const Params *p) m_outstanding_count = 0; - m_max_outstanding_requests = 0; m_deadlock_threshold = 0; m_instCache_ptr = NULL; m_dataCache_ptr = NULL; @@ -103,7 +108,7 @@ Sequencer::wakeup() panic("Possible Deadlock detected. Aborting!\n" "version: %d request.paddr: 0x%x m_readRequestTable: %d " "current time: %u issue_time: %d difference: %d\n", m_version, - request->ruby_request.m_PhysicalAddress, m_readRequestTable.size(), + Address(request->pkt->getAddr()), m_readRequestTable.size(), current_time, request->issue_time, current_time - request->issue_time); } @@ -118,7 +123,7 @@ Sequencer::wakeup() panic("Possible Deadlock detected. Aborting!\n" "version: %d request.paddr: 0x%x m_writeRequestTable: %d " "current time: %u issue_time: %d difference: %d\n", m_version, - request->ruby_request.m_PhysicalAddress, m_writeRequestTable.size(), + Address(request->pkt->getAddr()), m_writeRequestTable.size(), current_time, request->issue_time, current_time - request->issue_time); } @@ -213,8 +218,8 @@ Sequencer::printConfig(ostream& out) const // Insert the request on the correct request table. Return true if // the entry was already present. -bool -Sequencer::insertRequest(SequencerRequest* request) +RequestStatus +Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) { int total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size(); @@ -226,52 +231,64 @@ Sequencer::insertRequest(SequencerRequest* request) schedule(deadlockCheckEvent, m_deadlock_threshold + curTick()); } - Address line_addr(request->ruby_request.m_PhysicalAddress); + Address line_addr(pkt->getAddr()); line_addr.makeLineAddress(); - if ((request->ruby_request.m_Type == RubyRequestType_ST) || - (request->ruby_request.m_Type == RubyRequestType_ATOMIC) || - (request->ruby_request.m_Type == RubyRequestType_RMW_Read) || - (request->ruby_request.m_Type == RubyRequestType_RMW_Write) || - (request->ruby_request.m_Type == RubyRequestType_Load_Linked) || - (request->ruby_request.m_Type == RubyRequestType_Store_Conditional) || - (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Read) || - (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Write) || - (request->ruby_request.m_Type == RubyRequestType_FLUSH)) { + if ((request_type == RubyRequestType_ST) || + (request_type == RubyRequestType_RMW_Read) || + (request_type == RubyRequestType_RMW_Write) || + (request_type == RubyRequestType_Load_Linked) || + (request_type == RubyRequestType_Store_Conditional) || + (request_type == RubyRequestType_Locked_RMW_Read) || + (request_type == RubyRequestType_Locked_RMW_Write) || + (request_type == RubyRequestType_FLUSH)) { + + // Check if there is any outstanding read request for the same + // cache line. + if (m_readRequestTable.count(line_addr) > 0) { + m_store_waiting_on_load_cycles++; + return RequestStatus_Aliased; + } + pair<RequestTable::iterator, bool> r = m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0)); - bool success = r.second; - RequestTable::iterator i = r.first; - if (!success) { - i->second = request; - // return true; - - // drh5: isn't this an error? do you lose the initial request? - assert(0); + if (r.second) { + RequestTable::iterator i = r.first; + i->second = new SequencerRequest(pkt, request_type, + g_eventQueue_ptr->getTime()); + m_outstanding_count++; + } else { + // There is an outstanding write request for the cache line + m_store_waiting_on_store_cycles++; + return RequestStatus_Aliased; } - i->second = request; - m_outstanding_count++; } else { + // Check if there is any outstanding write request for the same + // cache line. + if (m_writeRequestTable.count(line_addr) > 0) { + m_load_waiting_on_store_cycles++; + return RequestStatus_Aliased; + } + pair<RequestTable::iterator, bool> r = m_readRequestTable.insert(RequestTable::value_type(line_addr, 0)); - bool success = r.second; - RequestTable::iterator i = r.first; - if (!success) { - i->second = request; - // return true; - - // drh5: isn't this an error? do you lose the initial request? - assert(0); + + if (r.second) { + RequestTable::iterator i = r.first; + i->second = new SequencerRequest(pkt, request_type, + g_eventQueue_ptr->getTime()); + m_outstanding_count++; + } else { + // There is an outstanding read request for the cache line + m_load_waiting_on_load_cycles++; + return RequestStatus_Aliased; } - i->second = request; - m_outstanding_count++; } g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count); - total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size(); assert(m_outstanding_count == total_outstanding); - return false; + return RequestStatus_Ready; } void @@ -288,16 +305,15 @@ Sequencer::removeRequest(SequencerRequest* srequest) assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size()); - const RubyRequest & ruby_request = srequest->ruby_request; - Address line_addr(ruby_request.m_PhysicalAddress); + Address line_addr(srequest->pkt->getAddr()); line_addr.makeLineAddress(); - if ((ruby_request.m_Type == RubyRequestType_ST) || - (ruby_request.m_Type == RubyRequestType_RMW_Read) || - (ruby_request.m_Type == RubyRequestType_RMW_Write) || - (ruby_request.m_Type == RubyRequestType_Load_Linked) || - (ruby_request.m_Type == RubyRequestType_Store_Conditional) || - (ruby_request.m_Type == RubyRequestType_Locked_RMW_Read) || - (ruby_request.m_Type == RubyRequestType_Locked_RMW_Write)) { + if ((srequest->m_type == RubyRequestType_ST) || + (srequest->m_type == RubyRequestType_RMW_Read) || + (srequest->m_type == RubyRequestType_RMW_Write) || + (srequest->m_type == RubyRequestType_Load_Linked) || + (srequest->m_type == RubyRequestType_Store_Conditional) || + (srequest->m_type == RubyRequestType_Locked_RMW_Read) || + (srequest->m_type == RubyRequestType_Locked_RMW_Write)) { m_writeRequestTable.erase(line_addr); } else { m_readRequestTable.erase(line_addr); @@ -315,32 +331,33 @@ Sequencer::handleLlsc(const Address& address, SequencerRequest* request) // longer locked. // bool success = true; - if (request->ruby_request.m_Type == RubyRequestType_Store_Conditional) { + if (request->m_type == RubyRequestType_Store_Conditional) { if (!m_dataCache_ptr->isLocked(address, m_version)) { // // For failed SC requests, indicate the failure to the cpu by // setting the extra data to zero. // - request->ruby_request.pkt->req->setExtraData(0); + request->pkt->req->setExtraData(0); success = false; } else { // // For successful SC requests, indicate the success to the cpu by // setting the extra data to one. // - request->ruby_request.pkt->req->setExtraData(1); + request->pkt->req->setExtraData(1); } // // Independent of success, all SC operations must clear the lock // m_dataCache_ptr->clearLocked(address); - } else if (request->ruby_request.m_Type == RubyRequestType_Load_Linked) { + } else if (request->m_type == RubyRequestType_Load_Linked) { // // Note: To fully follow Alpha LLSC semantics, should the LL clear any // previously locked cache lines? // m_dataCache_ptr->setLocked(address, m_version); - } else if ((m_dataCache_ptr->isTagPresent(address)) && (m_dataCache_ptr->isLocked(address, m_version))) { + } else if ((m_dataCache_ptr->isTagPresent(address)) && + (m_dataCache_ptr->isLocked(address, m_version))) { // // Normal writes should clear the locked address // @@ -381,15 +398,15 @@ Sequencer::writeCallback(const Address& address, m_writeRequestTable.erase(i); markRemoved(); - assert((request->ruby_request.m_Type == RubyRequestType_ST) || - (request->ruby_request.m_Type == RubyRequestType_ATOMIC) || - (request->ruby_request.m_Type == RubyRequestType_RMW_Read) || - (request->ruby_request.m_Type == RubyRequestType_RMW_Write) || - (request->ruby_request.m_Type == RubyRequestType_Load_Linked) || - (request->ruby_request.m_Type == RubyRequestType_Store_Conditional) || - (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Read) || - (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Write) || - (request->ruby_request.m_Type == RubyRequestType_FLUSH)); + assert((request->m_type == RubyRequestType_ST) || + (request->m_type == RubyRequestType_ATOMIC) || + (request->m_type == RubyRequestType_RMW_Read) || + (request->m_type == RubyRequestType_RMW_Write) || + (request->m_type == RubyRequestType_Load_Linked) || + (request->m_type == RubyRequestType_Store_Conditional) || + (request->m_type == RubyRequestType_Locked_RMW_Read) || + (request->m_type == RubyRequestType_Locked_RMW_Write) || + (request->m_type == RubyRequestType_FLUSH)); // @@ -402,9 +419,9 @@ Sequencer::writeCallback(const Address& address, if(!m_usingNetworkTester) success = handleLlsc(address, request); - if (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Read) { + if (request->m_type == RubyRequestType_Locked_RMW_Read) { m_controller->blockOnQueue(address, m_mandatory_q_ptr); - } else if (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Write) { + } else if (request->m_type == RubyRequestType_Locked_RMW_Write) { m_controller->unblock(address); } @@ -444,8 +461,8 @@ Sequencer::readCallback(const Address& address, m_readRequestTable.erase(i); markRemoved(); - assert((request->ruby_request.m_Type == RubyRequestType_LD) || - (request->ruby_request.m_Type == RubyRequestType_IFETCH)); + assert((request->m_type == RubyRequestType_LD) || + (request->m_type == RubyRequestType_IFETCH)); hitCallback(request, mach, data, true, initialRequestTime, forwardRequestTime, firstResponseTime); @@ -460,11 +477,11 @@ Sequencer::hitCallback(SequencerRequest* srequest, Time forwardRequestTime, Time firstResponseTime) { - const RubyRequest & ruby_request = srequest->ruby_request; - Address request_address(ruby_request.m_PhysicalAddress); - Address request_line_address(ruby_request.m_PhysicalAddress); + PacketPtr pkt = srequest->pkt; + Address request_address(pkt->getAddr()); + Address request_line_address(pkt->getAddr()); request_line_address.makeLineAddress(); - RubyRequestType type = ruby_request.m_Type; + RubyRequestType type = srequest->m_type; Time issued_time = srequest->issue_time; // Set this cache entry to the most recently used @@ -502,22 +519,22 @@ Sequencer::hitCallback(SequencerRequest* srequest, DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n", curTick(), m_version, "Seq", success ? "Done" : "SC_Failed", "", "", - ruby_request.m_PhysicalAddress, miss_latency); + request_address, miss_latency); } // update the data - if (ruby_request.data != NULL) { + if (pkt->getPtr<uint8_t>(true) != NULL) { if ((type == RubyRequestType_LD) || (type == RubyRequestType_IFETCH) || (type == RubyRequestType_RMW_Read) || (type == RubyRequestType_Locked_RMW_Read) || (type == RubyRequestType_Load_Linked)) { - memcpy(ruby_request.data, - data.getData(request_address.getOffset(), ruby_request.m_Size), - ruby_request.m_Size); + memcpy(pkt->getPtr<uint8_t>(true), + data.getData(request_address.getOffset(), pkt->getSize()), + pkt->getSize()); } else { - data.setData(ruby_request.data, request_address.getOffset(), - ruby_request.m_Size); + data.setData(pkt->getPtr<uint8_t>(true), + request_address.getOffset(), pkt->getSize()); } } else { DPRINTF(MemoryAccess, @@ -532,50 +549,16 @@ Sequencer::hitCallback(SequencerRequest* srequest, // RubyTester. if (m_usingRubyTester) { RubyPort::SenderState *requestSenderState = - safe_cast<RubyPort::SenderState*>(ruby_request.pkt->senderState); + safe_cast<RubyPort::SenderState*>(pkt->senderState); RubyTester::SenderState* testerSenderState = safe_cast<RubyTester::SenderState*>(requestSenderState->saved); testerSenderState->subBlock->mergeFrom(data); } - ruby_hit_callback(ruby_request.pkt); + ruby_hit_callback(pkt); delete srequest; } -// Returns true if the sequencer already has a load or store outstanding -RequestStatus -Sequencer::getRequestStatus(const RubyRequest& request) -{ - bool is_outstanding_store = - !!m_writeRequestTable.count(line_address(request.m_PhysicalAddress)); - bool is_outstanding_load = - !!m_readRequestTable.count(line_address(request.m_PhysicalAddress)); - if (is_outstanding_store) { - if ((request.m_Type == RubyRequestType_LD) || - (request.m_Type == RubyRequestType_IFETCH) || - (request.m_Type == RubyRequestType_RMW_Read)) { - m_store_waiting_on_load_cycles++; - } else { - m_store_waiting_on_store_cycles++; - } - return RequestStatus_Aliased; - } else if (is_outstanding_load) { - if ((request.m_Type == RubyRequestType_ST) || - (request.m_Type == RubyRequestType_RMW_Write)) { - m_load_waiting_on_store_cycles++; - } else { - m_load_waiting_on_load_cycles++; - } - return RequestStatus_Aliased; - } - - if (m_outstanding_count >= m_max_outstanding_requests) { - return RequestStatus_BufferFull; - } - - return RequestStatus_Ready; -} - bool Sequencer::empty() const { @@ -583,109 +566,118 @@ Sequencer::empty() const } RequestStatus -Sequencer::makeRequest(const RubyRequest &request) +Sequencer::makeRequest(PacketPtr pkt) { - assert(request.m_PhysicalAddress.getOffset() + request.m_Size <= - RubySystem::getBlockSizeBytes()); - RequestStatus status = getRequestStatus(request); - if (status != RequestStatus_Ready) - return status; + if (m_outstanding_count >= m_max_outstanding_requests) { + return RequestStatus_BufferFull; + } - SequencerRequest *srequest = - new SequencerRequest(request, g_eventQueue_ptr->getTime()); - bool found = insertRequest(srequest); - if (found) { - panic("Sequencer::makeRequest should never be called if the " - "request is already outstanding\n"); - return RequestStatus_NULL; + RubyRequestType primary_type = RubyRequestType_NULL; + RubyRequestType secondary_type = RubyRequestType_NULL; + + if (pkt->isLLSC()) { + // + // Alpha LL/SC instructions need to be handled carefully by the cache + // coherence protocol to ensure they follow the proper semantics. In + // particular, by identifying the operations as atomic, the protocol + // should understand that migratory sharing optimizations should not + // be performed (i.e. a load between the LL and SC should not steal + // away exclusive permission). + // + if (pkt->isWrite()) { + DPRINTF(RubySequencer, "Issuing SC\n"); + primary_type = RubyRequestType_Store_Conditional; + } else { + DPRINTF(RubySequencer, "Issuing LL\n"); + assert(pkt->isRead()); + primary_type = RubyRequestType_Load_Linked; + } + secondary_type = RubyRequestType_ATOMIC; + } else if (pkt->req->isLocked()) { + // + // x86 locked instructions are translated to store cache coherence + // requests because these requests should always be treated as read + // exclusive operations and should leverage any migratory sharing + // optimization built into the protocol. + // + if (pkt->isWrite()) { + DPRINTF(RubySequencer, "Issuing Locked RMW Write\n"); + primary_type = RubyRequestType_Locked_RMW_Write; + } else { + DPRINTF(RubySequencer, "Issuing Locked RMW Read\n"); + assert(pkt->isRead()); + primary_type = RubyRequestType_Locked_RMW_Read; + } + secondary_type = RubyRequestType_ST; + } else { + if (pkt->isRead()) { + if (pkt->req->isInstFetch()) { + primary_type = secondary_type = RubyRequestType_IFETCH; + } else { +#if THE_ISA == X86_ISA + uint32_t flags = pkt->req->getFlags(); + bool storeCheck = flags & + (TheISA::StoreCheck << TheISA::FlagShift); +#else + bool storeCheck = false; +#endif // X86_ISA + if (storeCheck) { + primary_type = RubyRequestType_RMW_Read; + secondary_type = RubyRequestType_ST; + } else { + primary_type = secondary_type = RubyRequestType_LD; + } + } + } else if (pkt->isWrite()) { + // + // Note: M5 packets do not differentiate ST from RMW_Write + // + primary_type = secondary_type = RubyRequestType_ST; + } else if (pkt->isFlush()) { + primary_type = secondary_type = RubyRequestType_FLUSH; + } else { + panic("Unsupported ruby packet type\n"); + } } - issueRequest(request); + RequestStatus status = insertRequest(pkt, primary_type); + if (status != RequestStatus_Ready) + return status; + + issueRequest(pkt, secondary_type); // TODO: issue hardware prefetches here return RequestStatus_Issued; } void -Sequencer::issueRequest(const RubyRequest& request) +Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) { - // TODO: Eliminate RubyRequest being copied again. - - RubyRequestType ctype = RubyRequestType_NUM; - switch(request.m_Type) { - case RubyRequestType_IFETCH: - ctype = RubyRequestType_IFETCH; - break; - case RubyRequestType_LD: - ctype = RubyRequestType_LD; - break; - case RubyRequestType_FLUSH: - ctype = RubyRequestType_FLUSH; - break; - case RubyRequestType_ST: - case RubyRequestType_RMW_Read: - case RubyRequestType_RMW_Write: - // - // x86 locked instructions are translated to store cache coherence - // requests because these requests should always be treated as read - // exclusive operations and should leverage any migratory sharing - // optimization built into the protocol. - // - case RubyRequestType_Locked_RMW_Read: - case RubyRequestType_Locked_RMW_Write: - ctype = RubyRequestType_ST; - break; - // - // Alpha LL/SC instructions need to be handled carefully by the cache - // coherence protocol to ensure they follow the proper semantics. In - // particular, by identifying the operations as atomic, the protocol - // should understand that migratory sharing optimizations should not be - // performed (i.e. a load between the LL and SC should not steal away - // exclusive permission). - // - case RubyRequestType_Load_Linked: - case RubyRequestType_Store_Conditional: - case RubyRequestType_ATOMIC: - ctype = RubyRequestType_ATOMIC; - break; - default: - assert(0); + int proc_id = -1; + if (pkt != NULL && pkt->req->hasContextId()) { + proc_id = pkt->req->contextId(); } - RubyAccessMode amtype = RubyAccessMode_NUM; - switch(request.m_AccessMode){ - case RubyAccessMode_User: - amtype = RubyAccessMode_User; - break; - case RubyAccessMode_Supervisor: - amtype = RubyAccessMode_Supervisor; - break; - case RubyAccessMode_Device: - amtype = RubyAccessMode_User; - break; - default: - assert(0); + // If valid, copy the pc to the ruby request + Addr pc = 0; + if (pkt->req->hasPC()) { + pc = pkt->req->getPC(); } - Address line_addr(request.m_PhysicalAddress); - line_addr.makeLineAddress(); - int proc_id = -1; - if (request.pkt != NULL && request.pkt->req->hasContextId()) { - proc_id = request.pkt->req->contextId(); - } - RubyRequest *msg = new RubyRequest(request.m_PhysicalAddress.getAddress(), - request.data, request.m_Size, - request.m_ProgramCounter.getAddress(), - ctype, amtype, request.pkt, + RubyRequest *msg = new RubyRequest(pkt->getAddr(), + pkt->getPtr<uint8_t>(true), + pkt->getSize(), pc, secondary_type, + RubyAccessMode_Supervisor, pkt, PrefetchBit_No, proc_id); DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n", curTick(), m_version, "Seq", "Begin", "", "", - request.m_PhysicalAddress, RubyRequestType_to_string(request.m_Type)); + msg->getPhysicalAddress(), + RubyRequestType_to_string(secondary_type)); Time latency = 0; // initialzed to an null value - if (request.m_Type == RubyRequestType_IFETCH) + if (secondary_type == RubyRequestType_IFETCH) latency = m_instCache_ptr->getLatency(); else latency = m_dataCache_ptr->getLatency(); diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 0589d8bbc..7c2d0af13 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -33,12 +33,9 @@ #include "base/hashmap.hh" #include "mem/protocol/GenericMachineType.hh" -#include "mem/protocol/PrefetchBit.hh" -#include "mem/protocol/RubyAccessMode.hh" #include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Consumer.hh" -#include "mem/ruby/common/Global.hh" #include "mem/ruby/system/RubyPort.hh" class DataBlock; @@ -50,11 +47,12 @@ class RubySequencerParams; struct SequencerRequest { - RubyRequest ruby_request; + PacketPtr pkt; + RubyRequestType m_type; Time issue_time; - SequencerRequest(const RubyRequest & _ruby_request, Time _issue_time) - : ruby_request(_ruby_request), issue_time(_issue_time) + SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, Time _issue_time) + : pkt(_pkt), m_type(_m_type), issue_time(_issue_time) {} }; @@ -100,8 +98,7 @@ class Sequencer : public RubyPort, public Consumer Time forwardRequestTime, Time firstResponseTime); - RequestStatus makeRequest(const RubyRequest & request); - RequestStatus getRequestStatus(const RubyRequest& request); + RequestStatus makeRequest(PacketPtr pkt); bool empty() const; void print(std::ostream& out) const; @@ -112,7 +109,7 @@ class Sequencer : public RubyPort, public Consumer void removeRequest(SequencerRequest* request); private: - void issueRequest(const RubyRequest& request); + void issueRequest(PacketPtr pkt, RubyRequestType type); void hitCallback(SequencerRequest* request, GenericMachineType mach, @@ -122,7 +119,7 @@ class Sequencer : public RubyPort, public Consumer Time forwardRequestTime, Time firstResponseTime); - bool insertRequest(SequencerRequest* request); + RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); bool handleLlsc(const Address& address, SequencerRequest* request); diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index fbd090d49..4d3618093 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -1355,7 +1355,7 @@ ${ident}_ProfileDumper::dumpStats(std::ostream& out) const #include "mem/protocol/${ident}_Event.hh" #include "mem/protocol/${ident}_State.hh" -#include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/TypeDefines.hh" class ${ident}_Profiler { diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py index b41ecc00f..ad00f2ac1 100644 --- a/src/mem/slicc/symbols/Type.py +++ b/src/mem/slicc/symbols/Type.py @@ -439,11 +439,16 @@ ${{self.c_ident}}::print(ostream& out) const #include <iostream> #include <string> -#include "mem/ruby/common/Global.hh" ''') if self.isStateDecl: code('#include "mem/protocol/AccessPermission.hh"') + if self.isMachineType: + code('#include "base/misc.hh"') + code('#include "mem/protocol/GenericMachineType.hh"') + code('#include "mem/ruby/common/Address.hh"') + code('struct MachineID;') + code(''' // Class definition @@ -488,7 +493,29 @@ int ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj); ''') for enum in self.enums.itervalues(): - code('#define MACHINETYPE_${{enum.ident}} 1') + if enum.ident == "DMA": + code(''' +MachineID map_Address_to_DMA(const Address &addr); +''') + code(''' + +MachineID get${{enum.ident}}MachineID(NodeID RubyNode); +''') + + code(''' +inline GenericMachineType +ConvertMachToGenericMach(MachineType machType) +{ +''') + for enum in self.enums.itervalues(): + code(''' + if (machType == MachineType_${{enum.ident}}) + return GenericMachineType_${{enum.ident}}; +''') + code(''' + panic("cannot convert to a GenericMachineType"); +} +''') if self.isStateDecl: code(''' @@ -550,6 +577,7 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj) if self.isMachineType: for enum in self.enums.itervalues(): code('#include "mem/protocol/${{enum.ident}}_Controller.hh"') + code('#include "mem/ruby/system/MachineID.hh"') code(''' // Code for output operator @@ -723,6 +751,27 @@ ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj) } ''') + for enum in self.enums.itervalues(): + if enum.ident == "DMA": + code(''' +MachineID +map_Address_to_DMA(const Address &addr) +{ + MachineID dma = {MachineType_DMA, 0}; + return dma; +} +''') + + code(''' + +MachineID +get${{enum.ident}}MachineID(NodeID RubyNode) +{ + MachineID mach = {MachineType_${{enum.ident}}, RubyNode}; + return mach; +} +''') + # Write the file code.write(path, "%s.cc" % self.c_ident) diff --git a/src/mem/translating_port.cc b/src/mem/translating_port.cc index 6a383a2bb..7d3123012 100644 --- a/src/mem/translating_port.cc +++ b/src/mem/translating_port.cc @@ -85,8 +85,8 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size) if (!pTable->translate(gen.addr(), paddr)) { if (allocating == Always) { - pTable->allocate(roundDown(gen.addr(), VMPageSize), - VMPageSize); + process->allocateMem(roundDown(gen.addr(), VMPageSize), + VMPageSize); } else if (allocating == NextPage) { // check if we've accessed the next page on the stack if (!process->fixupStackFault(gen.addr())) @@ -121,8 +121,8 @@ TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size) if (!pTable->translate(gen.addr(), paddr)) { if (allocating == Always) { - pTable->allocate(roundDown(gen.addr(), VMPageSize), - VMPageSize); + process->allocateMem(roundDown(gen.addr(), VMPageSize), + VMPageSize); pTable->translate(gen.addr(), paddr); } else { return false; diff --git a/src/python/SConscript b/src/python/SConscript index cbb37d0c5..c20389344 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -66,6 +66,7 @@ PySource('m5.util', 'm5/util/terminal.py') SwigSource('m5.internal', 'swig/core.i') SwigSource('m5.internal', 'swig/debug.i') SwigSource('m5.internal', 'swig/event.i') +SwigSource('m5.internal', 'swig/pyobject.i') SwigSource('m5.internal', 'swig/range.i') SwigSource('m5.internal', 'swig/stats.i') SwigSource('m5.internal', 'swig/trace.i') diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 9729fd30f..60693758c 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -97,37 +97,6 @@ allClasses = {} # dict to look up SimObjects based on path instanceDict = {} -def default_cxx_predecls(cls, code): - code('#include "params/$cls.hh"') - -def default_swig_predecls(cls, code): - code('%import "python/m5/internal/param_$cls.i"') - -def default_swig_objdecls(cls, code): - class_path = cls.cxx_class.split('::') - classname = class_path[-1] - namespaces = class_path[:-1] - - for ns in namespaces: - code('namespace $ns {') - - if namespaces: - code('// avoid name conflicts') - sep_string = '_COLONS_' - flat_name = sep_string.join(class_path) - code('%rename($flat_name) $classname;') - - code() - code('// stop swig from creating/wrapping default ctor/dtor') - code('%nodefault $classname;') - code('class $classname') - if cls._base: - code(' : public ${{cls._base.cxx_class}}') - code('{};') - - for ns in reversed(namespaces): - code('} // namespace $ns') - def public_value(key, value): return key.startswith('_') or \ isinstance(value, (FunctionType, MethodType, ModuleType, @@ -142,9 +111,6 @@ class MetaSimObject(type): init_keywords = { 'abstract' : bool, 'cxx_class' : str, 'cxx_type' : str, - 'cxx_predecls' : MethodType, - 'swig_objdecls' : MethodType, - 'swig_predecls' : MethodType, 'type' : str } # Attributes that can be set any time keywords = { 'check' : FunctionType } @@ -223,18 +189,20 @@ class MetaSimObject(type): cls._value_dict['cxx_class'] = cls._value_dict['type'] cls._value_dict['cxx_type'] = '%s *' % cls._value_dict['cxx_class'] - - if 'cxx_predecls' not in cls.__dict__: - m = MethodType(default_cxx_predecls, cls, MetaSimObject) - setattr(cls, 'cxx_predecls', m) - - if 'swig_predecls' not in cls.__dict__: - m = MethodType(default_swig_predecls, cls, MetaSimObject) - setattr(cls, 'swig_predecls', m) - if 'swig_objdecls' not in cls.__dict__: - m = MethodType(default_swig_objdecls, cls, MetaSimObject) - setattr(cls, 'swig_objdecls', m) + # Export methods are automatically inherited via C++, so we + # don't want the method declarations to get inherited on the + # python side (and thus end up getting repeated in the wrapped + # versions of derived classes). The code below basicallly + # suppresses inheritance by substituting in the base (null) + # versions of these methods unless a different version is + # explicitly supplied. + for method_name in ('export_methods', 'export_method_cxx_predecls', + 'export_method_swig_predecls'): + if method_name not in cls.__dict__: + base_method = getattr(MetaSimObject, method_name) + m = MethodType(base_method, cls, MetaSimObject) + setattr(cls, method_name, m) # Now process the _value_dict items. They could be defining # new (or overriding existing) parameters or ports, setting @@ -378,8 +346,99 @@ class MetaSimObject(type): def __str__(cls): return cls.__name__ - def cxx_decl(cls, code): - # The 'dict' attribute restricts us to the params declared in + # See ParamValue.cxx_predecls for description. + def cxx_predecls(cls, code): + code('#include "params/$cls.hh"') + + # See ParamValue.swig_predecls for description. + def swig_predecls(cls, code): + code('%import "python/m5/internal/param_$cls.i"') + + # Hook for exporting additional C++ methods to Python via SWIG. + # Default is none, override using @classmethod in class definition. + def export_methods(cls, code): + pass + + # Generate the code needed as a prerequisite for the C++ methods + # exported via export_methods() to be compiled in the _wrap.cc + # file. Typically generates one or more #include statements. If + # any methods are exported, typically at least the C++ header + # declaring the relevant SimObject class must be included. + def export_method_cxx_predecls(cls, code): + pass + + # Generate the code needed as a prerequisite for the C++ methods + # exported via export_methods() to be processed by SWIG. + # Typically generates one or more %include or %import statements. + # If any methods are exported, typically at least the C++ header + # declaring the relevant SimObject class must be included. + def export_method_swig_predecls(cls, code): + pass + + # Generate the declaration for this object for wrapping with SWIG. + # Generates code that goes into a SWIG .i file. Called from + # src/SConscript. + def swig_decl(cls, code): + class_path = cls.cxx_class.split('::') + classname = class_path[-1] + namespaces = class_path[:-1] + + # The 'local' attribute restricts us to the params declared in + # the object itself, not including inherited params (which + # will also be inherited from the base class's param struct + # here). + params = cls._params.local.values() + + code('%module(package="m5.internal") param_$cls') + code() + code('%{') + code('#include "params/$cls.hh"') + for param in params: + param.cxx_predecls(code) + cls.export_method_cxx_predecls(code) + code('%}') + code() + + for param in params: + param.swig_predecls(code) + cls.export_method_swig_predecls(code) + + code() + if cls._base: + code('%import "python/m5/internal/param_${{cls._base}}.i"') + code() + + for ns in namespaces: + code('namespace $ns {') + + if namespaces: + code('// avoid name conflicts') + sep_string = '_COLONS_' + flat_name = sep_string.join(class_path) + code('%rename($flat_name) $classname;') + + code() + code('// stop swig from creating/wrapping default ctor/dtor') + code('%nodefault $classname;') + code('class $classname') + if cls._base: + code(' : public ${{cls._base.cxx_class}}') + code('{') + code(' public:') + cls.export_methods(code) + code('};') + + for ns in reversed(namespaces): + code('} // namespace $ns') + + code() + code('%include "params/$cls.hh"') + + + # Generate the C++ declaration (.hh file) for this SimObject's + # param struct. Called from src/SConscript. + def cxx_param_decl(cls, code): + # The 'local' attribute restricts us to the params declared in # the object itself, not including inherited params (which # will also be inherited from the base class's param struct # here). @@ -408,6 +467,20 @@ class MetaSimObject(type): code('} // namespace $ns') code() + # The base SimObject has a couple of params that get + # automatically set from Python without being declared through + # the normal Param mechanism; we slip them in here (needed + # predecls now, actual declarations below) + if cls == SimObject: + code(''' +#ifndef PY_VERSION +struct PyObject; +#endif + +#include <string> + +struct EventQueue; +''') for param in params: param.cxx_predecls(code) code() @@ -421,65 +494,39 @@ class MetaSimObject(type): code('#include "enums/${{ptype.__name__}}.hh"') code() - cls.cxx_struct(code, cls._base, params) - - code() - code('#endif // __PARAMS__${cls}__') - return code - - def cxx_struct(cls, code, base, params): - if cls == SimObject: - code('#include "sim/sim_object_params.hh"') - return - # now generate the actual param struct code("struct ${cls}Params") - if base: - code(" : public ${{base.type}}Params") + if cls._base: + code(" : public ${{cls._base.type}}Params") code("{") if not hasattr(cls, 'abstract') or not cls.abstract: if 'type' in cls.__dict__: code(" ${{cls.cxx_type}} create();") code.indent() + if cls == SimObject: + code(''' + SimObjectParams() + { + extern EventQueue mainEventQueue; + eventq = &mainEventQueue; + } + virtual ~SimObjectParams() {} + + std::string name; + PyObject *pyobj; + EventQueue *eventq; + ''') for param in params: param.cxx_decl(code) code.dedent() code('};') - def swig_decl(cls, code): - code('''\ -%module $cls - -%{ -#include "params/$cls.hh" -%} - -''') - - # The 'dict' attribute restricts us to the params declared in - # the object itself, not including inherited params (which - # will also be inherited from the base class's param struct - # here). - params = cls._params.local.values() - ptypes = [p.ptype for p in params] - - # get all predeclarations - for param in params: - param.swig_predecls(code) code() + code('#endif // __PARAMS__${cls}__') + return code - if cls._base: - code('%import "python/m5/internal/param_${{cls._base.type}}.i"') - code() - - for ptype in ptypes: - if issubclass(ptype, Enum): - code('%import "enums/${{ptype.__name__}}.hh"') - code() - code('%import "params/${cls}_type.hh"') - code('%include "params/${cls}.hh"') # The SimObject class is the root of the special hierarchy. Most of # the code in this class deals with the configuration hierarchy itself @@ -492,8 +539,42 @@ class SimObject(object): abstract = True @classmethod - def swig_objdecls(cls, code): - code('%include "python/swig/sim_object.i"') + def export_method_cxx_predecls(cls, code): + code(''' +#include <Python.h> + +#include "sim/serialize.hh" +#include "sim/sim_object.hh" +''') + + @classmethod + def export_method_swig_predecls(cls, code): + code(''' +%include <std_string.i> +''') + + @classmethod + def export_methods(cls, code): + code(''' + enum State { + Running, + Draining, + Drained + }; + + void init(); + void loadState(Checkpoint *cp); + void initState(); + void regStats(); + void regFormulas(); + void resetStats(); + void startup(); + + unsigned int drain(Event *drain_event); + void resume(); + void switchOut(); + void takeOverFrom(BaseCPU *cpu); +''') # Initialize new instance. For objects with SimObject-valued # children, we need to recursively clone the classes represented diff --git a/src/python/m5/internal/__init__.py b/src/python/m5/internal/__init__.py index 4aa76cca7..ca09ab468 100644 --- a/src/python/m5/internal/__init__.py +++ b/src/python/m5/internal/__init__.py @@ -29,6 +29,5 @@ import core import debug import event -import random import stats import trace diff --git a/src/python/m5/params.py b/src/python/m5/params.py index ee94ae004..ee3678dc9 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -81,10 +81,17 @@ class MetaParamValue(type): class ParamValue(object): __metaclass__ = MetaParamValue + + # Generate the code needed as a prerequisite for declaring a C++ + # object of this type. Typically generates one or more #include + # statements. Used when declaring parameters of this type. @classmethod def cxx_predecls(cls, code): pass + # Generate the code needed as a prerequisite for including a + # reference to a C++ object of this type in a SWIG .i file. + # Typically generates one or more %import or %include statements. @classmethod def swig_predecls(cls, code): pass @@ -101,8 +108,6 @@ class ParamValue(object): # Regular parameter description. class ParamDesc(object): - file_ext = 'ptype' - def __init__(self, ptype_str, ptype, *args, **kwargs): self.ptype_str = ptype_str # remember ptype only if it is provided @@ -159,6 +164,7 @@ class ParamDesc(object): return self.ptype(value) def cxx_predecls(self, code): + code('#include <cstddef>') self.ptype.cxx_predecls(code) def swig_predecls(self, code): @@ -223,8 +229,6 @@ class SimObjectVector(VectorParamValue): yield obj class VectorParamDesc(ParamDesc): - file_ext = 'vptype' - # Convert assigned value to appropriate type. If the RHS is not a # list or tuple, it generates a single-element list. def convert(self, value): @@ -240,10 +244,14 @@ class VectorParamDesc(ParamDesc): else: return VectorParamValue(tmp_list) + def swig_module_name(self): + return "%s_vector" % self.ptype_str + def swig_predecls(self, code): - code('%import "vptype_${{self.ptype_str}}.i"') + code('%import "${{self.swig_module_name()}}.i"') def swig_decl(self, code): + code('%module(package="m5.internal") ${{self.swig_module_name()}}') code('%{') self.ptype.cxx_predecls(code) code('%}') @@ -1043,6 +1051,19 @@ namespace Enums { } // namespace Enums ''') + def swig_decl(cls, code): + name = cls.__name__ + code('''\ +%module(package="m5.internal") enum_$name + +%{ +#include "enums/$name.hh" +%} + +%include "enums/$name.hh" +''') + + # Base class for enum types. class Enum(ParamValue): __metaclass__ = MetaEnum @@ -1362,7 +1383,7 @@ class PortRef(object): # Call C++ to create corresponding port connection between C++ objects def ccConnect(self): - from m5.internal.params import connectPorts + from m5.internal.pyobject import connectPorts if self.ccConnected: # already done this return diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc index 82a54545f..3478310b1 100644 --- a/src/python/swig/pyobject.cc +++ b/src/python/swig/pyobject.cc @@ -88,16 +88,11 @@ int connectPorts(SimObject *o1, const std::string &name1, int i1, SimObject *o2, const std::string &name2, int i2) { - MemObject *mo1, *mo2; - mo1 = dynamic_cast<MemObject*>(o1); - mo2 = dynamic_cast<MemObject*>(o2); - if (FullSystem) { EtherObject *eo1, *eo2; EtherDevice *ed1, *ed2; eo1 = dynamic_cast<EtherObject*>(o1); ed1 = dynamic_cast<EtherDevice*>(o1); - eo2 = dynamic_cast<EtherObject*>(o2); ed2 = dynamic_cast<EtherDevice*>(o2); diff --git a/src/python/swig/sim_object.i b/src/python/swig/pyobject.i index 06f683aa1..a26f569ce 100644 --- a/src/python/swig/sim_object.i +++ b/src/python/swig/pyobject.i @@ -28,6 +28,8 @@ * Authors: Nathan Binkert */ +%module(package="m5.internal") pyobject + %{ #include "python/swig/pyobject.hh" %} @@ -36,34 +38,6 @@ %include <std_string.i> %include <stdint.i> -%include "base/types.hh" -%include "sim/sim_object_params.hh" - -class BaseCPU; - -class SimObject { - public: - enum State { - Running, - Draining, - Drained - }; - - void init(); - void loadState(Checkpoint *cp); - void initState(); - void regStats(); - void regFormulas(); - void resetStats(); - void startup(); - - unsigned int drain(Event *drain_event); - void resume(); - void switchOut(); - void takeOverFrom(BaseCPU *cpu); - SimObject(const SimObjectParams *p); -}; - int connectPorts(SimObject *o1, const std::string &name1, int i1, SimObject *o2, const std::string &name2, int i2); diff --git a/src/python/swig/system.i b/src/python/swig/system.i deleted file mode 100644 index 1aadcecc6..000000000 --- a/src/python/swig/system.i +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -%{ -#include "sim/system.hh" -%} - -%import "enums/MemoryMode.hh" -%import "python/swig/sim_object.i" - -class System : public SimObject -{ - private: - System(); - public: - Enums::MemoryMode getMemoryMode(); - void setMemoryMode(Enums::MemoryMode mode); -}; - diff --git a/src/sim/System.py b/src/sim/System.py index 25643099d..db214abc0 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -41,8 +41,15 @@ class System(SimObject): type = 'System' @classmethod - def swig_objdecls(cls, code): - code('%include "python/swig/system.i"') + def export_method_cxx_predecls(cls, code): + code('#include "sim/system.hh"') + + @classmethod + def export_methods(cls, code): + code(''' + Enums::MemoryMode getMemoryMode(); + void setMemoryMode(Enums::MemoryMode mode); +''') physmem = Param.PhysicalMemory("Physical Memory") mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") diff --git a/src/sim/process.cc b/src/sim/process.cc index ba43a6b77..468f42955 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -159,7 +159,7 @@ Process::Process(ProcessParams * params) mmap_start = mmap_end = 0; nxm_start = nxm_end = 0; - pTable = new PageTable(this); + pTable = new PageTable(name(), M5_pid); // other parameters will be initialized when the program is loaded } @@ -318,13 +318,21 @@ Process::sim_fd_obj(int tgt_fd) return &fd_map[tgt_fd]; } +void +Process::allocateMem(Addr vaddr, int64_t size, bool clobber) +{ + int npages = divCeil(size, (int64_t)VMPageSize); + Addr paddr = system->allocPhysPages(npages); + pTable->map(vaddr, paddr, size, clobber); +} + bool Process::fixupStackFault(Addr vaddr) { // Check if this is already on the stack and there's just no page there // yet. if (vaddr >= stack_min && vaddr < stack_base) { - pTable->allocate(roundDown(vaddr, VMPageSize), VMPageSize); + allocateMem(roundDown(vaddr, VMPageSize), VMPageSize); return true; } @@ -337,7 +345,7 @@ Process::fixupStackFault(Addr vaddr) fatal("Maximum stack size exceeded\n"); if (stack_base - stack_min > 8 * 1024 * 1024) fatal("Over max stack size for one thread\n"); - pTable->allocate(stack_min, TheISA::PageBytes); + allocateMem(stack_min, TheISA::PageBytes); inform("Increasing stack size by one page."); }; return true; diff --git a/src/sim/process.hh b/src/sim/process.hh index 82879c0e6..f738bb38a 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -203,6 +203,8 @@ class Process : public SimObject virtual void syscall(int64_t callnum, ThreadContext *tc) = 0; + void allocateMem(Addr vaddr, int64_t size, bool clobber = false); + /// Attempt to fix up a fault at vaddr by allocating a page on the stack. /// @return Whether the fault has been fixed. bool fixupStackFault(Addr vaddr); diff --git a/src/sim/sim_object_params.hh b/src/sim/sim_object_params.hh deleted file mode 100644 index 750181135..000000000 --- a/src/sim/sim_object_params.hh +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Nathan Binkert - */ - -#ifndef __SIM_SIM_OBJECT_PARAMS_HH__ -#define __SIM_SIM_OBJECT_PARAMS_HH__ - -#ifndef PY_VERSION -struct PyObject; -#endif - -#include <string> - -struct EventQueue; - -struct SimObjectParams -{ - SimObjectParams() - { - extern EventQueue mainEventQueue; - eventq = &mainEventQueue; - } - virtual ~SimObjectParams() {} - - std::string name; - PyObject *pyobj; - EventQueue *eventq; -}; - - -#endif // __SIM_SIM_OBJECT_PARAMS_HH__ diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc index 6873d4aa4..203eaff2a 100644 --- a/src/sim/syscall_emul.cc +++ b/src/sim/syscall_emul.cc @@ -166,8 +166,7 @@ brkFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc) for (ChunkGenerator gen(p->brk_point, new_brk - p->brk_point, VMPageSize); !gen.done(); gen.next()) { if (!p->pTable->translate(gen.addr())) - p->pTable->allocate(roundDown(gen.addr(), VMPageSize), - VMPageSize); + p->allocateMem(roundDown(gen.addr(), VMPageSize), VMPageSize); // if the address is already there, zero it out else { diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index aff66ae9c..5c480272d 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -678,7 +678,7 @@ mremapFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ThreadContext * if (new_length > old_length) { if ((start + old_length) == process->mmap_end) { uint64_t diff = new_length - old_length; - process->pTable->allocate(process->mmap_end, diff); + process->allocateMem(process->mmap_end, diff); process->mmap_end += diff; return start; } else { @@ -692,15 +692,15 @@ mremapFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ThreadContext * process->mmap_end, process->mmap_end + new_length, new_length); start = process->mmap_end; // add on the remaining unallocated pages - process->pTable->allocate(start + old_length, new_length - old_length); + process->allocateMem(start + old_length, + new_length - old_length); process->mmap_end += new_length; warn("returning %08p as start\n", start); return start; } } } else { - process->pTable->deallocate(start + new_length, old_length - - new_length); + process->pTable->unmap(start + new_length, old_length - new_length); return start; } } @@ -1028,20 +1028,45 @@ mmapFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc) return -EINVAL; } - if (start != 0) { - warn("mmap: ignoring suggested map address 0x%x, using 0x%x", - start, p->mmap_end); + // are we ok with clobbering existing mappings? only set this to + // true if the user has been warned. + bool clobber = false; + + // try to use the caller-provided address if there is one + bool use_provided_address = (start != 0); + + if (use_provided_address) { + // check to see if the desired address is already in use + if (!p->pTable->isUnmapped(start, length)) { + // there are existing mappings in the desired range + // whether we clobber them or not depends on whether the caller + // specified MAP_FIXED + if (flags & OS::TGT_MAP_FIXED) { + // MAP_FIXED specified: clobber existing mappings + warn("mmap: MAP_FIXED at 0x%x overwrites existing mappings\n", + start); + clobber = true; + } else { + // MAP_FIXED not specified: ignore suggested start address + warn("mmap: ignoring suggested map address 0x%x\n", start); + use_provided_address = false; + } + } } - // pick next address from our "mmap region" - if (OS::mmapGrowsDown()) { - start = p->mmap_end - length; - p->mmap_end = start; - } else { - start = p->mmap_end; - p->mmap_end += length; + if (!use_provided_address) { + // no address provided, or provided address unusable: + // pick next address from our "mmap region" + if (OS::mmapGrowsDown()) { + start = p->mmap_end - length; + p->mmap_end = start; + } else { + start = p->mmap_end; + p->mmap_end += length; + } } - p->pTable->allocate(start, length); + + p->allocateMem(start, length, clobber); return start; } diff --git a/src/sim/system.cc b/src/sim/system.cc index 654bcef80..3051cb64b 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -261,10 +261,10 @@ System::replaceThreadContext(ThreadContext *tc, int context_id) } Addr -System::new_page() +System::allocPhysPages(int npages) { Addr return_addr = pagePtr << LogVMPageSize; - ++pagePtr; + pagePtr += npages; if (return_addr >= physmem->size()) fatal("Out of memory, please increase size of physical memory."); return return_addr; diff --git a/src/sim/system.hh b/src/sim/system.hh index a8d336d03..00d8360e0 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -271,7 +271,9 @@ class System : public SimObject */ Addr getKernelEntry() const { return kernelEntry; } - Addr new_page(); + /// Allocate npages contiguous unused physical pages + /// @return Starting address of first page + Addr allocPhysPages(int npages); int registerThreadContext(ThreadContext *tc, int assigned=-1); void replaceThreadContext(ThreadContext *tc, int context_id); diff --git a/tests/SConscript b/tests/SConscript index 0ded4b9ec..12328c0c1 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -123,7 +123,9 @@ def run_test(target, source, env): nap += 1 outdiff = os.path.join(tgt_dir, 'outdiff') - diffcmd = 'diff -ubrs %s ${SOURCES[2].dir} %s > %s' \ + # tack 'true' on the end so scons doesn't report diff's + # non-zero exit code as a build error + diffcmd = 'diff -ubrs %s ${SOURCES[2].dir} %s > %s; true' \ % (output_ignore_args, tgt_dir, outdiff) env.Execute(env.subst(diffcmd, target=target, source=source)) print "===== Output differences =====" diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index 8176c7e05..ffb5e6ddd 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -3,10 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:24:14 -gem5 started Aug 20 2011 13:24:28 -gem5 executing on zizzer +gem5 compiled Nov 16 2011 11:08:03 +gem5 started Nov 17 2011 13:09:16 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing +tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -1064,4 +1065,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 586755503000 because target called exit() +Exiting @ tick 586294224000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 5610b27f8..db687aea5 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,144 +1,144 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.586756 # Number of seconds simulated -sim_ticks 586755503000 # Number of ticks simulated +sim_seconds 0.586294 # Number of seconds simulated +sim_ticks 586294224000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143909 # Simulator instruction rate (inst/s) -host_tick_rate 52074943 # Simulator tick rate (ticks/s) -host_mem_usage 212036 # Number of bytes of host memory used -host_seconds 11267.52 # Real time elapsed on the host +host_inst_rate 112274 # Simulator instruction rate (inst/s) +host_tick_rate 40595683 # Simulator tick rate (ticks/s) +host_mem_usage 244844 # Number of bytes of host memory used +host_seconds 14442.28 # Real time elapsed on the host sim_insts 1621493982 # Number of instructions simulated system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1173511007 # number of cpu cycles simulated +system.cpu.numCycles 1172588449 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 142841694 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 142841694 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7891104 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 135940863 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 135060067 # Number of BTB hits +system.cpu.BPredUnit.lookups 142448983 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 142448983 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7804844 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 134509889 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 133615988 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 143543484 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1144373207 # Number of instructions fetch has processed -system.cpu.fetch.Branches 142841694 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135060067 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 330625683 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 57747911 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 649508878 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 359 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 137309352 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 979465 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1173333177 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.784853 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.106580 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 143149229 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1143761055 # Number of instructions fetch has processed +system.cpu.fetch.Branches 142448983 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133615988 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 330199440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 57554993 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 649541012 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 331 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 137027209 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 996742 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1172439660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.784546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.109877 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 845712931 72.08% 72.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 16031093 1.37% 73.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 18099843 1.54% 74.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 17610691 1.50% 76.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 23355712 1.99% 78.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 16618957 1.42% 79.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 23183901 1.98% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28217498 2.40% 84.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 184502551 15.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 845244296 72.09% 72.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 17110181 1.46% 73.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 18043141 1.54% 75.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 16408368 1.40% 76.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 23340182 1.99% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16629602 1.42% 79.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 21855680 1.86% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28257046 2.41% 84.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 185551164 15.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1173333177 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121722 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.975170 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 241132491 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 558355752 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 229474776 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 94715442 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 49654716 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2072768748 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 49654716 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 290885704 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 132416469 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3327 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 257077103 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 443295858 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2043085659 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2266 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 278274210 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 129493006 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2031275937 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4957669219 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4957665711 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3508 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1172439660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.121483 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.975416 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 240695556 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 558473143 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 228947071 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 94774294 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 49549596 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2070409567 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 49549596 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 290323713 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 132525789 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3175 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 256725592 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 443311795 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2043122328 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2634 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 278313629 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 129499394 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2031527324 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4954653616 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4954649396 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4220 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 413281287 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 97 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 97 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 792932011 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 519352258 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 227004848 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 355033834 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 148905529 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1987362019 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1782207350 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 181989 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 365718291 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 672335048 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1173333177 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.518927 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.333963 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 413532674 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 91 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 793190427 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 519090632 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 226808407 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 354951645 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 148937435 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1986583518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1781630005 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 180825 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 364939190 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 670712331 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1172439660 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.519592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.333662 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 272616502 23.23% 23.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 416904584 35.53% 58.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234897308 20.02% 78.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 156871571 13.37% 92.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 54320414 4.63% 96.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 21136145 1.80% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 14479536 1.23% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1803096 0.15% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 304021 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 271921708 23.19% 23.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 416937500 35.56% 58.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234725234 20.02% 78.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 156776493 13.37% 92.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 54385701 4.64% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 21203892 1.81% 98.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 14378982 1.23% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1804798 0.15% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 305352 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1173333177 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1172439660 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 181055 7.04% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2242910 87.15% 94.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 149595 5.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 179772 6.92% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2269895 87.35% 94.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 148998 5.73% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 26996432 1.51% 1.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1102299326 61.85% 63.37% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 26894248 1.51% 1.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1102052870 61.86% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued @@ -167,85 +167,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 458202367 25.71% 89.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194709225 10.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 457985397 25.71% 89.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 194697490 10.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1782207350 # Type of FU issued -system.cpu.iq.rate 1.518697 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2573560 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001444 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4740503284 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2353289601 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1760306484 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 142 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 608 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 36 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1757784406 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 205673181 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1781630005 # Type of FU issued +system.cpu.iq.rate 1.519399 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2598665 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001459 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4738479065 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2351732069 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1760053766 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 95 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 542 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1757334382 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 205665909 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 100310133 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 59834 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 216613 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 38818791 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 100048507 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 60622 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 216417 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 38622350 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1385 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35852 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 849 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 34395 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 49654716 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1300952 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 134624 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1987362110 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 591185 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 519352258 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 227004848 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65366 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 216613 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4590434 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3486470 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8076904 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1768811104 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 452331737 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 13396246 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 49549596 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1308890 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 133908 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1986583734 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 659432 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 519090632 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 226808407 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 64911 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 28 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 216417 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4603219 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3388875 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7992094 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1768232809 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 452047218 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 13397196 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 646217865 # number of memory reference insts executed -system.cpu.iew.exec_branches 112172746 # Number of branches executed -system.cpu.iew.exec_stores 193886128 # Number of stores executed -system.cpu.iew.exec_rate 1.507281 # Inst execution rate -system.cpu.iew.wb_sent 1766741886 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1760306520 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1336435928 # num instructions producing a value -system.cpu.iew.wb_consumers 2002913192 # num instructions consuming a value +system.cpu.iew.exec_refs 645919458 # number of memory reference insts executed +system.cpu.iew.exec_branches 112169596 # Number of branches executed +system.cpu.iew.exec_stores 193872240 # Number of stores executed +system.cpu.iew.exec_rate 1.507974 # Inst execution rate +system.cpu.iew.wb_sent 1766226830 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1760053778 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1336567337 # num instructions producing a value +system.cpu.iew.wb_consumers 2003494286 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.500034 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.667246 # average fanout of values written-back +system.cpu.iew.wb_rate 1.500999 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667118 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 365887065 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 365103312 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7891152 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1123678461 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.443023 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.662640 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7804888 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1122890064 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.444036 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.662985 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 347480674 30.92% 30.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 438655867 39.04% 69.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 94938828 8.45% 78.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 133745830 11.90% 90.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36833685 3.28% 93.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26175862 2.33% 95.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22548594 2.01% 97.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8175613 0.73% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15123508 1.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 346724877 30.88% 30.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 438665808 39.07% 69.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 94902960 8.45% 78.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 133728922 11.91% 90.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36854784 3.28% 93.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26115374 2.33% 95.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22565758 2.01% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8207714 0.73% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15123867 1.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1123678461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1122890064 # Number of insts commited each cycle system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 607228182 # Number of memory references committed @@ -255,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15123508 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15123867 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3095936000 # The number of ROB reads -system.cpu.rob.rob_writes 4024437562 # The number of ROB writes -system.cpu.timesIdled 44153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 177830 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3094363491 # The number of ROB reads +system.cpu.rob.rob_writes 4022764791 # The number of ROB writes +system.cpu.timesIdled 43542 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 148789 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.723722 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.723722 # CPI: Total CPI of All Threads -system.cpu.ipc 1.381746 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.381746 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3273654764 # number of integer regfile reads -system.cpu.int_regfile_writes 1756473314 # number of integer regfile writes -system.cpu.fp_regfile_reads 36 # number of floating regfile reads -system.cpu.misc_regfile_reads 909253494 # number of misc regfile reads -system.cpu.icache.replacements 16 # number of replacements -system.cpu.icache.tagsinuse 813.268656 # Cycle average of tags in use -system.cpu.icache.total_refs 137308116 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 900 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 152564.573333 # Average number of references to valid blocks. +system.cpu.cpi 0.723153 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.723153 # CPI: Total CPI of All Threads +system.cpu.ipc 1.382833 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.382833 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3273039620 # number of integer regfile reads +system.cpu.int_regfile_writes 1756091293 # number of integer regfile writes +system.cpu.fp_regfile_reads 12 # number of floating regfile reads +system.cpu.misc_regfile_reads 908871446 # number of misc regfile reads +system.cpu.icache.replacements 12 # number of replacements +system.cpu.icache.tagsinuse 810.394392 # Cycle average of tags in use +system.cpu.icache.total_refs 137025977 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 893 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 153444.543113 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 813.268656 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.397104 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 137308116 # number of ReadReq hits -system.cpu.icache.demand_hits 137308116 # number of demand (read+write) hits -system.cpu.icache.overall_hits 137308116 # number of overall hits -system.cpu.icache.ReadReq_misses 1236 # number of ReadReq misses -system.cpu.icache.demand_misses 1236 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1236 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 43480000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 43480000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 43480000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 137309352 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 137309352 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 137309352 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 810.394392 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.395700 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 137025977 # number of ReadReq hits +system.cpu.icache.demand_hits 137025977 # number of demand (read+write) hits +system.cpu.icache.overall_hits 137025977 # number of overall hits +system.cpu.icache.ReadReq_misses 1232 # number of ReadReq misses +system.cpu.icache.demand_misses 1232 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1232 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 43328500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 43328500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 43328500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 137027209 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 137027209 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 137027209 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35177.993528 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35177.993528 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35177.993528 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 35169.237013 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35169.237013 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35169.237013 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -306,130 +306,130 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 336 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 336 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 900 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 900 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 900 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 339 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 339 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 893 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 893 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 893 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 31792500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 31792500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 31792500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 31560500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 31560500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 31560500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35325 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35325 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35325 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35342.105263 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35342.105263 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35342.105263 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 459082 # number of replacements -system.cpu.dcache.tagsinuse 4094.908409 # Cycle average of tags in use -system.cpu.dcache.total_refs 433296852 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 463178 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 935.486685 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 317735000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4094.908409 # Average occupied blocks per context +system.cpu.dcache.replacements 459077 # number of replacements +system.cpu.dcache.tagsinuse 4094.907333 # Cycle average of tags in use +system.cpu.dcache.total_refs 433034493 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463173 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 934.930346 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317767000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4094.907333 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 246417961 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 186878891 # number of WriteReq hits -system.cpu.dcache.demand_hits 433296852 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 433296852 # number of overall hits -system.cpu.dcache.ReadReq_misses 217222 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1307166 # number of WriteReq misses -system.cpu.dcache.demand_misses 1524388 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 1524388 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2206460500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 25191688497 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 27398148997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 27398148997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 246635183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 246142702 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 186891791 # number of WriteReq hits +system.cpu.dcache.demand_hits 433034493 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 433034493 # number of overall hits +system.cpu.dcache.ReadReq_misses 217277 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1294266 # number of WriteReq misses +system.cpu.dcache.demand_misses 1511543 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1511543 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 2206130500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 25062764496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 27268894996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 27268894996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 246359979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 434821240 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 434821240 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.000881 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.006946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.003506 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003506 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 10157.629062 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 19271.988789 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 17973.212199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 17973.212199 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1884500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 490158000 # number of cycles access was blocked +system.cpu.dcache.demand_accesses 434546036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 434546036 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000882 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.006878 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.003478 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.003478 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 10153.539031 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 19364.461785 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 18040.436161 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 18040.436161 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1883000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 482947000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 33499 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3909.751037 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14632.018866 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 32670 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3906.639004 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14782.583410 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 410010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 3618 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1057590 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1061208 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1061208 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 213604 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249576 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 463180 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 463180 # number of overall MSHR misses +system.cpu.dcache.writebacks 410037 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 3648 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1044720 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1048368 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1048368 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 213629 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249546 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 463175 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 463175 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1533784000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2518332500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4052116500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4052116500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1533480500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2506697000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4040177500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4040177500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000867 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.001065 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.001065 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7180.502238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10090.443392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.001066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.001066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7178.241250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10045.029774 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8722.788363 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8722.788363 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 73626 # number of replacements -system.cpu.l2cache.tagsinuse 17961.057219 # Cycle average of tags in use -system.cpu.l2cache.total_refs 452680 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 89247 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.072215 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 73618 # number of replacements +system.cpu.l2cache.tagsinuse 17964.500601 # Cycle average of tags in use +system.cpu.l2cache.total_refs 452679 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89237 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.072773 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 1976.377276 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15984.679942 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.060314 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.487814 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 181326 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 410010 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 190857 # number of ReadExReq hits +system.cpu.l2cache.occ_blocks::0 1976.098849 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15988.401752 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.060306 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.487927 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 181359 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 410037 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 190824 # number of ReadExReq hits system.cpu.l2cache.demand_hits 372183 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 372183 # number of overall hits -system.cpu.l2cache.ReadReq_misses 33178 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 58719 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 91897 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 91897 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1131489500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2019003500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 3150493000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 3150493000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 214504 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 410010 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 249576 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 464080 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 464080 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.154673 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.235275 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.198020 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.198020 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34103.607812 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34384.160153 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34282.871040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34282.871040 # average overall miss latency +system.cpu.l2cache.ReadReq_misses 33163 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 58722 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 91885 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 91885 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1130840000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2017374000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 3148214000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 3148214000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 214522 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 410037 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 249546 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 464068 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 464068 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.154590 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.235315 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.197999 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.197999 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34099.448180 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34354.654133 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34262.545573 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34262.545573 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 202000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 122 # number of cycles access was blocked @@ -438,27 +438,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1655.737705 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 58507 # number of writebacks +system.cpu.l2cache.writebacks 58503 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 33178 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 58719 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 91897 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 91897 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 33163 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 58722 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 91885 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 91885 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1028691000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828336500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2857027500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2857027500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1028236500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828595500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2856832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2856832000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154673 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235275 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.198020 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.198020 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.214299 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.051040 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154590 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.197999 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.197999 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.533275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31139.870917 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31091.385972 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31091.385972 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 96389038f..b4c2d7806 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -3,13 +3,14 @@ Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 15:40:58 -gem5 started Aug 20 2011 15:42:13 -gem5 executing on zizzer +gem5 compiled Nov 17 2011 18:36:33 +gem5 started Nov 17 2011 18:37:39 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing +tests warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5147601271500 because m5_exit instruction encountered +Exiting @ tick 5145286546500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index e13689c4a..4f78f7da1 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,97 +1,97 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.147601 # Number of seconds simulated -sim_ticks 5147601271500 # Number of ticks simulated +sim_seconds 5.145287 # Number of seconds simulated +sim_ticks 5145286546500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290249 # Simulator instruction rate (inst/s) -host_tick_rate 1780077210 # Simulator tick rate (ticks/s) -host_mem_usage 361700 # Number of bytes of host memory used -host_seconds 2891.79 # Real time elapsed on the host -sim_insts 839336586 # Number of instructions simulated -system.l2c.replacements 169225 # number of replacements -system.l2c.tagsinuse 38391.632338 # Cycle average of tags in use -system.l2c.total_refs 3787611 # Total number of references to valid blocks. -system.l2c.sampled_refs 204461 # Sample count of references to valid blocks. -system.l2c.avg_refs 18.524858 # Average number of references to valid blocks. +host_inst_rate 252508 # Simulator instruction rate (inst/s) +host_tick_rate 1546872935 # Simulator tick rate (ticks/s) +host_mem_usage 390244 # Number of bytes of host memory used +host_seconds 3326.25 # Real time elapsed on the host +sim_insts 839904894 # Number of instructions simulated +system.l2c.replacements 171120 # number of replacements +system.l2c.tagsinuse 38411.926866 # Cycle average of tags in use +system.l2c.total_refs 3818646 # Total number of references to valid blocks. +system.l2c.sampled_refs 206013 # Sample count of references to valid blocks. +system.l2c.avg_refs 18.535947 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 12004.760540 # Average occupied blocks per context -system.l2c.occ_blocks::1 26386.871797 # Average occupied blocks per context -system.l2c.occ_percent::0 0.183178 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.402632 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2307522 # number of ReadReq hits -system.l2c.ReadReq_hits::1 137003 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2444525 # number of ReadReq hits -system.l2c.Writeback_hits::0 1590016 # number of Writeback hits -system.l2c.Writeback_hits::total 1590016 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 326 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 326 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 147596 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 147596 # number of ReadExReq hits -system.l2c.demand_hits::0 2455118 # number of demand (read+write) hits -system.l2c.demand_hits::1 137003 # number of demand (read+write) hits -system.l2c.demand_hits::total 2592121 # number of demand (read+write) hits -system.l2c.overall_hits::0 2455118 # number of overall hits -system.l2c.overall_hits::1 137003 # number of overall hits -system.l2c.overall_hits::total 2592121 # number of overall hits -system.l2c.ReadReq_misses::0 66466 # number of ReadReq misses -system.l2c.ReadReq_misses::1 86 # number of ReadReq misses -system.l2c.ReadReq_misses::total 66552 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3784 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3784 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 142440 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142440 # number of ReadExReq misses -system.l2c.demand_misses::0 208906 # number of demand (read+write) misses -system.l2c.demand_misses::1 86 # number of demand (read+write) misses -system.l2c.demand_misses::total 208992 # number of demand (read+write) misses -system.l2c.overall_misses::0 208906 # number of overall misses -system.l2c.overall_misses::1 86 # number of overall misses -system.l2c.overall_misses::total 208992 # number of overall misses -system.l2c.ReadReq_miss_latency 3490673000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 33240000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7454154500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 10944827500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 10944827500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2373988 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 137089 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2511077 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1590016 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1590016 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4110 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4110 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 290036 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 290036 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2664024 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 137089 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2801113 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2664024 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 137089 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2801113 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027998 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000627 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028625 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.920681 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.491111 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.078417 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000627 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.079045 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.078417 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000627 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.079045 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52518.174706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 40589220.930233 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 40641739.104938 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8784.355180 # average UpgradeReq miss latency +system.l2c.occ_blocks::0 11983.527500 # Average occupied blocks per context +system.l2c.occ_blocks::1 26428.399366 # Average occupied blocks per context +system.l2c.occ_percent::0 0.182854 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.403265 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2330328 # number of ReadReq hits +system.l2c.ReadReq_hits::1 145914 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2476242 # number of ReadReq hits +system.l2c.Writeback_hits::0 1599020 # number of Writeback hits +system.l2c.Writeback_hits::total 1599020 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 343 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 343 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 150210 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 150210 # number of ReadExReq hits +system.l2c.demand_hits::0 2480538 # number of demand (read+write) hits +system.l2c.demand_hits::1 145914 # number of demand (read+write) hits +system.l2c.demand_hits::total 2626452 # number of demand (read+write) hits +system.l2c.overall_hits::0 2480538 # number of overall hits +system.l2c.overall_hits::1 145914 # number of overall hits +system.l2c.overall_hits::total 2626452 # number of overall hits +system.l2c.ReadReq_misses::0 68080 # number of ReadReq misses +system.l2c.ReadReq_misses::1 84 # number of ReadReq misses +system.l2c.ReadReq_misses::total 68164 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3905 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3905 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 142426 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142426 # number of ReadExReq misses +system.l2c.demand_misses::0 210506 # number of demand (read+write) misses +system.l2c.demand_misses::1 84 # number of demand (read+write) misses +system.l2c.demand_misses::total 210590 # number of demand (read+write) misses +system.l2c.overall_misses::0 210506 # number of overall misses +system.l2c.overall_misses::1 84 # number of overall misses +system.l2c.overall_misses::total 210590 # number of overall misses +system.l2c.ReadReq_miss_latency 3574844000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 37228000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7453066500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 11027910500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 11027910500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2398408 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 145998 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2544406 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1599020 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1599020 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 4248 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4248 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 292636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 292636 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2691044 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 145998 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2837042 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2691044 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 145998 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2837042 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.028385 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000575 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.028961 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.919256 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.486700 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.078225 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000575 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.078800 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.078225 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000575 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.078800 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52509.459459 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 42557666.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 42610176.126126 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 9533.418694 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52331.890621 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52329.395616 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52391.159182 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 127265436.046512 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 127317827.205693 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52391.159182 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 127265436.046512 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 127317827.205693 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52387.630281 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 131284648.809524 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 131337036.439805 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52387.630281 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 131284648.809524 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 131337036.439805 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -100,88 +100,88 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 142484 # number of writebacks +system.l2c.writebacks 142550 # number of writebacks system.l2c.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 2 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 66550 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3784 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 142440 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 208990 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 208990 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 68162 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3905 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 142426 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 210588 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 210588 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2679045000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 151709500 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5718096500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 8397141500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 8397141500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 61568859000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1235122000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 62803981000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028033 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.485451 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.513484 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.920681 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 2743592500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 156565000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5717024500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 8460617000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 8460617000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 61532546500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1222452000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 62754998500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.028420 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.466869 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.495289 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.919256 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.491111 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.486700 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.078449 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.524484 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.602933 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.078449 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.524484 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.602933 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40256.123216 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40092.362579 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40143.895675 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40179.632997 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40179.632997 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.078255 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.442403 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.520658 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.078255 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.442403 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.520658 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40251.056307 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.469910 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40140.314971 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40176.159135 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47520 # number of replacements -system.iocache.tagsinuse 0.153992 # Cycle average of tags in use +system.iocache.replacements 47572 # number of replacements +system.iocache.tagsinuse 0.146650 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47536 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994510016000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.153992 # Average occupied blocks per context -system.iocache.occ_percent::1 0.009624 # Average percentage of cache occupancy +system.iocache.warmup_cycle 4994510051000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.146650 # Average occupied blocks per context +system.iocache.occ_percent::1 0.009166 # Average percentage of cache occupancy system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 870 # number of ReadReq misses -system.iocache.ReadReq_misses::total 870 # number of ReadReq misses -system.iocache.WriteReq_misses::1 46704 # number of WriteReq misses -system.iocache.WriteReq_misses::total 46704 # number of WriteReq misses +system.iocache.ReadReq_misses::1 907 # number of ReadReq misses +system.iocache.ReadReq_misses::total 907 # number of ReadReq misses +system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses +system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47574 # number of demand (read+write) misses -system.iocache.demand_misses::total 47574 # number of demand (read+write) misses +system.iocache.demand_misses::1 47627 # number of demand (read+write) misses +system.iocache.demand_misses::total 47627 # number of demand (read+write) misses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47574 # number of overall misses -system.iocache.overall_misses::total 47574 # number of overall misses -system.iocache.ReadReq_miss_latency 108834936 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6370051162 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6478886098 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6478886098 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 870 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 870 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 46704 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 46704 # number of WriteReq accesses(hits+misses) +system.iocache.overall_misses::1 47627 # number of overall misses +system.iocache.overall_misses::total 47627 # number of overall misses +system.iocache.ReadReq_miss_latency 113785932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6369912160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6483698092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6483698092 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47574 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47574 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47627 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47574 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47574 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47627 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses @@ -191,37 +191,37 @@ system.iocache.overall_miss_rate::0 no_value # mi system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 125097.627586 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 125453.067255 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136391.982742 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136342.297945 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136185.439484 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136134.925399 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136185.439484 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136134.925399 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 68653524 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 68669502 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11268 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11260 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6092.787007 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6098.534813 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46652 # number of writebacks +system.iocache.writebacks 46667 # number of writebacks system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 870 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 46704 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47574 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47574 # number of overall MSHR misses +system.iocache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses 47627 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 47627 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 63576976 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3941129874 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4004706850 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4004706850 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 66598982 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3940155856 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4006754838 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4006754838 # number of overall MSHR miss cycles system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses @@ -235,434 +235,434 @@ system.iocache.demand_mshr_miss_rate::total inf # system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 73076.983908 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84385.274794 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84178.476689 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84178.476689 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency 73427.764057 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84335.527740 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84127.802255 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2984960 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 811 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 447857914 # number of cpu cycles simulated +system.cpu.numCycles 449021643 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90944358 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90944358 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1226473 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 89599267 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 83628993 # Number of BTB hits +system.cpu.BPredUnit.lookups 91138491 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 91138491 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1248082 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 89857544 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 83686998 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27835932 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449937499 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90944358 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83628993 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170885862 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5925894 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 181270 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 82341776 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 36741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 58576 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9686350 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 533599 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 3672 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 285953148 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.092624 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.403694 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28288670 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 450771327 # Number of instructions fetch has processed +system.cpu.fetch.Branches 91138491 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 83686998 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 171087914 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6045536 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 191873 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 82674920 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 36392 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 54951 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9822160 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 542562 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4016 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 287044907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.085924 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.403637 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 115559786 40.41% 40.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1486948 0.52% 40.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72839284 25.47% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1399836 0.49% 66.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1849088 0.65% 67.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3956894 1.38% 68.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1519974 0.53% 69.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2050817 0.72% 70.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85290521 29.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 116472661 40.58% 40.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1490084 0.52% 41.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72800190 25.36% 66.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1427390 0.50% 66.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1806479 0.63% 67.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3992507 1.39% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1571582 0.55% 69.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2063795 0.72% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85420219 29.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 285953148 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.203065 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.004643 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32848686 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 78733964 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165420335 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4337474 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4612689 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 880519790 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 603 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4612689 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37008244 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52433742 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9987311 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 165318823 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 16592339 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 876077378 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14259 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 11608934 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2117422 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 878323292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1719903468 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1719903124 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 842717831 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35605454 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 480050 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 481410 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42986896 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19404127 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10589665 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1106439 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 977378 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 869234759 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 887302 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 865293083 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 172874 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 29947401 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 43606928 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 139213 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 285953148 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.025996 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.373161 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 287044907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.202971 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.003897 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 33370892 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 79040686 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165533455 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4389968 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4709906 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 881886507 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 578 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4709906 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37547254 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 52554502 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10077381 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 165462513 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 16693351 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 877383155 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14371 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 11668719 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2142745 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 879650717 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1723132927 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1723132383 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 544 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 843287047 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36363663 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 486686 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 487762 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43318784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19666821 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10717044 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1121000 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1013044 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 870450598 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 900193 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 866206507 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178001 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 30597956 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 44655599 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 144106 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 287044907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.017669 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.373774 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 81963860 28.66% 28.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22232412 7.77% 36.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 13907684 4.86% 41.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 9593533 3.35% 44.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 79512028 27.81% 72.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4973941 1.74% 74.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72992433 25.53% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 625767 0.22% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 151490 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 82633676 28.79% 28.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22379993 7.80% 36.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 14042555 4.89% 41.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 9676323 3.37% 44.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 79535811 27.71% 72.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5032653 1.75% 74.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72954170 25.42% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 636902 0.22% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 152824 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 285953148 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 287044907 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 192405 8.66% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1837790 82.69% 91.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 192432 8.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 195893 8.77% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1841396 82.43% 91.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 196729 8.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 296605 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 830140846 95.94% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25417132 2.94% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9438500 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 302784 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 830728417 95.90% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 95.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25630184 2.96% 98.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9545122 1.10% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 865293083 # Type of FU issued -system.cpu.iq.rate 1.932071 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2222627 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.002569 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2019084567 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 900079448 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 854502226 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 147 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 154 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 42 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 867219037 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 68 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1353310 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 866206507 # Type of FU issued +system.cpu.iq.rate 1.929097 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2234018 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.002579 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2022023513 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 901959019 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 855369267 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 203 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 868137651 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1362479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4224491 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17341 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10951 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2251290 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4321864 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17926 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11344 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2286443 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7817207 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 160453 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7817280 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 160300 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4612689 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33472492 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6015693 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 870122061 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 301987 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19404127 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10589719 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 886500 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5552993 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 26264 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10951 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 883301 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 519788 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1403089 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 863190269 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24933733 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2102813 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4709906 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 33528904 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6021560 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 871350791 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 302780 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19666821 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10717077 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 894230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5567968 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 26441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11344 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 900317 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 526461 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1426778 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 864071451 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25139822 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2135055 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 34134363 # number of memory reference insts executed -system.cpu.iew.exec_branches 86606805 # Number of branches executed -system.cpu.iew.exec_stores 9200630 # Number of stores executed -system.cpu.iew.exec_rate 1.927375 # Inst execution rate -system.cpu.iew.wb_sent 862563162 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 854502268 # cumulative count of insts written-back -system.cpu.iew.wb_producers 670839861 # num instructions producing a value -system.cpu.iew.wb_consumers 1171063083 # num instructions consuming a value +system.cpu.iew.exec_refs 34444060 # number of memory reference insts executed +system.cpu.iew.exec_branches 86704764 # Number of branches executed +system.cpu.iew.exec_stores 9304238 # Number of stores executed +system.cpu.iew.exec_rate 1.924343 # Inst execution rate +system.cpu.iew.wb_sent 863434483 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 855369319 # cumulative count of insts written-back +system.cpu.iew.wb_producers 671433691 # num instructions producing a value +system.cpu.iew.wb_consumers 1171953644 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907976 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572847 # average fanout of values written-back +system.cpu.iew.wb_rate 1.904962 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572918 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 839336586 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 30675414 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 748087 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1233611 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 281355498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.983189 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.864496 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 839904894 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 31338704 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 756085 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1254700 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 282350978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.974684 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863709 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 102129547 36.30% 36.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 12394321 4.41% 40.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4610399 1.64% 42.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76952670 27.35% 69.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4007315 1.42% 71.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1836126 0.65% 71.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1044804 0.37% 72.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71657785 25.47% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6722531 2.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 102836465 36.42% 36.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 12523164 4.44% 40.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4697520 1.66% 42.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76975529 27.26% 69.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4042949 1.43% 71.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1857352 0.66% 71.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1067382 0.38% 72.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71607681 25.36% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6742936 2.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 281355498 # Number of insts commited each cycle -system.cpu.commit.count 839336586 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 282350978 # Number of insts commited each cycle +system.cpu.commit.count 839904894 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23518062 # Number of memory references committed -system.cpu.commit.loads 15179633 # Number of loads committed -system.cpu.commit.membars 801 # Number of memory barriers committed -system.cpu.commit.branches 85448275 # Number of branches committed +system.cpu.commit.refs 23775588 # Number of memory references committed +system.cpu.commit.loads 15344954 # Number of loads committed +system.cpu.commit.membars 3541 # Number of memory barriers committed +system.cpu.commit.branches 85526796 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 767896653 # Number of committed integer instructions. +system.cpu.commit.int_insts 768518485 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6722531 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6742936 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1144564074 # The number of ROB reads -system.cpu.rob.rob_writes 1744648535 # The number of ROB writes -system.cpu.timesIdled 3067742 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 161904766 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 839336586 # Number of Instructions Simulated -system.cpu.committedInsts_total 839336586 # Number of Instructions Simulated -system.cpu.cpi 0.533586 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.533586 # CPI: Total CPI of All Threads -system.cpu.ipc 1.874114 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.874114 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1405583914 # number of integer regfile reads -system.cpu.int_regfile_writes 856547410 # number of integer regfile writes -system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.misc_regfile_reads 281786405 # number of misc regfile reads -system.cpu.misc_regfile_writes 403681 # number of misc regfile writes -system.cpu.icache.replacements 1011974 # number of replacements -system.cpu.icache.tagsinuse 510.480374 # Cycle average of tags in use -system.cpu.icache.total_refs 8606970 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1012486 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.500829 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 54553287000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.480374 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997032 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 8606970 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8606970 # number of ReadReq hits -system.cpu.icache.demand_hits::0 8606970 # number of demand (read+write) hits +system.cpu.rob.rob_reads 1146769000 # The number of ROB reads +system.cpu.rob.rob_writes 1747209492 # The number of ROB writes +system.cpu.timesIdled 3079387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 161976736 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 839904894 # Number of Instructions Simulated +system.cpu.committedInsts_total 839904894 # Number of Instructions Simulated +system.cpu.cpi 0.534610 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.534610 # CPI: Total CPI of All Threads +system.cpu.ipc 1.870522 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.870522 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1407118516 # number of integer regfile reads +system.cpu.int_regfile_writes 857404874 # number of integer regfile writes +system.cpu.fp_regfile_reads 52 # number of floating regfile reads +system.cpu.misc_regfile_reads 282285829 # number of misc regfile reads +system.cpu.misc_regfile_writes 410057 # number of misc regfile writes +system.cpu.icache.replacements 1028866 # number of replacements +system.cpu.icache.tagsinuse 510.467349 # Cycle average of tags in use +system.cpu.icache.total_refs 8724446 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1029378 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8.475454 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 54553290000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.467349 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997007 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 8724446 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8724446 # number of ReadReq hits +system.cpu.icache.demand_hits::0 8724446 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8606970 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 8606970 # number of overall hits +system.cpu.icache.demand_hits::total 8724446 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 8724446 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 8606970 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1079377 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079377 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1079377 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 8724446 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1097711 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1097711 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1097711 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079377 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1079377 # number of overall misses +system.cpu.icache.demand_misses::total 1097711 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1097711 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1079377 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16165039489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16165039489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16165039489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 9686347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9686347 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 9686347 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1097711 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16447038991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16447038991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16447038991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 9822157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9822157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 9822157 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9686347 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 9686347 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 9822157 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 9822157 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9686347 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.111433 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.111433 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 9822157 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.111759 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.111759 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.111433 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.111759 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14976.268245 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14983.031956 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14976.268245 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14983.031956 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14976.268245 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14983.031956 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2584490 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2545992 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 245 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 258 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 10548.938776 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 9868.186047 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 1557 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 64335 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 64335 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 64335 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1015042 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1015042 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1015042 # number of overall MSHR misses +system.cpu.icache.writebacks 1562 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 65787 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 65787 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 65787 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1031924 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1031924 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1031924 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12263411490 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12263411490 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12263411490 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 12476028992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12476028992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12476028992 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.104791 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.105061 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.104791 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.105061 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.104791 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.105061 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 12081.678876 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 12081.678876 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 12081.678876 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12090.065734 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12090.065734 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 12307 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.013157 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 27450 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 12318 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.228446 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5128990426000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 6.013157 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.375822 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 27562 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 27562 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 14158 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.014381 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 26217 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 14168 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 1.850438 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5108050090000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 6.014381 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.375899 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::1 26573 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 26573 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 27565 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 27565 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 26576 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 26576 # number of demand (read+write) hits system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 27565 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 27565 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 13090 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 13090 # number of ReadReq misses +system.cpu.itb_walker_cache.overall_hits::1 26576 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 26576 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 15025 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 15025 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 13090 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 13090 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 15025 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 15025 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 13090 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 13090 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 170458000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 170458000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 170458000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 40652 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 40652 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.overall_misses::1 15025 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 15025 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 189764500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 189764500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 189764500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 41598 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41598 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::1 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 40655 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 40655 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 41601 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41601 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 40655 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 40655 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.322001 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.overall_accesses::1 41601 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41601 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.361195 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.321978 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.361169 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.321978 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.361169 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 13022.001528 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12629.916805 # average ReadReq miss latency system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 13022.001528 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12629.916805 # average overall miss latency system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 13022.001528 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12629.916805 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -672,83 +672,83 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 2568 # number of writebacks +system.cpu.itb_walker_cache.writebacks 2705 # number of writebacks system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 13090 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 13090 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 13090 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses 15025 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 15025 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 15025 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 130828500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 130828500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 130828500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 144320000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 144320000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency 144320000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.322001 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.361195 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.321978 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.361169 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.321978 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.361169 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9994.537815 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9994.537815 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9994.537815 # average overall mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 9605.324459 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 9605.324459 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 134574 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 13.858456 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 145276 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 134589 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.079405 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5098934716000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 13.858456 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.866154 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 145328 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 145328 # number of ReadReq hits +system.cpu.dtb_walker_cache.replacements 144708 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.855241 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 146935 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 144723 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.015284 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5098934458000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 13.855241 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.865953 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 147187 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 147187 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 145328 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 145328 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 147187 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 147187 # number of demand (read+write) hits system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 145328 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 145328 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 135405 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 135405 # number of ReadReq misses +system.cpu.dtb_walker_cache.overall_hits::1 147187 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 147187 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 145638 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 145638 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 135405 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 135405 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 145638 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 145638 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 135405 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 135405 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 1884318500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 1884318500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 1884318500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 280733 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 280733 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.overall_misses::1 145638 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 145638 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 2011660500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 2011660500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 2011660500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 292825 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 292825 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 280733 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 280733 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 292825 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 292825 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 280733 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 280733 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.482327 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.overall_accesses::1 292825 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 292825 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.497355 # miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.482327 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.497355 # miss rate for demand accesses system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.482327 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.497355 # miss rate for overall accesses system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13916.166316 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 13812.744613 # average ReadReq miss latency system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13916.166316 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 13812.744613 # average overall miss latency system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13916.166316 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 13812.744613 # average overall miss latency system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -758,136 +758,136 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 43317 # number of writebacks +system.cpu.dtb_walker_cache.writebacks 46772 # number of writebacks system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 135405 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 135405 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 135405 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 145638 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 145638 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 145638 # number of overall MSHR misses system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1474266000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1474266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1474266000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 1570780000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 1570780000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 1570780000 # number of overall MSHR miss cycles system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.482327 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.497355 # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.482327 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.497355 # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.482327 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.497355 # mshr miss rate for overall accesses system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10887.825413 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10887.825413 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10887.825413 # average overall mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 10785.509276 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 10785.509276 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1651577 # number of replacements -system.cpu.dcache.tagsinuse 511.998478 # Cycle average of tags in use -system.cpu.dcache.total_refs 17702284 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1652089 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.715091 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1661747 # number of replacements +system.cpu.dcache.tagsinuse 511.998367 # Cycle average of tags in use +system.cpu.dcache.total_refs 17960054 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1662259 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.804606 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 13135000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.998478 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 511.998367 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999997 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11207304 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11207304 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 6473053 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6473053 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 17680357 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 11390626 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11390626 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 6547450 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6547450 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 17938076 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 17680357 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 17680357 # number of overall hits +system.cpu.dcache.demand_hits::total 17938076 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 17938076 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 17680357 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 2476228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2476228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1855910 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1855910 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 4332138 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 17938076 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 2490346 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2490346 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 1873884 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1873884 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 4364230 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4332138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 4332138 # number of overall misses +system.cpu.dcache.demand_misses::total 4364230 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 4364230 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 4332138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 37330141500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 63200421145 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 100530562645 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 100530562645 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13683532 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13683532 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8328963 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8328963 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 22012495 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 4364230 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 37598789500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 63471421475 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 101070210975 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 101070210975 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13880972 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13880972 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8421334 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8421334 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 22302306 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22012495 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 22012495 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 22302306 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 22302306 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22012495 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.180964 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.222826 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.196804 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 22302306 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.179407 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.222516 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.195685 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.196804 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.195685 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15075.405617 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15097.817532 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 34053.602354 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33871.585154 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 23205.761831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 23158.772790 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 23205.761831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 23158.772790 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1081837152 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5932000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 72874 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 266 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14845.310426 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22300.751880 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1083244649 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6672500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73213 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 391 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14795.796498 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 17065.217391 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1542574 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1113618 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1561886 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 2675504 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 2675504 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1362610 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 294024 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1656634 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1656634 # number of overall MSHR misses +system.cpu.dcache.writebacks 1547981 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1120147 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 1577106 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 2697253 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 2697253 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1370199 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 296778 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1666977 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1666977 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 18053047500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 9720000152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 27773047652 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 27773047652 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86987590000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1400743000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 88388333000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.099580 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 18186929000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 9757421649 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 27944350649 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 27944350649 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 86947016500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1386048000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 88333064500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098711 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035301 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035241 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.075259 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.074745 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.075259 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.074745 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13248.873485 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33058.526352 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 16764.745654 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 16764.745654 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13273.202652 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32877.846906 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 16763.489028 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 5eb8fc418..85136ebe7 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -39,7 +39,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812515
+result 7812511
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index d1aeffbca..f9ce22b4b 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,10 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:24:14 -gem5 started Aug 20 2011 13:24:28 -gem5 executing on zizzer +gem5 compiled Nov 16 2011 11:08:03 +gem5 started Nov 17 2011 13:09:16 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing +tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 70374234500 because target called exit() +Exiting @ tick 70312944500 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index f17fe7434..011648483 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.070374 # Number of seconds simulated -sim_ticks 70374234500 # Number of ticks simulated +sim_seconds 0.070313 # Number of seconds simulated +sim_ticks 70312944500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169063 # Simulator instruction rate (inst/s) -host_tick_rate 42767879 # Simulator tick rate (ticks/s) -host_mem_usage 346452 # Number of bytes of host memory used -host_seconds 1645.49 # Real time elapsed on the host +host_inst_rate 125815 # Simulator instruction rate (inst/s) +host_tick_rate 31799589 # Simulator tick rate (ticks/s) +host_mem_usage 378944 # Number of bytes of host memory used +host_seconds 2211.13 # Real time elapsed on the host sim_insts 278192519 # Number of instructions simulated system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 140748470 # number of cpu cycles simulated +system.cpu.numCycles 140625890 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 37906853 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 37906853 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1330176 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 33468761 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 32955372 # Number of BTB hits +system.cpu.BPredUnit.lookups 37833804 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 37833804 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1322933 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 33591925 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 33081589 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29094074 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 203757407 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37906853 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32955372 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 63225813 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 10352620 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 38317432 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 97 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28270666 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 203655 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139622279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.293353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29087381 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 203627812 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37833804 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33081589 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 63297987 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 10276298 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 38195582 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 95 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28266291 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 204981 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139497150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.574262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.291399 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78878326 56.49% 56.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3468234 2.48% 58.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2811542 2.01% 60.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4524513 3.24% 64.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6755323 4.84% 69.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5317016 3.81% 72.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7687744 5.51% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4301095 3.08% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25878486 18.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78673130 56.40% 56.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3606277 2.59% 58.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2810090 2.01% 61.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4532102 3.25% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6824412 4.89% 69.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5279008 3.78% 72.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7637539 5.48% 78.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4315201 3.09% 81.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25819391 18.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139622279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.269323 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.447670 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 41959628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 28656621 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 52572729 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7448460 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8984841 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 355072137 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8984841 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 48879402 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4457870 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6893 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 52910993 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24382280 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350563031 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 104227 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20384891 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 314779048 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 862154595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 862151489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3106 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139497150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.269039 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.448011 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 41917744 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 28560060 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 52643719 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7459543 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8916084 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 354657218 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8916084 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 48823983 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4469241 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 53004642 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24276312 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350176569 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 101342 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20289844 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 314446851 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 861231533 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 861227904 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3629 # Number of floating rename lookups system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 66434856 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 66102659 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 479 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 56483579 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112824537 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37669092 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 48262856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8162457 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343955075 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 466 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 316373550 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 98329 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65563048 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 93813941 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139622279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.265925 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.753143 # Number of insts issued each cycle +system.cpu.rename.skidInsts 56104077 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112666461 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37647255 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 48253520 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8188094 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343455788 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 316242386 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 89834 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65098177 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 92870721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1849 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139497150 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.267017 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.750973 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 31939796 22.88% 22.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 18447556 13.21% 36.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25584563 18.32% 54.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 29944678 21.45% 75.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18447649 13.21% 89.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 10291416 7.37% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3138355 2.25% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1781100 1.28% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 47166 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 31795649 22.79% 22.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 18418675 13.20% 36.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25717845 18.44% 54.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 29872112 21.41% 75.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18507796 13.27% 89.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 10200782 7.31% 96.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3199934 2.29% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1737869 1.25% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 46488 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139622279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139497150 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 26426 1.39% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1802884 94.84% 96.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71697 3.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 25785 1.36% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1795857 94.47% 95.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79349 4.17% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 180370396 57.01% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 163 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101485830 32.08% 89.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34500450 10.90% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 180262574 57.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 195 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101451147 32.08% 89.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34511759 10.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 316373550 # Type of FU issued -system.cpu.iq.rate 2.247794 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1901007 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006009 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 774367858 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 409550255 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 312670753 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 857 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1937 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 344 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 318257421 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 425 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 45906074 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 316242386 # Type of FU issued +system.cpu.iq.rate 2.248821 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1900991 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006011 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 773971833 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 408587092 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 312537049 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 914 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2332 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 382 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 318126211 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 455 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 45906656 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 22045149 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 125133 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34222 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6229341 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21887073 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 122159 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33758 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6207504 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2799 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15405 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2763 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 15488 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8984841 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 901233 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 88686 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343955541 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 25713 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112824537 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37669092 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1563 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 48845 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34222 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1237215 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 226162 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1463377 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 314277739 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100905928 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2095811 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8916084 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 901068 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88602 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343458083 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 26305 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112666461 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37647255 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1597 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 48733 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33758 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1219939 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 230098 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1450037 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 314144155 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100864248 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2098231 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134999174 # number of memory reference insts executed -system.cpu.iew.exec_branches 31825957 # Number of branches executed -system.cpu.iew.exec_stores 34093246 # Number of stores executed -system.cpu.iew.exec_rate 2.232903 # Inst execution rate -system.cpu.iew.wb_sent 313326251 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 312671097 # cumulative count of insts written-back -system.cpu.iew.wb_producers 232527981 # num instructions producing a value -system.cpu.iew.wb_consumers 318649991 # num instructions consuming a value +system.cpu.iew.exec_refs 134973322 # number of memory reference insts executed +system.cpu.iew.exec_branches 31810521 # Number of branches executed +system.cpu.iew.exec_stores 34109074 # Number of stores executed +system.cpu.iew.exec_rate 2.233900 # Inst execution rate +system.cpu.iew.wb_sent 313190495 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 312537431 # cumulative count of insts written-back +system.cpu.iew.wb_producers 232392592 # num instructions producing a value +system.cpu.iew.wb_consumers 318468890 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.221488 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.729729 # average fanout of values written-back +system.cpu.iew.wb_rate 2.222474 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.729718 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 65767670 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 65270328 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1330190 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130637438 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.129501 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.662910 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1322946 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130581066 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.130420 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.663472 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 50443323 38.61% 38.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 24364180 18.65% 57.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 16505841 12.63% 69.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12375620 9.47% 79.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3710115 2.84% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3458000 2.65% 84.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2751645 2.11% 86.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1180245 0.90% 87.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 15848469 12.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 50414718 38.61% 38.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 24339651 18.64% 57.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 16499074 12.64% 69.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12376450 9.48% 79.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3696747 2.83% 82.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3466084 2.65% 84.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2761727 2.11% 86.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1175320 0.90% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 15851295 12.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130637438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 130581066 # Number of insts commited each cycle system.cpu.commit.count 278192519 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 122219139 # Number of memory references committed @@ -255,49 +255,49 @@ system.cpu.commit.branches 29309710 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 15848469 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 15851295 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 458749158 # The number of ROB reads -system.cpu.rob.rob_writes 696922141 # The number of ROB writes -system.cpu.timesIdled 33627 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1126191 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 458192618 # The number of ROB reads +system.cpu.rob.rob_writes 695856607 # The number of ROB writes +system.cpu.timesIdled 33615 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1128740 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 0.505939 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.505939 # CPI: Total CPI of All Threads -system.cpu.ipc 1.976523 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.976523 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 555004477 # number of integer regfile reads -system.cpu.int_regfile_writes 279973081 # number of integer regfile writes -system.cpu.fp_regfile_reads 378 # number of floating regfile reads -system.cpu.fp_regfile_writes 284 # number of floating regfile writes -system.cpu.misc_regfile_reads 201255053 # number of misc regfile reads +system.cpu.cpi 0.505498 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.505498 # CPI: Total CPI of All Threads +system.cpu.ipc 1.978245 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.978245 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 554794614 # number of integer regfile reads +system.cpu.int_regfile_writes 279836675 # number of integer regfile writes +system.cpu.fp_regfile_reads 437 # number of floating regfile reads +system.cpu.fp_regfile_writes 335 # number of floating regfile writes +system.cpu.misc_regfile_reads 201195947 # number of misc regfile reads system.cpu.icache.replacements 68 # number of replacements -system.cpu.icache.tagsinuse 824.627975 # Cycle average of tags in use -system.cpu.icache.total_refs 28269362 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1028 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 27499.379377 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 824.679926 # Cycle average of tags in use +system.cpu.icache.total_refs 28264985 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1027 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 27521.893866 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 824.627975 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.402650 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28269362 # number of ReadReq hits -system.cpu.icache.demand_hits 28269362 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28269362 # number of overall hits -system.cpu.icache.ReadReq_misses 1304 # number of ReadReq misses -system.cpu.icache.demand_misses 1304 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1304 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 47096500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 47096500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 47096500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28270666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28270666 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28270666 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 824.679926 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.402676 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28264985 # number of ReadReq hits +system.cpu.icache.demand_hits 28264985 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28264985 # number of overall hits +system.cpu.icache.ReadReq_misses 1306 # number of ReadReq misses +system.cpu.icache.demand_misses 1306 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1306 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 47073500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 47073500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 47073500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28266291 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28266291 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28266291 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36116.947853 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36116.947853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36116.947853 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 36044.027565 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36044.027565 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36044.027565 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 1029 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 1029 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 1029 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 278 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 278 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 278 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1028 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1028 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1028 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 36215000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 36215000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 36215000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 36154500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 36154500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 36154500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35194.363460 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35169.747082 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35169.747082 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35169.747082 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2073072 # number of replacements -system.cpu.dcache.tagsinuse 4076.002534 # Cycle average of tags in use -system.cpu.dcache.total_refs 83850634 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2077168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40.367767 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 23897616000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.002534 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995118 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 52653882 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 31196743 # number of WriteReq hits -system.cpu.dcache.demand_hits 83850625 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 83850625 # number of overall hits -system.cpu.dcache.ReadReq_misses 2263157 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 243008 # number of WriteReq misses -system.cpu.dcache.demand_misses 2506165 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 2506165 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 14623728000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4401886592 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19025614592 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19025614592 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 54917039 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2073066 # number of replacements +system.cpu.dcache.tagsinuse 4076.005888 # Cycle average of tags in use +system.cpu.dcache.total_refs 83808707 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2077162 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 40.347699 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 23845092000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4076.005888 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.995119 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 52611944 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 31196754 # number of WriteReq hits +system.cpu.dcache.demand_hits 83808698 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 83808698 # number of overall hits +system.cpu.dcache.ReadReq_misses 2262875 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 242997 # number of WriteReq misses +system.cpu.dcache.demand_misses 2505872 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 2505872 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 14629803500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4394648436 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19024451936 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19024451936 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 54874819 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 86356790 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 86356790 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.041210 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 86314570 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 86314570 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.041237 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.007729 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.029021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.029021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 6461.649810 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 18114.163287 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 7591.525136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 7591.525136 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 296000 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate 0.029032 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.029032 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 6465.139922 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 18085.196262 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 7591.948805 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 7591.948805 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 289000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 93 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3182.795699 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3141.304348 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1447092 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 291450 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 137543 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 428993 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 428993 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1971707 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 105465 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2077172 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2077172 # number of overall MSHR misses +system.cpu.dcache.writebacks 1447147 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 291175 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 137531 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 428706 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 428706 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1971700 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 105466 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2077166 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2077166 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5599733000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1876757592 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7476490592 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7476490592 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5609142000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1870309936 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7479451936 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7479451936 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.035903 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.035931 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.024053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.024053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2840.043171 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17795.075068 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.024065 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.024065 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2844.825278 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17733.771414 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3600.796439 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3600.796439 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 49070 # number of replacements -system.cpu.l2cache.tagsinuse 18849.812777 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3318008 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 77081 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 43.045731 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 49057 # number of replacements +system.cpu.l2cache.tagsinuse 18859.305089 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3318010 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 77063 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 43.055811 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 6745.826593 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 12103.986183 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.205866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.369384 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1938133 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 1447092 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 63539 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2001672 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2001672 # number of overall hits -system.cpu.l2cache.ReadReq_misses 34492 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 6747.919367 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 12111.385721 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.205930 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.369610 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1938157 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 1447147 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 63526 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 2001683 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2001683 # number of overall hits +system.cpu.l2cache.ReadReq_misses 34474 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses 42035 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 76527 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 76527 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1179607000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1438839000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 2618446000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 2618446000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1972625 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 1447092 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_misses 76509 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 76509 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1179443000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1438838000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 2618281000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 2618281000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1972631 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 1447147 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 105574 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2078199 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2078199 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.017485 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses 105561 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2078192 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2078192 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.017476 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.398157 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.036824 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.036824 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34199.437551 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.546806 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34215.976061 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34215.976061 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 39000 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 0.398206 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.036815 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.036815 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34212.536984 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.523017 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34221.869323 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34221.869323 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2785.714286 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2678.571429 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 29193 # number of writebacks +system.cpu.l2cache.writebacks 29185 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 34492 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 34474 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 42035 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 76527 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 76527 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 76509 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 76509 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1069993000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1069429500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307215500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 2377208500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 2377208500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307209000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2376638500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2376638500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017485 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398157 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.036824 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.036824 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.483242 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398206 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.036815 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.036815 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.334919 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.263352 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.108719 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.515403 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.515403 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index bc2d966a5..7acfed5bd 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -3,10 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:24:14 -gem5 started Aug 20 2011 13:24:28 -gem5 executing on zizzer +gem5 compiled Nov 16 2011 11:08:03 +gem5 started Nov 17 2011 13:09:16 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing +tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -81,4 +82,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 493847859500 because target called exit() +Exiting @ tick 494093841000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index d93a5470f..548cdcdb0 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.493848 # Number of seconds simulated -sim_ticks 493847859500 # Number of ticks simulated +sim_seconds 0.494094 # Number of seconds simulated +sim_ticks 494093841000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141014 # Simulator instruction rate (inst/s) -host_tick_rate 45545926 # Simulator tick rate (ticks/s) -host_mem_usage 250808 # Number of bytes of host memory used -host_seconds 10842.85 # Real time elapsed on the host +host_inst_rate 111156 # Simulator instruction rate (inst/s) +host_tick_rate 35920075 # Simulator tick rate (ticks/s) +host_mem_usage 281020 # Number of bytes of host memory used +host_seconds 13755.37 # Real time elapsed on the host sim_insts 1528988756 # Number of instructions simulated system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 987695720 # number of cpu cycles simulated +system.cpu.numCycles 988187683 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 245701836 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245701836 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16595687 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 236380847 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 218346080 # Number of BTB hits +system.cpu.BPredUnit.lookups 245753731 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245753731 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16579058 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 236460078 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218454939 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 205619767 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1343825400 # Number of instructions fetch has processed -system.cpu.fetch.Branches 245701836 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 218346080 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 436746169 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 120030037 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 218211728 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 32810 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 394519 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 194794908 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4074174 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 964173518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.600326 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.317708 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 205538766 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1343537923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 245753731 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 218454939 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436709904 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 120016352 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 218837683 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 345399 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 194719765 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4085375 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 964635983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.598912 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.317298 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 531478687 55.12% 55.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32400706 3.36% 58.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38829894 4.03% 62.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32544605 3.38% 65.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21858974 2.27% 68.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 36433886 3.78% 71.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 49094534 5.09% 77.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36959436 3.83% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 184572796 19.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 531979476 55.15% 55.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32383346 3.36% 58.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38813168 4.02% 62.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32534184 3.37% 65.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21860326 2.27% 68.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36455994 3.78% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 49125826 5.09% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36953777 3.83% 80.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 184529886 19.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 964173518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.248763 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.360566 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 264598468 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 174292947 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 373121057 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 48992521 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 103168525 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2446276906 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 964635983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.248691 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.359598 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 264568111 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 174813294 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 373028079 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49055371 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 103171128 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2446190376 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 103168525 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 301836329 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39995204 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12425 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 383530410 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 135630625 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2393744264 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2638 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25354791 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 92046607 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 28 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2227310497 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5630161832 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5629928430 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 233402 # Number of floating rename lookups +system.cpu.rename.SquashCycles 103171128 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 301809231 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40269862 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9996 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 383504038 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 135871728 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2393655047 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2663 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25553817 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 92121641 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2227336205 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5630423595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5630180918 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 242677 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 800011470 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1318 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1303 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 319166295 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 577919050 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 226606684 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 227271329 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 66051723 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2286915029 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6159 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1922683409 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1316831 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 755416366 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1189575311 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5606 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 964173518 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.994126 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.811461 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 800037178 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1323 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1277 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 319257105 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 577954406 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 226554784 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 227345729 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 66055755 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2286934263 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 9822 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1922478378 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1310077 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 755451043 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1190251690 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9269 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 964635983 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.992957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.810982 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 282941420 29.35% 29.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 159777972 16.57% 45.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 162985907 16.90% 62.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 148632114 15.42% 78.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 109327758 11.34% 89.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60035944 6.23% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 30803018 3.19% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 8626659 0.89% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1042726 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 283040019 29.34% 29.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 160280005 16.62% 45.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 162996180 16.90% 62.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 148777682 15.42% 78.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 109013815 11.30% 89.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60046720 6.22% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 30822079 3.20% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 8624231 0.89% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1035252 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 964173518 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 964635983 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2258663 14.74% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9960479 65.00% 79.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3103804 20.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2243375 14.67% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9951583 65.07% 79.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3098283 20.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2419995 0.13% 0.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1274972987 66.31% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2418078 0.13% 0.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1274783906 66.31% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 9 0.00% 66.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued @@ -169,85 +169,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 463702844 24.12% 90.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 181587574 9.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 463737726 24.12% 90.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 181538665 9.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1922683409 # Type of FU issued -system.cpu.iq.rate 1.946635 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15322946 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007970 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4826174769 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3042532180 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1874952899 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5344 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 78632 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 143 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1935584605 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1755 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 158265730 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1922478378 # Type of FU issued +system.cpu.iq.rate 1.945459 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15293241 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007955 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4826191069 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3042585561 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1874784055 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4988 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82956 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1935351994 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1547 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 158191943 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 193816890 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 368616 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 283851 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77446847 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 193852246 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 372238 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 283888 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77394965 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2334 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 103168525 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 9000117 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1434115 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2286921188 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1114031 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 577919050 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 226607032 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6159 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1032728 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29962 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 283851 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15679501 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2385329 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18064830 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1889474492 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 454765570 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 33208917 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 103171128 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 9041820 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1420232 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2286944085 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1121311 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 577954406 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 226555150 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6075 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1022506 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29752 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 283888 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15692203 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2347782 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18039985 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1889278448 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 454785721 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 33199930 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 629342688 # number of memory reference insts executed -system.cpu.iew.exec_branches 176743901 # Number of branches executed -system.cpu.iew.exec_stores 174577118 # Number of stores executed -system.cpu.iew.exec_rate 1.913013 # Inst execution rate -system.cpu.iew.wb_sent 1882825411 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1874953042 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1440779649 # num instructions producing a value -system.cpu.iew.wb_consumers 2134933130 # num instructions consuming a value +system.cpu.iew.exec_refs 629316980 # number of memory reference insts executed +system.cpu.iew.exec_branches 176731992 # Number of branches executed +system.cpu.iew.exec_stores 174531259 # Number of stores executed +system.cpu.iew.exec_rate 1.911862 # Inst execution rate +system.cpu.iew.wb_sent 1882655317 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1874784158 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1440755706 # num instructions producing a value +system.cpu.iew.wb_consumers 2135030641 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.898310 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.674859 # average fanout of values written-back +system.cpu.iew.wb_rate 1.897194 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674817 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 757942908 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 757965703 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16623561 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 861004993 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.775819 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.288206 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16607079 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 861464855 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.774871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.287572 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 338275347 39.29% 39.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 210593488 24.46% 63.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 75171542 8.73% 72.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92637359 10.76% 83.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34049472 3.95% 87.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27973994 3.25% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16051033 1.86% 92.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12256013 1.42% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 53996745 6.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 338524013 39.30% 39.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 210779915 24.47% 63.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 75257513 8.74% 72.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92637954 10.75% 83.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34058407 3.95% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27966548 3.25% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15953506 1.85% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12303443 1.43% 93.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 53983556 6.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 861004993 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 861464855 # Number of insts commited each cycle system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 533262345 # Number of memory references committed @@ -257,49 +257,49 @@ system.cpu.commit.branches 149758588 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 53996745 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 53983556 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3093939912 # The number of ROB reads -system.cpu.rob.rob_writes 4677211584 # The number of ROB writes -system.cpu.timesIdled 604649 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23522202 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3094435758 # The number of ROB reads +system.cpu.rob.rob_writes 4677260376 # The number of ROB writes +system.cpu.timesIdled 606046 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23551700 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 0.645980 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.645980 # CPI: Total CPI of All Threads -system.cpu.ipc 1.548036 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.548036 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3179615221 # number of integer regfile reads -system.cpu.int_regfile_writes 1745014633 # number of integer regfile writes -system.cpu.fp_regfile_reads 160 # number of floating regfile reads -system.cpu.fp_regfile_writes 9 # number of floating regfile writes -system.cpu.misc_regfile_reads 1039384818 # number of misc regfile reads -system.cpu.icache.replacements 9994 # number of replacements -system.cpu.icache.tagsinuse 979.138170 # Cycle average of tags in use -system.cpu.icache.total_refs 194574782 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11491 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 16932.798016 # Average number of references to valid blocks. +system.cpu.cpi 0.646301 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.646301 # CPI: Total CPI of All Threads +system.cpu.ipc 1.547266 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.547266 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3179235417 # number of integer regfile reads +system.cpu.int_regfile_writes 1744932190 # number of integer regfile writes +system.cpu.fp_regfile_reads 109 # number of floating regfile reads +system.cpu.fp_regfile_writes 3 # number of floating regfile writes +system.cpu.misc_regfile_reads 1039364909 # number of misc regfile reads +system.cpu.icache.replacements 9996 # number of replacements +system.cpu.icache.tagsinuse 975.733254 # Cycle average of tags in use +system.cpu.icache.total_refs 194489021 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11497 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 16916.501783 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 979.138170 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.478095 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 194581368 # number of ReadReq hits -system.cpu.icache.demand_hits 194581368 # number of demand (read+write) hits -system.cpu.icache.overall_hits 194581368 # number of overall hits -system.cpu.icache.ReadReq_misses 213540 # number of ReadReq misses -system.cpu.icache.demand_misses 213540 # number of demand (read+write) misses -system.cpu.icache.overall_misses 213540 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 1483328000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 1483328000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 1483328000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 194794908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 194794908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 194794908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 6946.370703 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 6946.370703 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 6946.370703 # average overall miss latency +system.cpu.icache.occ_blocks::0 975.733254 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.476432 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 194495909 # number of ReadReq hits +system.cpu.icache.demand_hits 194495909 # number of demand (read+write) hits +system.cpu.icache.overall_hits 194495909 # number of overall hits +system.cpu.icache.ReadReq_misses 223856 # number of ReadReq misses +system.cpu.icache.demand_misses 223856 # number of demand (read+write) misses +system.cpu.icache.overall_misses 223856 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 1547338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 1547338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 1547338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 194719765 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 194719765 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 194719765 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 6912.202487 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 6912.202487 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 6912.202487 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,137 +308,137 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 2095 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 2095 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 2095 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 211445 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 211445 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 211445 # number of overall MSHR misses +system.cpu.icache.writebacks 6 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 2117 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 2117 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 2117 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 221739 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 221739 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 221739 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 798407000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 798407000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 798407000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 830917000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 830917000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 830917000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.001085 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.001085 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.001085 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3775.955922 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.001139 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.001139 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.001139 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3747.274949 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2527816 # number of replacements -system.cpu.dcache.tagsinuse 4087.589623 # Cycle average of tags in use -system.cpu.dcache.total_refs 440722661 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2531912 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 174.067132 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 2123837000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4087.589623 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.997947 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 291994352 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 147612028 # number of WriteReq hits -system.cpu.dcache.demand_hits 439606380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 439606380 # number of overall hits -system.cpu.dcache.ReadReq_misses 3097887 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 1548173 # number of WriteReq misses -system.cpu.dcache.demand_misses 4646060 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 4646060 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 51505231500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 36276487000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 87781718500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 87781718500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 295092239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2527207 # number of replacements +system.cpu.dcache.tagsinuse 4087.569371 # Cycle average of tags in use +system.cpu.dcache.total_refs 440821768 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2531303 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 174.148163 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2135798000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4087.569371 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.997942 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 292074612 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 147577545 # number of WriteReq hits +system.cpu.dcache.demand_hits 439652157 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 439652157 # number of overall hits +system.cpu.dcache.ReadReq_misses 3115587 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 1582656 # number of WriteReq misses +system.cpu.dcache.demand_misses 4698243 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 4698243 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 51949082000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 37383634500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 89332716500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 89332716500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 295190199 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 444252440 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 444252440 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.010498 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.010379 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.010458 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.010458 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 16625.923250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 23431.804456 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 18893.797863 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 18893.797863 # average overall miss latency +system.cpu.dcache.demand_accesses 444350400 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 444350400 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.010555 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.010610 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.010573 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.010573 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 16673.930787 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23620.821265 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 19014.068983 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 19014.068983 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 74500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 18625 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 2229445 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 1337511 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 584931 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1922442 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1922442 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1760376 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 963242 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2723618 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2723618 # number of overall MSHR misses +system.cpu.dcache.writebacks 2229206 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 1355757 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 609338 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 1965095 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 1965095 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1759830 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 973318 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2733148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2733148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14910828500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 16810626500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 31721455000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 31721455000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 14896925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 17174770000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 32071695000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 32071695000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.005966 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006458 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.006131 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.006131 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8470.252094 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17452.131967 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006525 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.006151 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.006151 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8464.979572 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17645.589622 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 574929 # number of replacements -system.cpu.l2cache.tagsinuse 21600.538558 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3193840 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 594089 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 5.376030 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 271573746000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 7800.784816 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13799.753742 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.238061 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.421135 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1433037 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 2229452 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits 1223 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits 524485 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 1957522 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1957522 # number of overall hits -system.cpu.l2cache.ReadReq_misses 338639 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 198705 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 247104 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 585743 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 585743 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11565729500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency 9755500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 8475498500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20041228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20041228000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 1771676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 2229452 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 199928 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 771589 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 2543265 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 2543265 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.191140 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate 0.993883 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.320253 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.230311 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.230311 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34153.566187 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency 49.095393 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34299.317292 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34215.053360 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34215.053360 # average overall miss latency +system.cpu.l2cache.replacements 574699 # number of replacements +system.cpu.l2cache.tagsinuse 21595.701500 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3193363 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 593876 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 5.377154 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 271431195000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 7794.557657 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13801.143843 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.237871 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.421177 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 1432788 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 2229212 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits 1238 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits 524381 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 1957169 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 1957169 # number of overall hits +system.cpu.l2cache.ReadReq_misses 338369 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 208965 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 247135 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 585504 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 585504 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 11556474000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 9921000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 8477435500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 20033909500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 20033909500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 1771157 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 2229212 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 210203 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 771516 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 2542673 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 2542673 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.191044 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate 0.994110 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.320324 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.230271 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.230271 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34153.465595 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 47.476850 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34302.852692 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34216.520297 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34216.520297 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,31 +447,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 411255 # number of writebacks +system.cpu.l2cache.writebacks 411193 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 338639 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 198705 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 247104 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 585743 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 585743 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 338369 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 208965 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 247135 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 585504 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 585504 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10504876500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6160011500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7664207000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18169083500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18169083500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 10496162500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6478082000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666148000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18162310500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18162310500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191140 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.993883 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320253 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.230311 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.230311 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.870307 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.787600 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31016.118719 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191044 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994110 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320324 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.230271 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.230271 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.870319 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.799177 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.082141 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index f7d229ce0..ac0a4779d 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 20 2011 13:24:14 -gem5 started Aug 20 2011 13:24:28 -gem5 executing on zizzer +gem5 compiled Nov 16 2011 11:08:03 +gem5 started Nov 17 2011 13:09:16 +gem5 executing on ribera.cs.wisc.edu command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 +tests Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +25,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 96610526000 because target called exit() +122 123 124 Exiting @ tick 96689893000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 43a8220e5..7b2ddaff9 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,251 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.096611 # Number of seconds simulated -sim_ticks 96610526000 # Number of ticks simulated +sim_seconds 0.096690 # Number of seconds simulated +sim_ticks 96689893000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102112 # Simulator instruction rate (inst/s) -host_tick_rate 44565176 # Simulator tick rate (ticks/s) -host_mem_usage 220868 # Number of bytes of host memory used -host_seconds 2167.85 # Real time elapsed on the host +host_inst_rate 89575 # Simulator instruction rate (inst/s) +host_tick_rate 39125952 # Simulator tick rate (ticks/s) +host_mem_usage 253168 # Number of bytes of host memory used +host_seconds 2471.25 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 193221053 # number of cpu cycles simulated +system.cpu.numCycles 193379787 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25817967 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25817967 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2894858 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 23614164 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 20981330 # Number of BTB hits +system.cpu.BPredUnit.lookups 25818202 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 25818202 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2898724 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23602930 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 20841363 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30977399 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 261503264 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25817967 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 20981330 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70791188 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26915794 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 67651206 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 160 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1398 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 28846864 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 549492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 193133856 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.260391 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.334586 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30995459 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 261573615 # Number of instructions fetch has processed +system.cpu.fetch.Branches 25818202 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 20841363 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70808397 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26924712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 67767699 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 120 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1017 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28859729 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 549788 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 193293197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.259018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335260 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 124189193 64.30% 64.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4110604 2.13% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3242349 1.68% 68.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4337138 2.25% 70.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4293938 2.22% 72.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4598067 2.38% 74.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5546943 2.87% 77.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3021455 1.56% 79.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39794169 20.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 124336745 64.33% 64.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4112034 2.13% 66.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3238737 1.68% 68.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4462671 2.31% 70.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4295145 2.22% 72.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4476640 2.32% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5418723 2.80% 77.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3020771 1.56% 79.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39931731 20.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 193133856 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133619 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.353389 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 44744191 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57710964 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 57165261 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9800935 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23712505 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 424257825 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23712505 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53368695 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14594998 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21883 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57606354 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43829421 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 411666463 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18981117 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22454802 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 438110122 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1066455351 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1055559190 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10896161 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 193293197 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.133510 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.352642 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 44764810 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57827624 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 57161965 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9818293 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23720505 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 424367292 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 23720505 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53388300 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14632169 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21921 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 57615812 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43914490 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 411765049 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19034939 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22478875 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 438156432 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1066580371 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1055689317 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10891054 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 203746713 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1780 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1774 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 94916865 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104240418 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37277466 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67123936 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21592423 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 396698453 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1768 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 287681057 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 248197 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 174766428 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 350779105 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 522 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 193133856 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.489542 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.479240 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 203793023 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1794 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1788 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 94980657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104262380 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37289638 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67232013 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21668119 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 396788007 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2705 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 287703359 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 254770 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 174855842 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 350938331 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1459 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 193293197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.488430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.480803 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 60593209 31.37% 31.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 53908728 27.91% 59.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 35738338 18.50% 77.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 21062429 10.91% 88.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 13747169 7.12% 95.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 5239198 2.71% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2106456 1.09% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 621668 0.32% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 116661 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 60724695 31.42% 31.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54019027 27.95% 59.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 35712551 18.48% 77.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 21012235 10.87% 88.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 13686479 7.08% 95.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5222239 2.70% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2184583 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 593188 0.31% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 138200 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 193133856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 193293197 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 106266 3.87% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2319161 84.53% 88.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 318223 11.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 110269 4.01% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2317531 84.31% 88.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 321034 11.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1204809 0.42% 0.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187032245 65.01% 65.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1651608 0.57% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 73242981 25.46% 91.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 24549414 8.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1208234 0.42% 0.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187072997 65.02% 65.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1650386 0.57% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 73223880 25.45% 91.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 24547862 8.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 287681057 # Type of FU issued -system.cpu.iq.rate 1.488870 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2743650 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009537 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 765972748 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 566387994 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 278383951 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5515069 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5414925 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2649060 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 286446350 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2773548 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18375293 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 287703359 # Type of FU issued +system.cpu.iq.rate 1.487763 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2748834 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009554 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 766190945 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 566572341 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 278374724 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5512574 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 5407408 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2648186 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 286471551 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2772408 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18351013 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 47590828 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 32389 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 343467 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16761750 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 47612790 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32223 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 339608 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16773922 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 46017 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 46155 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23712505 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 356267 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 212332 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 396700221 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 134682 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104240418 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37277466 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 118966 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14039 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 343467 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2505670 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 594786 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3100456 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 283858854 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 71711617 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3822203 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23720505 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 359624 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 213865 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 396790712 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 135718 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104262380 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 37289638 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1786 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 119790 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15845 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 339608 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2505263 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 598160 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3103423 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 283855997 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 71689961 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3847362 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 95762495 # number of memory reference insts executed -system.cpu.iew.exec_branches 15668383 # Number of branches executed -system.cpu.iew.exec_stores 24050878 # Number of stores executed -system.cpu.iew.exec_rate 1.469089 # Inst execution rate -system.cpu.iew.wb_sent 282330192 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 281033011 # cumulative count of insts written-back -system.cpu.iew.wb_producers 227942764 # num instructions producing a value -system.cpu.iew.wb_consumers 378918606 # num instructions consuming a value +system.cpu.iew.exec_refs 95739480 # number of memory reference insts executed +system.cpu.iew.exec_branches 15662592 # Number of branches executed +system.cpu.iew.exec_stores 24049519 # Number of stores executed +system.cpu.iew.exec_rate 1.467868 # Inst execution rate +system.cpu.iew.wb_sent 282319460 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 281022910 # cumulative count of insts written-back +system.cpu.iew.wb_producers 227917239 # num instructions producing a value +system.cpu.iew.wb_consumers 378870882 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.454464 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.601561 # average fanout of values written-back +system.cpu.iew.wb_rate 1.453218 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.601570 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 175344362 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 175435625 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2895014 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 169421351 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.306583 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.742468 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2898838 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 169572692 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.305417 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.741291 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 63568929 37.52% 37.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 62259787 36.75% 74.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15643694 9.23% 83.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11988406 7.08% 90.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5417709 3.20% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2980917 1.76% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2013932 1.19% 96.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1192205 0.70% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4355772 2.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 63662174 37.54% 37.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 62350604 36.77% 74.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15592003 9.19% 83.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11999288 7.08% 90.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5440588 3.21% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2982193 1.76% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2011991 1.19% 96.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1185528 0.70% 97.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4348323 2.56% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 169421351 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 169572692 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -255,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 4355772 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4348323 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 561772958 # The number of ROB reads -system.cpu.rob.rob_writes 817171098 # The number of ROB writes -system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 87197 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 562023011 # The number of ROB reads +system.cpu.rob.rob_writes 817360743 # The number of ROB writes +system.cpu.timesIdled 1880 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 86590 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.872870 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.872870 # CPI: Total CPI of All Threads -system.cpu.ipc 1.145646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.145646 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 530742767 # number of integer regfile reads -system.cpu.int_regfile_writes 288972647 # number of integer regfile writes -system.cpu.fp_regfile_reads 3616458 # number of floating regfile reads -system.cpu.fp_regfile_writes 2303580 # number of floating regfile writes -system.cpu.misc_regfile_reads 149927786 # number of misc regfile reads +system.cpu.cpi 0.873587 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.873587 # CPI: Total CPI of All Threads +system.cpu.ipc 1.144706 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.144706 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 530675330 # number of integer regfile reads +system.cpu.int_regfile_writes 288962100 # number of integer regfile writes +system.cpu.fp_regfile_reads 3614411 # number of floating regfile reads +system.cpu.fp_regfile_writes 2302807 # number of floating regfile writes +system.cpu.misc_regfile_reads 149913222 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 4235 # number of replacements -system.cpu.icache.tagsinuse 1597.100373 # Cycle average of tags in use -system.cpu.icache.total_refs 28839309 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6200 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4651.501452 # Average number of references to valid blocks. +system.cpu.icache.replacements 4227 # number of replacements +system.cpu.icache.tagsinuse 1595.324923 # Cycle average of tags in use +system.cpu.icache.total_refs 28852140 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6194 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4658.078786 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1597.100373 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.779834 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 28839309 # number of ReadReq hits -system.cpu.icache.demand_hits 28839309 # number of demand (read+write) hits -system.cpu.icache.overall_hits 28839309 # number of overall hits -system.cpu.icache.ReadReq_misses 7555 # number of ReadReq misses -system.cpu.icache.demand_misses 7555 # number of demand (read+write) misses -system.cpu.icache.overall_misses 7555 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 173857500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 173857500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 173857500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 28846864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 28846864 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 28846864 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000262 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000262 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000262 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 23012.243547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 23012.243547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 23012.243547 # average overall miss latency +system.cpu.icache.occ_blocks::0 1595.324923 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.778967 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28852140 # number of ReadReq hits +system.cpu.icache.demand_hits 28852140 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28852140 # number of overall hits +system.cpu.icache.ReadReq_misses 7589 # number of ReadReq misses +system.cpu.icache.demand_misses 7589 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7589 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 174464500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 174464500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 174464500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28859729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28859729 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28859729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000263 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000263 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000263 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 22989.129003 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 22989.129003 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 22989.129003 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -308,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 1113 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 1113 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 1113 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 6442 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 6442 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 6442 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 1125 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 1125 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 1125 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6464 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6464 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6464 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 125492000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 125492000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 125492000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125677000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125677000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125677000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000223 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000223 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000223 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19480.285626 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000224 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000224 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000224 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 19442.605198 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 19442.605198 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 19442.605198 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 59 # number of replacements -system.cpu.dcache.tagsinuse 1420.172872 # Cycle average of tags in use -system.cpu.dcache.total_refs 73596568 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1416.877097 # Cycle average of tags in use +system.cpu.dcache.total_refs 73598603 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37057.687815 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 37058.712487 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1420.172872 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.346722 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 53088625 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20507488 # number of WriteReq hits -system.cpu.dcache.demand_hits 73596113 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 73596113 # number of overall hits -system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 8242 # number of WriteReq misses -system.cpu.dcache.demand_misses 9086 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 9086 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 26292500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 227102000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 253394500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 253394500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 53089469 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1416.877097 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.345917 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 53090649 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20507453 # number of WriteReq hits +system.cpu.dcache.demand_hits 73598102 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 73598102 # number of overall hits +system.cpu.dcache.ReadReq_misses 848 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 8277 # number of WriteReq misses +system.cpu.dcache.demand_misses 9125 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 9125 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 26447500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 228348000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 254795500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 254795500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 53091497 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 73605199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 73605199 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 73607227 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 73607227 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000402 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000123 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000123 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31152.251185 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 27554.234409 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27888.454766 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27888.454766 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate 0.000403 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31188.089623 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 27588.256615 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27922.794521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27922.794521 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 14 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 420 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 6436 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 6856 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 6856 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 6443 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 6867 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 6867 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1806 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 2230 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 2230 # number of overall MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1834 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 2258 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 2258 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14047000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 63209500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 77256500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 77256500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 13981500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 64146500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 78128000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 78128000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33129.716981 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34999.723145 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32975.235849 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34976.281352 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34600.531444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34600.531444 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2499.008056 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2867 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3761 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.762297 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2499.166941 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2858 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3763 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.759500 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2497.026903 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.981153 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.076203 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.000060 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2866 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::0 2497.181729 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.985212 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076208 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.000061 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2857 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2874 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2874 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3757 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 242 # number of UpgradeReq misses +system.cpu.l2cache.demand_hits 2865 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2865 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3759 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 270 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5314 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5314 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 128666000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53239000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 181905000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 181905000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 6623 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 5316 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5316 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128731000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53240500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 181971500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 181971500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6616 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 242 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses 270 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1565 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 8188 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 8188 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.567266 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 8181 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8181 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.568168 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.994888 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.648999 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.648999 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34247.005590 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34193.320488 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34231.275875 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34231.275875 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.649798 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.649798 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34246.076084 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34194.283879 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34230.906697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34230.906697 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3757 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 242 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3759 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 270 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5314 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5314 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 5316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5316 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 116539500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7502000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48375000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 164914500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 164914500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116600500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 8370000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48374500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 164975000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 164975000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567266 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.568168 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994888 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.648999 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.648999 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.297312 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.649798 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.649798 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.021016 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.364162 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.043031 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.671934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.671934 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index d1e2ef704..eef6427c6 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,542 +1,542 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3814417 # Simulator instruction rate (inst/s) -host_mem_usage 349920 # Number of bytes of host memory used -host_seconds 106.60 # Real time elapsed on the host -host_tick_rate 47954478135 # Simulator tick rate (ticks/s) +sim_seconds 5.112037 # Number of seconds simulated +sim_ticks 5112036996000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 406624458 # Number of instructions simulated -sim_seconds 5.112051 # Number of seconds simulated -sim_ticks 5112051446000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses::0 13367989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13367989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits::0 12059464 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12059464 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate::0 0.097885 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1308525 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308525 # number of ReadReq misses -system.cpu.dcache.WriteReq_accesses::0 8403116 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8403116 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 8086815 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8086815 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.037641 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 316301 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316301 # number of WriteReq misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.417813 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 21771105 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21771105 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 20146279 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20146279 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.074632 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 1624826 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1624826 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 511.999375 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 21771105 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21771105 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 20146279 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 20146279 # number of overall hits -system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.074632 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 1624826 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 1624826 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1622039 # number of replacements -system.cpu.dcache.sampled_refs 1622551 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.999375 # Cycle average of tags in use -system.cpu.dcache.total_refs 20148535 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1526505 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_accesses::1 21821 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21821 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_hits::1 12006 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12006 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.449796 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_misses::1 9815 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9815 # number of ReadReq misses -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.avg_refs 1.388452 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 21821 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21821 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 12006 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12006 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.449796 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 9815 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9815 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.occ_blocks::1 5.010366 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.313148 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 21821 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21821 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 12006 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12006 # number of overall hits -system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.449796 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 9815 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9815 # number of overall misses -system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.replacements 8629 # number of replacements -system.cpu.dtb_walker_cache.sampled_refs 8642 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dtb_walker_cache.tagsinuse 5.010366 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 11999 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5100489496500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.writebacks 2437 # number of writebacks -system.cpu.icache.ReadReq_accesses::0 254189385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 254189385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits::0 253396964 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 253396964 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate::0 0.003117 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 792421 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792421 # number of ReadReq misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 319.778505 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 254189385 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 254189385 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits::0 253396964 # number of demand (read+write) hits +host_inst_rate 2883648 # Simulator instruction rate (inst/s) +host_tick_rate 36256565088 # Simulator tick rate (ticks/s) +host_mem_usage 375496 # Number of bytes of host memory used +host_seconds 141.00 # Real time elapsed on the host +sim_insts 406583262 # Number of instructions simulated +system.l2c.replacements 163860 # number of replacements +system.l2c.tagsinuse 36838.766351 # Cycle average of tags in use +system.l2c.total_refs 3334365 # Total number of references to valid blocks. +system.l2c.sampled_refs 195829 # Sample count of references to valid blocks. +system.l2c.avg_refs 17.026921 # Average number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 9696.304444 # Average occupied blocks per context +system.l2c.occ_blocks::1 27142.461907 # Average occupied blocks per context +system.l2c.occ_percent::0 0.147954 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.414161 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2042982 # number of ReadReq hits +system.l2c.ReadReq_hits::1 10263 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2053245 # number of ReadReq hits +system.l2c.Writeback_hits::0 1528802 # number of Writeback hits +system.l2c.Writeback_hits::total 1528802 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 28 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 168885 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168885 # number of ReadExReq hits +system.l2c.demand_hits::0 2211867 # number of demand (read+write) hits +system.l2c.demand_hits::1 10263 # number of demand (read+write) hits +system.l2c.demand_hits::total 2222130 # number of demand (read+write) hits +system.l2c.overall_hits::0 2211867 # number of overall hits +system.l2c.overall_hits::1 10263 # number of overall hits +system.l2c.overall_hits::total 2222130 # number of overall hits +system.l2c.ReadReq_misses::0 56047 # number of ReadReq misses +system.l2c.ReadReq_misses::1 29 # number of ReadReq misses +system.l2c.ReadReq_misses::total 56076 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1784 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1784 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 144391 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 144391 # number of ReadExReq misses +system.l2c.demand_misses::0 200438 # number of demand (read+write) misses +system.l2c.demand_misses::1 29 # number of demand (read+write) misses +system.l2c.demand_misses::total 200467 # number of demand (read+write) misses +system.l2c.overall_misses::0 200438 # number of overall misses +system.l2c.overall_misses::1 29 # number of overall misses +system.l2c.overall_misses::total 200467 # number of overall misses +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2099029 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 10292 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2109321 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1528802 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1528802 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 1812 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1812 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 313276 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313276 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2412305 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 10292 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2422597 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2412305 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 10292 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2422597 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026701 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.002818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.029519 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.984547 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.460907 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.083090 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.002818 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.085908 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.083090 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.002818 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.085908 # miss rate for overall accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 144360 # number of writebacks +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses +system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 47572 # number of replacements +system.iocache.tagsinuse 0.042404 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.warmup_cycle 4994772178509 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.042404 # Average occupied blocks per context +system.iocache.occ_percent::1 0.002650 # Average percentage of cache occupancy +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.ReadReq_misses::1 907 # number of ReadReq misses +system.iocache.ReadReq_misses::total 907 # number of ReadReq misses +system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses +system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 47627 # number of demand (read+write) misses +system.iocache.demand_misses::total 47627 # number of demand (read+write) misses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 47627 # number of overall misses +system.iocache.overall_misses::total 47627 # number of overall misses +system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 0 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47627 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47627 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 46667 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 0 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.cpu.numCycles 10224074013 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 406583262 # Number of instructions executed +system.cpu.num_int_alu_accesses 391790000 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 42454615 # number of instructions that are conditional controls +system.cpu.num_int_insts 391790000 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 836247135 # number of times the integer registers were read +system.cpu.num_int_register_writes 419118732 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 38123075 # number of memory refs +system.cpu.num_load_insts 29716799 # Number of load instructions +system.cpu.num_store_insts 8406276 # Number of store instructions +system.cpu.num_idle_cycles 9770647500.086761 # Number of idle cycles +system.cpu.num_busy_cycles 453426512.913238 # Number of busy cycles +system.cpu.not_idle_fraction 0.044349 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955651 # Percentage of idle cycles +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.icache.replacements 790768 # number of replacements +system.cpu.icache.tagsinuse 510.627880 # Cycle average of tags in use +system.cpu.icache.total_refs 253353258 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791280 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 320.181551 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148756117000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.627880 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::0 253353258 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 253353258 # number of ReadReq hits +system.cpu.icache.demand_hits::0 253353258 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 253396964 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 253353258 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 253353258 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 253353258 # number of overall hits +system.cpu.icache.ReadReq_misses::0 791287 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791287 # number of ReadReq misses +system.cpu.icache.demand_misses::0 791287 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791287 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 791287 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 791287 # number of overall misses system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.003117 # miss rate for demand accesses +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 254144545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 254144545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 254144545 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 254144545 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 254144545 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 254144545 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.003114 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.003114 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 792421 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792421 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total no_value # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 253396964 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 253396964 # number of overall hits -system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.003117 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 792421 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 792421 # number of overall misses +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 806 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 791902 # number of replacements -system.cpu.icache.sampled_refs 792414 # Sample count of references to valid blocks. +system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 510.627884 # Cycle average of tags in use -system.cpu.icache.total_refs 253396964 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 148756026000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 809 # number of writebacks -system.cpu.idle_fraction 0.955646 # Percentage of idle cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 12217 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_hits::1 7611 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7611 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.377016 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_misses::1 4606 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4606 # 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number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7719 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.itb_walker_cache.avg_refs 2.010607 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 12219 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 7613 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7613 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::1 7721 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7721 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::1 7721 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7721 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 4507 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4507 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::1 4507 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4507 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::1 4507 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4507 # number of overall misses system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 12226 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 12228 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::1 12228 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.368641 # miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.376954 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.368580 # miss rate for demand accesses system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 4606 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4606 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.occ_blocks::1 3.020778 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.188799 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 12219 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::1 0.368580 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency system.cpu.itb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 7613 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7613 # number of overall hits -system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.376954 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 4606 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4606 # number of overall misses +system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.itb_walker_cache.writebacks 405 # number of writebacks +system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.replacements 3761 # number of replacements -system.cpu.itb_walker_cache.sampled_refs 3771 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.itb_walker_cache.tagsinuse 3.020778 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7582 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5105305893500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.writebacks 603 # number of writebacks -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles -system.cpu.numCycles 10224102915 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 453482144.002058 # Number of busy cycles -system.cpu.num_conditional_control_insts 42460207 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 9770620770.997942 # Number of idle cycles -system.cpu.num_insts 406624458 # Number of instructions executed -system.cpu.num_int_alu_accesses 391833838 # Number of integer alu accesses -system.cpu.num_int_insts 391833838 # number of integer instructions -system.cpu.num_int_register_reads 836347889 # number of times the integer registers were read -system.cpu.num_int_register_writes 419160873 # number of times the integer registers were written -system.cpu.num_load_insts 29720540 # Number of load instructions -system.cpu.num_mem_refs 38133606 # number of memory refs -system.cpu.num_store_insts 8413066 # Number of store instructions -system.iocache.ReadReq_accesses::1 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 909 # number of ReadReq misses -system.iocache.ReadReq_misses::total 909 # number of ReadReq misses -system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses -system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47629 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47629 # number of demand (read+write) misses -system.iocache.demand_misses::total 47629 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_blocks::1 0.042448 # Average occupied blocks per context -system.iocache.occ_percent::1 0.002653 # Average percentage of cache occupancy -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47629 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47629 # number of overall misses -system.iocache.overall_misses::total 47629 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 47574 # number of replacements -system.iocache.sampled_refs 47590 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.042448 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 4994772176509 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 46667 # number of writebacks -system.l2c.ReadExReq_accesses::0 314040 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 314040 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits::0 169169 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 169169 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate::0 0.461314 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 144871 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 144871 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 2100261 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 10262 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2110523 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 2044272 # number of ReadReq hits -system.l2c.ReadReq_hits::1 10235 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2054507 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.026658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002631 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.029289 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 55989 # number of ReadReq misses -system.l2c.ReadReq_misses::1 27 # number of ReadReq misses -system.l2c.ReadReq_misses::total 56016 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 1821 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1821 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_hits::0 24 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_rate::0 0.986820 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1797 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1797 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 1530354 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1530354 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 1530354 # number of Writeback hits -system.l2c.Writeback_hits::total 1530354 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 16.953097 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2414301 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 10262 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2424563 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 2213441 # number of demand (read+write) hits -system.l2c.demand_hits::1 10235 # number of demand (read+write) hits -system.l2c.demand_hits::total 2223676 # number of demand (read+write) hits -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.083196 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002631 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.085827 # miss rate for demand accesses -system.l2c.demand_misses::0 200860 # number of demand (read+write) misses -system.l2c.demand_misses::1 27 # number of demand (read+write) misses -system.l2c.demand_misses::total 200887 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 9697.448079 # Average occupied blocks per context -system.l2c.occ_blocks::1 27143.733047 # Average occupied blocks per context -system.l2c.occ_percent::0 0.147971 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.414180 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 2414301 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 10262 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2424563 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 2213441 # number of overall hits -system.l2c.overall_hits::1 10235 # number of overall hits -system.l2c.overall_hits::total 2223676 # number of overall hits -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.083196 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002631 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.085827 # miss rate for overall accesses -system.l2c.overall_misses::0 200860 # number of overall misses -system.l2c.overall_misses::1 27 # number of overall misses -system.l2c.overall_misses::total 200887 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 164351 # number of replacements -system.l2c.sampled_refs 196384 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36841.181126 # Cycle average of tags in use -system.l2c.total_refs 3329317 # Total number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 144194 # number of writebacks -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dtb_walker_cache.replacements 8177 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.011395 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12378 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 8191 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.511171 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5101233676500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 5.011395 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.313212 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 12392 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12392 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 12392 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12392 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::1 12392 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12392 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 9345 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9345 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 9345 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9345 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::1 9345 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9345 # number of overall misses +system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 21737 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21737 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 21737 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21737 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::1 21737 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21737 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.429912 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.429912 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.429912 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.dtb_walker_cache.writebacks 2332 # number of writebacks +system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1621118 # number of replacements +system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use +system.cpu.dcache.total_refs 20138941 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621630 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.418949 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 12055886 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12055886 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 8080806 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8080806 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 20136692 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20136692 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 20136692 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 20136692 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1308365 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308365 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 315530 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315530 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 1623895 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623895 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 1623895 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 1623895 # number of overall misses +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13364251 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13364251 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8396336 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8396336 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 21760587 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21760587 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 21760587 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21760587 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.097900 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.037579 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.074626 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::0 0.074626 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 1525259 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses +system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 5e1d5b2a8..f2563a156 100644 --- a/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,650 +1,650 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2432424 # Simulator instruction rate (inst/s) -host_mem_usage 346476 # Number of bytes of host memory used -host_seconds 108.67 # Real time elapsed on the host -host_tick_rate 47808116930 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 264339287 # Number of instructions simulated sim_seconds 5.195470 # Number of seconds simulated sim_ticks 5195470393000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses::0 13288006 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 11977182 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 19851809000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.098647 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1310824 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 15919294500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1310824 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 75925324500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_accesses::0 8347353 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 30172.881044 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 8032009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 9514837000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.037778 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 315344 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 8568794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.037778 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 315344 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1379728500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 21635359 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 18058.802043 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 20009191 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 29366646000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.075163 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 1626168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 24488089000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.075163 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1626168 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 511.997312 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses::0 21635359 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 18058.802043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 20009191 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 20009191 # number of overall hits -system.cpu.dcache.overall_miss_latency 29366646000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.075163 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 1626168 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 1626168 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 24488089000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.075163 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1626168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 77305053000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1623424 # number of replacements -system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use -system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1529951 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_accesses::1 21947 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 11678.900629 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 8678.844424 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_hits::1 13051 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_miss_latency 103895500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.405340 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_misses::1 8896 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 77207000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.405340 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 8896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 21947 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 13051 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_miss_latency 103895500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.405340 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 8896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 77207000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.405340 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_misses 8896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.occ_blocks::1 5.052403 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.315775 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 21947 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 13051 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits -system.cpu.dtb_walker_cache.overall_miss_latency 103895500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.405340 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 8896 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses -system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 77207000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.405340 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_misses 8896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.replacements 7704 # number of replacements -system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.writebacks 2985 # number of writebacks -system.cpu.icache.ReadReq_accesses::0 159222590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14812.203135 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11810.878733 # average ReadReq mshr miss latency +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1914891 # Simulator instruction rate (inst/s) +host_tick_rate 37635937594 # Simulator tick rate (ticks/s) +host_mem_usage 372104 # Number of bytes of host memory used +host_seconds 138.05 # Real time elapsed on the host +sim_insts 264342001 # Number of instructions simulated +system.l2c.replacements 136133 # number of replacements +system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use +system.l2c.total_refs 3363370 # Total number of references to valid blocks. +system.l2c.sampled_refs 168244 # Sample count of references to valid blocks. +system.l2c.avg_refs 19.991025 # Average number of references to valid blocks. +system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::0 7910.895776 # Average occupied blocks per context +system.l2c.occ_blocks::1 23478.999694 # Average occupied blocks per context +system.l2c.occ_percent::0 0.120711 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.358261 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 2047882 # number of ReadReq hits +system.l2c.ReadReq_hits::1 9561 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits +system.l2c.Writeback_hits::0 1534567 # number of Writeback hits +system.l2c.Writeback_hits::total 1534567 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 320 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::0 192958 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits +system.l2c.demand_hits::0 2240840 # number of demand (read+write) hits +system.l2c.demand_hits::1 9561 # number of demand (read+write) hits +system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits +system.l2c.overall_hits::0 2240840 # number of overall hits +system.l2c.overall_hits::1 9561 # number of overall hits +system.l2c.overall_hits::total 2250401 # number of overall hits +system.l2c.ReadReq_misses::0 50807 # number of ReadReq misses +system.l2c.ReadReq_misses::1 23 # number of ReadReq misses +system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 1369 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::0 120168 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses +system.l2c.demand_misses::0 170975 # number of demand (read+write) misses +system.l2c.demand_misses::1 23 # number of demand (read+write) misses +system.l2c.demand_misses::total 170998 # number of demand (read+write) misses +system.l2c.overall_misses::0 170975 # number of overall misses +system.l2c.overall_misses::1 23 # number of overall misses +system.l2c.overall_misses::total 170998 # number of overall misses +system.l2c.ReadReq_miss_latency 2656122500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 33778000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6249324500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 8905447000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 8905447000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 2098689 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 9584 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 1534567 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 1689 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 313126 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 2411815 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 9584 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 2411815 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 9584 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.024209 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.002400 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.026609 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.810539 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.383769 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.070891 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.002400 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.073290 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.070891 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.002400 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.073290 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52278.672230 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 115483586.956522 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 115535865.628752 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 24673.484295 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52004.897310 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::0 52086.252376 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 387193347.826087 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 387245434.078463 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52086.252376 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 387193347.826087 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 387245434.078463 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks 116255 # number of writebacks +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 50830 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1369 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 120168 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 170998 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 170998 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency 2046144000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 55109000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 4807305000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 6853449000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 6853449000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 56051785000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 1218050000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 57269835000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.024220 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 5.303631 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 5.327851 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.810539 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.383769 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::0 0.070900 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 17.842028 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 17.912929 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.070900 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 17.842028 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 17.912929 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40254.652764 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40004.868185 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.replacements 47510 # number of replacements +system.iocache.tagsinuse 0.120586 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.avg_refs 0 # Average number of references to valid blocks. +system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::1 0.120586 # Average occupied blocks per context +system.iocache.occ_percent::1 0.007537 # Average percentage of cache occupancy +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits +system.iocache.ReadReq_misses::1 844 # number of ReadReq misses +system.iocache.ReadReq_misses::total 844 # number of ReadReq misses +system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses +system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 47564 # number of demand (read+write) misses +system.iocache.demand_misses::total 47564 # number of demand (read+write) misses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 47564 # number of overall misses +system.iocache.overall_misses::total 47564 # number of overall misses +system.iocache.ReadReq_miss_latency 106575932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency 6391379160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency 6497955092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency 6497955092 # number of overall miss cycles +system.iocache.ReadReq_accesses::1 844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 47564 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 47564 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 126274.800948 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 136801.779966 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 136614.983853 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 136614.983853 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.writebacks 46668 # number of writebacks +system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.iocache.overall_mshr_hits 0 # number of overall MSHR hits +system.iocache.ReadReq_mshr_misses 844 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses 47564 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses 47564 # number of overall MSHR misses +system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.iocache.ReadReq_mshr_miss_latency 62666978 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3961676998 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency 4024343976 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency 4024343976 # number of overall MSHR miss cycles +system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency 74249.973934 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency 84796.168622 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency +system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated +system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.cpu.numCycles 10390940786 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 264342001 # Number of instructions executed +system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls +system.cpu.num_int_insts 249556386 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 543487907 # number of times the integer registers were read +system.cpu.num_int_register_writes 266037487 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 23169904 # number of memory refs +system.cpu.num_load_insts 14812525 # Number of load instructions +system.cpu.num_store_insts 8357379 # Number of store instructions +system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles +system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles +system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941953 # Percentage of idle cycles +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu.icache.replacements 788139 # number of replacements +system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use +system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 510.361283 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.996799 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::0 158433932 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 11681762500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.004953 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 788658 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 9314744000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.004953 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 788658 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 159222590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14812.203135 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency system.cpu.icache.demand_hits::0 158433932 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 11681762500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.004953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.overall_hits::0 158433932 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 158433932 # number of overall hits +system.cpu.icache.ReadReq_misses::0 788658 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses system.cpu.icache.demand_misses::0 788658 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9314744000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.004953 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 788658 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 510.361283 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.996799 # Average percentage of cache occupancy +system.cpu.icache.overall_misses::0 788658 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 788658 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 11681762500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 11681762500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 11681762500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 159222590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 159222590 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::0 159222590 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14812.203135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 158433932 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 158433932 # number of overall hits -system.cpu.icache.overall_miss_latency 11681762500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.004953 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.004953 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.icache.overall_miss_rate::0 0.004953 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 788658 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 788658 # number of overall misses +system.cpu.icache.ReadReq_avg_miss_latency::0 14812.203135 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::0 14812.203135 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14812.203135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 805 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 788658 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 788658 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 788658 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 9314744000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9314744000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 9314744000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.004953 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.004953 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::0 0.004953 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 788658 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 788139 # number of replacements -system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11810.878733 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use -system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 805 # number of writebacks -system.cpu.idle_fraction 0.941953 # Percentage of idle cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 12221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 11042.372881 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 8042.372881 # average ReadReq mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.itb_walker_cache.replacements 3754 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::1 3.070606 # Average occupied blocks per context +system.cpu.itb_walker_cache.occ_percent::1 0.191913 # Average percentage of cache occupancy system.cpu.itb_walker_cache.ReadReq_hits::1 7619 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_miss_latency 50817000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.376565 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_misses::1 4602 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 37011000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.376565 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_misses 4602 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits system.cpu.itb_walker_cache.demand_hits::1 7621 # number of demand (read+write) hits system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_miss_latency 50817000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.376503 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::1 7621 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::1 4602 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses system.cpu.itb_walker_cache.demand_misses::1 4602 # number of demand (read+write) misses system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.itb_walker_cache.demand_mshr_miss_latency 37011000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.376503 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_misses 4602 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.occ_blocks::1 3.070606 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.191913 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::1 4602 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency 50817000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency 50817000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency 50817000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::1 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::1 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::1 12223 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 7621 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits -system.cpu.itb_walker_cache.overall_miss_latency 50817000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.376565 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::1 0.376503 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::1 0.376503 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 4602 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 11042.372881 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::1 11042.372881 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::1 11042.372881 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.itb_walker_cache.writebacks 826 # number of writebacks +system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.itb_walker_cache.ReadReq_mshr_misses 4602 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses 4602 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses 4602 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 37011000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency 37011000 # number of demand (read+write) MSHR miss cycles system.cpu.itb_walker_cache.overall_mshr_miss_latency 37011000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.376565 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.376503 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.376503 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_misses 4602 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.replacements 3754 # number of replacements -system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 8042.372881 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.writebacks 826 # number of writebacks -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles -system.cpu.numCycles 10390940786 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles -system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles -system.cpu.num_insts 264339287 # Number of instructions executed -system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses -system.cpu.num_int_insts 249556386 # number of integer instructions -system.cpu.num_int_register_reads 543487907 # number of times the integer registers were read -system.cpu.num_int_register_writes 266037487 # number of times the integer registers were written -system.cpu.num_load_insts 14812525 # Number of load instructions -system.cpu.num_mem_refs 23169904 # number of memory refs -system.cpu.num_store_insts 8357379 # Number of store instructions -system.iocache.ReadReq_accesses::1 844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 126274.800948 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 74249.973934 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 106575932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 844 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 62666978 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 844 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136801.779966 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84796.168622 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 6391379160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses -system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3961676998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47564 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136614.983853 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 6497955092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47564 # number of demand (read+write) misses -system.iocache.demand_misses::total 47564 # number of demand (read+write) misses -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 4024343976 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 47564 # number of demand (read+write) MSHR misses -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_blocks::1 0.120586 # Average occupied blocks per context -system.iocache.occ_percent::1 0.007537 # Average percentage of cache occupancy -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47564 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136614.983853 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 6497955092 # number of overall miss cycles -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47564 # number of overall misses -system.iocache.overall_misses::total 47564 # number of overall misses -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 4024343976 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 47564 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 47510 # number of replacements -system.iocache.sampled_refs 47526 # Sample count of references to valid blocks. -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.120586 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit. -system.iocache.writebacks 46668 # number of writebacks -system.l2c.ReadExReq_accesses::0 313126 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52004.897310 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40004.868185 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 192958 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6249324500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.383769 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 120168 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4807305000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.383769 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 120168 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2098689 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 9584 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52278.672230 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 115483586.956522 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 115535865.628752 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40254.652764 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 2047882 # number of ReadReq hits -system.l2c.ReadReq_hits::1 9561 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 2656122500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.024209 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002400 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026609 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 50807 # number of ReadReq misses -system.l2c.ReadReq_misses::1 23 # number of ReadReq misses -system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 2046144000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.024220 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 5.303631 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 5.327851 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 50830 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 56051785000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1689 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 24673.484295 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 320 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 33778000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.810539 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1369 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 55109000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.810539 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1369 # number of UpgradeReq MSHR misses -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1218050000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 1534567 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 1534567 # number of Writeback hits -system.l2c.Writeback_hits::total 1534567 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 19.991025 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2411815 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 9584 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52086.252376 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 387193347.826087 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 387245434.078463 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency -system.l2c.demand_hits::0 2240840 # number of demand (read+write) hits -system.l2c.demand_hits::1 9561 # number of demand (read+write) hits -system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits -system.l2c.demand_miss_latency 8905447000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.070891 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002400 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.073290 # miss rate for demand accesses -system.l2c.demand_misses::0 170975 # number of demand (read+write) misses -system.l2c.demand_misses::1 23 # number of demand (read+write) misses -system.l2c.demand_misses::total 170998 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 6853449000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.070900 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 17.842028 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 17.912929 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 170998 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_blocks::0 7910.895776 # Average occupied blocks per context -system.l2c.occ_blocks::1 23478.999694 # Average occupied blocks per context -system.l2c.occ_percent::0 0.120711 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.358261 # Average percentage of cache occupancy -system.l2c.overall_accesses::0 2411815 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 9584 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52086.252376 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 387193347.826087 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 387245434.078463 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 2240840 # number of overall hits -system.l2c.overall_hits::1 9561 # number of overall hits -system.l2c.overall_hits::total 2250401 # number of overall hits -system.l2c.overall_miss_latency 8905447000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.070891 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002400 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.073290 # miss rate for overall accesses -system.l2c.overall_misses::0 170975 # number of overall misses -system.l2c.overall_misses::1 23 # number of overall misses -system.l2c.overall_misses::total 170998 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 6853449000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.070900 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 17.842028 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 17.912929 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 170998 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 57269835000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 136133 # number of replacements -system.l2c.sampled_refs 168244 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use -system.l2c.total_refs 3363370 # Total number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 116255 # number of writebacks -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dtb_walker_cache.replacements 7704 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::1 5.052403 # Average occupied blocks per context +system.cpu.dtb_walker_cache.occ_percent::1 0.315775 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::1 13051 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::1 13051 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::1 13051 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::1 8896 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::1 8896 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::1 8896 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency 103895500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency 103895500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency 103895500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::1 21947 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::1 21947 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::1 21947 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.405340 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::1 0.405340 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::1 0.405340 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 11678.900629 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 11678.900629 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 11678.900629 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.dtb_walker_cache.writebacks 2985 # number of writebacks +system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dtb_walker_cache.ReadReq_mshr_misses 8896 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses 8896 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses 8896 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 77207000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency 77207000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency 77207000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.405340 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.405340 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.405340 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 8678.844424 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1623424 # number of replacements +system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use +system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 511.997312 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::0 11977182 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 8032009 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits +system.cpu.dcache.demand_hits::0 20009191 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 20009191 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 20009191 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 1310824 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 315344 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses +system.cpu.dcache.demand_misses::0 1626168 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 1626168 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 1626168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 19851809000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 9514837000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 29366646000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 29366646000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 13288006 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 8347353 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 21635359 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 21635359 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.098647 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.037778 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::0 0.075163 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::0 0.075163 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 30172.881044 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 18058.802043 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 18058.802043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 1529951 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 1310824 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 315344 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1626168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1626168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 15919294500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8568794500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 24488089000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 24488089000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 75925324500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1379728500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 77305053000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098647 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.037778 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.075163 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.075163 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |