diff options
| -rw-r--r-- | src/mem/packet.cc | 4 | ||||
| -rw-r--r-- | src/mem/packet.hh | 9 |
2 files changed, 10 insertions, 3 deletions
diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 4c3a785dc..69cf36a5c 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -98,11 +98,11 @@ MemCmd::commandInfo[] = /* HardPFResp */ { SET4(IsRead, IsResponse, IsHWPrefetch, HasData), InvalidCmd, "HardPFResp" }, - /* WriteInvalidateReq */ + /* WriteInvalidateReq (currently unused, see packet.hh) */ { SET6(IsWrite, NeedsExclusive, IsInvalidate, IsRequest, HasData, NeedsResponse), WriteInvalidateResp, "WriteInvalidateReq" }, - /* WriteInvalidateResp */ + /* WriteInvalidateResp (currently unused, see packet.hh) */ { SET3(IsWrite, NeedsExclusive, IsResponse), InvalidCmd, "WriteInvalidateResp" }, /* UpgradeReq */ diff --git a/src/mem/packet.hh b/src/mem/packet.hh index e49fa67b8..fc48b08ce 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -91,6 +91,14 @@ class MemCmd HardPFReq, SoftPFResp, HardPFResp, + // WriteInvalidateReq transactions used to be generated by the + // DMA ports when writing full blocks to memory, however, it + // is not used anymore since we put the I/O cache in place to + // deal with partial block writes. Hence, WriteInvalidateReq + // and WriteInvalidateResp are currently unused. The + // implication is that the I/O cache does read-exclusive + // operations on every full-cache-block DMA, and ultimately + // this needs to be fixed. WriteInvalidateReq, WriteInvalidateResp, UpgradeReq, @@ -133,7 +141,6 @@ class MemCmd IsRead, //!< Data flows from responder to requester IsWrite, //!< Data flows from requester to responder IsUpgrade, - IsPrefetch, //!< Not a demand access IsInvalidate, NeedsExclusive, //!< Requires exclusive copy to complete in-cache IsRequest, //!< Issued by requester |