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-rw-r--r--src/arch/SConscript2
-rw-r--r--src/arch/alpha/mmapped_ipr.hh (renamed from src/arch/alpha/mmaped_ipr.hh)6
-rw-r--r--src/arch/arm/mmapped_ipr.hh (renamed from src/arch/arm/mmaped_ipr.hh)4
-rw-r--r--src/arch/mips/mmapped_ipr.hh (renamed from src/arch/mips/mmaped_ipr.hh)4
-rw-r--r--src/arch/power/mmapped_ipr.hh (renamed from src/arch/power/mmaped_ipr.hh)6
-rw-r--r--src/arch/sparc/mmapped_ipr.hh (renamed from src/arch/sparc/mmaped_ipr.hh)4
-rw-r--r--src/arch/sparc/tlb.cc2
-rw-r--r--src/arch/x86/mmapped_ipr.hh (renamed from src/arch/x86/mmaped_ipr.hh)6
-rw-r--r--src/arch/x86/tlb.cc4
-rw-r--r--src/cpu/simple/atomic.cc6
-rw-r--r--src/cpu/simple/timing.cc8
-rw-r--r--src/mem/physical.cc2
-rw-r--r--src/mem/request.hh4
13 files changed, 29 insertions, 29 deletions
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 8c537182d..34367b274 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -50,7 +50,7 @@ isa_switch_hdrs = Split('''
kernel_stats.hh
locked_mem.hh
microcode_rom.hh
- mmaped_ipr.hh
+ mmapped_ipr.hh
mt.hh
process.hh
predecoder.hh
diff --git a/src/arch/alpha/mmaped_ipr.hh b/src/arch/alpha/mmapped_ipr.hh
index 99f8aeb06..6c3403b33 100644
--- a/src/arch/alpha/mmaped_ipr.hh
+++ b/src/arch/alpha/mmapped_ipr.hh
@@ -28,8 +28,8 @@
* Authors: Ali Saidi
*/
-#ifndef __ARCH_ALPHA_MMAPED_IPR_HH__
-#define __ARCH_ALPHA_MMAPED_IPR_HH__
+#ifndef __ARCH_ALPHA_MMAPPED_IPR_HH__
+#define __ARCH_ALPHA_MMAPPED_IPR_HH__
/**
* @file
@@ -60,4 +60,4 @@ handleIprWrite(ThreadContext *xc, Packet *pkt)
} // namespace AlphaISA
-#endif // __ARCH_ALPHA_MMAPED_IPR_HH__
+#endif // __ARCH_ALPHA_MMAPPED_IPR_HH__
diff --git a/src/arch/arm/mmaped_ipr.hh b/src/arch/arm/mmapped_ipr.hh
index 8483ef7a2..0f90ac35d 100644
--- a/src/arch/arm/mmaped_ipr.hh
+++ b/src/arch/arm/mmapped_ipr.hh
@@ -30,8 +30,8 @@
* Stephen Hines
*/
-#ifndef __ARCH_ARM_MMAPED_IPR_HH__
-#define __ARCH_ARM_MMAPED_IPR_HH__
+#ifndef __ARCH_ARM_MMAPPED_IPR_HH__
+#define __ARCH_ARM_MMAPPED_IPR_HH__
/**
* @file
diff --git a/src/arch/mips/mmaped_ipr.hh b/src/arch/mips/mmapped_ipr.hh
index 99c2e7fc7..14d6e3f42 100644
--- a/src/arch/mips/mmaped_ipr.hh
+++ b/src/arch/mips/mmapped_ipr.hh
@@ -28,8 +28,8 @@
* Authors: Ali Saidi
*/
-#ifndef __ARCH_MIPS_MMAPED_IPR_HH__
-#define __ARCH_MIPS_MMAPED_IPR_HH__
+#ifndef __ARCH_MIPS_MMAPPED_IPR_HH__
+#define __ARCH_MIPS_MMAPPED_IPR_HH__
/**
* @file
diff --git a/src/arch/power/mmaped_ipr.hh b/src/arch/power/mmapped_ipr.hh
index fc88634dc..a55ef8f7d 100644
--- a/src/arch/power/mmaped_ipr.hh
+++ b/src/arch/power/mmapped_ipr.hh
@@ -32,8 +32,8 @@
* Timothy M. Jones
*/
-#ifndef __ARCH_POWER_MMAPED_IPR_HH__
-#define __ARCH_POWER_MMAPED_IPR_HH__
+#ifndef __ARCH_POWER_MMAPPED_IPR_HH__
+#define __ARCH_POWER_MMAPPED_IPR_HH__
/**
* @file
@@ -63,4 +63,4 @@ handleIprWrite(ThreadContext *xc, Packet *pkt)
} // namespace PowerISA
-#endif // __ARCH_POWER_MMAPED_IPR_HH__
+#endif // __ARCH_POWER_MMAPPED_IPR_HH__
diff --git a/src/arch/sparc/mmaped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index 52310086e..777242e7c 100644
--- a/src/arch/sparc/mmaped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -28,8 +28,8 @@
* Authors: Ali Saidi
*/
-#ifndef __ARCH_SPARC_MMAPED_IPR_HH__
-#define __ARCH_SPARC_MMAPED_IPR_HH__
+#ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
+#define __ARCH_SPARC_MMAPPED_IPR_HH__
/**
* @file
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 7c7819561..8aa007168 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -816,7 +816,7 @@ handleSparcErrorRegAccess:
regAccessOk:
handleMmuRegAccess:
DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
- req->setFlags(Request::MMAPED_IPR);
+ req->setFlags(Request::MMAPPED_IPR);
req->setPaddr(req->getVaddr());
return NoFault;
};
diff --git a/src/arch/x86/mmaped_ipr.hh b/src/arch/x86/mmapped_ipr.hh
index 82fe95cef..525f54bfb 100644
--- a/src/arch/x86/mmaped_ipr.hh
+++ b/src/arch/x86/mmapped_ipr.hh
@@ -37,8 +37,8 @@
* Authors: Gabe Black
*/
-#ifndef __ARCH_X86_MMAPEDIPR_HH__
-#define __ARCH_X86_MMAPEDIPR_HH__
+#ifndef __ARCH_X86_MMAPPEDIPR_HH__
+#define __ARCH_X86_MMAPPEDIPR_HH__
/**
* @file
@@ -89,4 +89,4 @@ namespace X86ISA
}
};
-#endif // __ARCH_X86_MMAPEDIPR_HH__
+#endif // __ARCH_X86_MMAPPEDIPR_HH__
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index dff62a4d7..ac32e86d7 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -179,7 +179,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc)
panic("CPUID memory space not yet implemented!\n");
} else if (prefix == IntAddrPrefixMSR) {
vaddr = vaddr >> 3;
- req->setFlags(Request::MMAPED_IPR);
+ req->setFlags(Request::MMAPPED_IPR);
Addr regNum = 0;
switch (vaddr & ~IntAddrPrefixMask) {
case 0x10:
@@ -508,7 +508,7 @@ TLB::translateInt(RequestPtr req, ThreadContext *tc)
// space.
assert(!(IOPort & ~0xFFFF));
if (IOPort == 0xCF8 && req->getSize() == 4) {
- req->setFlags(Request::MMAPED_IPR);
+ req->setFlags(Request::MMAPPED_IPR);
req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
} else if ((IOPort & ~mask(2)) == 0xCFC) {
req->setFlags(Request::UNCACHEABLE);
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index da4258fb9..27635d3ce 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -29,7 +29,7 @@
*/
#include "arch/locked_mem.hh"
-#include "arch/mmaped_ipr.hh"
+#include "arch/mmapped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
#include "config/the_isa.hh"
@@ -334,7 +334,7 @@ AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
Packet::Broadcast);
pkt.dataStatic(data);
- if (req->isMmapedIpr())
+ if (req->isMmappedIpr())
dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
else {
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
@@ -501,7 +501,7 @@ AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
Packet pkt = Packet(req, cmd, Packet::Broadcast);
pkt.dataStatic(data);
- if (req->isMmapedIpr()) {
+ if (req->isMmappedIpr()) {
dcache_latency +=
TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ab1ff91e8..632e83356 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -41,7 +41,7 @@
*/
#include "arch/locked_mem.hh"
-#include "arch/mmaped_ipr.hh"
+#include "arch/mmapped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
#include "config/the_isa.hh"
@@ -264,7 +264,7 @@ bool
TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
{
RequestPtr req = pkt->req;
- if (req->isMmapedIpr()) {
+ if (req->isMmappedIpr()) {
Tick delay;
delay = TheISA::handleIprRead(thread->getTC(), pkt);
new IprEvent(pkt, this, nextCycle(curTick() + delay));
@@ -401,7 +401,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
{
pkt1 = pkt2 = NULL;
- assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
+ assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
if (req->getFlags().isSet(Request::NO_ACCESS)) {
buildPacket(pkt1, req, read);
@@ -536,7 +536,7 @@ bool
TimingSimpleCPU::handleWritePacket()
{
RequestPtr req = dcache_pkt->req;
- if (req->isMmapedIpr()) {
+ if (req->isMmappedIpr()) {
Tick delay;
delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index a134165bc..e7c96ab54 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -548,7 +548,7 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
fatal("Insufficient memory to allocate compression state for %s\n",
filename);
- // unmap file that was mmaped in the constructor
+ // unmap file that was mmapped in the constructor
// This is done here to make sure that gzip and open don't muck with our
// nice large space of memory before we reallocate it
munmap((char*)pmemAddr, size());
diff --git a/src/mem/request.hh b/src/mem/request.hh
index ec1b8ba29..4aa3a821a 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -70,7 +70,7 @@ class Request : public FastAlloc
/** The request is to an uncacheable address. */
static const FlagsType UNCACHEABLE = 0x00001000;
/** This request is to a memory mapped register. */
- static const FlagsType MMAPED_IPR = 0x00002000;
+ static const FlagsType MMAPPED_IPR = 0x00002000;
/** This request is a clear exclusive. */
static const FlagsType CLEAR_LL = 0x00004000;
@@ -453,7 +453,7 @@ class Request : public FastAlloc
bool isLocked() const { return _flags.isSet(LOCKED); }
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
- bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
+ bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 19:03:22 +0000