diff options
| -rwxr-xr-x | src/cpu/o3/thread_context.hh | 10 | ||||
| -rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 30 | ||||
| -rw-r--r-- | src/cpu/thread_context.hh | 16 |
3 files changed, 55 insertions, 1 deletions
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 31e08db4c..55b385d11 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -203,6 +203,16 @@ class O3ThreadContext : public ThreadContext /** Sets this thread's next PC. */ virtual void setNextPC(uint64_t val); + virtual uint64_t readMicroPC() + { return cpu->readMicroPC(thread->readTid()); } + + virtual void setMicroPC(uint64_t val); + + virtual uint64_t readNextMicroPC() + { return cpu->readNextMicroPC(thread->readTid()); } + + virtual void setNextMicroPC(uint64_t val); + /** Reads a miscellaneous register. */ virtual MiscReg readMiscRegNoEffect(int misc_reg) { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index efbbc2329..55584629e 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -289,9 +289,13 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc) // Copy the misc regs. TheISA::copyMiscRegs(tc, this); - // Then finally set the PC and the next PC. + // Then finally set the PC, the next PC, the nextNPC, the micropc, and the + // next micropc. cpu->setPC(tc->readPC(), tid); cpu->setNextPC(tc->readNextPC(), tid); + cpu->setNextNPC(tc->readNextNPC(), tid); + cpu->setMicroPC(tc->readMicroPC(), tid); + cpu->setNextMicroPC(tc->readNextMicroPC(), tid); #if !FULL_SYSTEM this->thread->funcExeInst = tc->readFuncExeInst(); #endif @@ -450,6 +454,30 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val) template <class Impl> void +O3ThreadContext<Impl>::setMicroPC(uint64_t val) +{ + cpu->setMicroPC(val, thread->readTid()); + + // Squash if we're not already in a state update mode. + if (!thread->trapPending && !thread->inSyscall) { + cpu->squashFromTC(thread->readTid()); + } +} + +template <class Impl> +void +O3ThreadContext<Impl>::setNextMicroPC(uint64_t val) +{ + cpu->setNextMicroPC(val, thread->readTid()); + + // Squash if we're not already in a state update mode. + if (!thread->trapPending && !thread->inSyscall) { + cpu->squashFromTC(thread->readTid()); + } +} + +template <class Impl> +void O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val) { cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid()); diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 31fdb42c2..0d09492ee 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -226,6 +226,14 @@ class ThreadContext virtual void setNextNPC(uint64_t val) = 0; + virtual uint64_t readMicroPC() = 0; + + virtual void setMicroPC(uint64_t val) = 0; + + virtual uint64_t readNextMicroPC() = 0; + + virtual void setNextMicroPC(uint64_t val) = 0; + virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; virtual MiscReg readMiscReg(int misc_reg) = 0; @@ -419,6 +427,14 @@ class ProxyThreadContext : public ThreadContext void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } + uint64_t readMicroPC() { return actualTC->readMicroPC(); } + + void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } + + uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } + + void setNextMicroPC(uint64_t val) { actualTC->setMicroPC(val); } + MiscReg readMiscRegNoEffect(int misc_reg) { return actualTC->readMiscRegNoEffect(misc_reg); } |