diff options
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 17 | ||||
| -rw-r--r-- | src/mem/cache/coherence/coherence_protocol.cc | 3 | ||||
| -rw-r--r-- | src/mem/cache/coherence/simple_coherence.hh | 6 | ||||
| -rw-r--r-- | src/mem/cache/miss/mshr_queue.cc | 1 | ||||
| -rw-r--r-- | src/mem/packet.cc | 11 | ||||
| -rw-r--r-- | src/mem/packet.hh | 4 |
6 files changed, 13 insertions, 29 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 6b9eac865..56352c110 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -794,14 +794,7 @@ Cache<TagStore,Coherence>::snoop(PacketPtr &pkt) return; } - //Send a timing (true) invalidate up if the protocol calls for it - if (coherence->propogateInvalidate(pkt, true)) { - //Temp hack, we had a functional read hit in the L1, mark as success - pkt->flags |= SATISFIED; - pkt->result = Packet::Success; - respondToSnoop(pkt, curTick + hitLatency); - return; - } + ///// PROPAGATE SNOOP UPWARD HERE Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); BlkType *blk = tags->findBlock(pkt->getAddr()); @@ -1097,13 +1090,7 @@ template<class TagStore, class Coherence> Tick Cache<TagStore,Coherence>::snoopProbe(PacketPtr &pkt) { - //Send a atomic (false) invalidate up if the protocol calls for it - if (coherence->propogateInvalidate(pkt, false)) { - //Temp hack, we had a functional read hit in the L1, mark as success - pkt->flags |= SATISFIED; - pkt->result = Packet::Success; - return hitLatency; - } + ///// PROPAGATE SNOOP UPWARD HERE Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); BlkType *blk = tags->findBlock(pkt->getAddr()); diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc index 33a8a4e63..bc8de0d26 100644 --- a/src/mem/cache/coherence/coherence_protocol.cc +++ b/src/mem/cache/coherence/coherence_protocol.cc @@ -295,11 +295,14 @@ CoherenceProtocol::CoherenceProtocol(const string &name, tt[Invalid][MC::ReadReq].onRequest(MC::ReadReq); // we only support write allocate right now tt[Invalid][MC::WriteReq].onRequest(MC::ReadExReq); + tt[Invalid][MC::ReadExReq].onRequest(MC::ReadExReq); tt[Invalid][MC::SwapReq].onRequest(MC::ReadExReq); tt[Shared][MC::WriteReq].onRequest(writeToSharedCmd); + tt[Shared][MC::ReadExReq].onRequest(MC::ReadExReq); tt[Shared][MC::SwapReq].onRequest(writeToSharedCmd); if (hasOwned) { tt[Owned][MC::WriteReq].onRequest(writeToSharedCmd); + tt[Owned][MC::ReadExReq].onRequest(MC::ReadExReq); tt[Owned][MC::SwapReq].onRequest(writeToSharedCmd); } diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh index 1c89c703a..095260ca4 100644 --- a/src/mem/cache/coherence/simple_coherence.hh +++ b/src/mem/cache/coherence/simple_coherence.hh @@ -161,12 +161,6 @@ class SimpleCoherence bool allowFastWrites() { return false; } bool hasProtocol() { return true; } - - bool propogateInvalidate(PacketPtr pkt, bool isTiming) - { - //For now we do nothing, asssumes simple coherence is top level of cache - return false; - } }; #endif //__SIMPLE_COHERENCE_HH__ diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index add11dfe7..e9aa89bf8 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -119,7 +119,6 @@ MSHRQueue::allocate(PacketPtr &pkt, int size) if (!pkt->needsResponse()) { mshr->allocateAsBuffer(pkt); } else { - assert(size !=0); mshr->allocate(pkt->cmd, aligned_addr, size, pkt); allocatedTargets += 1; } diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 2463a19ba..8c69def37 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -56,17 +56,18 @@ MemCmd::commandInfo[] = { 0, InvalidCmd, "InvalidCmd" }, /* ReadReq */ { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" }, + /* ReadResp */ + { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" }, /* WriteReq */ { SET4(IsWrite, IsRequest, NeedsResponse, HasData), WriteResp, "WriteReq" }, - /* WriteReqNoAck */ - { SET3(IsWrite, IsRequest, HasData), InvalidCmd, "WriteReqNoAck" }, - /* ReadResp */ - { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" }, /* WriteResp */ { SET2(IsWrite, IsResponse), InvalidCmd, "WriteResp" }, /* Writeback */ - { SET3(IsWrite, IsRequest, HasData), InvalidCmd, "Writeback" }, + { SET4(IsWrite, IsRequest, HasData, NeedsResponse), + WritebackAck, "Writeback" }, + /* WritebackAck */ + { SET2(IsWrite, IsResponse), InvalidCmd, "WritebackAck" }, /* SoftPFReq */ { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse), SoftPFResp, "SoftPFReq" }, diff --git a/src/mem/packet.hh b/src/mem/packet.hh index 577f99116..413ffa26b 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -73,11 +73,11 @@ class MemCmd { InvalidCmd, ReadReq, - WriteReq, - WriteReqNoAck, ReadResp, + WriteReq, WriteResp, Writeback, + WritebackAck, SoftPFReq, HardPFReq, SoftPFResp, |