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-rw-r--r--src/cpu/simple/timing.cc3
-rw-r--r--util/m5/m5.c5
2 files changed, 7 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 1670cb066..b04288ca6 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -891,6 +891,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
// received a response from the dcache: complete the load or store
// instruction
assert(!pkt->isError());
+ assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
+ pkt->req->getFlags().isSet(Request::NO_ACCESS));
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
@@ -920,7 +922,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
}
}
- assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
_status = Running;
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
diff --git a/util/m5/m5.c b/util/m5/m5.c
index 7747fc0bc..96150f2bb 100644
--- a/util/m5/m5.c
+++ b/util/m5/m5.c
@@ -65,6 +65,11 @@ read_file(int dest_fid)
int offset = 0;
int len;
+ // Touch all buffer pages to ensure they are mapped in the
+ // page table. This is required in the case of X86_FS, where
+ // Linux does demand paging.
+ memset(buf, 0, sizeof(buf));
+
while ((len = m5_readfile(buf, sizeof(buf), offset)) > 0) {
write(dest_fid, buf, len);
offset += len;