diff options
| -rw-r--r-- | src/arch/mips/isa/operands.isa | 5 | ||||
| -rw-r--r-- | src/arch/mips/registers.hh | 1 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 50726cd30..27cb4357a 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -109,8 +109,11 @@ def operands {{ #LL Flag 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1), + #Thread pointer value for SE mode + 'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1), + # Index Register - 'Index':('ControlReg','uw','MISCREG_INDEX',None,1), + 'Index': ('ControlReg','uw','MISCREG_INDEX',None,1), 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1), diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index fdb04b131..5cf76634d 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -275,6 +275,7 @@ enum MiscRegIndex{ MISCREG_DESAVE = 248, //Bank 31: 248-256 MISCREG_LLFLAG = 257, + MISCREG_TP_VALUE, MISCREG_NUMREGS }; |