diff options
| -rw-r--r-- | src/arch/arm/faults.cc | 5 | ||||
| -rw-r--r-- | src/arch/arm/miscregs_types.hh | 1 |
2 files changed, 1 insertions, 5 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index ab0d0de0f..bd06ea288 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -300,10 +300,6 @@ ArmFault::getVector(ThreadContext *tc) // ARM ARM issue C B1.8.1 bool haveSecurity = ArmSystem::haveSecurity(tc); - // panic if SCTLR.VE because I have no idea what to do with vectored - // interrupts - SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); - assert(!sctlr.ve); // Check for invalid modes CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); assert(haveSecurity || cpsr.mode != MODE_MON); @@ -318,6 +314,7 @@ ArmFault::getVector(ThreadContext *tc) base = tc->readMiscReg(MISCREG_HVBAR); break; default: + SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); if (sctlr.v) { base = HighVecs; } else { diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh index 0a862360e..c3ee6ca00 100644 --- a/src/arch/arm/miscregs_types.hh +++ b/src/arch/arm/miscregs_types.hh @@ -319,7 +319,6 @@ namespace ArmISA // DC CVAC and IC IVAU instructions // (AArch64 SCTLR_EL1 only) Bitfield<25> ee; // Exception Endianness - Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only) Bitfield<24> e0e; // Endianness of explicit data accesses at EL0 // (AArch64 SCTLR_EL1 only) Bitfield<23> xp; // Extended page table enable (dropped in ARMv7) |