8 files changed, 17 insertions, 80 deletions
diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py
index 91da1ed76..3101c33de 100644
--- a/src/arch/arm/ArmNativeTrace.py
+++ b/src/arch/arm/ArmNativeTrace.py
@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from NativeTrace import NativeTrace
+from CPUTracers import NativeTrace
 
 class ArmNativeTrace(NativeTrace):
     type = 'ArmNativeTrace'
diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py
index cdc34b541..46b606652 100644
--- a/src/arch/sparc/SparcNativeTrace.py
+++ b/src/arch/sparc/SparcNativeTrace.py
@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from NativeTrace import NativeTrace
+from CPUTracers import NativeTrace
 
 class SparcNativeTrace(NativeTrace):
     type = 'SparcNativeTrace'
diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py
index 281a2df50..e6eae8918 100644
--- a/src/arch/x86/X86NativeTrace.py
+++ b/src/arch/x86/X86NativeTrace.py
@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from NativeTrace import NativeTrace
+from CPUTracers import NativeTrace
 
 class X86NativeTrace(NativeTrace):
     type = 'X86NativeTrace'
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 8ba90209a..052df5702 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -49,7 +49,7 @@ from m5.proxy import *
 
 from XBar import CoherentXBar
 from InstTracer import InstTracer
-from ExeTracer import ExeTracer
+from CPUTracers import ExeTracer
 from MemObject import MemObject
 from ClockDomain import *
 
diff --git a/src/cpu/IntelTrace.py b/src/cpu/CPUTracers.py
index 6319ed1aa..df7a8939f 100644
--- a/src/cpu/IntelTrace.py
+++ b/src/cpu/CPUTracers.py
@@ -30,7 +30,19 @@ from m5.SimObject import SimObject
 from m5.params import *
 from InstTracer import InstTracer
 
+class ExeTracer(InstTracer):
+    type = 'ExeTracer'
+    cxx_class = 'Trace::ExeTracer'
+    cxx_header = "cpu/exetrace.hh"
+
 class IntelTrace(InstTracer):
     type = 'IntelTrace'
     cxx_class = 'Trace::IntelTrace'
     cxx_header = "cpu/inteltrace.hh"
+
+class NativeTrace(ExeTracer):
+    abstract = True
+    type = 'NativeTrace'
+    cxx_class = 'Trace::NativeTrace'
+    cxx_header = 'cpu/nativetrace.hh'
+
diff --git a/src/cpu/ExeTracer.py b/src/cpu/ExeTracer.py
deleted file mode 100644
index f672fd65f..000000000
--- a/src/cpu/ExeTracer.py
+++ /dev/null
@@ -1,36 +0,0 @@
-# Copyright (c) 2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-
-from m5.SimObject import SimObject
-from m5.params import *
-from InstTracer import InstTracer
-
-class ExeTracer(InstTracer):
-    type = 'ExeTracer'
-    cxx_class = 'Trace::ExeTracer'
-    cxx_header = "cpu/exetrace.hh"
diff --git a/src/cpu/NativeTrace.py b/src/cpu/NativeTrace.py
deleted file mode 100644
index fbcb341f0..000000000
--- a/src/cpu/NativeTrace.py
+++ /dev/null
@@ -1,37 +0,0 @@
-# Copyright (c) 2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-
-from m5.SimObject import SimObject
-from m5.params import *
-from ExeTracer import ExeTracer
-
-class NativeTrace(ExeTracer):
-    abstract = True
-    type = 'NativeTrace'
-    cxx_class = 'Trace::NativeTrace'
-    cxx_header = "cpu/nativetrace.hh"
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 0f5d53b37..88ea535b7 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -38,11 +38,9 @@ if env['TARGET_ISA'] == 'null':
 SimObject('CheckerCPU.py')
 
 SimObject('BaseCPU.py')
+SimObject('CPUTracers.py')
 SimObject('FuncUnit.py')
-SimObject('ExeTracer.py')
-SimObject('IntelTrace.py')
 SimObject('IntrControl.py')
-SimObject('NativeTrace.py')
 SimObject('TimingExpr.py')
 
 Source('activity.cc')