diff options
| -rw-r--r-- | src/arch/sparc/miscregfile.cc | 9 | ||||
| -rw-r--r-- | src/arch/sparc/tlb.cc | 34 | ||||
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 3 |
3 files changed, 39 insertions, 7 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index c58a1fd09..2dde5afd5 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -326,7 +326,6 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) | mbits(tick,63,63); case MISCREG_FPRS: - warn("FPRS register read and FPU stuff not really implemented\n"); // in legion if fp is enabled du and dl are set if (fprs & 0x4) return 0x7; @@ -389,7 +388,6 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) asi = val; break; case MISCREG_FPRS: - warn("FPU not really implemented writing %#X to FPRS\n", val); fprs = val; break; case MISCREG_TICK: @@ -612,6 +610,8 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) void MiscRegFile::setRegWithEffect(int miscReg, const MiscReg &val, ThreadContext * tc) { + MiscReg new_val = val; + switch (miscReg) { case MISCREG_STICK: case MISCREG_TICK: @@ -634,7 +634,8 @@ void MiscRegFile::setRegWithEffect(int miscReg, tl = val; return; case MISCREG_CWP: - tc->changeRegFileContext(CONTEXT_CWP, val); + new_val = val > NWindows ? NWindows - 1 : val; + tc->changeRegFileContext(CONTEXT_CWP, new_val); break; case MISCREG_GL: tc->changeRegFileContext(CONTEXT_GLOBALS, val); @@ -671,7 +672,7 @@ void MiscRegFile::setRegWithEffect(int miscReg, panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val); #endif } - setReg(miscReg, val); + setReg(miscReg, new_val); } void MiscRegFile::serialize(std::ostream & os) diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 40542a9a6..1cecb4ebb 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -625,13 +625,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) return new DataAccessException; } - } else if (hpriv) { + } /*else if (hpriv) {*/ if (asi == ASI_P) { ct = Primary; context = pri_context; goto continueDtbFlow; } - } + //} if (!implicit) { if (AsiIsLittle(asi)) @@ -933,6 +933,36 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); pkt->set(data); break; + case ASI_IMMU_TSB_PS0_PTR_REG: + temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); + if (bits(temp,12,0) == 0) { + tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0); + cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); + } else { + tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0); + cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); + } + data = mbits(tsbtemp,63,13); + data |= temp >> (9 + bits(cnftemp,2,0) * 3) & + mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); + pkt->set(data); + break; + case ASI_IMMU_TSB_PS1_PTR_REG: + temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); + if (bits(temp,12,0) == 0) { + tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1); + cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); + } else { + tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1); + cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); + } + data = mbits(tsbtemp,63,13); + if (bits(tsbtemp,12,12)) + data |= ULL(1) << (13+bits(tsbtemp,3,0)); + data |= temp >> (9 + bits(cnftemp,2,0) * 3) & + mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); + pkt->set(data); + break; default: doMmuReadError: diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 1f7f65045..f03c4da57 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -47,7 +47,8 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, // Check if we are going to interrupt because of something setReg(miscReg, val); tc->getCpuPtr()->checkInterrupts = true; - warn("Writing to softint not really supported, writing: %#x\n", val); + if (val != 0x10000 && val != 0) + warn("Writing to softint not really supported, writing: %#x\n", val); break; case MISCREG_SOFTINT_CLR: |