diff options
| -rw-r--r-- | src/mem/cache/base.cc | 23 | ||||
| -rw-r--r-- | src/mem/cache/cache.cc | 15 |
2 files changed, 19 insertions, 19 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 8f7a8922d..ec0383dea 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -569,29 +569,14 @@ BaseCache::recvTimingResp(PacketPtr pkt) Tick BaseCache::recvAtomic(PacketPtr pkt) { - // We are in atomic mode so we pay just for lookupLatency here. - Cycles lat = lookupLatency; - - // follow the same flow as in recvTimingReq, and check if a cache - // above us is responding - if (pkt->cacheResponding() && !pkt->isClean()) { - assert(!pkt->req->isCacheInvalidate()); - DPRINTF(Cache, "Cache above responding to %s: not responding\n", - pkt->print()); - - // if a cache is responding, and it had the line in Owned - // rather than Modified state, we need to invalidate any - // copies that are not on the same path to memory - assert(pkt->needsWritable() && !pkt->responderHadWritable()); - lat += ticksToCycles(memSidePort.sendAtomic(pkt)); - - return lat * clockPeriod(); - } - // should assert here that there are no outstanding MSHRs or // writebacks... that would mean that someone used an atomic // access in timing mode + // We use lookupLatency here because it is used to specify the latency + // to access. + Cycles lat = lookupLatency; + CacheBlk *blk = nullptr; PacketList writebacks; bool satisfied = access(pkt, blk, lat, writebacks); diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc index 3bb2667af..624f244ce 100644 --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -658,6 +658,21 @@ Cache::recvAtomic(PacketPtr pkt) { promoteWholeLineWrites(pkt); + // follow the same flow as in recvTimingReq, and check if a cache + // above us is responding + if (pkt->cacheResponding()) { + assert(!pkt->req->isCacheInvalidate()); + DPRINTF(Cache, "Cache above responding to %s: not responding\n", + pkt->print()); + + // if a cache is responding, and it had the line in Owned + // rather than Modified state, we need to invalidate any + // copies that are not on the same path to memory + assert(pkt->needsWritable() && !pkt->responderHadWritable()); + + return memSidePort.sendAtomic(pkt); + } + return BaseCache::recvAtomic(pkt); } |