diff options
| -rw-r--r-- | src/arch/alpha/remote_gdb.cc | 12 | ||||
| -rw-r--r-- | src/arch/alpha/utility.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/alpha/dyn_inst.hh | 5 | ||||
| -rw-r--r-- | src/cpu/o3/alpha/dyn_inst_impl.hh | 5 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 7 |
5 files changed, 22 insertions, 11 deletions
diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index f23fc3205..4637bd7a6 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -121,14 +121,18 @@ #include <string> #include <unistd.h> +#include "config/full_system.hh" +#if FULL_SYSTEM +#include "arch/alpha/vtophys.hh" +#endif + #include "arch/alpha/kgdb.h" +#include "arch/alpha/utility.hh" #include "arch/alpha/remote_gdb.hh" -#include "arch/vtophys.hh" #include "base/intmath.hh" #include "base/remote_gdb.hh" #include "base/socket.hh" #include "base/trace.hh" -#include "config/full_system.hh" #include "cpu/thread_context.hh" #include "cpu/static_inst.hh" #include "mem/physical.hh" @@ -152,6 +156,9 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) bool RemoteGDB::acc(Addr va, size_t len) { +#if !FULL_SYSTEM + panic("acc function needs to be rewritten for SE mode\n"); +#else Addr last_va; va = TheISA::TruncPage(va); @@ -191,6 +198,7 @@ RemoteGDB::acc(Addr va, size_t len) DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); return true; +#endif } /////////////////////////////////////////////////////////// diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index 100736555..9a06cc2a4 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -121,9 +121,9 @@ namespace AlphaISA template <class TC> void zeroRegisters(TC *tc); -#if FULL_SYSTEM // Alpha IPR register accessors - inline bool PcPAL(Addr addr) { return addr & 0x1; } + inline bool PcPAL(Addr addr) { return addr & 0x3; } +#if FULL_SYSTEM //////////////////////////////////////////////////////////////////////// // diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index ee895d77c..603a1b52d 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -73,8 +73,9 @@ class AlphaDynInst : public BaseDynInst<Impl> public: /** BaseDynInst constructor given a binary instruction. */ - AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num, - O3CPU *cpu); + AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC, + Addr Pred_PC, Addr Pred_NPC, + InstSeqNum seq_num, O3CPU *cpu); /** BaseDynInst constructor given a static inst pointer. */ AlphaDynInst(StaticInstPtr &_staticInst); diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index 02432f721..50cdec408 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -31,9 +31,10 @@ #include "cpu/o3/alpha/dyn_inst.hh" template <class Impl> -AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, +AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC, + Addr Pred_PC, Addr Pred_NPC, InstSeqNum seq_num, O3CPU *cpu) - : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu) + : BaseDynInst<Impl>(inst, PC, NPC, Pred_PC, Pred_NPC, seq_num, cpu) { initVars(); } diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 815935db3..07d02b20b 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1256,10 +1256,11 @@ DefaultFetch<Impl>::fetch(bool &status_change) ext_inst = TheISA::NoopMachInst; // Create a new DynInst from the dummy nop. - DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, - next_PC, + DynInstPtr instruction = new DynInst(ext_inst, + fetch_PC, fetch_NPC, + next_PC, next_NPC, inst_seq, cpu); - instruction->setPredTarg(next_PC + instSize); + instruction->setPredTarg(next_PC, next_NPC); instruction->setTid(tid); instruction->setASID(tid); |