diff options
| -rw-r--r-- | arch/alpha/ev5.cc | 24 | ||||
| -rw-r--r-- | cpu/base_cpu.cc | 7 | ||||
| -rw-r--r-- | cpu/base_cpu.hh | 1 | ||||
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 6 |
4 files changed, 18 insertions, 20 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 8b95e8b3d..aa52916b9 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -101,17 +101,17 @@ AlphaISA::initIPRs(RegFile *regs) } -template <class XC> +template <class CPU> void -AlphaISA::processInterrupts(XC *xc) +AlphaISA::processInterrupts(CPU *cpu) { //Check if there are any outstanding interrupts //Handle the interrupts int ipl = 0; int summary = 0; - IntReg *ipr = xc->getIprPtr(); + IntReg *ipr = cpu->getIprPtr(); - check_interrupts = 0; + cpu->checkInterrupts = false; if (ipr[IPR_ASTRR]) panic("asynchronous traps not implemented\n"); @@ -127,7 +127,7 @@ AlphaISA::processInterrupts(XC *xc) } } - uint64_t interrupts = xc->intr_status(); + uint64_t interrupts = cpu->intr_status(); if (interrupts) { for (int i = INTLEVEL_EXTERNAL_MIN; @@ -143,22 +143,22 @@ AlphaISA::processInterrupts(XC *xc) if (ipl && ipl > ipr[IPR_IPLR]) { ipr[IPR_ISR] = summary; ipr[IPR_INTID] = ipl; - xc->trap(Interrupt_Fault); + cpu->trap(Interrupt_Fault); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", ipr[IPR_IPLR], ipl, summary); } } -template <class XC> +template <class CPU> void -AlphaISA::zeroRegisters(XC *xc) +AlphaISA::zeroRegisters(CPU *cpu) { // Insure ISA semantics // (no longer very clean due to the change in setIntReg() in the // cpu model. Consider changing later.) - xc->xc->setIntReg(ZeroReg, 0); - xc->xc->setFloatRegDouble(ZeroReg, 0.0); + cpu->xc->setIntReg(ZeroReg, 0); + cpu->xc->setFloatRegDouble(ZeroReg, 0.0); } void @@ -220,8 +220,6 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc) // that's it! (orders of magnitude less painful than x86) } -bool AlphaISA::check_interrupts = false; - Fault ExecContext::hwrei() { @@ -238,7 +236,7 @@ ExecContext::hwrei() if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0) AlphaISA::swap_palshadow(®s, false); - AlphaISA::check_interrupts = true; + cpu->checkInterrupts = true; } // FIXME: XXX check for interrupts? XXX diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc index 7fb8b414f..e4dd744a6 100644 --- a/cpu/base_cpu.cc +++ b/cpu/base_cpu.cc @@ -53,8 +53,9 @@ BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, Counter max_loads_any_thread, Counter max_loads_all_threads, System *_system, Tick freq) - : SimObject(_name), frequency(freq), deferRegistration(_def_reg), - number_of_threads(_number_of_threads), system(_system) + : SimObject(_name), frequency(freq), checkInterrupts(true), + deferRegistration(_def_reg), number_of_threads(_number_of_threads), + system(_system) #else BaseCPU::BaseCPU(const string &_name, int _number_of_threads, bool _def_reg, Counter max_insts_any_thread, @@ -219,7 +220,7 @@ BaseCPU::post_interrupt(int int_num, int index) if (index < 0 || index >= sizeof(uint64_t) * 8) panic("int_num out of bounds\n"); - AlphaISA::check_interrupts = 1; + checkInterrupts = true; interrupts[int_num] |= 1 << index; intstatus |= (ULL(1) << int_num); } diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh index 7e937c755..8668c3216 100644 --- a/cpu/base_cpu.hh +++ b/cpu/base_cpu.hh @@ -55,6 +55,7 @@ class BaseCPU : public SimObject virtual void post_interrupt(int int_num, int index); virtual void clear_interrupt(int int_num, int index); virtual void clear_interrupts(); + bool checkInterrupts; bool check_interrupt(int int_num) const { if (int_num > NumInterruptLevels) diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index 6af67eee0..04783574f 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -641,13 +641,11 @@ SimpleCPU::tick() Fault fault = No_Fault; #ifdef FULL_SYSTEM - if (AlphaISA::check_interrupts && - xc->cpu->check_interrupts() && - !PC_PAL(xc->regs.pc) && + if (checkInterrupts && check_interrupts() && !xc->inPalMode() && status() != IcacheMissComplete) { int ipl = 0; int summary = 0; - AlphaISA::check_interrupts = 0; + checkInterrupts = false; IntReg *ipr = xc->regs.ipr; if (xc->regs.ipr[TheISA::IPR_SIRR]) { |