diff options
| -rw-r--r-- | configs/common/Caches.py | 39 | ||||
| -rw-r--r-- | configs/common/Options.py | 57 | ||||
| -rw-r--r-- | configs/common/Simulation.py | 175 | ||||
| -rw-r--r-- | configs/example/fs.py | 169 | ||||
| -rw-r--r-- | configs/example/se.py | 204 | ||||
| -rw-r--r-- | src/dev/i8254xGBe.cc | 53 |
6 files changed, 340 insertions, 357 deletions
diff --git a/configs/common/Caches.py b/configs/common/Caches.py new file mode 100644 index 000000000..d86fba246 --- /dev/null +++ b/configs/common/Caches.py @@ -0,0 +1,39 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +import m5 +from m5.objects import * + +class L1Cache(BaseCache): + assoc = 2 + block_size = 64 + latency = 1 + mshrs = 10 + tgts_per_mshr = 5 + protocol = CoherenceProtocol(protocol='moesi') + diff --git a/configs/common/Options.py b/configs/common/Options.py new file mode 100644 index 000000000..d9c1cc64e --- /dev/null +++ b/configs/common/Options.py @@ -0,0 +1,57 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +# system options +parser.add_option("-d", "--detailed", action="store_true") +parser.add_option("-t", "--timing", action="store_true") +parser.add_option("-n", "--num_cpus", type="int", default=1) +parser.add_option("--caches", action="store_true") + +# Run duration options +parser.add_option("-m", "--maxtick", type="int") +parser.add_option("--maxtime", type="float") + +# Checkpointing options +###Note that performing checkpointing via python script files will override +###checkpoint instructions built into binaries. +parser.add_option("--take_checkpoints", action="store", type="string", + help="<M,N> will take checkpoint at cycle M and every N cycles \ + thereafter") +parser.add_option("--max_checkpoints", action="store", type="int", + help="the maximum number of checkpoints to drop", + default=5) +parser.add_option("--checkpoint_dir", action="store", type="string", + help="Place all checkpoints in this absolute directory") +parser.add_option("-r", "--checkpoint_restore", action="store", type="int", + help="restore from checkpoint <N>") + +# CPU Switching - default switch model goes from a checkpoint +# to a timing simple CPU with caches to warm up, then to detailed CPU for +# data measurement +parser.add_option("-s", "--standard_switch", action="store_true", + help="switch from one cpu mode to another") diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py new file mode 100644 index 000000000..b927315ba --- /dev/null +++ b/configs/common/Simulation.py @@ -0,0 +1,175 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Lisa Hsu + +from os import getcwd +import m5 +from m5.objects import * +m5.AddToPath('../common') +from Caches import * + +def run(options, root, testsys): + if options.maxtick: + maxtick = options.maxtick + elif options.maxtime: + simtime = int(options.maxtime * root.clock.value) + print "simulating for: ", simtime + maxtick = simtime + else: + maxtick = -1 + + if options.checkpoint_dir: + cptdir = options.checkpoint_dir + else: + cptdir = getcwd() + + np = options.num_cpus + max_checkpoints = options.max_checkpoints + + if options.standard_switch: + switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) + for i in xrange(np)] + switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) + for i in xrange(np)] + for i in xrange(np): + switch_cpus[i].system = testsys + switch_cpus1[i].system = testsys + if not m5.build_env['FULL_SYSTEM']: + switch_cpus[i].workload = testsys.cpu[i].workload + switch_cpus1[i].workload = testsys.cpu[i].workload + switch_cpus[i].clock = testsys.cpu[0].clock + switch_cpus1[i].clock = testsys.cpu[0].clock + if options.caches: + switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L1Cache(size = '64kB')) + + switch_cpus[i].mem = testsys.physmem + switch_cpus1[i].mem = testsys.physmem + switch_cpus[i].connectMemPorts(testsys.membus) + root.switch_cpus = switch_cpus + root.switch_cpus1 = switch_cpus1 + switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)] + switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)] + + m5.instantiate(root) + + if options.checkpoint_restore: + from os.path import isdir + from os import listdir + import re + + if not isdir(cptdir): + m5.panic("checkpoint dir %s does not exist!" % cptdir) + + dirs = listdir(cptdir) + expr = re.compile('cpt.([0-9]*)') + cpts = [] + for dir in dirs: + match = expr.match(dir) + if match: + cpts.append(match.group(1)) + + cpts.sort(lambda a,b: cmp(long(a), long(b))) + + cpt_num = options.checkpoint_restore + + if cpt_num > len(cpts): + m5.panic('Checkpoint %d not found' % cpt_num) + + m5.restoreCheckpoint(root, + "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]])) + + if options.standard_switch: + exit_event = m5.simulate(10000) + + ## when you change to Timing (or Atomic), you halt the system given + ## as argument. When you are finished with the system changes + ## (including switchCpus), you must resume the system manually. + ## You DON'T need to resume after just switching CPUs if you haven't + ## changed anything on the system level. + + m5.changeToTiming(testsys) + m5.switchCpus(switch_cpu_list) + m5.resume(testsys) + + exit_event = m5.simulate(3000000) + m5.switchCpus(switch_cpu_list1) + + num_checkpoints = 0 + exit_cause = '' + + if options.take_checkpoints: + [when, period] = options.take_checkpoints.split(",", 1) + when = int(when) + period = int(period) + + print "when is ", when, " period is ", period + exit_event = m5.simulate(when) + while exit_event.getCause() == "checkpoint": + exit_event = m5.simulate(when - m5.curTick()) + + if exit_event.getCause() == "simulate() limit reached": + m5.checkpoint(root, cptdir + "cpt.%d") + num_checkpoints += 1 + + sim_ticks = when + exit_cause = "maximum %d checkpoints dropped" % max_checkpoints + while num_checkpoints < max_checkpoints: + if (sim_ticks + period) > maxtick and maxtick != -1: + exit_event = m5.simulate(maxtick - sim_ticks) + exit_cause = exit_event.getCause() + break + else: + exit_event = m5.simulate(period) + sim_ticks += period + while exit_event.getCause() == "checkpoint": + exit_event = m5.simulate(sim_ticks - m5.curTick()) + if exit_event.getCause() == "simulate() limit reached": + m5.checkpoint(root, cptdir + "cpt.%d") + num_checkpoints += 1 + + else: #no checkpoints being taken via this script + exit_event = m5.simulate(maxtick) + + while exit_event.getCause() == "checkpoint": + m5.checkpoint(root, cptdir + "cpt.%d") + num_checkpoints += 1 + if num_checkpoints == max_checkpoints: + exit_cause = "maximum %d checkpoints dropped" % max_checkpoints + break + + if maxtick == -1: + exit_event = m5.simulate(maxtick) + else: + exit_event = m5.simulate(maxtick - m5.curTick()) + + exit_cause = exit_event.getCause() + + if exit_cause == '': + exit_cause = exit_event.getCause() + print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause + diff --git a/configs/example/fs.py b/configs/example/fs.py index 76b62a066..ec3be835a 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -34,6 +34,7 @@ m5.AddToPath('../common') from FSConfig import * from SysPaths import * from Benchmarks import * +import Simulation if not m5.build_env['FULL_SYSTEM']: m5.panic("This script requires full-system mode (ALPHA_FS).") @@ -48,40 +49,13 @@ parser.add_option("-b", "--benchmark", action="store", type="string", help="Specify the benchmark to run. Available benchmarks: %s"\ % DefinedBenchmarks) -# system options -parser.add_option("-d", "--detailed", action="store_true") -parser.add_option("-t", "--timing", action="store_true") -parser.add_option("-n", "--num_cpus", type="int", default=1) -parser.add_option("--caches", action="store_true") - -# Run duration options -parser.add_option("-m", "--maxtick", type="int") -parser.add_option("--maxtime", type="float") - # Metafile options parser.add_option("--etherdump", action="store", type="string", dest="etherdump", help="Specify the filename to dump a pcap capture of the" \ "ethernet traffic") -# Checkpointing options -###Note that performing checkpointing via python script files will override -###checkpoint instructions built into binaries. -parser.add_option("--take_checkpoints", action="store", type="string", - help="<M,N> will take checkpoint at cycle M and every N cycles \ - thereafter") -parser.add_option("--max_checkpoints", action="store", type="int", - help="the maximum number of checkpoints to drop", - default=5) -parser.add_option("--checkpoint_dir", action="store", type="string", - help="Place all checkpoints in this absolute directory") -parser.add_option("-r", "--checkpoint_restore", action="store", type="int", - help="restore from checkpoint <N>") -# CPU Switching - default switch model goes from a checkpoint -# to a timing simple CPU with caches to warm up, then to detailed CPU for -# data measurement -parser.add_option("-s", "--standard_switch", action="store_true", - help="switch from one cpu mode to another") +execfile("Options.py") (options, args) = parser.parse_args() @@ -89,14 +63,6 @@ if args: print "Error: script doesn't take any positional arguments" sys.exit(1) -class MyCache(BaseCache): - assoc = 2 - block_size = 64 - latency = 1 - mshrs = 10 - tgts_per_mshr = 5 - protocol = CoherenceProtocol(protocol='moesi') - # driver system CPU is always simple... note this is an assignment of # a class, not an instance. DriveCPUClass = AtomicSimpleCPU @@ -134,8 +100,8 @@ np = options.num_cpus test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] for i in xrange(np): if options.caches and not options.standard_switch: - test_sys.cpu[i].addPrivateSplitL1Caches(MyCache(size = '32kB'), - MyCache(size = '64kB')) + test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L2Cache(size = '64kB')) test_sys.cpu[i].connectMemPorts(test_sys.membus) test_sys.cpu[i].mem = test_sys.physmem @@ -151,129 +117,4 @@ else: print "Error I don't know how to create more than 2 systems." sys.exit(1) -if options.standard_switch: - switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i)) for i in xrange(np)] - switch_cpus1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i)) for i in xrange(np)] - for i in xrange(np): - switch_cpus[i].system = test_sys - switch_cpus1[i].system = test_sys - switch_cpus[i].clock = TestCPUClass.clock - switch_cpus1[i].clock = TestCPUClass.clock - if options.caches: - switch_cpus[i].addPrivateSplitL1Caches(MyCache(size = '32kB'), - MyCache(size = '64kB')) - - switch_cpus[i].mem = test_sys.physmem - switch_cpus1[i].mem = test_sys.physmem - switch_cpus[i].connectMemPorts(test_sys.membus) - root.switch_cpus = switch_cpus - root.switch_cpus1 = switch_cpus1 - switch_cpu_list = [(test_sys.cpu[i], switch_cpus[i]) for i in xrange(np)] - switch_cpu_list1 = [(switch_cpus[i], switch_cpus1[i]) for i in xrange(np)] - -m5.instantiate(root) - -if options.checkpoint_dir: - cptdir = options.checkpoint_dir -else: - cptdir = os.getcwd() - -if options.checkpoint_restore: - from os.path import isdir - from os import listdir, getcwd - import re - - if not isdir(cptdir): - m5.panic("checkpoint dir %s does not exist!" % cptdir) - - dirs = listdir(cptdir) - expr = re.compile('cpt.([0-9]*)') - cpts = [] - for dir in dirs: - match = expr.match(dir) - if match: - cpts.append(match.group(1)) - - cpts.sort(lambda a,b: cmp(long(a), long(b))) - - if options.checkpoint_restore > len(cpts): - m5.panic('Checkpoint %d not found' % options.checkpoint_restore) - - m5.restoreCheckpoint(root, "/".join([cptdir, "cpt.%s" % cpts[options.checkpoint_restore - 1]])) - -if options.standard_switch: - exit_event = m5.simulate(1000) - ## when you change to Timing (or Atomic), you halt the system given - ## as argument. When you are finished with the system changes - ## (including switchCpus), you must resume the system manually. - ## You DON'T need to resume after just switching CPUs if you haven't - ## changed anything on the system level. - m5.changeToTiming(test_sys) - m5.switchCpus(switch_cpu_list) - m5.resume(test_sys) - - exit_event = m5.simulate(500000000000) - m5.switchCpus(switch_cpu_list1) - -if options.maxtick: - maxtick = options.maxtick -elif options.maxtime: - simtime = int(options.maxtime * root.clock.value) - print "simulating for: ", simtime - maxtick = simtime -else: - maxtick = -1 - -num_checkpoints = 0 - -exit_cause = '' - -if options.take_checkpoints: - [when, period] = options.take_checkpoints.split(",", 1) - when = int(when) - period = int(period) - - exit_event = m5.simulate(when) - while exit_event.getCause() == "checkpoint": - exit_event = m5.simulate(when - m5.curTick()) - - if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - - sim_ticks = when - exit_cause = "maximum %d checkpoints dropped" % options.max_checkpoints - while num_checkpoints < options.max_checkpoints: - if (sim_ticks + period) > maxtick and maxtick != -1: - exit_event = m5.simulate(maxtick - sim_ticks) - exit_cause = exit_event.getCause() - break - else: - exit_event = m5.simulate(period) - sim_ticks += period - while exit_event.getCause() == "checkpoint": - exit_event = m5.simulate(period - m5.curTick()) - if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - -else: #no checkpoints being taken via this script - exit_event = m5.simulate(maxtick) - - while exit_event.getCause() == "checkpoint": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - if num_checkpoints == options.max_checkpoints: - exit_cause = "maximum %d checkpoints dropped" % options.max_checkpoints - break - - if maxtick == -1: - exit_event = m5.simulate(maxtick) - else: - exit_event = m5.simulate(maxtick - m5.curTick()) - - exit_cause = exit_event.getCause() - -if exit_cause == '': - exit_cause = exit_event.getCause() -print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause +Simulation.run(options, root, test_sys) diff --git a/configs/example/se.py b/configs/example/se.py index c4150eed7..e4fe93294 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -34,6 +34,7 @@ import m5 from m5.objects import * import os, optparse, sys m5.AddToPath('../common') +import Simulation parser = optparse.OptionParser() @@ -47,34 +48,7 @@ parser.add_option("-o", "--options", default="", parser.add_option("-i", "--input", default="", help="A file of input to give to the binary.") -# System options -parser.add_option("-d", "--detailed", action="store_true") -parser.add_option("-t", "--timing", action="store_true") -parser.add_option("--caches", action="store_true") - -# Run duration options -parser.add_option("-m", "--maxtick", type="int") -parser.add_option("--maxtime", type="float") - -#Checkpointing options -###Note that performing checkpointing via python script files will override -###checkpoint instructions built into binaries. -parser.add_option("--take_checkpoints", action="store", type="string", - help="<M,N> will take checkpoint at cycle M and every N cycles \ - thereafter") -parser.add_option("--max_checkpoints", action="store", type="int", - help="the maximum number of checkpoints to drop", - default=5) -parser.add_option("--checkpoint_dir", action="store", type="string", - help="Place all checkpoints in this absolute directory") -parser.add_option("-r", "--checkpoint_restore", action="store", type="int", - help="restore from checkpoint <N>") - -#CPU Switching - default switch model generally goes from a checkpoint -#to a timing simple CPU with caches to warm up, then to detailed CPU for -#data measurement -parser.add_option("-s", "--standard_switch", action="store_true", - help="switch from one cpu mode to another") +execfile("Options.py") (options, args) = parser.parse_args() @@ -82,13 +56,6 @@ if args: print "Error: script doesn't take any positional arguments" sys.exit(1) -class MyCache(BaseCache): - assoc = 2 - block_size = 64 - latency = 1 - mshrs = 10 - tgts_per_mshr = 5 - process = LiveProcess() process.executable = options.cmd process.cmd = options.cmd + " " + options.options @@ -117,160 +84,33 @@ if options.detailed: if options.timing: - cpu = TimingSimpleCPU() + CPUClass = TimingSimpleCPU + test_mem_mode = 'timing' elif options.detailed: - cpu = DerivO3CPU() + CPUClass = DerivO3CPU + test_mem_mode = 'timing' else: - cpu = AtomicSimpleCPU() + CPUClass = AtomicSimpleCPU + test_mem_mode = 'atomic' -cpu.workload = process -cpu.cpu_id = 0 +CPUClass.clock = '2GHz' -system = System(cpu = cpu, - physmem = PhysicalMemory(range=AddrRange("512MB")), - membus = Bus()) +np = options.num_cpus -if options.caches and not options.standard_switch: - system.cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'), - MyCache(size = '64kB')) +system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], + physmem = PhysicalMemory(range=AddrRange("512MB")), + membus = Bus(), mem_mode = test_mem_mode) system.physmem.port = system.membus.port -system.cpu.connectMemPorts(system.membus) -system.cpu.mem = system.physmem -system.cpu.clock = '2GHz' -root = Root(system = system) - -if options.timing or options.detailed: - root.system.mem_mode = 'timing' - -if options.standard_switch: - switch_cpu = TimingSimpleCPU(defer_registration=True, cpu_id=1) - switch_cpu1 = DerivO3CPU(defer_registration=True, cpu_id=2) - switch_cpu.system = system - switch_cpu1.system = system - switch_cpu.clock = cpu.clock - switch_cpu1.clock = cpu.clock - if options.caches: - switch_cpu.addPrivateSplitL1Caches(MyCache(size = '32kB'), - MyCache(size = '64kB')) - - switch_cpu.workload = process - switch_cpu1.workload = process - switch_cpu.mem = system.physmem - switch_cpu1.mem = system.physmem - switch_cpu.connectMemPorts(system.membus) - root.switch_cpu = switch_cpu - root.switch_cpu1 = switch_cpu1 - switch_cpu_list = [(system.cpu, switch_cpu)] - switch_cpu_list1 = [(switch_cpu, switch_cpu1)] - -# instantiate configuration -m5.instantiate(root) - -if options.checkpoint_dir: - cptdir = options.checkpoint_dir -else: - cptdir = os.getcwd() - -if options.checkpoint_restore: - from os.path import isdir - from os import listdir, getcwd - import re - - if not isdir(cptdir): - m5.panic("checkpoint dir %s does not exist!" % cptdir) - - dirs = listdir(cptdir) - expr = re.compile('cpt.([0-9]*)') - cpts = [] - for dir in dirs: - match = expr.match(dir) - if match: - cpts.append(match.group(1)) - - cpts.sort(lambda a,b: cmp(long(a), long(b))) - if options.checkpoint_restore > len(cpts): - m5.panic('Checkpoint %d not found' % options.checkpoint_restore) - - print "restoring checkpoint from ","/".join([cptdir, "cpt.%s" % cpts[options.checkpoint_restore - 1]]) - m5.restoreCheckpoint(root, "/".join([cptdir, "cpt.%s" % cpts[options.checkpoint_restore - 1]])) - -if options.standard_switch: - exit_event = m5.simulate(10000) - ## when you change to Timing (or Atomic), you halt the system given - ## as argument. When you are finished with the system changes - ## (including switchCpus), you must resume the system manually. - ## You DON'T need to resume after just switching CPUs if you haven't - ## changed anything on the system level. - m5.changeToTiming(system) - m5.switchCpus(switch_cpu_list) - m5.resume(system) - - exit_event = m5.simulate(500000000000) - m5.switchCpus(switch_cpu_list1) - -if options.maxtick: - maxtick = options.maxtick -elif options.maxtime: - simtime = int(options.maxtime * root.clock.value) - print "simulating for: ", simtime - maxtick = simtime -else: - maxtick = -1 - -num_checkpoints = 0 - -exit_cause = '' - -if options.take_checkpoints: - [when, period] = options.take_checkpoints.split(",", 1) - when = int(when) - period = int(period) - - exit_event = m5.simulate(when) - while exit_event.getCause() == "checkpoint": - exit_event = m5.simulate(when - m5.curTick()) - - if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - - sim_ticks = when - exit_cause = "maximum %d checkpoints dropped" % options.max_checkpoints - while num_checkpoints < options.max_checkpoints: - if (sim_ticks + period) > maxtick and maxtick != -1: - exit_event = m5.simulate(maxtick - sim_ticks) - exit_cause = exit_event.getCause() - break - else: - exit_event = m5.simulate(period) - sim_ticks += period - while exit_event.getCause() == "checkpoint": - exit_event = m5.simulate(period - m5.curTick()) - if exit_event.getCause() == "simulate() limit reached": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - -else: #no checkpoints being taken via this script - exit_event = m5.simulate(maxtick) - - while exit_event.getCause() == "checkpoint": - m5.checkpoint(root, cptdir + "cpt.%d") - num_checkpoints += 1 - if num_checkpoints == options.max_checkpoints: - exit_cause = "maximum %d checkpoints dropped" % options.max_checkpoints - break - - if maxtick == -1: - exit_event = m5.simulate(maxtick) - else: - exit_event = m5.simulate(maxtick - m5.curTick()) - - exit_cause = exit_event.getCause() - -if exit_cause == '': - exit_cause = exit_event.getCause() -print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause +for i in xrange(np): + if options.caches and not options.standard_switch: + system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L2Cache(size = '64kB')) + system.cpu[i].connectMemPorts(system.membus) + system.cpu[i].mem = system.physmem + system.cpu[i].workload = process +root = Root(system = system) +Simulation.run(options, root, system) diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index e52a3e73d..7fc68f4e7 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -38,6 +38,7 @@ #include "base/inet.hh" #include "dev/i8254xGBe.hh" #include "mem/packet.hh" +#include "mem/packet_access.hh" #include "sim/builder.hh" #include "sim/stats.hh" #include "sim/system.hh" @@ -66,12 +67,17 @@ IGbE::IGbE(Params *p) regs.tctl.reg = 0; regs.manc.reg = 0; + regs.pba.rxa = 0x30; + regs.pba.txa = 0x10; + eeOpBits = 0; eeAddrBits = 0; eeDataBits = 0; eeOpcode = 0; - memset(&flash, 0, EEPROM_SIZE); + // clear all 64 16 bit words of the eeprom + memset(&flash, 0, EEPROM_SIZE*2); + // Magic happy checksum value flash[0] = 0xBABA; } @@ -108,7 +114,7 @@ IGbE::read(PacketPtr pkt) // Only 32bit accesses allowed assert(pkt->getSize() == 4); - DPRINTF(Ethernet, "Read device register %#X\n", daddr); + //DPRINTF(Ethernet, "Read device register %#X\n", daddr); pkt->allocate(); @@ -116,6 +122,7 @@ IGbE::read(PacketPtr pkt) /// Handle read of register here /// + switch (daddr) { case CTRL: pkt->set<uint32_t>(regs.ctrl.reg); @@ -141,11 +148,23 @@ IGbE::read(PacketPtr pkt) case TCTL: pkt->set<uint32_t>(regs.tctl.reg); break; + case PBA: + pkt->set<uint32_t>(regs.pba.reg); + break; + case WUC: + case LEDCTL: + pkt->set<uint32_t>(0); // We don't care, so just return 0 + break; case MANC: pkt->set<uint32_t>(regs.manc.reg); break; default: - panic("Read request to unknown register number: %#x\n", daddr); + if (!(daddr >= VFTA && daddr < (VFTA + VLAN_FILTER_TABLE_SIZE)*4) && + !(daddr >= RAL && daddr < (RAL + RCV_ADDRESS_TABLE_SIZE)*4) && + !(daddr >= MTA && daddr < (MTA + MULTICAST_TABLE_SIZE)*4)) + pkt->set<uint32_t>(0); + else + panic("Read request to unknown register number: %#x\n", daddr); }; pkt->result = Packet::Success; @@ -168,7 +187,7 @@ IGbE::write(PacketPtr pkt) // Only 32bit accesses allowed assert(pkt->getSize() == sizeof(uint32_t)); - DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", daddr, pkt->get<uint32_t>()); + //DPRINTF(Ethernet, "Wrote device register %#X value %#X\n", daddr, pkt->get<uint32_t>()); /// /// Handle write of register here @@ -195,10 +214,10 @@ IGbE::write(PacketPtr pkt) eeAddr = eeAddr << 1 | regs.eecd.din; eeAddrBits++; } else if (eeDataBits < 16 && eeOpcode == EEPROM_READ_OPCODE_SPI) { - assert(eeAddr < EEPROM_SIZE); - DPRINTF(Ethernet, "EEPROM bit read: %d word: %#X\n", - flash[eeAddr] >> eeDataBits & 0x1, flash[eeAddr]); - regs.eecd.dout = (flash[eeAddr] >> eeDataBits) & 0x1; + assert(eeAddr>>1 < EEPROM_SIZE); + DPRINTF(EthernetEEPROM, "EEPROM bit read: %d word: %#X\n", + flash[eeAddr>>1] >> eeDataBits & 0x1, flash[eeAddr>>1]); + regs.eecd.dout = (flash[eeAddr>>1] >> (15-eeDataBits)) & 0x1; eeDataBits++; } else if (eeDataBits < 8 && eeOpcode == EEPROM_RDSR_OPCODE_SPI) { regs.eecd.dout = 0; @@ -219,8 +238,9 @@ IGbE::write(PacketPtr pkt) eeAddr = 0; } - DPRINTF(Ethernet, "EEPROM: opcode: %#X:%d\n", - (uint32_t)eeOpcode, (uint32_t) eeOpBits); + DPRINTF(EthernetEEPROM, "EEPROM: opcode: %#X:%d addr: %#X:%d\n", + (uint32_t)eeOpcode, (uint32_t) eeOpBits, + (uint32_t)eeAddr>>1, (uint32_t)eeAddrBits); if (eeOpBits == 8 && !(eeOpcode == EEPROM_READ_OPCODE_SPI || eeOpcode == EEPROM_RDSR_OPCODE_SPI )) panic("Unknown eeprom opcode: %#X:%d\n", (uint32_t)eeOpcode, @@ -246,11 +266,22 @@ IGbE::write(PacketPtr pkt) case TCTL: regs.tctl.reg = val; break; + case PBA: + regs.pba.rxa = val; + regs.pba.txa = 64 - regs.pba.rxa; + break; + case WUC: + case LEDCTL: + ; // We don't care, so don't store anything + break; case MANC: regs.manc.reg = val; break; default: - panic("Write request to unknown register number: %#x\n", daddr); + if (!(daddr >= VFTA && daddr < (VFTA + VLAN_FILTER_TABLE_SIZE)*4) && + !(daddr >= RAL && daddr < (RAL + RCV_ADDRESS_TABLE_SIZE)*4) && + !(daddr >= MTA && daddr < (MTA + MULTICAST_TABLE_SIZE)*4)) + panic("Write request to unknown register number: %#x\n", daddr); }; pkt->result = Packet::Success; |