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-rw-r--r--src/cpu/checker/cpu_impl.hh6
-rw-r--r--src/cpu/inorder/cpu.cc8
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc12
-rw-r--r--src/cpu/inorder/thread_context.cc6
-rw-r--r--src/cpu/inorder/thread_state.hh14
-rw-r--r--src/cpu/o3/commit_impl.hh18
-rw-r--r--src/cpu/o3/cpu.cc10
-rw-r--r--src/cpu/o3/dyn_inst.hh6
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh18
-rwxr-xr-xsrc/cpu/o3/thread_context.hh10
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh40
-rw-r--r--src/cpu/o3/thread_state.hh13
-rw-r--r--src/cpu/ozone/back_end_impl.hh8
-rw-r--r--src/cpu/ozone/cpu_impl.hh26
-rw-r--r--src/cpu/ozone/dyn_inst_impl.hh12
-rw-r--r--src/cpu/ozone/inorder_back_end_impl.hh24
-rw-r--r--src/cpu/ozone/lw_back_end_impl.hh18
-rw-r--r--src/cpu/ozone/thread_state.hh6
18 files changed, 128 insertions, 127 deletions
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 5637eb08b..49ff8eaa1 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -573,12 +573,12 @@ Checker<Impl>::validateState()
"registers from main CPU", curTick(), unverifiedInst->instAddr());
// Terribly convoluted way to make sure O3 model does not implode
- bool inSyscall = unverifiedInst->thread->inSyscall;
- unverifiedInst->thread->inSyscall = true;
+ bool no_squash_from_TC = unverifiedInst->thread->noSquashFromTC;
+ unverifiedInst->thread->noSquashFromTC = true;
// Heavy-weight copying of all registers
thread->copyArchRegs(unverifiedInst->tcBase());
- unverifiedInst->thread->inSyscall = inSyscall;
+ unverifiedInst->thread->noSquashFromTC = no_squash_from_TC;
// Set curStaticInst to unverifiedInst->staticInst
curStaticInst = unverifiedInst->staticInst;
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 3dad7d1f4..5815775f9 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -786,9 +786,9 @@ InOrderCPU::init()
BaseCPU::init();
for (ThreadID tid = 0; tid < numThreads; ++tid) {
- // Set inSyscall so that the CPU doesn't squash when initially
+ // Set noSquashFromTC so that the CPU doesn't squash when initially
// setting up registers.
- thread[tid]->inSyscall = true;
+ thread[tid]->noSquashFromTC = true;
// Initialise the ThreadContext's memory proxies
thread[tid]->initMemProxies(thread[tid]->getTC());
}
@@ -800,9 +800,9 @@ InOrderCPU::init()
}
}
- // Clear inSyscall.
+ // Clear noSquashFromTC.
for (ThreadID tid = 0; tid < numThreads; ++tid)
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
// Call Initializiation Routine for Resource Pool
resPool->init();
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index 760c63948..dcf0ce6ae 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -220,12 +220,12 @@ InOrderDynInst::execute()
// when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
// the TC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->execute(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
@@ -244,12 +244,12 @@ InOrderDynInst::initiateAcc()
// when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
// the TC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->initiateAcc(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index 16ffd5b0f..b8662ef4c 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -90,10 +90,10 @@ InOrderThreadContext::takeOverFrom(ThreadContext *old_context)
copyArchRegs(old_context);
thread->funcExeInst = old_context->readFuncExeInst();
-
+
old_context->setStatus(ThreadContext::Halted);
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
thread->trapPending = false;
}
@@ -159,7 +159,7 @@ InOrderThreadContext::serialize(std::ostream &os)
void
InOrderThreadContext::unserialize(Checkpoint *cp, const std::string &section)
{
- panic("unserialize unimplemented");
+ panic("unserialize unimplemented");
}
diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh
index 34c146b42..4472bf1dd 100644
--- a/src/cpu/inorder/thread_state.hh
+++ b/src/cpu/inorder/thread_state.hh
@@ -61,10 +61,15 @@ class InOrderThreadState : public ThreadState {
InOrderCPU *cpu;
public:
- /** Whether or not the thread is currently in syscall mode, and
- * thus able to be externally updated without squashing.
+ /* This variable controls if writes to a thread context should cause a all
+ * dynamic/speculative state to be thrown away. Nominally this is the
+ * desired behavior because the external thread context write has updated
+ * some state that could be used by an inflight instruction, however there
+ * are some cases like in a fault/trap handler where this behavior would
+ * lead to successive restarts and forward progress couldn't be made. This
+ * variable controls if the squashing will occur.
*/
- bool inSyscall;
+ bool noSquashFromTC;
/** Whether or not the thread is currently waiting on a trap, and
* thus able to be externally updated without squashing.
@@ -75,7 +80,8 @@ class InOrderThreadState : public ThreadState {
Process *_process)
: ThreadState(reinterpret_cast<BaseCPU*>(_cpu), _thread_num,
_process),
- cpu(_cpu), inSyscall(0), trapPending(0), lastGradIsBranch(false)
+ cpu(_cpu), noSquashFromTC(false), trapPending(false),
+ lastGradIsBranch(false)
{ }
/** Handles the syscall. */
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index f6c868720..351b4794d 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -559,7 +559,7 @@ DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
thread[tid]->trapPending = false;
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
trapInFlight[tid] = false;
trapSquash[tid] = false;
@@ -576,7 +576,7 @@ DefaultCommit<Impl>::squashFromTC(ThreadID tid)
DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
assert(!thread[tid]->trapPending);
commitStatus[tid] = ROBSquashing;
@@ -721,8 +721,8 @@ DefaultCommit<Impl>::handleInterrupt()
// Clear the interrupt now that it's going to be handled
toIEW->commitInfo[0].clearInterrupt = true;
- assert(!thread[0]->inSyscall);
- thread[0]->inSyscall = true;
+ assert(!thread[0]->noSquashFromTC);
+ thread[0]->noSquashFromTC = true;
if (cpu->checker) {
cpu->checker->handlePendingInt();
@@ -731,7 +731,7 @@ DefaultCommit<Impl>::handleInterrupt()
// CPU will handle interrupt.
cpu->processInterrupts(interrupt);
- thread[0]->inSyscall = false;
+ thread[0]->noSquashFromTC = false;
commitStatus[0] = TrapPending;
@@ -1014,7 +1014,7 @@ DefaultCommit<Impl>::commitInsts()
Addr oldpc;
// Debug statement. Checks to make sure we're not
// currently updating state while handling PC events.
- assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
+ assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
do {
oldpc = pc[tid].instAddr();
cpu->system->pcEventQueue.service(thread[tid]->getTC());
@@ -1140,11 +1140,11 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
cpu->checker->verify(head_inst);
}
- assert(!thread[tid]->inSyscall);
+ assert(!thread[tid]->noSquashFromTC);
// Mark that we're in state update mode so that the trap's
// execution doesn't generate extra squashes.
- thread[tid]->inSyscall = true;
+ thread[tid]->noSquashFromTC = true;
// Execute the trap. Although it's slightly unrealistic in
// terms of timing (as it doesn't wait for the full timing of
@@ -1155,7 +1155,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
cpu->trap(inst_fault, tid, head_inst->staticInst);
// Exit state update mode to avoid accidental updating.
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
commitStatus[tid] = TrapPending;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index bc5f096e6..c5421302d 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -644,9 +644,9 @@ FullO3CPU<Impl>::init()
BaseCPU::init();
for (ThreadID tid = 0; tid < numThreads; ++tid) {
- // Set inSyscall so that the CPU doesn't squash when initially
+ // Set noSquashFromTC so that the CPU doesn't squash when initially
// setting up registers.
- thread[tid]->inSyscall = true;
+ thread[tid]->noSquashFromTC = true;
// Initialise the ThreadContext's memory proxies
thread[tid]->initMemProxies(thread[tid]->getTC());
}
@@ -665,9 +665,9 @@ FullO3CPU<Impl>::init()
}
}
- // Clear inSyscall.
+ // Clear noSquashFromTC.
for (int tid = 0; tid < numThreads; ++tid)
- thread[tid]->inSyscall = false;
+ thread[tid]->noSquashFromTC = false;
// Initialize stages.
fetch.initStage();
@@ -1464,7 +1464,7 @@ template <class Impl>
void
FullO3CPU<Impl>::squashFromTC(ThreadID tid)
{
- this->thread[tid]->inSyscall = true;
+ this->thread[tid]->noSquashFromTC = true;
this->commit.generateTCEvent(tid);
}
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index b5344f875..de50bbda9 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -183,14 +183,14 @@ class BaseO3DynInst : public BaseDynInst<Impl>
// using the TC during an instruction's execution (specifically for
// instructions that have side-effects that use the TC). Fix this.
// See cpu/o3/dyn_inst_impl.hh.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
for (int i = 0; i < _numDestMiscRegs; i++)
this->cpu->setMiscReg(
_destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
}
void forwardOldRegs()
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 7f8d5a030..e37caf7f0 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -130,12 +130,12 @@ BaseO3DynInst<Impl>::execute()
// when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
// the TC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->execute(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
@@ -148,12 +148,12 @@ BaseO3DynInst<Impl>::initiateAcc()
// when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
// the TC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->initiateAcc(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
@@ -166,8 +166,8 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
// when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
// the TC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
if (this->cpu->checker) {
if (this->isStoreConditional()) {
@@ -177,7 +177,7 @@ BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 520f07b0f..c6fa178b5 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -257,6 +257,16 @@ class O3ThreadContext : public ThreadContext
{
return this->thread->quiesceEvent;
}
+ /** check if the cpu is currently in state update mode and squash if not.
+ * This function will return true if a trap is pending or if a fault or
+ * similar is currently writing to the thread context and doesn't want
+ * reset all the state (see noSquashFromTC).
+ */
+ inline void conditionalSquash()
+ {
+ if (!thread->trapPending && !thread->noSquashFromTC)
+ cpu->squashFromTC(thread->threadId());
+ }
};
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 8a8ee636a..38e7c5dec 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -96,7 +96,7 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
old_context->setStatus(ThreadContext::Halted);
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
thread->trapPending = false;
}
@@ -207,9 +207,9 @@ void
O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
{
// Prevent squashing
- thread->inSyscall = true;
+ thread->noSquashFromTC = true;
TheISA::copyRegs(tc, this);
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
if (!FullSystem)
this->thread->funcExeInst = tc->readFuncExeInst();
@@ -253,10 +253,7 @@ O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
cpu->setArchIntReg(reg_idx, val, thread->threadId());
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
+ conditionalSquash();
}
template <class Impl>
@@ -266,9 +263,7 @@ O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
cpu->setArchFloatReg(reg_idx, val, thread->threadId());
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
+ conditionalSquash();
}
template <class Impl>
@@ -278,10 +273,7 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
+ conditionalSquash();
}
template <class Impl>
@@ -290,10 +282,7 @@ O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
{
cpu->pcState(val, thread->threadId());
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
+ conditionalSquash();
}
template <class Impl>
@@ -302,10 +291,7 @@ O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
{
cpu->pcState(val, thread->threadId());
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
+ conditionalSquash();
}
template <class Impl>
@@ -328,10 +314,7 @@ O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
+ conditionalSquash();
}
template <class Impl>
@@ -340,9 +323,6 @@ O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
{
cpu->setMiscReg(misc_reg, val, thread->threadId());
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->threadId());
- }
+ conditionalSquash();
}
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 9273b00da..96ccfc95c 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -61,10 +61,15 @@ struct O3ThreadState : public ThreadState {
/** Pointer to the CPU. */
O3CPU *cpu;
public:
- /** Whether or not the thread is currently in syscall mode, and
- * thus able to be externally updated without squashing.
+ /* This variable controls if writes to a thread context should cause a all
+ * dynamic/speculative state to be thrown away. Nominally this is the
+ * desired behavior because the external thread context write has updated
+ * some state that could be used by an inflight instruction, however there
+ * are some cases like in a fault/trap handler where this behavior would
+ * lead to successive restarts and forward progress couldn't be made. This
+ * variable controls if the squashing will occur.
*/
- bool inSyscall;
+ bool noSquashFromTC;
/** Whether or not the thread is currently waiting on a trap, and
* thus able to be externally updated without squashing.
@@ -73,7 +78,7 @@ struct O3ThreadState : public ThreadState {
O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
: ThreadState(_cpu, _thread_num, _process),
- cpu(_cpu), inSyscall(0), trapPending(0)
+ cpu(_cpu), noSquashFromTC(false), trapPending(false)
{
if (!FullSystem)
return;
diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh
index 9c9ca311e..bcc897369 100644
--- a/src/cpu/ozone/back_end_impl.hh
+++ b/src/cpu/ozone/back_end_impl.hh
@@ -1513,16 +1513,16 @@ BackEnd<Impl>::commitInst(int inst_num)
DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
inst->seqNum, inst->readPC());
-// assert(!thread->inSyscall);
+// assert(!thread->noSquashFromTC);
-// thread->inSyscall = true;
+// thread->noSquashFromTC = true;
// Consider holding onto the trap and waiting until the trap event
// happens for this to be executed.
inst_fault->invoke(thread->getXCProxy());
// Exit state update mode to avoid accidental updating.
-// thread->inSyscall = false;
+// thread->noSquashFromTC = false;
// commitStatus = TrapPending;
@@ -1571,7 +1571,7 @@ BackEnd<Impl>::commitInst(int inst_num)
Addr oldpc;
do {
if (count == 0)
- assert(!thread->inSyscall && !thread->trapPending);
+ assert(!thread->noSquashFromTC && !thread->trapPending);
oldpc = thread->readPC();
cpu->system->pcEventQueue.service(
thread->getXCProxy());
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 3a32c07c6..fe8ae2551 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -110,7 +110,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
ozoneTC.cpu = this;
ozoneTC.thread = &thread;
- thread.inSyscall = false;
+ thread.noSquashFromTC = false;
itb = p->itb;
dtb = p->dtb;
@@ -236,7 +236,7 @@ OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
BaseCPU::takeOverFrom(oldCPU);
thread.trapPending = false;
- thread.inSyscall = false;
+ thread.noSquashFromTC = false;
backEnd->takeOverFrom();
frontEnd->takeOverFrom();
@@ -375,7 +375,7 @@ OzoneCPU<Impl>::init()
BaseCPU::init();
// Mark this as in syscall so it won't need to squash
- thread.inSyscall = true;
+ thread.noSquashFromTC = true;
if (FullSystem) {
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
@@ -387,7 +387,7 @@ OzoneCPU<Impl>::init()
frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable);
- thread.inSyscall = false;
+ thread.noSquashFromTC = false;
}
template <class Impl>
@@ -476,7 +476,7 @@ template <class Impl>
void
OzoneCPU<Impl>::squashFromTC()
{
- thread.inSyscall = true;
+ thread.noSquashFromTC = true;
backEnd->generateTCEvent();
}
@@ -487,7 +487,7 @@ OzoneCPU<Impl>::syscall(uint64_t &callnum)
// Not sure this copy is needed, depending on how the TC proxy is made.
thread.renameTable.copyFrom(backEnd->renameTable);
- thread.inSyscall = true;
+ thread.noSquashFromTC = true;
thread.funcExeInst++;
@@ -497,7 +497,7 @@ OzoneCPU<Impl>::syscall(uint64_t &callnum)
thread.funcExeInst--;
- thread.inSyscall = false;
+ thread.noSquashFromTC = false;
frontEnd->renameTable.copyFrom(thread.renameTable);
backEnd->renameTable.copyFrom(thread.renameTable);
@@ -774,7 +774,7 @@ OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
{
thread->renameTable[reg_idx]->setIntResult(val);
- if (!thread->inSyscall) {
+ if (!thread->noSquashFromTC) {
cpu->squashFromTC();
}
}
@@ -787,7 +787,7 @@ OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
thread->renameTable[idx]->setDoubleResult(val);
- if (!thread->inSyscall) {
+ if (!thread->noSquashFromTC) {
cpu->squashFromTC();
}
}
@@ -806,7 +806,7 @@ OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
thread->PC = val;
cpu->frontEnd->setPC(val);
- if (!thread->inSyscall) {
+ if (!thread->noSquashFromTC) {
cpu->squashFromTC();
}
}
@@ -818,7 +818,7 @@ OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
thread->nextPC = val;
cpu->frontEnd->setNextPC(val);
- if (!thread->inSyscall) {
+ if (!thread->noSquashFromTC) {
cpu->squashFromTC();
}
}
@@ -844,7 +844,7 @@ OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
// Needs to setup a squash event unless we're in syscall mode
thread->miscRegFile.setRegNoEffect(misc_reg, val);
- if (!thread->inSyscall) {
+ if (!thread->noSquashFromTC) {
cpu->squashFromTC();
}
}
@@ -856,7 +856,7 @@ OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
// Needs to setup a squash event unless we're in syscall mode
thread->miscRegFile.setReg(misc_reg, val, this);
- if (!thread->inSyscall) {
+ if (!thread->noSquashFromTC) {
cpu->squashFromTC();
}
}
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 96d326ffc..2066c58d7 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -71,12 +71,12 @@ OzoneDynInst<Impl>::execute()
// @todo: Pretty convoluted way to avoid squashing from happening when using
// the XC during an instruction's execution (specifically for instructions
// that have sideeffects that use the XC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->execute(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
@@ -88,12 +88,12 @@ OzoneDynInst<Impl>::initiateAcc()
// @todo: Pretty convoluted way to avoid squashing from happening when using
// the XC during an instruction's execution (specifically for instructions
// that have sideeffects that use the XC). Fix this.
- bool in_syscall = this->thread->inSyscall;
- this->thread->inSyscall = true;
+ bool no_squash_from_TC = this->thread->noSquashFromTC;
+ this->thread->noSquashFromTC = true;
this->fault = this->staticInst->initiateAcc(this, this->traceData);
- this->thread->inSyscall = in_syscall;
+ this->thread->noSquashFromTC = no_squash_from_TC;
return this->fault;
}
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 59d1dab0d..7bb876e4a 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -117,7 +117,7 @@ InorderBackEnd<Impl>::checkInterrupts()
}
if (ipl && ipl > thread->readMiscRegNoEffect(IPR_IPLR)) {
- thread->inSyscall = true;
+ thread->noSquashFromTC = true;
thread->setMiscRegNoEffect(IPR_ISR, summary);
thread->setMiscRegNoEffect(IPR_INTID, ipl);
@@ -128,7 +128,7 @@ InorderBackEnd<Impl>::checkInterrupts()
// May need to go 1 inst prior
squashPending = true;
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
setSquashInfoFromXC();
}
@@ -206,7 +206,7 @@ InorderBackEnd<Impl>::executeInsts()
Addr oldpc;
do {
if (count == 0)
- assert(!thread->inSyscall && !thread->trapPending);
+ assert(!thread->noSquashFromTC && !thread->trapPending);
oldpc = thread->readPC();
cpu->system->pcEventQueue.service(
thread->getXCProxy());
@@ -291,16 +291,16 @@ InorderBackEnd<Impl>::executeInsts()
DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n",
inst->seqNum, inst->readPC());
- assert(!thread->inSyscall);
+ assert(!thread->noSquashFromTC);
- thread->inSyscall = true;
+ thread->noSquashFromTC = true;
// Consider holding onto the trap and waiting until the trap event
// happens for this to be executed.
inst_fault->invoke(xc);
// Exit state update mode to avoid accidental updating.
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
squashPending = true;
@@ -365,16 +365,16 @@ InorderBackEnd<Impl>::handleFault()
{
DPRINTF(Commit, "Handling fault from fetch\n");
- assert(!thread->inSyscall);
+ assert(!thread->noSquashFromTC);
- thread->inSyscall = true;
+ thread->noSquashFromTC = true;
// Consider holding onto the trap and waiting until the trap event
// happens for this to be executed.
faultFromFetch->invoke(xc);
// Exit state update mode to avoid accidental updating.
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
squashPending = true;
@@ -415,8 +415,8 @@ InorderBackEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC)
squashPending = false;
// Probably want to make sure that this squash is the one that set the
- // thread into inSyscall mode.
- thread->inSyscall = false;
+ // thread into noSquashFromTC mode.
+ thread->noSquashFromTC = false;
// Tell front end to squash, reset PC to new one.
frontEnd->squash(squash_num, next_PC);
@@ -431,7 +431,7 @@ InorderBackEnd<Impl>::squashFromXC()
// Record that I need to squash
squashPending = true;
- thread->inSyscall = true;
+ thread->noSquashFromTC = true;
}
template <class Impl>
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index cd23293b4..79ae43465 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -531,8 +531,8 @@ LWBackEnd<Impl>::checkInterrupts()
// Not sure which thread should be the one to interrupt. For now
// always do thread 0.
- assert(!thread->inSyscall);
- thread->inSyscall = true;
+ assert(!thread->noSquashFromTC);
+ thread->noSquashFromTC = true;
// CPU will handle implementation of the interrupt.
cpu->processInterrupts();
@@ -541,7 +541,7 @@ LWBackEnd<Impl>::checkInterrupts()
commitStatus = TrapPending;
// Exit state update mode to avoid accidental updating.
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
// Generate trap squash event.
generateTrapEvent();
@@ -559,16 +559,16 @@ LWBackEnd<Impl>::handleFault(Fault &fault, Tick latency)
{
DPRINTF(BE, "Handling fault!\n");
- assert(!thread->inSyscall);
+ assert(!thread->noSquashFromTC);
- thread->inSyscall = true;
+ thread->noSquashFromTC = true;
// Consider holding onto the trap and waiting until the trap event
// happens for this to be executed.
fault->invoke(thread->getTC());
// Exit state update mode to avoid accidental updating.
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
commitStatus = TrapPending;
@@ -1205,7 +1205,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
Addr oldpc;
do {
if (count == 0)
- assert(!thread->inSyscall && !thread->trapPending);
+ assert(!thread->noSquashFromTC && !thread->trapPending);
oldpc = thread->readPC();
cpu->system->pcEventQueue.service(
thread->getTC());
@@ -1357,7 +1357,7 @@ LWBackEnd<Impl>::squashFromTC()
frontEnd->interruptPending = false;
thread->trapPending = false;
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
tcSquash = false;
commitStatus = Running;
}
@@ -1373,7 +1373,7 @@ LWBackEnd<Impl>::squashFromTrap()
frontEnd->interruptPending = false;
thread->trapPending = false;
- thread->inSyscall = false;
+ thread->noSquashFromTC = false;
trapSquash = false;
commitStatus = Running;
}
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index 98ecd850c..0c03155b8 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -65,7 +65,7 @@ struct OzoneThreadState : public ThreadState {
OzoneThreadState(CPUType *_cpu, int _thread_num)
: ThreadState(_cpu, -1, _thread_num),
- intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0)
+ intrflag(0), cpu(_cpu), noSquashFromTC(false), trapPending(false)
{
if (cpu->params->profile) {
profile = new FunctionProfile(cpu->params->system->kernelSymtab);
@@ -85,7 +85,7 @@ struct OzoneThreadState : public ThreadState {
OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process)
: ThreadState(_cpu, -1, _thread_num, _process),
- cpu(_cpu), inSyscall(0), trapPending(0)
+ cpu(_cpu), noSquashFromTC(false), trapPending(false)
{
miscRegFile.clear();
}
@@ -102,7 +102,7 @@ struct OzoneThreadState : public ThreadState {
typename Impl::CPUType *cpu;
- bool inSyscall;
+ bool noSquashFromTC;
bool trapPending;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 03:04:48 +0000