diff options
635 files changed, 34767 insertions, 19076 deletions
diff --git a/RELEASE_NOTES b/RELEASE_NOTES index 1c781ac29..e91f5432d 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -1,32 +1,37 @@ Outstanding issues for 2.0 release: -------------------- -1. Better statistics for the caches. -2. Clean up more SimObject parameter stuff -3. Checkpoint/switchover testing -4. FS mode doesn't work under Cygwin -5. memtest regression crashes under Cygwin -6. Make repository public -7. Testing -8. Validation -9. Testing +1. Fix multi-level coherence/dma issues +2. Fix O3 CPU bug in SE 40.perlbmk fails +3. Fix O3 processing nacks/coherence messages +4. Better statistics for the caches. +5. Clean up more SimObject parameter stuff +6. Checkpoint/switchover testing +7. FS mode doesn't work under Cygwin +8. memtest regression crashes under Cygwin +9. Make repository public +10. Testing +11. Validation +12. Testing -May XX, 2007: m5_2.0_beta3 +May 16, 2007: m5_2.0_beta3 -------------------- New Features 1. Some support for SPARC full-system simulation +2. Reworking of trace facitities (parameter names changed, variadic macros + removed) +3. Scons script cleanups +4. Some support for compiling with Intel CC Bug fixes since beta 2: 1. Many SPARC linux syscall emulation support fixes 2. Multiprocessor linux boot using the detailed O3 CPU module -3. Simulator performance and memory leak fixes -4. Fixed issue where console could stop printing in ALPHA_FS -5. Fix issues with remote debugging -6. Several compile fixes, including gcc 4.1 -7. Reworking of trace facitities (parameter names changed, variadic macros removed) -8. Scons script cleanups -9. Some support for compiling with Intel CC -10. Many other minor fixes and enhancements - +3. Workaround for DMA bug (final solution to be released with 2.0f) +4. Simulator performance and memory leak fixes +5. Fixed issue where console could stop printing in ALPHA_FS +6. Fix issues with remote debugging +7. Several compile fixes, including gcc 4.1 +8. Many other minor fixes and enhancements + Nov. 28, 2006: m5_2.0_beta2 -------------------- Bug fixes since beta 1: diff --git a/SConstruct b/SConstruct index a6659fe9b..fa2366963 100644 --- a/SConstruct +++ b/SConstruct @@ -182,7 +182,6 @@ for t in abs_targets: env = Environment(ENV = os.environ, # inherit user's environment vars ROOT = ROOT, SRCDIR = SRCDIR) -Export('env') #Parse CC/CXX early so that we use the correct compiler for # to test for dependencies/versions/libraries/includes @@ -192,6 +191,8 @@ if ARGUMENTS.get('CC', None): if ARGUMENTS.get('CXX', None): env['CXX'] = ARGUMENTS.get('CXX') +Export('env') + env.SConsignFile(joinpath(build_root,"sconsign")) # Default duplicate option is to use hard links, but this messes up @@ -269,16 +270,29 @@ if compare_versions(swig_version[2], min_swig_version) < 0: Exit(1) # Set up SWIG flags & scanner -env.Append(SWIGFLAGS=Split('-c++ -python -modern $_CPPINCFLAGS')) +swig_flags=Split('-c++ -python -modern -templatereduce $_CPPINCFLAGS') +env.Append(SWIGFLAGS=swig_flags) + +# filter out all existing swig scanners, they mess up the dependency +# stuff for some reason +scanners = [] +for scanner in env['SCANNERS']: + skeys = scanner.skeys + if skeys == '.i': + continue + + if isinstance(skeys, (list, tuple)) and '.i' in skeys: + continue -import SCons.Scanner + scanners.append(scanner) +# add the new swig scanner that we like better +from SCons.Scanner import ClassicCPP as CPPScanner swig_inc_re = '^[ \t]*[%,#][ \t]*(?:include|import)[ \t]*(<|")([^>"]+)(>|")' +scanners.append(CPPScanner("SwigScan", [ ".i" ], "CPPPATH", swig_inc_re)) -swig_scanner = SCons.Scanner.ClassicCPP("SwigScan", ".i", "CPPPATH", - swig_inc_re) - -env.Append(SCANNERS = swig_scanner) +# replace the scanners list that has what we want +env['SCANNERS'] = scanners # Platform-specific configuration. Note again that we assume that all # builds under a given build root run on the same host platform. diff --git a/configs/boot/devtime.rcS b/configs/boot/devtime.rcS index 22a5469b8..4d1ca9407 100644 --- a/configs/boot/devtime.rcS +++ b/configs/boot/devtime.rcS @@ -1,7 +1,4 @@ -echo "switching cpus" -m5 switchcpu -echo "done" -insmod /modules/devtime.ko dataAddr=0x9000004 count=100 +insmod /modules/devtime.ko dataAddr=0x9000008 count=100 rmmod devtime insmod /modules/devtime.ko dataAddr=0x1a0000300 count=100 rmmod devtime diff --git a/configs/boot/netperf-stream-udp-client.rcS b/configs/boot/netperf-stream-udp-client.rcS index 91268ea50..4acb4243a 100644 --- a/configs/boot/netperf-stream-udp-client.rcS +++ b/configs/boot/netperf-stream-udp-client.rcS @@ -23,7 +23,7 @@ netcat -c -l -p 8000 BINARY=/benchmarks/netperf-bin/netperf TEST="UDP_STREAM" -SHORT_ARGS="-l 2 -- -m 4096" +SHORT_ARGS="-l 2 -- -m 16384 -M 16384 -s 262144 -S 262144" #LONG_ARGS="-k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144" diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 4692ef537..4bff2c8a4 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,7 +32,7 @@ from m5.objects import * class L1Cache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 protocol = CoherenceProtocol(protocol='moesi') @@ -40,7 +40,7 @@ class L1Cache(BaseCache): class L2Cache(BaseCache): assoc = 8 block_size = 64 - latency = 10 + latency = '10ns' mshrs = 20 tgts_per_mshr = 12 diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 289a7a5f4..6bcdafb14 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -38,22 +38,14 @@ class CowIdeDisk(IdeDisk): def childImage(self, ci): self.image.child.image_file = ci -class CowMmDisk(MmDisk): - image = CowDiskImage(child=RawDiskImage(read_only=True), - read_only=False) - - def childImage(self, ci): - self.image.child.image_file = ci - - -class BaseTsunami(Tsunami): - ethernet = NSGigE(configdata=NSGigEPciData(), - pci_bus=0, pci_dev=1, pci_func=0) - etherint = NSGigEInt(device=Parent.ethernet) - ide = IdeController(disks=[Parent.disk0, Parent.disk2], - pci_func=0, pci_dev=0, pci_bus=0) - def makeLinuxAlphaSystem(mem_mode, mdesc = None): + class BaseTsunami(Tsunami): + ethernet = NSGigE(configdata=NSGigEPciData(), + pci_bus=0, pci_dev=1, pci_func=0) + etherint = NSGigEInt(device=Parent.ethernet) + ide = IdeController(disks=[Parent.disk0, Parent.disk2], + pci_func=0, pci_dev=0, pci_bus=0) + self = LinuxAlphaSystem() if not mdesc: # generic system @@ -61,7 +53,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = Bus(bus_id=1) - self.bridge = Bridge(fix_partial_write_b=True) + self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) self.bridge.side_a = self.iobus.port self.bridge.side_b = self.membus.port @@ -87,6 +79,13 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): return self def makeSparcSystem(mem_mode, mdesc = None): + class CowMmDisk(MmDisk): + image = CowDiskImage(child=RawDiskImage(read_only=True), + read_only=False) + + def childImage(self, ci): + self.image.child.image_file = ci + self = SparcSystem() if not mdesc: # generic system @@ -94,7 +93,7 @@ def makeSparcSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = Bus(bus_id=1) - self.bridge = Bridge() + self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') self.t1000 = T1000() self.t1000.attachOnChipIO(self.membus) self.t1000.attachIO(self.iobus) diff --git a/configs/common/Options.py b/configs/common/Options.py index 69f48dc3b..4f2b317c0 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -31,6 +31,7 @@ parser.add_option("-d", "--detailed", action="store_true") parser.add_option("-t", "--timing", action="store_true") parser.add_option("-n", "--num_cpus", type="int", default=1) parser.add_option("--caches", action="store_true") +parser.add_option("--l2cache", action="store_true") # Run duration options parser.add_option("-m", "--maxtick", type="int") diff --git a/configs/common/cpu2000.py b/configs/common/cpu2000.py index 18f6aedea..2f5844dc6 100644 --- a/configs/common/cpu2000.py +++ b/configs/common/cpu2000.py @@ -131,7 +131,7 @@ class Benchmark(object): def makeLiveProcessArgs(self, **kwargs): # set up default args for LiveProcess object process_args = {} - process_args['cmd'] = self.name + ' ' + ' '.join(self.args) + process_args['cmd'] = [ self.name ] + self.args process_args['executable'] = self.executable if self.stdin: process_args['input'] = self.stdin diff --git a/configs/example/fs.py b/configs/example/fs.py index bd4637e95..76c12bd9e 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -51,7 +51,6 @@ parser.add_option("--kernel", action="store", type="string") parser.add_option("--script", action="store", type="string") # Benchmark options -parser.add_option("--l2cache", action="store_true") parser.add_option("--dual", action="store_true", help="Simulate two systems attached with an ethernet link") parser.add_option("-b", "--benchmark", action="store", type="string", diff --git a/configs/example/memtest.py b/configs/example/memtest.py index e42a92ba1..c28ffab10 100644 --- a/configs/example/memtest.py +++ b/configs/example/memtest.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -53,7 +53,7 @@ if args: # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -65,7 +65,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 10 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -75,28 +75,24 @@ if options.numtesters > 8: print "Error: NUmber of testers limited to 8 because of false sharing" sys,exit(1) -if options.timing: - cpus = [ MemTest(atomic=False, max_loads=options.maxloads, percent_functional=50, - percent_uncacheable=10, progress_interval=1000) - for i in xrange(options.numtesters) ] -else: - cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50, - percent_uncacheable=10, progress_interval=1000) - for i in xrange(options.numtesters) ] +cpus = [ MemTest(atomic=not options.timing, max_loads=options.maxloads, + percent_functional=50, percent_uncacheable=10, + progress_interval=1000) + for i in xrange(options.numtesters) ] + # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), - physmem = PhysicalMemory(latency = "50ps"), membus = Bus(clock="500GHz", width=16)) + physmem = PhysicalMemory(latency = "50ns"), membus = Bus(clock="500MHz", width=16)) # l2cache & bus if options.caches: - system.toL2Bus = Bus(clock="500GHz", width=16) + system.toL2Bus = Bus(clock="500MHz", width=16) system.l2c = L2(size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port # connect l2c to membus system.l2c.mem_side = system.membus.port -which_port = 0 # add L1 caches for cpu in cpus: if options.caches: @@ -105,12 +101,7 @@ for cpu in cpus: cpu.l1c.mem_side = system.toL2Bus.port else: cpu.test = system.membus.port - if which_port == 0: - system.funcmem.port = cpu.functional - which_port = 1 - else: - system.funcmem.functional = cpu.functional - + system.funcmem.port = cpu.functional # connect memory to membus system.physmem.port = system.membus.port @@ -126,6 +117,9 @@ if options.timing: else: root.system.mem_mode = 'atomic' +# Not much point in this being higher than the L1 latency +m5.ticks.setGlobalFrequency('1ns') + # instantiate configuration m5.instantiate(root) diff --git a/configs/example/se.py b/configs/example/se.py index 0944a030e..b294480f6 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -104,7 +104,14 @@ for i in xrange(np): if options.caches: system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) - system.cpu[i].connectMemPorts(system.membus) + if options.l2cache: + system.l2 = L2Cache(size='2MB') + system.tol2bus = Bus() + system.l2.cpu_side = system.tol2bus.port + system.l2.mem_side = system.membus.port + system.cpu[i].connectMemPorts(system.tol2bus) + else: + system.cpu[i].connectMemPorts(system.membus) system.cpu[i].workload = process root = Root(system = system) diff --git a/ext/libelf/SConscript b/ext/libelf/SConscript new file mode 100644 index 000000000..31e570396 --- /dev/null +++ b/ext/libelf/SConscript @@ -0,0 +1,120 @@ +# -*- mode:python -*- + +# Copyright (c) 2004-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +import os, subprocess + +Import('env') + +elf_files = [] +def ElfFile(filename): + elf_files.append(File(filename)) + +ElfFile('elf_begin.c') +ElfFile('elf_cntl.c') +ElfFile('elf_data.c') +ElfFile('elf_end.c') +ElfFile('elf_fill.c') +ElfFile('elf_flag.c') +ElfFile('elf_getarhdr.c') +ElfFile('elf_getarsym.c') +ElfFile('elf_getbase.c') +ElfFile('elf_getident.c') +ElfFile('elf_hash.c') +ElfFile('elf_kind.c') +ElfFile('elf_memory.c') +ElfFile('elf_next.c') +ElfFile('elf_phnum.c') +ElfFile('elf_rand.c') +ElfFile('elf_rawfile.c') +ElfFile('elf_scn.c') +ElfFile('elf_shnum.c') +ElfFile('elf_shstrndx.c') +ElfFile('elf_strptr.c') +ElfFile('elf_update.c') +ElfFile('elf_version.c') +ElfFile('gelf_checksum.c') +ElfFile('gelf_dyn.c') +ElfFile('gelf_ehdr.c') +ElfFile('gelf_fsize.c') +ElfFile('gelf_getclass.c') +ElfFile('gelf_phdr.c') +ElfFile('gelf_rel.c') +ElfFile('gelf_rela.c') +ElfFile('gelf_shdr.c') +ElfFile('gelf_sym.c') +ElfFile('gelf_symshndx.c') +ElfFile('gelf_xlate.c') +ElfFile('libelf.c') +ElfFile('libelf_align.c') +ElfFile('libelf_allocate.c') +ElfFile('libelf_ar.c') +ElfFile('libelf_checksum.c') +ElfFile('libelf_data.c') +ElfFile('libelf_ehdr.c') +ElfFile('libelf_extended.c') +ElfFile('libelf_phdr.c') +ElfFile('libelf_shdr.c') +ElfFile('libelf_xlate.c') + +ElfFile('libelf_convert.c') +ElfFile('libelf_fsize.c') +ElfFile('libelf_msize.c') + +m4env = Environment(ENV=os.environ) +if env.get('CC'): + m4env['CC'] = env['CC'] +if env.get('CXX'): + m4env['CXX'] = env['CXX'] + +# If we have gm4 use it +if m4env.Detect('gm4'): + m4env['M4'] = 'gm4' + +# Check that m4 is available +import SCons.Tool.m4 +if not SCons.Tool.m4.exists(m4env): + print "Error: Can't find version of M4 macro processor. " + \ + "Please install M4 and try again." + Exit(1) + +m4env.Append(M4FLAGS='-DSRCDIR=%s' % Dir('.').path) +m4env['M4COM'] = '$M4 $M4FLAGS $SOURCES > $TARGET' +m4env.M4(target=File('libelf_convert.c'), + source=[File('elf_types.m4'), File('libelf_convert.m4')]) +m4env.M4(target=File('libelf_fsize.c'), + source=[File('elf_types.m4'), File('libelf_fsize.m4')]) +m4env.M4(target=File('libelf_msize.c'), + source=[File('elf_types.m4'), File('libelf_msize.m4')]) +m4env.Library('elf', elf_files) + +env.Append(CPPPATH=Dir('.')) +env.Append(LIBS=['elf']) +env.Append(LIBPATH=[Dir('.')]) + diff --git a/ext/libelf/_libelf.h b/ext/libelf/_libelf.h new file mode 100644 index 000000000..a811abb1a --- /dev/null +++ b/ext/libelf/_libelf.h @@ -0,0 +1,193 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/libelf/_libelf.h,v 1.2 2006/12/25 02:22:22 jkoshy Exp $ + */ + +#ifndef __LIBELF_H_ +#define __LIBELF_H_ + +#include "elf_queue.h" + +#ifndef NULL +#define NULL ((void *) 0) +#endif + +/* + * Library-private data structures. + */ + +#define LIBELF_MSG_SIZE 256 + +struct _libelf_globals { + int libelf_arch; + unsigned int libelf_byteorder; + int libelf_class; + int libelf_error; + int libelf_fillchar; + unsigned int libelf_version; + char libelf_msg[LIBELF_MSG_SIZE]; +}; + +struct _libelf_globals *_libelf_private(); + +#define LIBELF_PRIVATE(N) (_libelf_private()->libelf_##N) + +#define LIBELF_ELF_ERROR_MASK 0xFF +#define LIBELF_OS_ERROR_SHIFT 8 + +#define LIBELF_SET_ERROR(E, O) do { \ + LIBELF_PRIVATE(error) = ((ELF_E_##E & LIBELF_ELF_ERROR_MASK)| \ + ((O) << LIBELF_OS_ERROR_SHIFT)); \ + } while (0) + +#define LIBELF_ADJUST_AR_SIZE(S) (((S) + 1U) & ~1U) + +/* + * Flags for library internal use. These use the upper 16 bits of a + * flags field. + */ +#define LIBELF_F_MALLOCED 0x010000 /* whether data was malloc'ed */ +#define LIBELF_F_MMAP 0x020000 /* whether e_rawfile was mmap'ed */ +#define LIBELF_F_SHDRS_LOADED 0x040000 /* whether all shdrs were read in */ + +struct _Elf { + int e_activations; /* activation count */ + Elf_Arhdr *e_arhdr; /* header for archive members */ + unsigned int e_byteorder; /* ELFDATA* */ + int e_class; /* ELFCLASS* */ + Elf_Cmd e_cmd; /* ELF_C_* used at creation time */ + int e_fd; /* associated file descriptor */ + unsigned int e_flags; /* ELF_F_*, LIBELF_F_* flags */ + Elf_Kind e_kind; /* ELF_K_* */ + Elf *e_parent; /* non-NULL for archive members */ + char *e_rawfile; /* uninterpreted bytes */ + size_t e_rawsize; /* size of uninterpreted bytes */ + unsigned int e_version; /* file version */ + + union { + struct { /* ar(1) archives */ + off_t e_next; /* set by elf_rand()/elf_next() */ + int e_nchildren; + char *e_rawstrtab; /* file name strings */ + size_t e_rawstrtabsz; + char *e_rawsymtab; /* symbol table */ + size_t e_rawsymtabsz; + Elf_Arsym *e_symtab; + size_t e_symtabsz; + } e_ar; + struct { /* regular ELF files */ + union { + Elf32_Ehdr *e_ehdr32; + Elf64_Ehdr *e_ehdr64; + } e_ehdr; + union { + Elf32_Phdr *e_phdr32; + Elf64_Phdr *e_phdr64; + } e_phdr; + STAILQ_HEAD(, _Elf_Scn) e_scn; /* section list */ + size_t e_nphdr; /* number of Phdr entries */ + size_t e_nscn; /* number of sections */ + size_t e_strndx; /* string table section index */ + } e_elf; + } e_u; +}; + +struct _Elf_Scn { + union { + Elf32_Shdr s_shdr32; + Elf64_Shdr s_shdr64; + } s_shdr; + STAILQ_HEAD(, _Elf_Data) s_data; /* list of Elf_Data descriptors */ + STAILQ_HEAD(, _Elf_Data) s_rawdata; /* raw data for this section */ + STAILQ_ENTRY(_Elf_Scn) s_next; + struct _Elf *s_elf; /* parent ELF descriptor */ + unsigned int s_flags; /* flags for the section as a whole */ + size_t s_ndx; /* index# for this section */ + uint64_t s_offset; /* managed by elf_update() */ + uint64_t s_rawoff; /* original offset in the file */ + uint64_t s_size; /* managed by elf_update() */ +}; + + +enum { + ELF_TOFILE, + ELF_TOMEMORY +}; + +#define LIBELF_COPY_U32(DST,SRC,NAME) do { \ + if ((SRC)->NAME > UINT_MAX) { \ + LIBELF_SET_ERROR(RANGE, 0); \ + return (0); \ + } \ + (DST)->NAME = (SRC)->NAME; \ + } while (0) + +#define LIBELF_COPY_S32(DST,SRC,NAME) do { \ + if ((SRC)->NAME > INT_MAX || \ + (SRC)->NAME < INT_MIN) { \ + LIBELF_SET_ERROR(RANGE, 0); \ + return (0); \ + } \ + (DST)->NAME = (SRC)->NAME; \ + } while (0) + + +/* + * Prototypes + */ + +Elf_Data *_libelf_allocate_data(Elf_Scn *_s); +Elf *_libelf_allocate_elf(void); +Elf_Scn *_libelf_allocate_scn(Elf *_e, size_t _ndx); +Elf_Arhdr *_libelf_ar_gethdr(Elf *_e); +Elf *_libelf_ar_open(Elf *_e); +Elf *_libelf_ar_open_member(int _fd, Elf_Cmd _c, Elf *_ar); +Elf_Arsym *_libelf_ar_process_symtab(Elf *_ar, size_t *_dst); +unsigned long _libelf_checksum(Elf *_e, int _elfclass); +void *_libelf_ehdr(Elf *_e, int _elfclass, int _allocate); +int _libelf_falign(Elf_Type _t, int _elfclass); +size_t _libelf_fsize(Elf_Type _t, int _elfclass, unsigned int _version, + size_t count); +void (*_libelf_get_translator(Elf_Type _t, int _direction, int _elfclass)) + (char *_dst, char *_src, size_t _cnt, int _byteswap); +void *_libelf_getphdr(Elf *_e, int _elfclass); +void *_libelf_getshdr(Elf_Scn *_scn, int _elfclass); +void _libelf_init_elf(Elf *_e, Elf_Kind _kind); +int _libelf_malign(Elf_Type _t, int _elfclass); +size_t _libelf_msize(Elf_Type _t, int _elfclass, unsigned int _version); +void *_libelf_newphdr(Elf *_e, int _elfclass, size_t _count); +Elf_Data *_libelf_release_data(Elf_Data *_d); +Elf *_libelf_release_elf(Elf *_e); +Elf_Scn *_libelf_release_scn(Elf_Scn *_s); +int _libelf_setphnum(Elf *_e, void *_eh, int _elfclass, size_t _phnum); +int _libelf_setshnum(Elf *_e, void *_eh, int _elfclass, size_t _shnum); +int _libelf_setshstrndx(Elf *_e, void *_eh, int _elfclass, + size_t _shstrndx); +Elf_Data *_libelf_xlate(Elf_Data *_d, const Elf_Data *_s, + unsigned int _encoding, int _elfclass, int _direction); +int _libelf_xlate_shtype(uint32_t _sht); + +#endif /* __LIBELF_H_ */ diff --git a/ext/libelf/elf32.h b/ext/libelf/elf32.h new file mode 100644 index 000000000..d62de5039 --- /dev/null +++ b/ext/libelf/elf32.h @@ -0,0 +1,245 @@ +/*- + * Copyright (c) 1996-1998 John D. Polstra. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/sys/elf32.h,v 1.13 2006/10/17 05:43:30 jkoshy Exp $ + */ + +#ifndef _SYS_ELF32_H_ +#define _SYS_ELF32_H_ 1 + +#include "elf_common.h" + +/* + * ELF definitions common to all 32-bit architectures. + */ + +typedef uint32_t Elf32_Addr; +typedef uint16_t Elf32_Half; +typedef uint32_t Elf32_Off; +typedef int32_t Elf32_Sword; +typedef uint32_t Elf32_Word; +typedef uint64_t Elf32_Lword; + +typedef Elf32_Word Elf32_Hashelt; + +/* Non-standard class-dependent datatype used for abstraction. */ +typedef Elf32_Word Elf32_Size; +typedef Elf32_Sword Elf32_Ssize; + +/* + * ELF header. + */ + +typedef struct { + unsigned char e_ident[EI_NIDENT]; /* File identification. */ + Elf32_Half e_type; /* File type. */ + Elf32_Half e_machine; /* Machine architecture. */ + Elf32_Word e_version; /* ELF format version. */ + Elf32_Addr e_entry; /* Entry point. */ + Elf32_Off e_phoff; /* Program header file offset. */ + Elf32_Off e_shoff; /* Section header file offset. */ + Elf32_Word e_flags; /* Architecture-specific flags. */ + Elf32_Half e_ehsize; /* Size of ELF header in bytes. */ + Elf32_Half e_phentsize; /* Size of program header entry. */ + Elf32_Half e_phnum; /* Number of program header entries. */ + Elf32_Half e_shentsize; /* Size of section header entry. */ + Elf32_Half e_shnum; /* Number of section header entries. */ + Elf32_Half e_shstrndx; /* Section name strings section. */ +} Elf32_Ehdr; + +/* + * Section header. + */ + +typedef struct { + Elf32_Word sh_name; /* Section name (index into the + section header string table). */ + Elf32_Word sh_type; /* Section type. */ + Elf32_Word sh_flags; /* Section flags. */ + Elf32_Addr sh_addr; /* Address in memory image. */ + Elf32_Off sh_offset; /* Offset in file. */ + Elf32_Word sh_size; /* Size in bytes. */ + Elf32_Word sh_link; /* Index of a related section. */ + Elf32_Word sh_info; /* Depends on section type. */ + Elf32_Word sh_addralign; /* Alignment in bytes. */ + Elf32_Word sh_entsize; /* Size of each entry in section. */ +} Elf32_Shdr; + +/* + * Program header. + */ + +typedef struct { + Elf32_Word p_type; /* Entry type. */ + Elf32_Off p_offset; /* File offset of contents. */ + Elf32_Addr p_vaddr; /* Virtual address in memory image. */ + Elf32_Addr p_paddr; /* Physical address (not used). */ + Elf32_Word p_filesz; /* Size of contents in file. */ + Elf32_Word p_memsz; /* Size of contents in memory. */ + Elf32_Word p_flags; /* Access permission flags. */ + Elf32_Word p_align; /* Alignment in memory and file. */ +} Elf32_Phdr; + +/* + * Dynamic structure. The ".dynamic" section contains an array of them. + */ + +typedef struct { + Elf32_Sword d_tag; /* Entry type. */ + union { + Elf32_Word d_val; /* Integer value. */ + Elf32_Addr d_ptr; /* Address value. */ + } d_un; +} Elf32_Dyn; + +/* + * Relocation entries. + */ + +/* Relocations that don't need an addend field. */ +typedef struct { + Elf32_Addr r_offset; /* Location to be relocated. */ + Elf32_Word r_info; /* Relocation type and symbol index. */ +} Elf32_Rel; + +/* Relocations that need an addend field. */ +typedef struct { + Elf32_Addr r_offset; /* Location to be relocated. */ + Elf32_Word r_info; /* Relocation type and symbol index. */ + Elf32_Sword r_addend; /* Addend. */ +} Elf32_Rela; + +/* Macros for accessing the fields of r_info. */ +#define ELF32_R_SYM(info) ((info) >> 8) +#define ELF32_R_TYPE(info) ((unsigned char)(info)) + +/* Macro for constructing r_info from field values. */ +#define ELF32_R_INFO(sym, type) (((sym) << 8) + (unsigned char)(type)) + +/* + * Note entry header + */ +typedef Elf_Note Elf32_Nhdr; + +/* + * Move entry + */ +typedef struct { + Elf32_Lword m_value; /* symbol value */ + Elf32_Word m_info; /* size + index */ + Elf32_Word m_poffset; /* symbol offset */ + Elf32_Half m_repeat; /* repeat count */ + Elf32_Half m_stride; /* stride info */ +} Elf32_Move; + +/* + * The macros compose and decompose values for Move.r_info + * + * sym = ELF32_M_SYM(M.m_info) + * size = ELF32_M_SIZE(M.m_info) + * M.m_info = ELF32_M_INFO(sym, size) + */ +#define ELF32_M_SYM(info) ((info)>>8) +#define ELF32_M_SIZE(info) ((unsigned char)(info)) +#define ELF32_M_INFO(sym, size) (((sym)<<8)+(unsigned char)(size)) + +/* + * Hardware/Software capabilities entry + */ +typedef struct { + Elf32_Word c_tag; /* how to interpret value */ + union { + Elf32_Word c_val; + Elf32_Addr c_ptr; + } c_un; +} Elf32_Cap; + +/* + * Symbol table entries. + */ + +typedef struct { + Elf32_Word st_name; /* String table index of name. */ + Elf32_Addr st_value; /* Symbol value. */ + Elf32_Word st_size; /* Size of associated object. */ + unsigned char st_info; /* Type and binding information. */ + unsigned char st_other; /* Reserved (not used). */ + Elf32_Half st_shndx; /* Section index of symbol. */ +} Elf32_Sym; + +/* Macros for accessing the fields of st_info. */ +#define ELF32_ST_BIND(info) ((info) >> 4) +#define ELF32_ST_TYPE(info) ((info) & 0xf) + +/* Macro for constructing st_info from field values. */ +#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) + +/* Macro for accessing the fields of st_other. */ +#define ELF32_ST_VISIBILITY(oth) ((oth) & 0x3) + +/* Structures used by Sun & GNU symbol versioning. */ +typedef struct +{ + Elf32_Half vd_version; + Elf32_Half vd_flags; + Elf32_Half vd_ndx; + Elf32_Half vd_cnt; + Elf32_Word vd_hash; + Elf32_Word vd_aux; + Elf32_Word vd_next; +} Elf32_Verdef; + +typedef struct +{ + Elf32_Word vda_name; + Elf32_Word vda_next; +} Elf32_Verdaux; + +typedef struct +{ + Elf32_Half vn_version; + Elf32_Half vn_cnt; + Elf32_Word vn_file; + Elf32_Word vn_aux; + Elf32_Word vn_next; +} Elf32_Verneed; + +typedef struct +{ + Elf32_Word vna_hash; + Elf32_Half vna_flags; + Elf32_Half vna_other; + Elf32_Word vna_name; + Elf32_Word vna_next; +} Elf32_Vernaux; + +typedef Elf32_Half Elf32_Versym; + +typedef struct { + Elf32_Half si_boundto; /* direct bindings - symbol bound to */ + Elf32_Half si_flags; /* per symbol flags */ +} Elf32_Syminfo; + +#endif /* !_SYS_ELF32_H_ */ diff --git a/ext/libelf/elf64.h b/ext/libelf/elf64.h new file mode 100644 index 000000000..a59f3a09d --- /dev/null +++ b/ext/libelf/elf64.h @@ -0,0 +1,248 @@ +/*- + * Copyright (c) 1996-1998 John D. Polstra. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/sys/elf64.h,v 1.17 2006/10/17 05:43:30 jkoshy Exp $ + */ + +#ifndef _SYS_ELF64_H_ +#define _SYS_ELF64_H_ 1 + +#include "elf_common.h" + +/* + * ELF definitions common to all 64-bit architectures. + */ + +typedef uint64_t Elf64_Addr; +typedef uint16_t Elf64_Half; +typedef uint64_t Elf64_Off; +typedef int32_t Elf64_Sword; +typedef int64_t Elf64_Sxword; +typedef uint32_t Elf64_Word; +typedef uint64_t Elf64_Lword; +typedef uint64_t Elf64_Xword; + +/* + * Types of dynamic symbol hash table bucket and chain elements. + * + * This is inconsistent among 64 bit architectures, so a machine dependent + * typedef is required. + */ + +typedef Elf64_Word Elf64_Hashelt; + +/* Non-standard class-dependent datatype used for abstraction. */ +typedef Elf64_Xword Elf64_Size; +typedef Elf64_Sxword Elf64_Ssize; + +/* + * ELF header. + */ + +typedef struct { + unsigned char e_ident[EI_NIDENT]; /* File identification. */ + Elf64_Half e_type; /* File type. */ + Elf64_Half e_machine; /* Machine architecture. */ + Elf64_Word e_version; /* ELF format version. */ + Elf64_Addr e_entry; /* Entry point. */ + Elf64_Off e_phoff; /* Program header file offset. */ + Elf64_Off e_shoff; /* Section header file offset. */ + Elf64_Word e_flags; /* Architecture-specific flags. */ + Elf64_Half e_ehsize; /* Size of ELF header in bytes. */ + Elf64_Half e_phentsize; /* Size of program header entry. */ + Elf64_Half e_phnum; /* Number of program header entries. */ + Elf64_Half e_shentsize; /* Size of section header entry. */ + Elf64_Half e_shnum; /* Number of section header entries. */ + Elf64_Half e_shstrndx; /* Section name strings section. */ +} Elf64_Ehdr; + +/* + * Section header. + */ + +typedef struct { + Elf64_Word sh_name; /* Section name (index into the + section header string table). */ + Elf64_Word sh_type; /* Section type. */ + Elf64_Xword sh_flags; /* Section flags. */ + Elf64_Addr sh_addr; /* Address in memory image. */ + Elf64_Off sh_offset; /* Offset in file. */ + Elf64_Xword sh_size; /* Size in bytes. */ + Elf64_Word sh_link; /* Index of a related section. */ + Elf64_Word sh_info; /* Depends on section type. */ + Elf64_Xword sh_addralign; /* Alignment in bytes. */ + Elf64_Xword sh_entsize; /* Size of each entry in section. */ +} Elf64_Shdr; + +/* + * Program header. + */ + +typedef struct { + Elf64_Word p_type; /* Entry type. */ + Elf64_Word p_flags; /* Access permission flags. */ + Elf64_Off p_offset; /* File offset of contents. */ + Elf64_Addr p_vaddr; /* Virtual address in memory image. */ + Elf64_Addr p_paddr; /* Physical address (not used). */ + Elf64_Xword p_filesz; /* Size of contents in file. */ + Elf64_Xword p_memsz; /* Size of contents in memory. */ + Elf64_Xword p_align; /* Alignment in memory and file. */ +} Elf64_Phdr; + +/* + * Dynamic structure. The ".dynamic" section contains an array of them. + */ + +typedef struct { + Elf64_Sxword d_tag; /* Entry type. */ + union { + Elf64_Xword d_val; /* Integer value. */ + Elf64_Addr d_ptr; /* Address value. */ + } d_un; +} Elf64_Dyn; + +/* + * Relocation entries. + */ + +/* Relocations that don't need an addend field. */ +typedef struct { + Elf64_Addr r_offset; /* Location to be relocated. */ + Elf64_Xword r_info; /* Relocation type and symbol index. */ +} Elf64_Rel; + +/* Relocations that need an addend field. */ +typedef struct { + Elf64_Addr r_offset; /* Location to be relocated. */ + Elf64_Xword r_info; /* Relocation type and symbol index. */ + Elf64_Sxword r_addend; /* Addend. */ +} Elf64_Rela; + +/* Macros for accessing the fields of r_info. */ +#define ELF64_R_SYM(info) ((info) >> 32) +#define ELF64_R_TYPE(info) ((info) & 0xffffffffL) + +/* Macro for constructing r_info from field values. */ +#define ELF64_R_INFO(sym, type) (((sym) << 32) + ((type) & 0xffffffffL)) + +#define ELF64_R_TYPE_DATA(info) (((Elf64_Xword)(info)<<32)>>40) +#define ELF64_R_TYPE_ID(info) (((Elf64_Xword)(info)<<56)>>56) +#define ELF64_R_TYPE_INFO(data, type) \ + (((Elf64_Xword)(data)<<8)+(Elf64_Xword)(type)) + +/* + * Note entry header + */ +typedef Elf_Note Elf64_Nhdr; + +/* + * Move entry + */ +typedef struct { + Elf64_Lword m_value; /* symbol value */ + Elf64_Xword m_info; /* size + index */ + Elf64_Xword m_poffset; /* symbol offset */ + Elf64_Half m_repeat; /* repeat count */ + Elf64_Half m_stride; /* stride info */ +} Elf64_Move; + +#define ELF64_M_SYM(info) ((info)>>8) +#define ELF64_M_SIZE(info) ((unsigned char)(info)) +#define ELF64_M_INFO(sym, size) (((sym)<<8)+(unsigned char)(size)) + +/* + * Hardware/Software capabilities entry + */ +typedef struct { + Elf64_Xword c_tag; /* how to interpret value */ + union { + Elf64_Xword c_val; + Elf64_Addr c_ptr; + } c_un; +} Elf64_Cap; + +/* + * Symbol table entries. + */ + +typedef struct { + Elf64_Word st_name; /* String table index of name. */ + unsigned char st_info; /* Type and binding information. */ + unsigned char st_other; /* Reserved (not used). */ + Elf64_Half st_shndx; /* Section index of symbol. */ + Elf64_Addr st_value; /* Symbol value. */ + Elf64_Xword st_size; /* Size of associated object. */ +} Elf64_Sym; + +/* Macros for accessing the fields of st_info. */ +#define ELF64_ST_BIND(info) ((info) >> 4) +#define ELF64_ST_TYPE(info) ((info) & 0xf) + +/* Macro for constructing st_info from field values. */ +#define ELF64_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) + +/* Macro for accessing the fields of st_other. */ +#define ELF64_ST_VISIBILITY(oth) ((oth) & 0x3) + +/* Structures used by Sun & GNU-style symbol versioning. */ +typedef struct { + Elf64_Half vd_version; + Elf64_Half vd_flags; + Elf64_Half vd_ndx; + Elf64_Half vd_cnt; + Elf64_Word vd_hash; + Elf64_Word vd_aux; + Elf64_Word vd_next; +} Elf64_Verdef; + +typedef struct { + Elf64_Word vda_name; + Elf64_Word vda_next; +} Elf64_Verdaux; + +typedef struct { + Elf64_Half vn_version; + Elf64_Half vn_cnt; + Elf64_Word vn_file; + Elf64_Word vn_aux; + Elf64_Word vn_next; +} Elf64_Verneed; + +typedef struct { + Elf64_Word vna_hash; + Elf64_Half vna_flags; + Elf64_Half vna_other; + Elf64_Word vna_name; + Elf64_Word vna_next; +} Elf64_Vernaux; + +typedef Elf64_Half Elf64_Versym; + +typedef struct { + Elf64_Half si_boundto; /* direct bindings - symbol bound to */ + Elf64_Half si_flags; /* per symbol flags */ +} Elf64_Syminfo; + +#endif /* !_SYS_ELF64_H_ */ diff --git a/ext/libelf/elf_begin.c b/ext/libelf/elf_begin.c new file mode 100644 index 000000000..1b37aa061 --- /dev/null +++ b/ext/libelf/elf_begin.c @@ -0,0 +1,154 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <sys/types.h> +#include <errno.h> +#include <sys/mman.h> +#include <sys/stat.h> + +#include <ar.h> +#include <ctype.h> +#include "libelf.h" + +#include "_libelf.h" + +static Elf * +_libelf_open_object(int fd, Elf_Cmd c) +{ + Elf *e; + void *m; + struct stat sb; + + /* + * 'Raw' files are always mapped with 'PROT_READ'. At + * elf_update(3) time for files opened with ELF_C_RDWR the + * mapping is unmapped, file data is written to using write(2) + * and then the raw data is immediately mapped back in. + */ + if (fstat(fd, &sb) < 0) { + LIBELF_SET_ERROR(IO, errno); + return (NULL); + } + + m = NULL; + if ((m = mmap(NULL, (size_t) sb.st_size, PROT_READ, MAP_PRIVATE, fd, + (off_t) 0)) == MAP_FAILED) { + LIBELF_SET_ERROR(IO, errno); + return (NULL); + } + + if ((e = elf_memory(m, (size_t) sb.st_size)) == NULL) { + (void) munmap(m, (size_t) sb.st_size); + return (NULL); + } + + e->e_flags |= LIBELF_F_MMAP; + e->e_fd = fd; + e->e_cmd = c; + + if (c == ELF_C_RDWR && e->e_kind == ELF_K_AR) { + (void) elf_end(e); + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + return (e); +} + +Elf * +elf_begin(int fd, Elf_Cmd c, Elf *a) +{ + Elf *e; + + e = NULL; + + if (LIBELF_PRIVATE(version) == EV_NONE) { + LIBELF_SET_ERROR(SEQUENCE, 0); + return (NULL); + } + + switch (c) { + case ELF_C_NULL: + return (NULL); + + case ELF_C_WRITE: + + if (a != NULL) { /* not allowed for ar(1) archives. */ + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + /* + * Check writeability of `fd' immediately and fail if + * not writeable. + */ + if (ftruncate(fd, (off_t) 0) < 0) { + LIBELF_SET_ERROR(IO, errno); + return (NULL); + } + + if ((e = _libelf_allocate_elf()) != NULL) { + _libelf_init_elf(e, ELF_K_ELF); + e->e_byteorder = LIBELF_PRIVATE(byteorder); + e->e_fd = fd; + e->e_cmd = c; + } + return (e); + + case ELF_C_RDWR: + if (a != NULL) { /* not allowed for ar(1) archives. */ + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + /*FALLTHROUGH*/ + case ELF_C_READ: + /* + * Descriptor `a' could be for a regular ELF file, or + * for an ar(1) archive. + */ + if (a && (a->e_fd != fd || c != a->e_cmd)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + break; + + default: + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + + } + + if (a == NULL) + e = _libelf_open_object(fd, c); + else if (a->e_kind == ELF_K_AR) + e = _libelf_ar_open_member(fd, c, a); + else + (e = a)->e_activations++; + + return (e); +} diff --git a/ext/libelf/elf_cntl.c b/ext/libelf/elf_cntl.c new file mode 100644 index 000000000..20b0af8ca --- /dev/null +++ b/ext/libelf/elf_cntl.c @@ -0,0 +1,57 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +#include "_libelf.h" + +int +elf_cntl(Elf *e, Elf_Cmd c) +{ + if (e == NULL || + (c != ELF_C_FDDONE && c != ELF_C_FDREAD)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (-1); + } + + if (e->e_parent) { + LIBELF_SET_ERROR(ARCHIVE, 0); + return (-1); + } + + if (c == ELF_C_FDREAD) { + if (e->e_cmd == ELF_C_WRITE) { + LIBELF_SET_ERROR(MODE, 0); + return (-1); + } + else + return (0); + } + + e->e_fd = -1; + return 0; +} diff --git a/ext/libelf/elf_common.h b/ext/libelf/elf_common.h new file mode 100644 index 000000000..c169e7e40 --- /dev/null +++ b/ext/libelf/elf_common.h @@ -0,0 +1,846 @@ +/*- + * Copyright (c) 1998 John D. Polstra. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/sys/sys/elf_common.h,v 1.22 2007/04/03 01:47:07 kan Exp $ + */ + +#ifndef _SYS_ELF_COMMON_H_ +#define _SYS_ELF_COMMON_H_ 1 + +#include <inttypes.h> + +/* + * ELF definitions that are independent of architecture or word size. + */ + +/* + * Note header. The ".note" section contains an array of notes. Each + * begins with this header, aligned to a word boundary. Immediately + * following the note header is n_namesz bytes of name, padded to the + * next word boundary. Then comes n_descsz bytes of descriptor, again + * padded to a word boundary. The values of n_namesz and n_descsz do + * not include the padding. + */ + +typedef struct { + uint32_t n_namesz; /* Length of name. */ + uint32_t n_descsz; /* Length of descriptor. */ + uint32_t n_type; /* Type of this note. */ +} Elf_Note; + +/* Indexes into the e_ident array. Keep synced with + http://www.sco.com/developers/gabi/latest/ch4.eheader.html */ +#define EI_MAG0 0 /* Magic number, byte 0. */ +#define EI_MAG1 1 /* Magic number, byte 1. */ +#define EI_MAG2 2 /* Magic number, byte 2. */ +#define EI_MAG3 3 /* Magic number, byte 3. */ +#define EI_CLASS 4 /* Class of machine. */ +#define EI_DATA 5 /* Data format. */ +#define EI_VERSION 6 /* ELF format version. */ +#define EI_OSABI 7 /* Operating system / ABI identification */ +#define EI_ABIVERSION 8 /* ABI version */ +#define OLD_EI_BRAND 8 /* Start of architecture identification. */ +#define EI_PAD 9 /* Start of padding (per SVR4 ABI). */ +#define EI_NIDENT 16 /* Size of e_ident array. */ + +/* Values for the magic number bytes. */ +#define ELFMAG0 0x7f +#define ELFMAG1 'E' +#define ELFMAG2 'L' +#define ELFMAG3 'F' +#define ELFMAG "\177ELF" /* magic string */ +#define SELFMAG 4 /* magic string size */ + +/* Values for e_ident[EI_VERSION] and e_version. */ +#define EV_NONE 0 +#define EV_CURRENT 1 + +/* Values for e_ident[EI_CLASS]. */ +#define ELFCLASSNONE 0 /* Unknown class. */ +#define ELFCLASS32 1 /* 32-bit architecture. */ +#define ELFCLASS64 2 /* 64-bit architecture. */ + +/* Values for e_ident[EI_DATA]. */ +#define ELFDATANONE 0 /* Unknown data format. */ +#define ELFDATA2LSB 1 /* 2's complement little-endian. */ +#define ELFDATA2MSB 2 /* 2's complement big-endian. */ + +/* Values for e_ident[EI_OSABI]. */ +#define ELFOSABI_NONE 0 /* UNIX System V ABI */ +#define ELFOSABI_HPUX 1 /* HP-UX operating system */ +#define ELFOSABI_NETBSD 2 /* NetBSD */ +#define ELFOSABI_LINUX 3 /* GNU/Linux */ +#define ELFOSABI_HURD 4 /* GNU/Hurd */ +#define ELFOSABI_86OPEN 5 /* 86Open common IA32 ABI */ +#define ELFOSABI_SOLARIS 6 /* Solaris */ +#define ELFOSABI_AIX 7 /* AIX */ +#define ELFOSABI_IRIX 8 /* IRIX */ +#define ELFOSABI_FREEBSD 9 /* FreeBSD */ +#define ELFOSABI_TRU64 10 /* TRU64 UNIX */ +#define ELFOSABI_MODESTO 11 /* Novell Modesto */ +#define ELFOSABI_OPENBSD 12 /* OpenBSD */ +#define ELFOSABI_OPENVMS 13 /* Open VMS */ +#define ELFOSABI_NSK 14 /* HP Non-Stop Kernel */ +#define ELFOSABI_ARM 97 /* ARM */ +#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ + +#define ELFOSABI_SYSV ELFOSABI_NONE /* symbol used in old spec */ +#define ELFOSABI_MONTEREY ELFOSABI_AIX /* Monterey */ + +/* e_ident */ +#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \ + (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \ + (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \ + (ehdr).e_ident[EI_MAG3] == ELFMAG3) + +/* Values for e_type. */ +#define ET_NONE 0 /* Unknown type. */ +#define ET_REL 1 /* Relocatable. */ +#define ET_EXEC 2 /* Executable. */ +#define ET_DYN 3 /* Shared object. */ +#define ET_CORE 4 /* Core file. */ +#define ET_LOOS 0xfe00 /* First operating system specific. */ +#define ET_HIOS 0xfeff /* Last operating system-specific. */ +#define ET_LOPROC 0xff00 /* First processor-specific. */ +#define ET_HIPROC 0xffff /* Last processor-specific. */ + +/* Values for e_machine. */ +#define EM_NONE 0 /* Unknown machine. */ +#define EM_M32 1 /* AT&T WE32100. */ +#define EM_SPARC 2 /* Sun SPARC. */ +#define EM_386 3 /* Intel i386. */ +#define EM_68K 4 /* Motorola 68000. */ +#define EM_88K 5 /* Motorola 88000. */ +#define EM_860 7 /* Intel i860. */ +#define EM_MIPS 8 /* MIPS R3000 Big-Endian only. */ +#define EM_S370 9 /* IBM System/370. */ +#define EM_MIPS_RS3_LE 10 /* MIPS R3000 Little-Endian. */ +#define EM_SPARC64 11 /* SPARC 64-bit */ +#define EM_PARISC 15 /* HP PA-RISC. */ +#define EM_VPP500 17 /* Fujitsu VPP500. */ +#define EM_SPARC32PLUS 18 /* SPARC v8plus. */ +#define EM_960 19 /* Intel 80960. */ +#define EM_PPC 20 /* PowerPC 32-bit. */ +#define EM_PPC64 21 /* PowerPC 64-bit. */ +#define EM_S390 22 /* IBM System/390. */ +#define EM_V800 36 /* NEC V800. */ +#define EM_FR20 37 /* Fujitsu FR20. */ +#define EM_RH32 38 /* TRW RH-32. */ +#define EM_RCE 39 /* Motorola RCE. */ +#define EM_ARM 40 /* ARM. */ +#define EM_SH 42 /* Hitachi SH. */ +#define EM_SPARCV9 43 /* SPARC v9 64-bit. */ +#define EM_TRICORE 44 /* Siemens TriCore embedded processor. */ +#define EM_ARC 45 /* Argonaut RISC Core. */ +#define EM_H8_300 46 /* Hitachi H8/300. */ +#define EM_H8_300H 47 /* Hitachi H8/300H. */ +#define EM_H8S 48 /* Hitachi H8S. */ +#define EM_H8_500 49 /* Hitachi H8/500. */ +#define EM_IA_64 50 /* Intel IA-64 Processor. */ +#define EM_MIPS_X 51 /* Stanford MIPS-X. */ +#define EM_COLDFIRE 52 /* Motorola ColdFire. */ +#define EM_68HC12 53 /* Motorola M68HC12. */ +#define EM_MMA 54 /* Fujitsu MMA. */ +#define EM_PCP 55 /* Siemens PCP. */ +#define EM_NCPU 56 /* Sony nCPU. */ +#define EM_NDR1 57 /* Denso NDR1 microprocessor. */ +#define EM_STARCORE 58 /* Motorola Star*Core processor. */ +#define EM_ME16 59 /* Toyota ME16 processor. */ +#define EM_ST100 60 /* STMicroelectronics ST100 processor. */ +#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ processor. */ +#define EM_X86_64 62 /* Advanced Micro Devices x86-64 */ +#define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */ + +/* Non-standard or deprecated. */ +#define EM_486 6 /* Intel i486. */ +#define EM_MIPS_RS4_BE 10 /* MIPS R4000 Big-Endian */ +#define EM_ALPHA_STD 41 /* Digital Alpha (standard value). */ +#define EM_ALPHA 0x9026 /* Alpha (written in the absence of an ABI) */ + +/* Special section indexes. */ +#define SHN_UNDEF 0 /* Undefined, missing, irrelevant. */ +#define SHN_LORESERVE 0xff00 /* First of reserved range. */ +#define SHN_LOPROC 0xff00 /* First processor-specific. */ +#define SHN_HIPROC 0xff1f /* Last processor-specific. */ +#define SHN_LOOS 0xff20 /* First operating system-specific. */ +#define SHN_HIOS 0xff3f /* Last operating system-specific. */ +#define SHN_ABS 0xfff1 /* Absolute values. */ +#define SHN_COMMON 0xfff2 /* Common data. */ +#define SHN_XINDEX 0xffff /* Escape -- index stored elsewhere. */ +#define SHN_HIRESERVE 0xffff /* Last of reserved range. */ + +/* sh_type */ +#define SHT_NULL 0 /* inactive */ +#define SHT_PROGBITS 1 /* program defined information */ +#define SHT_SYMTAB 2 /* symbol table section */ +#define SHT_STRTAB 3 /* string table section */ +#define SHT_RELA 4 /* relocation section with addends */ +#define SHT_HASH 5 /* symbol hash table section */ +#define SHT_DYNAMIC 6 /* dynamic section */ +#define SHT_NOTE 7 /* note section */ +#define SHT_NOBITS 8 /* no space section */ +#define SHT_REL 9 /* relocation section - no addends */ +#define SHT_SHLIB 10 /* reserved - purpose unknown */ +#define SHT_DYNSYM 11 /* dynamic symbol table section */ +#define SHT_INIT_ARRAY 14 /* Initialization function pointers. */ +#define SHT_FINI_ARRAY 15 /* Termination function pointers. */ +#define SHT_PREINIT_ARRAY 16 /* Pre-initialization function ptrs. */ +#define SHT_GROUP 17 /* Section group. */ +#define SHT_SYMTAB_SHNDX 18 /* Section indexes (see SHN_XINDEX). */ +#define SHT_LOOS 0x60000000 /* First of OS specific semantics */ +#define SHT_LOSUNW 0x6ffffff4 +#define SHT_SUNW_dof 0x6ffffff4 +#define SHT_SUNW_cap 0x6ffffff5 +#define SHT_SUNW_SIGNATURE 0x6ffffff6 +#define SHT_SUNW_ANNOTATE 0x6ffffff7 +#define SHT_SUNW_DEBUGSTR 0x6ffffff8 +#define SHT_SUNW_DEBUG 0x6ffffff9 +#define SHT_SUNW_move 0x6ffffffa +#define SHT_SUNW_COMDAT 0x6ffffffb +#define SHT_SUNW_syminfo 0x6ffffffc +#define SHT_SUNW_verdef 0x6ffffffd +#define SHT_GNU_verdef 0x6ffffffd /* Symbol versions provided */ +#define SHT_SUNW_verneed 0x6ffffffe +#define SHT_GNU_verneed 0x6ffffffe /* Symbol versions required */ +#define SHT_SUNW_versym 0x6fffffff +#define SHT_GNU_versym 0x6fffffff /* Symbol version table */ +#define SHT_HISUNW 0x6fffffff +#define SHT_HIOS 0x6fffffff /* Last of OS specific semantics */ +#define SHT_LOPROC 0x70000000 /* reserved range for processor */ +#define SHT_AMD64_UNWIND 0x70000001 /* unwind information */ +#define SHT_HIPROC 0x7fffffff /* specific section header types */ +#define SHT_LOUSER 0x80000000 /* reserved range for application */ +#define SHT_HIUSER 0xffffffff /* specific indexes */ + +/* Flags for sh_flags. */ +#define SHF_WRITE 0x1 /* Section contains writable data. */ +#define SHF_ALLOC 0x2 /* Section occupies memory. */ +#define SHF_EXECINSTR 0x4 /* Section contains instructions. */ +#define SHF_MERGE 0x10 /* Section may be merged. */ +#define SHF_STRINGS 0x20 /* Section contains strings. */ +#define SHF_INFO_LINK 0x40 /* sh_info holds section index. */ +#define SHF_LINK_ORDER 0x80 /* Special ordering requirements. */ +#define SHF_OS_NONCONFORMING 0x100 /* OS-specific processing required. */ +#define SHF_GROUP 0x200 /* Member of section group. */ +#define SHF_TLS 0x400 /* Section contains TLS data. */ +#define SHF_MASKOS 0x0ff00000 /* OS-specific semantics. */ +#define SHF_MASKPROC 0xf0000000 /* Processor-specific semantics. */ + +/* Values for p_type. */ +#define PT_NULL 0 /* Unused entry. */ +#define PT_LOAD 1 /* Loadable segment. */ +#define PT_DYNAMIC 2 /* Dynamic linking information segment. */ +#define PT_INTERP 3 /* Pathname of interpreter. */ +#define PT_NOTE 4 /* Auxiliary information. */ +#define PT_SHLIB 5 /* Reserved (not used). */ +#define PT_PHDR 6 /* Location of program header itself. */ +#define PT_TLS 7 /* Thread local storage segment */ +#define PT_LOOS 0x60000000 /* First OS-specific. */ +#define PT_SUNW_UNWIND 0x6464e550 /* amd64 UNWIND program header */ +#define PT_GNU_EH_FRAME 0x6474e550 +#define PT_LOSUNW 0x6ffffffa +#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ +#define PT_SUNWSTACK 0x6ffffffb /* describes the stack segment */ +#define PT_SUNWDTRACE 0x6ffffffc /* private */ +#define PT_SUNWCAP 0x6ffffffd /* hard/soft capabilities segment */ +#define PT_HISUNW 0x6fffffff +#define PT_HIOS 0x6fffffff /* Last OS-specific. */ +#define PT_LOPROC 0x70000000 /* First processor-specific type. */ +#define PT_HIPROC 0x7fffffff /* Last processor-specific type. */ + +/* Values for p_flags. */ +#define PF_X 0x1 /* Executable. */ +#define PF_W 0x2 /* Writable. */ +#define PF_R 0x4 /* Readable. */ +#define PF_MASKOS 0x0ff00000 /* Operating system-specific. */ +#define PF_MASKPROC 0xf0000000 /* Processor-specific. */ + +/* Extended program header index. */ +#define PN_XNUM 0xffff + +/* Values for d_tag. */ +#define DT_NULL 0 /* Terminating entry. */ +#define DT_NEEDED 1 /* String table offset of a needed shared + library. */ +#define DT_PLTRELSZ 2 /* Total size in bytes of PLT relocations. */ +#define DT_PLTGOT 3 /* Processor-dependent address. */ +#define DT_HASH 4 /* Address of symbol hash table. */ +#define DT_STRTAB 5 /* Address of string table. */ +#define DT_SYMTAB 6 /* Address of symbol table. */ +#define DT_RELA 7 /* Address of ElfNN_Rela relocations. */ +#define DT_RELASZ 8 /* Total size of ElfNN_Rela relocations. */ +#define DT_RELAENT 9 /* Size of each ElfNN_Rela relocation entry. */ +#define DT_STRSZ 10 /* Size of string table. */ +#define DT_SYMENT 11 /* Size of each symbol table entry. */ +#define DT_INIT 12 /* Address of initialization function. */ +#define DT_FINI 13 /* Address of finalization function. */ +#define DT_SONAME 14 /* String table offset of shared object + name. */ +#define DT_RPATH 15 /* String table offset of library path. [sup] */ +#define DT_SYMBOLIC 16 /* Indicates "symbolic" linking. [sup] */ +#define DT_REL 17 /* Address of ElfNN_Rel relocations. */ +#define DT_RELSZ 18 /* Total size of ElfNN_Rel relocations. */ +#define DT_RELENT 19 /* Size of each ElfNN_Rel relocation. */ +#define DT_PLTREL 20 /* Type of relocation used for PLT. */ +#define DT_DEBUG 21 /* Reserved (not used). */ +#define DT_TEXTREL 22 /* Indicates there may be relocations in + non-writable segments. [sup] */ +#define DT_JMPREL 23 /* Address of PLT relocations. */ +#define DT_BIND_NOW 24 /* [sup] */ +#define DT_INIT_ARRAY 25 /* Address of the array of pointers to + initialization functions */ +#define DT_FINI_ARRAY 26 /* Address of the array of pointers to + termination functions */ +#define DT_INIT_ARRAYSZ 27 /* Size in bytes of the array of + initialization functions. */ +#define DT_FINI_ARRAYSZ 28 /* Size in bytes of the array of + terminationfunctions. */ +#define DT_RUNPATH 29 /* String table offset of a null-terminated + library search path string. */ +#define DT_FLAGS 30 /* Object specific flag values. */ +#define DT_ENCODING 32 /* Values greater than or equal to DT_ENCODING + and less than DT_LOOS follow the rules for + the interpretation of the d_un union + as follows: even == 'd_ptr', even == 'd_val' + or none */ +#define DT_PREINIT_ARRAY 32 /* Address of the array of pointers to + pre-initialization functions. */ +#define DT_PREINIT_ARRAYSZ 33 /* Size in bytes of the array of + pre-initialization functions. */ +#define DT_MAXPOSTAGS 34 /* number of positive tags */ +#define DT_LOOS 0x6000000d /* First OS-specific */ +#define DT_SUNW_AUXILIARY 0x6000000d /* symbol auxiliary name */ +#define DT_SUNW_RTLDINF 0x6000000e /* ld.so.1 info (private) */ +#define DT_SUNW_FILTER 0x6000000f /* symbol filter name */ +#define DT_SUNW_CAP 0x60000010 /* hardware/software */ +#define DT_HIOS 0x6ffff000 /* Last OS-specific */ + +/* + * DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the + * Dyn.d_un.d_val field of the Elf*_Dyn structure. + */ +#define DT_VALRNGLO 0x6ffffd00 +#define DT_CHECKSUM 0x6ffffdf8 /* elf checksum */ +#define DT_PLTPADSZ 0x6ffffdf9 /* pltpadding size */ +#define DT_MOVEENT 0x6ffffdfa /* move table entry size */ +#define DT_MOVESZ 0x6ffffdfb /* move table size */ +#define DT_FEATURE_1 0x6ffffdfc /* feature holder */ +#define DT_POSFLAG_1 0x6ffffdfd /* flags for DT_* entries, effecting */ + /* the following DT_* entry. */ + /* See DF_P1_* definitions */ +#define DT_SYMINSZ 0x6ffffdfe /* syminfo table size (in bytes) */ +#define DT_SYMINENT 0x6ffffdff /* syminfo entry size (in bytes) */ +#define DT_VALRNGHI 0x6ffffdff + +/* + * DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the + * Dyn.d_un.d_ptr field of the Elf*_Dyn structure. + * + * If any adjustment is made to the ELF object after it has been + * built, these entries will need to be adjusted. + */ +#define DT_ADDRRNGLO 0x6ffffe00 +#define DT_CONFIG 0x6ffffefa /* configuration information */ +#define DT_DEPAUDIT 0x6ffffefb /* dependency auditing */ +#define DT_AUDIT 0x6ffffefc /* object auditing */ +#define DT_PLTPAD 0x6ffffefd /* pltpadding (sparcv9) */ +#define DT_MOVETAB 0x6ffffefe /* move table */ +#define DT_SYMINFO 0x6ffffeff /* syminfo table */ +#define DT_ADDRRNGHI 0x6ffffeff + +#define DT_VERSYM 0x6ffffff0 /* Address of versym section. */ +#define DT_RELACOUNT 0x6ffffff9 /* number of RELATIVE relocations */ +#define DT_RELCOUNT 0x6ffffffa /* number of RELATIVE relocations */ +#define DT_FLAGS_1 0x6ffffffb /* state flags - see DF_1_* defs */ +#define DT_VERDEF 0x6ffffffc /* Address of verdef section. */ +#define DT_VERDEFNUM 0x6ffffffd /* Number of elems in verdef section */ +#define DT_VERNEED 0x6ffffffe /* Address of verneed section. */ +#define DT_VERNEEDNUM 0x6fffffff /* Number of elems in verneed section */ + +#define DT_LOPROC 0x70000000 /* First processor-specific type. */ +#define DT_DEPRECATED_SPARC_REGISTER 0x7000001 +#define DT_AUXILIARY 0x7ffffffd /* shared library auxiliary name */ +#define DT_USED 0x7ffffffe /* ignored - same as needed */ +#define DT_FILTER 0x7fffffff /* shared library filter name */ +#define DT_HIPROC 0x7fffffff /* Last processor-specific type. */ + +/* Values for DT_FLAGS */ +#define DF_ORIGIN 0x0001 /* Indicates that the object being loaded may + make reference to the $ORIGIN substitution + string */ +#define DF_SYMBOLIC 0x0002 /* Indicates "symbolic" linking. */ +#define DF_TEXTREL 0x0004 /* Indicates there may be relocations in + non-writable segments. */ +#define DF_BIND_NOW 0x0008 /* Indicates that the dynamic linker should + process all relocations for the object + containing this entry before transferring + control to the program. */ +#define DF_STATIC_TLS 0x0010 /* Indicates that the shared object or + executable contains code using a static + thread-local storage scheme. */ + +/* Values for n_type. Used in core files. */ +#define NT_PRSTATUS 1 /* Process status. */ +#define NT_FPREGSET 2 /* Floating point registers. */ +#define NT_PRPSINFO 3 /* Process state info. */ + +/* Symbol Binding - ELFNN_ST_BIND - st_info */ +#define STB_LOCAL 0 /* Local symbol */ +#define STB_GLOBAL 1 /* Global symbol */ +#define STB_WEAK 2 /* like global - lower precedence */ +#define STB_LOOS 10 /* Reserved range for operating system */ +#define STB_HIOS 12 /* specific semantics. */ +#define STB_LOPROC 13 /* reserved range for processor */ +#define STB_HIPROC 15 /* specific semantics. */ + +/* Symbol type - ELFNN_ST_TYPE - st_info */ +#define STT_NOTYPE 0 /* Unspecified type. */ +#define STT_OBJECT 1 /* Data object. */ +#define STT_FUNC 2 /* Function. */ +#define STT_SECTION 3 /* Section. */ +#define STT_FILE 4 /* Source file. */ +#define STT_COMMON 5 /* Uninitialized common block. */ +#define STT_TLS 6 /* TLS object. */ +#define STT_NUM 7 +#define STT_LOOS 10 /* Reserved range for operating system */ +#define STT_HIOS 12 /* specific semantics. */ +#define STT_LOPROC 13 /* reserved range for processor */ +#define STT_HIPROC 15 /* specific semantics. */ + +/* Symbol visibility - ELFNN_ST_VISIBILITY - st_other */ +#define STV_DEFAULT 0x0 /* Default visibility (see binding). */ +#define STV_INTERNAL 0x1 /* Special meaning in relocatable objects. */ +#define STV_HIDDEN 0x2 /* Not visible. */ +#define STV_PROTECTED 0x3 /* Visible but not preemptible. */ + +/* Special symbol table indexes. */ +#define STN_UNDEF 0 /* Undefined symbol index. */ + +/* Symbol versioning flags. */ +#define VER_DEF_CURRENT 1 +#define VER_DEF_IDX(x) VER_NDX(x) + +#define VER_FLG_BASE 0x01 +#define VER_FLG_WEAK 0x02 + +#define VER_NEED_CURRENT 1 +#define VER_NEED_WEAK (1u << 15) +#define VER_NEED_HIDDEN VER_NDX_HIDDEN +#define VER_NEED_IDX(x) VER_NDX(x) + +#define VER_NDX_LOCAL 0 +#define VER_NDX_GLOBAL 1 +#define VER_NDX_GIVEN 2 + +#define VER_NDX_HIDDEN (1u << 15) +#define VER_NDX(x) ((x) & ~(1u << 15)) + +#define CA_SUNW_NULL 0 +#define CA_SUNW_HW_1 1 /* first hardware capabilities entry */ +#define CA_SUNW_SF_1 2 /* first software capabilities entry */ + +/* + * Syminfo flag values + */ +#define SYMINFO_FLG_DIRECT 0x0001 /* symbol ref has direct association */ + /* to object containing defn. */ +#define SYMINFO_FLG_PASSTHRU 0x0002 /* ignored - see SYMINFO_FLG_FILTER */ +#define SYMINFO_FLG_COPY 0x0004 /* symbol is a copy-reloc */ +#define SYMINFO_FLG_LAZYLOAD 0x0008 /* object containing defn should be */ + /* lazily-loaded */ +#define SYMINFO_FLG_DIRECTBIND 0x0010 /* ref should be bound directly to */ + /* object containing defn. */ +#define SYMINFO_FLG_NOEXTDIRECT 0x0020 /* don't let an external reference */ + /* directly bind to this symbol */ +#define SYMINFO_FLG_FILTER 0x0002 /* symbol ref is associated to a */ +#define SYMINFO_FLG_AUXILIARY 0x0040 /* standard or auxiliary filter */ + +/* + * Syminfo.si_boundto values. + */ +#define SYMINFO_BT_SELF 0xffff /* symbol bound to self */ +#define SYMINFO_BT_PARENT 0xfffe /* symbol bound to parent */ +#define SYMINFO_BT_NONE 0xfffd /* no special symbol binding */ +#define SYMINFO_BT_EXTERN 0xfffc /* symbol defined as external */ +#define SYMINFO_BT_LOWRESERVE 0xff00 /* beginning of reserved entries */ + +/* + * Syminfo version values. + */ +#define SYMINFO_NONE 0 /* Syminfo version */ +#define SYMINFO_CURRENT 1 +#define SYMINFO_NUM 2 + +/* + * Relocation types. + * + * All machine architectures are defined here to allow tools on one to + * handle others. + */ + +#define R_386_NONE 0 /* No relocation. */ +#define R_386_32 1 /* Add symbol value. */ +#define R_386_PC32 2 /* Add PC-relative symbol value. */ +#define R_386_GOT32 3 /* Add PC-relative GOT offset. */ +#define R_386_PLT32 4 /* Add PC-relative PLT offset. */ +#define R_386_COPY 5 /* Copy data from shared object. */ +#define R_386_GLOB_DAT 6 /* Set GOT entry to data address. */ +#define R_386_JMP_SLOT 7 /* Set GOT entry to code address. */ +#define R_386_RELATIVE 8 /* Add load address of shared object. */ +#define R_386_GOTOFF 9 /* Add GOT-relative symbol address. */ +#define R_386_GOTPC 10 /* Add PC-relative GOT table address. */ +#define R_386_TLS_TPOFF 14 /* Negative offset in static TLS block */ +#define R_386_TLS_IE 15 /* Absolute address of GOT for -ve static TLS */ +#define R_386_TLS_GOTIE 16 /* GOT entry for negative static TLS block */ +#define R_386_TLS_LE 17 /* Negative offset relative to static TLS */ +#define R_386_TLS_GD 18 /* 32 bit offset to GOT (index,off) pair */ +#define R_386_TLS_LDM 19 /* 32 bit offset to GOT (index,zero) pair */ +#define R_386_TLS_GD_32 24 /* 32 bit offset to GOT (index,off) pair */ +#define R_386_TLS_GD_PUSH 25 /* pushl instruction for Sun ABI GD sequence */ +#define R_386_TLS_GD_CALL 26 /* call instruction for Sun ABI GD sequence */ +#define R_386_TLS_GD_POP 27 /* popl instruction for Sun ABI GD sequence */ +#define R_386_TLS_LDM_32 28 /* 32 bit offset to GOT (index,zero) pair */ +#define R_386_TLS_LDM_PUSH 29 /* pushl instruction for Sun ABI LD sequence */ +#define R_386_TLS_LDM_CALL 30 /* call instruction for Sun ABI LD sequence */ +#define R_386_TLS_LDM_POP 31 /* popl instruction for Sun ABI LD sequence */ +#define R_386_TLS_LDO_32 32 /* 32 bit offset from start of TLS block */ +#define R_386_TLS_IE_32 33 /* 32 bit offset to GOT static TLS offset entry */ +#define R_386_TLS_LE_32 34 /* 32 bit offset within static TLS block */ +#define R_386_TLS_DTPMOD32 35 /* GOT entry containing TLS index */ +#define R_386_TLS_DTPOFF32 36 /* GOT entry containing TLS offset */ +#define R_386_TLS_TPOFF32 37 /* GOT entry of -ve static TLS offset */ + +#define R_ARM_NONE 0 /* No relocation. */ +#define R_ARM_PC24 1 +#define R_ARM_ABS32 2 +#define R_ARM_REL32 3 +#define R_ARM_PC13 4 +#define R_ARM_ABS16 5 +#define R_ARM_ABS12 6 +#define R_ARM_THM_ABS5 7 +#define R_ARM_ABS8 8 +#define R_ARM_SBREL32 9 +#define R_ARM_THM_PC22 10 +#define R_ARM_THM_PC8 11 +#define R_ARM_AMP_VCALL9 12 +#define R_ARM_SWI24 13 +#define R_ARM_THM_SWI8 14 +#define R_ARM_XPC25 15 +#define R_ARM_THM_XPC22 16 +#define R_ARM_COPY 20 /* Copy data from shared object. */ +#define R_ARM_GLOB_DAT 21 /* Set GOT entry to data address. */ +#define R_ARM_JUMP_SLOT 22 /* Set GOT entry to code address. */ +#define R_ARM_RELATIVE 23 /* Add load address of shared object. */ +#define R_ARM_GOTOFF 24 /* Add GOT-relative symbol address. */ +#define R_ARM_GOTPC 25 /* Add PC-relative GOT table address. */ +#define R_ARM_GOT32 26 /* Add PC-relative GOT offset. */ +#define R_ARM_PLT32 27 /* Add PC-relative PLT offset. */ +#define R_ARM_GNU_VTENTRY 100 +#define R_ARM_GNU_VTINHERIT 101 +#define R_ARM_RSBREL32 250 +#define R_ARM_THM_RPC22 251 +#define R_ARM_RREL32 252 +#define R_ARM_RABS32 253 +#define R_ARM_RPC24 254 +#define R_ARM_RBASE 255 + +/* Name Value Field Calculation */ +#define R_IA_64_NONE 0 /* None */ +#define R_IA_64_IMM14 0x21 /* immediate14 S + A */ +#define R_IA_64_IMM22 0x22 /* immediate22 S + A */ +#define R_IA_64_IMM64 0x23 /* immediate64 S + A */ +#define R_IA_64_DIR32MSB 0x24 /* word32 MSB S + A */ +#define R_IA_64_DIR32LSB 0x25 /* word32 LSB S + A */ +#define R_IA_64_DIR64MSB 0x26 /* word64 MSB S + A */ +#define R_IA_64_DIR64LSB 0x27 /* word64 LSB S + A */ +#define R_IA_64_GPREL22 0x2a /* immediate22 @gprel(S + A) */ +#define R_IA_64_GPREL64I 0x2b /* immediate64 @gprel(S + A) */ +#define R_IA_64_GPREL32MSB 0x2c /* word32 MSB @gprel(S + A) */ +#define R_IA_64_GPREL32LSB 0x2d /* word32 LSB @gprel(S + A) */ +#define R_IA_64_GPREL64MSB 0x2e /* word64 MSB @gprel(S + A) */ +#define R_IA_64_GPREL64LSB 0x2f /* word64 LSB @gprel(S + A) */ +#define R_IA_64_LTOFF22 0x32 /* immediate22 @ltoff(S + A) */ +#define R_IA_64_LTOFF64I 0x33 /* immediate64 @ltoff(S + A) */ +#define R_IA_64_PLTOFF22 0x3a /* immediate22 @pltoff(S + A) */ +#define R_IA_64_PLTOFF64I 0x3b /* immediate64 @pltoff(S + A) */ +#define R_IA_64_PLTOFF64MSB 0x3e /* word64 MSB @pltoff(S + A) */ +#define R_IA_64_PLTOFF64LSB 0x3f /* word64 LSB @pltoff(S + A) */ +#define R_IA_64_FPTR64I 0x43 /* immediate64 @fptr(S + A) */ +#define R_IA_64_FPTR32MSB 0x44 /* word32 MSB @fptr(S + A) */ +#define R_IA_64_FPTR32LSB 0x45 /* word32 LSB @fptr(S + A) */ +#define R_IA_64_FPTR64MSB 0x46 /* word64 MSB @fptr(S + A) */ +#define R_IA_64_FPTR64LSB 0x47 /* word64 LSB @fptr(S + A) */ +#define R_IA_64_PCREL60B 0x48 /* immediate60 form1 S + A - P */ +#define R_IA_64_PCREL21B 0x49 /* immediate21 form1 S + A - P */ +#define R_IA_64_PCREL21M 0x4a /* immediate21 form2 S + A - P */ +#define R_IA_64_PCREL21F 0x4b /* immediate21 form3 S + A - P */ +#define R_IA_64_PCREL32MSB 0x4c /* word32 MSB S + A - P */ +#define R_IA_64_PCREL32LSB 0x4d /* word32 LSB S + A - P */ +#define R_IA_64_PCREL64MSB 0x4e /* word64 MSB S + A - P */ +#define R_IA_64_PCREL64LSB 0x4f /* word64 LSB S + A - P */ +#define R_IA_64_LTOFF_FPTR22 0x52 /* immediate22 @ltoff(@fptr(S + A)) */ +#define R_IA_64_LTOFF_FPTR64I 0x53 /* immediate64 @ltoff(@fptr(S + A)) */ +#define R_IA_64_LTOFF_FPTR32MSB 0x54 /* word32 MSB @ltoff(@fptr(S + A)) */ +#define R_IA_64_LTOFF_FPTR32LSB 0x55 /* word32 LSB @ltoff(@fptr(S + A)) */ +#define R_IA_64_LTOFF_FPTR64MSB 0x56 /* word64 MSB @ltoff(@fptr(S + A)) */ +#define R_IA_64_LTOFF_FPTR64LSB 0x57 /* word64 LSB @ltoff(@fptr(S + A)) */ +#define R_IA_64_SEGREL32MSB 0x5c /* word32 MSB @segrel(S + A) */ +#define R_IA_64_SEGREL32LSB 0x5d /* word32 LSB @segrel(S + A) */ +#define R_IA_64_SEGREL64MSB 0x5e /* word64 MSB @segrel(S + A) */ +#define R_IA_64_SEGREL64LSB 0x5f /* word64 LSB @segrel(S + A) */ +#define R_IA_64_SECREL32MSB 0x64 /* word32 MSB @secrel(S + A) */ +#define R_IA_64_SECREL32LSB 0x65 /* word32 LSB @secrel(S + A) */ +#define R_IA_64_SECREL64MSB 0x66 /* word64 MSB @secrel(S + A) */ +#define R_IA_64_SECREL64LSB 0x67 /* word64 LSB @secrel(S + A) */ +#define R_IA_64_REL32MSB 0x6c /* word32 MSB BD + A */ +#define R_IA_64_REL32LSB 0x6d /* word32 LSB BD + A */ +#define R_IA_64_REL64MSB 0x6e /* word64 MSB BD + A */ +#define R_IA_64_REL64LSB 0x6f /* word64 LSB BD + A */ +#define R_IA_64_LTV32MSB 0x74 /* word32 MSB S + A */ +#define R_IA_64_LTV32LSB 0x75 /* word32 LSB S + A */ +#define R_IA_64_LTV64MSB 0x76 /* word64 MSB S + A */ +#define R_IA_64_LTV64LSB 0x77 /* word64 LSB S + A */ +#define R_IA_64_PCREL21BI 0x79 /* immediate21 form1 S + A - P */ +#define R_IA_64_PCREL22 0x7a /* immediate22 S + A - P */ +#define R_IA_64_PCREL64I 0x7b /* immediate64 S + A - P */ +#define R_IA_64_IPLTMSB 0x80 /* function descriptor MSB special */ +#define R_IA_64_IPLTLSB 0x81 /* function descriptor LSB speciaal */ +#define R_IA_64_SUB 0x85 /* immediate64 A - S */ +#define R_IA_64_LTOFF22X 0x86 /* immediate22 special */ +#define R_IA_64_LDXMOV 0x87 /* immediate22 special */ +#define R_IA_64_TPREL14 0x91 /* imm14 @tprel(S + A) */ +#define R_IA_64_TPREL22 0x92 /* imm22 @tprel(S + A) */ +#define R_IA_64_TPREL64I 0x93 /* imm64 @tprel(S + A) */ +#define R_IA_64_TPREL64MSB 0x96 /* word64 MSB @tprel(S + A) */ +#define R_IA_64_TPREL64LSB 0x97 /* word64 LSB @tprel(S + A) */ +#define R_IA_64_LTOFF_TPREL22 0x9a /* imm22 @ltoff(@tprel(S+A)) */ +#define R_IA_64_DTPMOD64MSB 0xa6 /* word64 MSB @dtpmod(S + A) */ +#define R_IA_64_DTPMOD64LSB 0xa7 /* word64 LSB @dtpmod(S + A) */ +#define R_IA_64_LTOFF_DTPMOD22 0xaa /* imm22 @ltoff(@dtpmod(S+A)) */ +#define R_IA_64_DTPREL14 0xb1 /* imm14 @dtprel(S + A) */ +#define R_IA_64_DTPREL22 0xb2 /* imm22 @dtprel(S + A) */ +#define R_IA_64_DTPREL64I 0xb3 /* imm64 @dtprel(S + A) */ +#define R_IA_64_DTPREL32MSB 0xb4 /* word32 MSB @dtprel(S + A) */ +#define R_IA_64_DTPREL32LSB 0xb5 /* word32 LSB @dtprel(S + A) */ +#define R_IA_64_DTPREL64MSB 0xb6 /* word64 MSB @dtprel(S + A) */ +#define R_IA_64_DTPREL64LSB 0xb7 /* word64 LSB @dtprel(S + A) */ +#define R_IA_64_LTOFF_DTPREL22 0xba /* imm22 @ltoff(@dtprel(S+A)) */ + +#define R_PPC_NONE 0 /* No relocation. */ +#define R_PPC_ADDR32 1 +#define R_PPC_ADDR24 2 +#define R_PPC_ADDR16 3 +#define R_PPC_ADDR16_LO 4 +#define R_PPC_ADDR16_HI 5 +#define R_PPC_ADDR16_HA 6 +#define R_PPC_ADDR14 7 +#define R_PPC_ADDR14_BRTAKEN 8 +#define R_PPC_ADDR14_BRNTAKEN 9 +#define R_PPC_REL24 10 +#define R_PPC_REL14 11 +#define R_PPC_REL14_BRTAKEN 12 +#define R_PPC_REL14_BRNTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLTREL24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_UADDR32 24 +#define R_PPC_UADDR16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 + +/* + * TLS relocations + */ +#define R_PPC_TLS 67 +#define R_PPC_DTPMOD32 68 +#define R_PPC_TPREL16 69 +#define R_PPC_TPREL16_LO 70 +#define R_PPC_TPREL16_HI 71 +#define R_PPC_TPREL16_HA 72 +#define R_PPC_TPREL32 73 +#define R_PPC_DTPREL16 74 +#define R_PPC_DTPREL16_LO 75 +#define R_PPC_DTPREL16_HI 76 +#define R_PPC_DTPREL16_HA 77 +#define R_PPC_DTPREL32 78 +#define R_PPC_GOT_TLSGD16 79 +#define R_PPC_GOT_TLSGD16_LO 80 +#define R_PPC_GOT_TLSGD16_HI 81 +#define R_PPC_GOT_TLSGD16_HA 82 +#define R_PPC_GOT_TLSLD16 83 +#define R_PPC_GOT_TLSLD16_LO 84 +#define R_PPC_GOT_TLSLD16_HI 85 +#define R_PPC_GOT_TLSLD16_HA 86 +#define R_PPC_GOT_TPREL16 87 +#define R_PPC_GOT_TPREL16_LO 88 +#define R_PPC_GOT_TPREL16_HI 89 +#define R_PPC_GOT_TPREL16_HA 90 + +/* + * The remaining relocs are from the Embedded ELF ABI, and are not in the + * SVR4 ELF ABI. + */ + +#define R_PPC_EMB_NADDR32 101 +#define R_PPC_EMB_NADDR16 102 +#define R_PPC_EMB_NADDR16_LO 103 +#define R_PPC_EMB_NADDR16_HI 104 +#define R_PPC_EMB_NADDR16_HA 105 +#define R_PPC_EMB_SDAI16 106 +#define R_PPC_EMB_SDA2I16 107 +#define R_PPC_EMB_SDA2REL 108 +#define R_PPC_EMB_SDA21 109 +#define R_PPC_EMB_MRKREF 110 +#define R_PPC_EMB_RELSEC16 111 +#define R_PPC_EMB_RELST_LO 112 +#define R_PPC_EMB_RELST_HI 113 +#define R_PPC_EMB_RELST_HA 114 +#define R_PPC_EMB_BIT_FLD 115 +#define R_PPC_EMB_RELSDA 116 + +#define R_SPARC_NONE 0 +#define R_SPARC_8 1 +#define R_SPARC_16 2 +#define R_SPARC_32 3 +#define R_SPARC_DISP8 4 +#define R_SPARC_DISP16 5 +#define R_SPARC_DISP32 6 +#define R_SPARC_WDISP30 7 +#define R_SPARC_WDISP22 8 +#define R_SPARC_HI22 9 +#define R_SPARC_22 10 +#define R_SPARC_13 11 +#define R_SPARC_LO10 12 +#define R_SPARC_GOT10 13 +#define R_SPARC_GOT13 14 +#define R_SPARC_GOT22 15 +#define R_SPARC_PC10 16 +#define R_SPARC_PC22 17 +#define R_SPARC_WPLT30 18 +#define R_SPARC_COPY 19 +#define R_SPARC_GLOB_DAT 20 +#define R_SPARC_JMP_SLOT 21 +#define R_SPARC_RELATIVE 22 +#define R_SPARC_UA32 23 +#define R_SPARC_PLT32 24 +#define R_SPARC_HIPLT22 25 +#define R_SPARC_LOPLT10 26 +#define R_SPARC_PCPLT32 27 +#define R_SPARC_PCPLT22 28 +#define R_SPARC_PCPLT10 29 +#define R_SPARC_10 30 +#define R_SPARC_11 31 +#define R_SPARC_64 32 +#define R_SPARC_OLO10 33 +#define R_SPARC_HH22 34 +#define R_SPARC_HM10 35 +#define R_SPARC_LM22 36 +#define R_SPARC_PC_HH22 37 +#define R_SPARC_PC_HM10 38 +#define R_SPARC_PC_LM22 39 +#define R_SPARC_WDISP16 40 +#define R_SPARC_WDISP19 41 +#define R_SPARC_GLOB_JMP 42 +#define R_SPARC_7 43 +#define R_SPARC_5 44 +#define R_SPARC_6 45 +#define R_SPARC_DISP64 46 +#define R_SPARC_PLT64 47 +#define R_SPARC_HIX22 48 +#define R_SPARC_LOX10 49 +#define R_SPARC_H44 50 +#define R_SPARC_M44 51 +#define R_SPARC_L44 52 +#define R_SPARC_REGISTER 53 +#define R_SPARC_UA64 54 +#define R_SPARC_UA16 55 +#define R_SPARC_TLS_GD_HI22 56 +#define R_SPARC_TLS_GD_LO10 57 +#define R_SPARC_TLS_GD_ADD 58 +#define R_SPARC_TLS_GD_CALL 59 +#define R_SPARC_TLS_LDM_HI22 60 +#define R_SPARC_TLS_LDM_LO10 61 +#define R_SPARC_TLS_LDM_ADD 62 +#define R_SPARC_TLS_LDM_CALL 63 +#define R_SPARC_TLS_LDO_HIX22 64 +#define R_SPARC_TLS_LDO_LOX10 65 +#define R_SPARC_TLS_LDO_ADD 66 +#define R_SPARC_TLS_IE_HI22 67 +#define R_SPARC_TLS_IE_LO10 68 +#define R_SPARC_TLS_IE_LD 69 +#define R_SPARC_TLS_IE_LDX 70 +#define R_SPARC_TLS_IE_ADD 71 +#define R_SPARC_TLS_LE_HIX22 72 +#define R_SPARC_TLS_LE_LOX10 73 +#define R_SPARC_TLS_DTPMOD32 74 +#define R_SPARC_TLS_DTPMOD64 75 +#define R_SPARC_TLS_DTPOFF32 76 +#define R_SPARC_TLS_DTPOFF64 77 +#define R_SPARC_TLS_TPOFF32 78 +#define R_SPARC_TLS_TPOFF64 79 + +#define R_X86_64_NONE 0 /* No relocation. */ +#define R_X86_64_64 1 /* Add 64 bit symbol value. */ +#define R_X86_64_PC32 2 /* PC-relative 32 bit signed sym value. */ +#define R_X86_64_GOT32 3 /* PC-relative 32 bit GOT offset. */ +#define R_X86_64_PLT32 4 /* PC-relative 32 bit PLT offset. */ +#define R_X86_64_COPY 5 /* Copy data from shared object. */ +#define R_X86_64_GLOB_DAT 6 /* Set GOT entry to data address. */ +#define R_X86_64_JMP_SLOT 7 /* Set GOT entry to code address. */ +#define R_X86_64_RELATIVE 8 /* Add load address of shared object. */ +#define R_X86_64_GOTPCREL 9 /* Add 32 bit signed pcrel offset to GOT. */ +#define R_X86_64_32 10 /* Add 32 bit zero extended symbol value */ +#define R_X86_64_32S 11 /* Add 32 bit sign extended symbol value */ +#define R_X86_64_16 12 /* Add 16 bit zero extended symbol value */ +#define R_X86_64_PC16 13 /* Add 16 bit signed extended pc relative symbol value */ +#define R_X86_64_8 14 /* Add 8 bit zero extended symbol value */ +#define R_X86_64_PC8 15 /* Add 8 bit signed extended pc relative symbol value */ +#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ +#define R_X86_64_DTPOFF64 17 /* Offset in TLS block */ +#define R_X86_64_TPOFF64 18 /* Offset in static TLS block */ +#define R_X86_64_TLSGD 19 /* PC relative offset to GD GOT entry */ +#define R_X86_64_TLSLD 20 /* PC relative offset to LD GOT entry */ +#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ +#define R_X86_64_GOTTPOFF 22 /* PC relative offset to IE GOT entry */ +#define R_X86_64_TPOFF32 23 /* Offset in static TLS block */ + + +#endif /* !_SYS_ELF_COMMON_H_ */ diff --git a/ext/libelf/elf_data.c b/ext/libelf/elf_data.c new file mode 100644 index 000000000..71e957502 --- /dev/null +++ b/ext/libelf/elf_data.c @@ -0,0 +1,222 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <assert.h> +#include <errno.h> +#include "libelf.h" +#include <stdlib.h> + +#include "_libelf.h" + + +Elf_Data * +elf_getdata(Elf_Scn *s, Elf_Data *d) +{ + Elf *e; + char *dst; + size_t fsz, msz, count; + int elfclass, elftype; + unsigned int sh_type; + uint64_t sh_align, sh_offset, sh_size; + void (*xlate)(char *_d, char *_s, size_t _c, int _swap); + + if (s == NULL || (e = s->s_elf) == NULL || e->e_kind != ELF_K_ELF || + (d != NULL && s != d->d_scn)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (d == NULL && (d = STAILQ_FIRST(&s->s_data)) != NULL) + return (d); + + if (d != NULL) + return (STAILQ_NEXT(d, d_next)); + + if (e->e_rawfile == NULL) { + LIBELF_SET_ERROR(SEQUENCE, 0); + return (NULL); + } + + elfclass = e->e_class; + + assert(elfclass == ELFCLASS32 || elfclass == ELFCLASS64); + + if (elfclass == ELFCLASS32) { + sh_type = s->s_shdr.s_shdr32.sh_type; + sh_offset = (uint64_t) s->s_shdr.s_shdr32.sh_offset; + sh_size = (uint64_t) s->s_shdr.s_shdr32.sh_size; + sh_align = (uint64_t) s->s_shdr.s_shdr32.sh_addralign; + } else { + sh_type = s->s_shdr.s_shdr64.sh_type; + sh_offset = s->s_shdr.s_shdr64.sh_offset; + sh_size = s->s_shdr.s_shdr64.sh_size; + sh_align = s->s_shdr.s_shdr64.sh_addralign; + } + + if ((elftype = _libelf_xlate_shtype(sh_type)) < ELF_T_FIRST || + elftype > ELF_T_LAST || + sh_offset + sh_size > (uint64_t) e->e_rawsize) { + LIBELF_SET_ERROR(SECTION, 0); + return (NULL); + } + + if ((fsz = (elfclass == ELFCLASS32 ? elf32_fsize : elf64_fsize)(elftype, + (size_t) 1, e->e_version)) == 0) { + LIBELF_SET_ERROR(UNIMPL, 0); + return (NULL); + } + + + if (sh_size % fsz) { + LIBELF_SET_ERROR(SECTION, 0); + return (NULL); + } + + count = sh_size / fsz; + + msz = _libelf_msize(elftype, elfclass, e->e_version); + + assert(msz > 0); + + if ((dst = malloc(msz*count)) == NULL) { + LIBELF_SET_ERROR(RESOURCE, 0); + return (NULL); + } + + if ((d = _libelf_allocate_data(s)) == NULL) + return (NULL); + + d->d_buf = dst; + d->d_off = 0; + d->d_align = sh_align; + d->d_size = msz * count; + d->d_type = elftype; + d->d_version = e->e_version; + + d->d_flags |= LIBELF_F_MALLOCED; + STAILQ_INSERT_TAIL(&s->s_data, d, d_next); + + xlate = _libelf_get_translator(elftype, ELF_TOMEMORY, elfclass); + (*xlate)(d->d_buf, e->e_rawfile + sh_offset, count, e->e_byteorder != + LIBELF_PRIVATE(byteorder)); + + return (d); +} + +Elf_Data * +elf_newdata(Elf_Scn *s) +{ + Elf *e; + Elf_Data *d; + + if (s == NULL || (e = s->s_elf) == NULL || + e->e_kind != ELF_K_ELF) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + /* + * elf_newdata() has to append a data descriptor, so + * bring in existing section data if not already present. + */ + if (e->e_rawfile && s->s_size > 0 && STAILQ_EMPTY(&s->s_data)) + if (elf_getdata(s, NULL) == NULL) + return (NULL); + + if ((d = malloc(sizeof(Elf_Data))) == NULL) { + LIBELF_SET_ERROR(RESOURCE, errno); + return (NULL); + } + + STAILQ_INSERT_TAIL(&s->s_data, d, d_next); + d->d_flags = 0; + d->d_scn = s; + + d->d_align = 1; + d->d_buf = NULL; + d->d_off = (uint64_t) ~0; + d->d_size = 0; + d->d_type = ELF_T_BYTE; + d->d_version = LIBELF_PRIVATE(version); + + (void) elf_flagscn(s, ELF_C_SET, ELF_F_DIRTY); + + return (d); +} + +/* + * Retrieve a data descriptor for raw (untranslated) data for section + * `s'. + */ + +Elf_Data * +elf_rawdata(Elf_Scn *s, Elf_Data *d) +{ + Elf *e; + int elf_class; + uint64_t sh_align, sh_offset, sh_size; + + if (s == NULL || (e = s->s_elf) == NULL || + e->e_kind != ELF_K_ELF || e->e_rawfile == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (d == NULL && (d = STAILQ_FIRST(&s->s_rawdata)) != NULL) + return (d); + + if (d != NULL) + return (STAILQ_NEXT(d, d_next)); + + elf_class = e->e_class; + + assert(elf_class == ELFCLASS32 || elf_class == ELFCLASS64); + + if (elf_class == ELFCLASS32) { + sh_offset = (uint64_t) s->s_shdr.s_shdr32.sh_offset; + sh_size = (uint64_t) s->s_shdr.s_shdr32.sh_size; + sh_align = (uint64_t) s->s_shdr.s_shdr32.sh_addralign; + } else { + sh_offset = s->s_shdr.s_shdr64.sh_offset; + sh_size = s->s_shdr.s_shdr64.sh_size; + sh_align = s->s_shdr.s_shdr64.sh_addralign; + } + + if ((d = _libelf_allocate_data(s)) == NULL) + return (NULL); + + d->d_buf = e->e_rawfile + sh_offset; + d->d_off = 0; + d->d_align = sh_align; + d->d_size = sh_size; + d->d_type = ELF_T_BYTE; + d->d_version = e->e_version; + + STAILQ_INSERT_TAIL(&s->s_rawdata, d, d_next); + + return (d); +} diff --git a/ext/libelf/elf_end.c b/ext/libelf/elf_end.c new file mode 100644 index 000000000..082ca2db4 --- /dev/null +++ b/ext/libelf/elf_end.c @@ -0,0 +1,86 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <sys/mman.h> + +#include <assert.h> +#include "libelf.h" +#include <stdlib.h> + +#include "_libelf.h" + +int +elf_end(Elf *e) +{ + Elf *sv; + Elf_Scn *scn, *tscn; + + if (e == NULL || e->e_activations == 0) + return (0); + + if (--e->e_activations > 0) + return (e->e_activations); + + assert(e->e_activations == 0); + + while (e && e->e_activations == 0) { + switch (e->e_kind) { + case ELF_K_AR: + /* + * If we still have open child descriptors, we + * need to defer reclaiming resources till all + * the child descriptors for the archive are + * closed. + */ + if (e->e_u.e_ar.e_nchildren > 0) + return (0); + break; + case ELF_K_ELF: + /* + * Reclaim all section descriptors. + */ + STAILQ_FOREACH_SAFE(scn, &e->e_u.e_elf.e_scn, s_next, tscn) + scn = _libelf_release_scn(scn); + break; + case ELF_K_NUM: + assert(0); + default: + break; + } + + if (e->e_flags & LIBELF_F_MMAP) + (void) munmap(e->e_rawfile, e->e_rawsize); + + sv = e; + if ((e = e->e_parent) != NULL) + e->e_u.e_ar.e_nchildren--; + sv = _libelf_release_elf(sv); + } + + return (0); +} + diff --git a/ext/libelf/elf_errmsg.c b/ext/libelf/elf_errmsg.c new file mode 100644 index 000000000..88607ebf4 --- /dev/null +++ b/ext/libelf/elf_errmsg.c @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <string.h> + +#include "_libelf.h" +#include "libelf.h" + +/* + * Retrieve a human readable translation for an error message. + */ + +const char *_libelf_errors[] = { +#define DEFINE_ERROR(N,S) [ELF_E_##N] = S + DEFINE_ERROR(NONE, "No Error"), + DEFINE_ERROR(ARCHIVE, "Malformed ar(1) archive"), + DEFINE_ERROR(ARGUMENT, "Invalid argument"), + DEFINE_ERROR(CLASS, "ELF class mismatch"), + DEFINE_ERROR(DATA, "Invalid data buffer descriptor"), + DEFINE_ERROR(HEADER, "Missing or malformed ELF header"), + DEFINE_ERROR(IO, "I/O error"), + DEFINE_ERROR(LAYOUT, "Layout constraint violation"), + DEFINE_ERROR(MODE, "Incorrect ELF descriptor mode"), + DEFINE_ERROR(RANGE, "Value out of range of target"), + DEFINE_ERROR(RESOURCE, "Resource exhaustion"), + DEFINE_ERROR(SECTION, "Invalid section descriptor"), + DEFINE_ERROR(SEQUENCE, "API calls out of sequence"), + DEFINE_ERROR(UNIMPL, "Unimplemented feature"), + DEFINE_ERROR(VERSION, "Unknown ELF API version"), + DEFINE_ERROR(NUM, "Unknown error") +#undef DEFINE_ERROR +}; + +const char * +elf_errmsg(int error) +{ + int oserr; + + if (error == 0 && (error = LIBELF_PRIVATE(error)) == 0) + return NULL; + else if (error == -1) + error = LIBELF_PRIVATE(error); + + oserr = error >> LIBELF_OS_ERROR_SHIFT; + error &= LIBELF_ELF_ERROR_MASK; + + if (error < 0 || error >= ELF_E_NUM) + return _libelf_errors[ELF_E_NUM]; + if (oserr) { + strlcpy(LIBELF_PRIVATE(msg), _libelf_errors[error], + sizeof(LIBELF_PRIVATE(msg))); + strlcat(LIBELF_PRIVATE(msg), ": ", sizeof(LIBELF_PRIVATE(msg))); + strlcat(LIBELF_PRIVATE(msg), strerror(oserr), + sizeof(LIBELF_PRIVATE(msg))); + return (const char *)&LIBELF_PRIVATE(msg); + } + return _libelf_errors[error]; +} diff --git a/ext/libelf/elf_errno.c b/ext/libelf/elf_errno.c new file mode 100644 index 000000000..f860d1a8e --- /dev/null +++ b/ext/libelf/elf_errno.c @@ -0,0 +1,40 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +#include "_libelf.h" + +int +elf_errno(void) +{ + int old; + + old = LIBELF_PRIVATE(error); + LIBELF_PRIVATE(error) = 0; + return (old & LIBELF_ELF_ERROR_MASK); +} diff --git a/ext/libelf/elf_fill.c b/ext/libelf/elf_fill.c new file mode 100644 index 000000000..7d0ca63e4 --- /dev/null +++ b/ext/libelf/elf_fill.c @@ -0,0 +1,36 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +#include "_libelf.h" + +void +elf_fill(int fill) +{ + LIBELF_PRIVATE(fillchar) = fill; +} diff --git a/ext/libelf/elf_flag.c b/ext/libelf/elf_flag.c new file mode 100644 index 000000000..234964b07 --- /dev/null +++ b/ext/libelf/elf_flag.c @@ -0,0 +1,162 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +#include "_libelf.h" + +unsigned int +elf_flagdata(Elf_Data *d, Elf_Cmd c, unsigned int flags) +{ + Elf *e; + Elf_Scn *scn; + unsigned int r; + + if (d == NULL) + return (0); + + if ((c != ELF_C_SET && c != ELF_C_CLR) || (scn = d->d_scn) == NULL || + (e = scn->s_elf) == NULL || e->e_kind != ELF_K_ELF || + (flags & ~ELF_F_DIRTY) != 0) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (c == ELF_C_SET) + r = scn->s_flags |= flags; + else + r = scn->s_flags &= ~flags; + + return (r); +} + +unsigned int +elf_flagehdr(Elf *e, Elf_Cmd c, unsigned int flags) +{ + int ec; + void *ehdr; + + if (e == NULL) + return (0); + + if ((c != ELF_C_SET && c != ELF_C_CLR) || + (e->e_kind != ELF_K_ELF) || (flags & ~ELF_F_DIRTY) != 0 || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (ec == ELFCLASS32) + ehdr = e->e_u.e_elf.e_ehdr.e_ehdr32; + else + ehdr = e->e_u.e_elf.e_ehdr.e_ehdr64; + + if (ehdr == NULL) { + LIBELF_SET_ERROR(SEQUENCE, 0); + return (0); + } + + return (elf_flagelf(e, c, flags)); +} + +unsigned int +elf_flagelf(Elf *e, Elf_Cmd c, unsigned int flags) +{ + int r; + + if (e == NULL) + return (0); + + if ((c != ELF_C_SET && c != ELF_C_CLR) || + (e->e_kind != ELF_K_ELF) || + (flags & ~(ELF_F_DIRTY|ELF_F_LAYOUT)) != 0) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (c == ELF_C_SET) + r = e->e_flags |= flags; + else + r = e->e_flags &= ~flags; + return (r); +} + +unsigned int +elf_flagphdr(Elf *e, Elf_Cmd c, unsigned int flags) +{ + int ec; + void *phdr; + + if (e == NULL) + return (0); + + if ((c != ELF_C_SET && c != ELF_C_CLR) || + (e->e_kind != ELF_K_ELF) || (flags & ~ELF_F_DIRTY) != 0 || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (ec == ELFCLASS32) + phdr = e->e_u.e_elf.e_phdr.e_phdr32; + else + phdr = e->e_u.e_elf.e_phdr.e_phdr64; + + if (phdr == NULL) { + LIBELF_SET_ERROR(SEQUENCE, 0); + return (0); + } + + return (elf_flagelf(e, c, flags)); +} + +unsigned int +elf_flagscn(Elf_Scn *s, Elf_Cmd c, unsigned int flags) +{ + int r; + + if (s == NULL) + return (0); + + if ((c != ELF_C_SET && c != ELF_C_CLR) || + (flags & ~ELF_F_DIRTY) != 0) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (c == ELF_C_SET) + r = s->s_flags |= flags; + else + r = s->s_flags &= ~flags; + return (r); +} + +unsigned int +elf_flagshdr(Elf_Scn *s, Elf_Cmd c, unsigned int flags) +{ + return (elf_flagscn(s, c, flags)); +} diff --git a/ext/libelf/elf_getarhdr.c b/ext/libelf/elf_getarhdr.c new file mode 100644 index 000000000..e8456c291 --- /dev/null +++ b/ext/libelf/elf_getarhdr.c @@ -0,0 +1,46 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +#include "_libelf.h" + +Elf_Arhdr * +elf_getarhdr(Elf *e) +{ + Elf_Arhdr *arh; + + if (e == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if ((arh = e->e_arhdr) != NULL) + return (arh); + + return (_libelf_ar_gethdr(e)); +} diff --git a/ext/libelf/elf_getarsym.c b/ext/libelf/elf_getarsym.c new file mode 100644 index 000000000..fc71decb9 --- /dev/null +++ b/ext/libelf/elf_getarsym.c @@ -0,0 +1,54 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +#include "_libelf.h" + +Elf_Arsym * +elf_getarsym(Elf *ar, size_t *ptr) +{ + size_t n; + Elf_Arsym *symtab; + + n = 0; + symtab = NULL; + + if (ar == NULL || ar->e_kind != ELF_K_AR) + LIBELF_SET_ERROR(ARGUMENT, 0); + else if ((symtab = ar->e_u.e_ar.e_symtab) != NULL) + n = ar->e_u.e_ar.e_symtabsz; + else if (ar->e_u.e_ar.e_rawsymtab) + symtab = _libelf_ar_process_symtab(ar, &n); + else + LIBELF_SET_ERROR(ARCHIVE, 0); + + if (ptr) + *ptr = n; + return (symtab); +} + diff --git a/ext/libelf/elf_getbase.c b/ext/libelf/elf_getbase.c new file mode 100644 index 000000000..28f097aa2 --- /dev/null +++ b/ext/libelf/elf_getbase.c @@ -0,0 +1,43 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +#include "_libelf.h" + +off_t +elf_getbase(Elf *e) +{ + if (e == NULL || + e->e_parent == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (off_t) -1; + } + + return ((off_t) ((uintptr_t) e->e_rawfile - + (uintptr_t) e->e_parent->e_rawfile)); +} diff --git a/ext/libelf/elf_getident.c b/ext/libelf/elf_getident.c new file mode 100644 index 000000000..41d09da20 --- /dev/null +++ b/ext/libelf/elf_getident.c @@ -0,0 +1,65 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <ar.h> +#include <assert.h> +#include "libelf.h" + +#include "_libelf.h" + +char * +elf_getident(Elf *e, size_t *sz) +{ + + if (e == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + goto error; + } + + if (e->e_cmd == ELF_C_WRITE && e->e_rawfile == NULL) { + LIBELF_SET_ERROR(SEQUENCE, 0); + goto error; + } + + assert(e->e_kind != ELF_K_AR || e->e_cmd == ELF_C_READ); + + if (sz) { + if (e->e_kind == ELF_K_AR) + *sz = SARMAG; + else if (e->e_kind == ELF_K_ELF) + *sz = EI_NIDENT; + else + *sz = e->e_rawsize; + } + + return (e->e_rawfile); + + error: + if (sz) + *sz = 0; + return (NULL); +} diff --git a/ext/libelf/elf_hash.c b/ext/libelf/elf_hash.c new file mode 100644 index 000000000..b2e4a0ac0 --- /dev/null +++ b/ext/libelf/elf_hash.c @@ -0,0 +1,52 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +/* + * This elf_hash function is defined by the System V ABI. It must be + * kept compatible with "src/libexec/rtld-elf/rtld.c". + */ + +unsigned long +elf_hash(const char *name) +{ + unsigned long h, t; + const unsigned char *s; + + s = (const unsigned char *) name; + h = t = 0; + + for (; *s != '\0'; h = h & ~t) { + h = (h << 4) + *s++; + t = h & 0xF0000000UL; + if (t) + h ^= t >> 24; + } + + return (h); +} diff --git a/ext/libelf/elf_kind.c b/ext/libelf/elf_kind.c new file mode 100644 index 000000000..8f4b1b678 --- /dev/null +++ b/ext/libelf/elf_kind.c @@ -0,0 +1,41 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +#include "_libelf.h" + +Elf_Kind +elf_kind(Elf *e) +{ + if (e == NULL) + return (ELF_K_NONE); + if (e->e_kind == ELF_K_AR || + e->e_kind == ELF_K_ELF) + return (e->e_kind); + return (ELF_K_NONE); +} diff --git a/ext/libelf/elf_memory.c b/ext/libelf/elf_memory.c new file mode 100644 index 000000000..07c645bad --- /dev/null +++ b/ext/libelf/elf_memory.c @@ -0,0 +1,89 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <ar.h> +#include "libelf.h" +#include <string.h> + +#include "_libelf.h" + +Elf * +elf_memory(char *image, size_t sz) +{ + Elf *e; + + if (LIBELF_PRIVATE(version) == EV_NONE) { + LIBELF_SET_ERROR(SEQUENCE, 0); + return (NULL); + } + + if (image == NULL || sz == 0) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if ((e = _libelf_allocate_elf()) == NULL) + return (NULL); + + e->e_cmd = ELF_C_READ; + e->e_rawfile = image; + e->e_rawsize = sz; + +#undef LIBELF_IS_ELF +#define LIBELF_IS_ELF(P) ((P)[EI_MAG0] == ELFMAG0 && \ + (P)[EI_MAG1] == ELFMAG1 && (P)[EI_MAG2] == ELFMAG2 && \ + (P)[EI_MAG3] == ELFMAG3) + + if (sz > EI_NIDENT && LIBELF_IS_ELF(image)) { + _libelf_init_elf(e, ELF_K_ELF); + e->e_class = image[EI_CLASS]; + e->e_byteorder = image[EI_DATA]; + e->e_version = image[EI_VERSION]; + + if (e->e_version > EV_CURRENT) { + e = _libelf_release_elf(e); + LIBELF_SET_ERROR(VERSION, 0); + return (NULL); + } + + if ((e->e_byteorder != ELFDATA2LSB && e->e_byteorder != + ELFDATA2MSB) || (e->e_class != ELFCLASS32 && e->e_class != + ELFCLASS64)) { + e = _libelf_release_elf(e); + LIBELF_SET_ERROR(HEADER, 0); + return (NULL); + } + + } else if (sz >= SARMAG && + strncmp(image, ARMAG, (size_t) SARMAG) == 0) { + _libelf_init_elf(e, ELF_K_AR); + e = _libelf_ar_open(e); + } else + _libelf_init_elf(e, ELF_K_NONE); + + return (e); +} diff --git a/ext/libelf/elf_next.c b/ext/libelf/elf_next.c new file mode 100644 index 000000000..1b1c4090b --- /dev/null +++ b/ext/libelf/elf_next.c @@ -0,0 +1,59 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <ar.h> +#include <assert.h> +#include "libelf.h" + +#include "_libelf.h" + +Elf_Cmd +elf_next(Elf *e) +{ + off_t next; + Elf *parent; + + if (e == NULL) + return (ELF_C_NULL); + + if ((parent = e->e_parent) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (ELF_C_NULL); + } + + assert (parent->e_kind == ELF_K_AR); + assert (parent->e_cmd == ELF_C_READ); + assert((uintptr_t) e->e_rawfile % 2 == 0); + assert(e->e_rawfile > parent->e_rawfile); + + next = e->e_rawfile - parent->e_rawfile + e->e_rawsize; + next = (next + 1) & ~1; /* round up to an even boundary */ + + parent->e_u.e_ar.e_next = (next >= (off_t) parent->e_rawsize) ? (off_t) 0 : next; + + return (ELF_C_READ); +} diff --git a/ext/libelf/elf_phnum.c b/ext/libelf/elf_phnum.c new file mode 100644 index 000000000..0f0c5aa51 --- /dev/null +++ b/ext/libelf/elf_phnum.c @@ -0,0 +1,51 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <ar.h> +#include "libelf.h" + +#include "_libelf.h" + +int +elf_getphnum(Elf *e, size_t *phnum) +{ + void *eh; + int ec; + + if (e == NULL || e->e_kind != ELF_K_ELF || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if ((eh = _libelf_ehdr(e, ec, 0)) == NULL) + return (0); + + *phnum = e->e_u.e_elf.e_nphdr; + + return (1); +} diff --git a/ext/libelf/elf_queue.h b/ext/libelf/elf_queue.h new file mode 100644 index 000000000..37456ddbb --- /dev/null +++ b/ext/libelf/elf_queue.h @@ -0,0 +1,616 @@ +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + * $FreeBSD: src/sys/sys/queue.h,v 1.68 2006/10/24 11:20:29 ru Exp $ + */ + +#ifndef _SYS_QUEUE_H_ +#define _SYS_QUEUE_H_ + +/* + * This file defines four types of data structures: singly-linked lists, + * singly-linked tail queues, lists and tail queues. + * + * A singly-linked list is headed by a single forward pointer. The elements + * are singly linked for minimum space and pointer manipulation overhead at + * the expense of O(n) removal for arbitrary elements. New elements can be + * added to the list after an existing element or at the head of the list. + * Elements being removed from the head of the list should use the explicit + * macro for this purpose for optimum efficiency. A singly-linked list may + * only be traversed in the forward direction. Singly-linked lists are ideal + * for applications with large datasets and few or no removals or for + * implementing a LIFO queue. + * + * A singly-linked tail queue is headed by a pair of pointers, one to the + * head of the list and the other to the tail of the list. The elements are + * singly linked for minimum space and pointer manipulation overhead at the + * expense of O(n) removal for arbitrary elements. New elements can be added + * to the list after an existing element, at the head of the list, or at the + * end of the list. Elements being removed from the head of the tail queue + * should use the explicit macro for this purpose for optimum efficiency. + * A singly-linked tail queue may only be traversed in the forward direction. + * Singly-linked tail queues are ideal for applications with large datasets + * and few or no removals or for implementing a FIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * For details on the use of these macros, see the queue(3) manual page. + * + * + * SLIST LIST STAILQ TAILQ + * _HEAD + + + + + * _HEAD_INITIALIZER + + + + + * _ENTRY + + + + + * _INIT + + + + + * _EMPTY + + + + + * _FIRST + + + + + * _NEXT + + + + + * _PREV - - - + + * _LAST - - + + + * _FOREACH + + + + + * _FOREACH_SAFE + + + + + * _FOREACH_REVERSE - - - + + * _FOREACH_REVERSE_SAFE - - - + + * _INSERT_HEAD + + + + + * _INSERT_BEFORE - + - + + * _INSERT_AFTER + + + + + * _INSERT_TAIL - - + + + * _CONCAT - - + + + * _REMOVE_HEAD + - + - + * _REMOVE + + + + + * + */ +#ifdef QUEUE_MACRO_DEBUG +/* Store the last 2 places the queue element or head was altered */ +struct qm_trace { + char * lastfile; + int lastline; + char * prevfile; + int prevline; +}; + +#define TRACEBUF struct qm_trace trace; +#define TRASHIT(x) do {(x) = (void *)-1;} while (0) + +#define QMD_TRACE_HEAD(head) do { \ + (head)->trace.prevline = (head)->trace.lastline; \ + (head)->trace.prevfile = (head)->trace.lastfile; \ + (head)->trace.lastline = __LINE__; \ + (head)->trace.lastfile = __FILE__; \ +} while (0) + +#define QMD_TRACE_ELEM(elem) do { \ + (elem)->trace.prevline = (elem)->trace.lastline; \ + (elem)->trace.prevfile = (elem)->trace.lastfile; \ + (elem)->trace.lastline = __LINE__; \ + (elem)->trace.lastfile = __FILE__; \ +} while (0) + +#else +#define QMD_TRACE_ELEM(elem) +#define QMD_TRACE_HEAD(head) +#define TRACEBUF +#define TRASHIT(x) +#endif /* QUEUE_MACRO_DEBUG */ + +/* + * Singly-linked List declarations. + */ +#define SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define SLIST_EMPTY(head) ((head)->slh_first == NULL) + +#define SLIST_FIRST(head) ((head)->slh_first) + +#define SLIST_FOREACH(var, head, field) \ + for ((var) = SLIST_FIRST((head)); \ + (var); \ + (var) = SLIST_NEXT((var), field)) + +#define SLIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = SLIST_FIRST((head)); \ + (var) && ((tvar) = SLIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \ + for ((varp) = &SLIST_FIRST((head)); \ + ((var) = *(varp)) != NULL; \ + (varp) = &SLIST_NEXT((var), field)) + +#define SLIST_INIT(head) do { \ + SLIST_FIRST((head)) = NULL; \ +} while (0) + +#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \ + SLIST_NEXT((slistelm), field) = (elm); \ +} while (0) + +#define SLIST_INSERT_HEAD(head, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \ + SLIST_FIRST((head)) = (elm); \ +} while (0) + +#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define SLIST_REMOVE(head, elm, type, field) do { \ + if (SLIST_FIRST((head)) == (elm)) { \ + SLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = SLIST_FIRST((head)); \ + while (SLIST_NEXT(curelm, field) != (elm)) \ + curelm = SLIST_NEXT(curelm, field); \ + SLIST_NEXT(curelm, field) = \ + SLIST_NEXT(SLIST_NEXT(curelm, field), field); \ + } \ + TRASHIT((elm)->field.sle_next); \ +} while (0) + +#define SLIST_REMOVE_HEAD(head, field) do { \ + SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \ +} while (0) + +/* + * Singly-linked Tail queue declarations. + */ +#define STAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ +} + +#define STAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first } + +#define STAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue functions. + */ +#define STAILQ_CONCAT(head1, head2) do { \ + if (!STAILQ_EMPTY((head2))) { \ + *(head1)->stqh_last = (head2)->stqh_first; \ + (head1)->stqh_last = (head2)->stqh_last; \ + STAILQ_INIT((head2)); \ + } \ +} while (0) + +#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) + +#define STAILQ_FIRST(head) ((head)->stqh_first) + +#define STAILQ_FOREACH(var, head, field) \ + for((var) = STAILQ_FIRST((head)); \ + (var); \ + (var) = STAILQ_NEXT((var), field)) + + +#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = STAILQ_FIRST((head)); \ + (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define STAILQ_INIT(head) do { \ + STAILQ_FIRST((head)) = NULL; \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_NEXT((tqelm), field) = (elm); \ +} while (0) + +#define STAILQ_INSERT_HEAD(head, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_FIRST((head)) = (elm); \ +} while (0) + +#define STAILQ_INSERT_TAIL(head, elm, field) do { \ + STAILQ_NEXT((elm), field) = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ +} while (0) + +#define STAILQ_LAST(head, type, field) \ + (STAILQ_EMPTY((head)) ? \ + NULL : \ + ((struct type *)(void *) \ + ((char *)((head)->stqh_last) - offsetof(struct type, field)))) + +#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) + +#define STAILQ_REMOVE(head, elm, type, field) do { \ + if (STAILQ_FIRST((head)) == (elm)) { \ + STAILQ_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = STAILQ_FIRST((head)); \ + while (STAILQ_NEXT(curelm, field) != (elm)) \ + curelm = STAILQ_NEXT(curelm, field); \ + if ((STAILQ_NEXT(curelm, field) = \ + STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\ + (head)->stqh_last = &STAILQ_NEXT((curelm), field);\ + } \ + TRASHIT((elm)->field.stqe_next); \ +} while (0) + +#define STAILQ_REMOVE_HEAD(head, field) do { \ + if ((STAILQ_FIRST((head)) = \ + STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +/* + * List declarations. + */ +#define LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List functions. + */ + +#if (defined(_KERNEL) && defined(INVARIANTS)) +#define QMD_LIST_CHECK_HEAD(head, field) do { \ + if (LIST_FIRST((head)) != NULL && \ + LIST_FIRST((head))->field.le_prev != \ + &LIST_FIRST((head))) \ + panic("Bad list head %p first->prev != head", (head)); \ +} while (0) + +#define QMD_LIST_CHECK_NEXT(elm, field) do { \ + if (LIST_NEXT((elm), field) != NULL && \ + LIST_NEXT((elm), field)->field.le_prev != \ + &((elm)->field.le_next)) \ + panic("Bad link elm %p next->prev != elm", (elm)); \ +} while (0) + +#define QMD_LIST_CHECK_PREV(elm, field) do { \ + if (*(elm)->field.le_prev != (elm)) \ + panic("Bad link elm %p prev->next != elm", (elm)); \ +} while (0) +#else +#define QMD_LIST_CHECK_HEAD(head, field) +#define QMD_LIST_CHECK_NEXT(elm, field) +#define QMD_LIST_CHECK_PREV(elm, field) +#endif /* (_KERNEL && INVARIANTS) */ + +#define LIST_EMPTY(head) ((head)->lh_first == NULL) + +#define LIST_FIRST(head) ((head)->lh_first) + +#define LIST_FOREACH(var, head, field) \ + for ((var) = LIST_FIRST((head)); \ + (var); \ + (var) = LIST_NEXT((var), field)) + +#define LIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = LIST_FIRST((head)); \ + (var) && ((tvar) = LIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define LIST_INIT(head) do { \ + LIST_FIRST((head)) = NULL; \ +} while (0) + +#define LIST_INSERT_AFTER(listelm, elm, field) do { \ + QMD_LIST_CHECK_NEXT(listelm, field); \ + if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\ + LIST_NEXT((listelm), field)->field.le_prev = \ + &LIST_NEXT((elm), field); \ + LIST_NEXT((listelm), field) = (elm); \ + (elm)->field.le_prev = &LIST_NEXT((listelm), field); \ +} while (0) + +#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ + QMD_LIST_CHECK_PREV(listelm, field); \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + LIST_NEXT((elm), field) = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &LIST_NEXT((elm), field); \ +} while (0) + +#define LIST_INSERT_HEAD(head, elm, field) do { \ + QMD_LIST_CHECK_HEAD((head), field); \ + if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \ + LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\ + LIST_FIRST((head)) = (elm); \ + (elm)->field.le_prev = &LIST_FIRST((head)); \ +} while (0) + +#define LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define LIST_REMOVE(elm, field) do { \ + QMD_LIST_CHECK_NEXT(elm, field); \ + QMD_LIST_CHECK_PREV(elm, field); \ + if (LIST_NEXT((elm), field) != NULL) \ + LIST_NEXT((elm), field)->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = LIST_NEXT((elm), field); \ + TRASHIT((elm)->field.le_next); \ + TRASHIT((elm)->field.le_prev); \ +} while (0) + +/* + * Tail queue declarations. + */ +#define TAILQ_HEAD(name, type) \ +struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ + TRACEBUF \ +} + +#define TAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).tqh_first } + +#define TAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ + TRACEBUF \ +} + +/* + * Tail queue functions. + */ +#if (defined(_KERNEL) && defined(INVARIANTS)) +#define QMD_TAILQ_CHECK_HEAD(head, field) do { \ + if (!TAILQ_EMPTY(head) && \ + TAILQ_FIRST((head))->field.tqe_prev != \ + &TAILQ_FIRST((head))) \ + panic("Bad tailq head %p first->prev != head", (head)); \ +} while (0) + +#define QMD_TAILQ_CHECK_TAIL(head, field) do { \ + if (*(head)->tqh_last != NULL) \ + panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); \ +} while (0) + +#define QMD_TAILQ_CHECK_NEXT(elm, field) do { \ + if (TAILQ_NEXT((elm), field) != NULL && \ + TAILQ_NEXT((elm), field)->field.tqe_prev != \ + &((elm)->field.tqe_next)) \ + panic("Bad link elm %p next->prev != elm", (elm)); \ +} while (0) + +#define QMD_TAILQ_CHECK_PREV(elm, field) do { \ + if (*(elm)->field.tqe_prev != (elm)) \ + panic("Bad link elm %p prev->next != elm", (elm)); \ +} while (0) +#else +#define QMD_TAILQ_CHECK_HEAD(head, field) +#define QMD_TAILQ_CHECK_TAIL(head, headname) +#define QMD_TAILQ_CHECK_NEXT(elm, field) +#define QMD_TAILQ_CHECK_PREV(elm, field) +#endif /* (_KERNEL && INVARIANTS) */ + +#define TAILQ_CONCAT(head1, head2, field) do { \ + if (!TAILQ_EMPTY(head2)) { \ + *(head1)->tqh_last = (head2)->tqh_first; \ + (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ + (head1)->tqh_last = (head2)->tqh_last; \ + TAILQ_INIT((head2)); \ + QMD_TRACE_HEAD(head1); \ + QMD_TRACE_HEAD(head2); \ + } \ +} while (0) + +#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) + +#define TAILQ_FIRST(head) ((head)->tqh_first) + +#define TAILQ_FOREACH(var, head, field) \ + for ((var) = TAILQ_FIRST((head)); \ + (var); \ + (var) = TAILQ_NEXT((var), field)) + +#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = TAILQ_FIRST((head)); \ + (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \ + (var) = (tvar)) + +#define TAILQ_INIT(head) do { \ + TAILQ_FIRST((head)) = NULL; \ + (head)->tqh_last = &TAILQ_FIRST((head)); \ + QMD_TRACE_HEAD(head); \ +} while (0) + +#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + QMD_TAILQ_CHECK_NEXT(listelm, field); \ + if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else { \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_HEAD(head); \ + } \ + TAILQ_NEXT((listelm), field) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \ + QMD_TRACE_ELEM(&(elm)->field); \ + QMD_TRACE_ELEM(&listelm->field); \ +} while (0) + +#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + QMD_TAILQ_CHECK_PREV(listelm, field); \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + TAILQ_NEXT((elm), field) = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_ELEM(&(elm)->field); \ + QMD_TRACE_ELEM(&listelm->field); \ +} while (0) + +#define TAILQ_INSERT_HEAD(head, elm, field) do { \ + QMD_TAILQ_CHECK_HEAD(head, field); \ + if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \ + TAILQ_FIRST((head))->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + TAILQ_FIRST((head)) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \ + QMD_TRACE_HEAD(head); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_INSERT_TAIL(head, elm, field) do { \ + QMD_TAILQ_CHECK_TAIL(head, field); \ + TAILQ_NEXT((elm), field) = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_HEAD(head); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + +#define TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define TAILQ_REMOVE(head, elm, field) do { \ + QMD_TAILQ_CHECK_NEXT(elm, field); \ + QMD_TAILQ_CHECK_PREV(elm, field); \ + if ((TAILQ_NEXT((elm), field)) != NULL) \ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else { \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + QMD_TRACE_HEAD(head); \ + } \ + *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \ + TRASHIT((elm)->field.tqe_next); \ + TRASHIT((elm)->field.tqe_prev); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + + +#ifdef _KERNEL + +/* + * XXX insque() and remque() are an old way of handling certain queues. + * They bogusly assumes that all queue heads look alike. + */ + +struct quehead { + struct quehead *qh_link; + struct quehead *qh_rlink; +}; + +#ifdef __CC_SUPPORTS___INLINE + +static __inline void +insque(void *a, void *b) +{ + struct quehead *element = (struct quehead *)a, + *head = (struct quehead *)b; + + element->qh_link = head->qh_link; + element->qh_rlink = head; + head->qh_link = element; + element->qh_link->qh_rlink = element; +} + +static __inline void +remque(void *a) +{ + struct quehead *element = (struct quehead *)a; + + element->qh_link->qh_rlink = element->qh_rlink; + element->qh_rlink->qh_link = element->qh_link; + element->qh_rlink = 0; +} + +#else /* !__CC_SUPPORTS___INLINE */ + +void insque(void *a, void *b); +void remque(void *a); + +#endif /* __CC_SUPPORTS___INLINE */ + +#endif /* _KERNEL */ + +#endif /* !_SYS_QUEUE_H_ */ diff --git a/ext/libelf/elf_rand.c b/ext/libelf/elf_rand.c new file mode 100644 index 000000000..ac44aea31 --- /dev/null +++ b/ext/libelf/elf_rand.c @@ -0,0 +1,56 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <ar.h> +#include "libelf.h" + +#include "_libelf.h" + +off_t +elf_rand(Elf *ar, off_t offset) +{ + struct ar_hdr *arh; + + if (ar == NULL || ar->e_kind != ELF_K_AR || + (offset & 1) || offset < SARMAG || + offset + sizeof(struct ar_hdr) >= ar->e_rawsize) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return 0; + } + + arh = (struct ar_hdr *) (ar->e_rawfile + offset); + + /* a too simple sanity check */ + if (arh->ar_fmag[0] != '`' || arh->ar_fmag[1] != '\n') { + LIBELF_SET_ERROR(ARCHIVE, 0); + return 0; + } + + ar->e_u.e_ar.e_next = offset; + + return (offset); +} diff --git a/ext/libelf/elf_rawfile.c b/ext/libelf/elf_rawfile.c new file mode 100644 index 000000000..d92624385 --- /dev/null +++ b/ext/libelf/elf_rawfile.c @@ -0,0 +1,50 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include "libelf.h" + +#include "_libelf.h" + +char * +elf_rawfile(Elf *e, size_t *sz) +{ + char *ptr; + size_t size; + + size = e ? e->e_rawsize : 0; + ptr = NULL; + + if (e == NULL) + LIBELF_SET_ERROR(ARGUMENT, 0); + else if ((ptr = e->e_rawfile) == NULL && e->e_cmd == ELF_C_WRITE) + LIBELF_SET_ERROR(SEQUENCE, 0); + + if (sz) + *sz = size; + + return (ptr); +} diff --git a/ext/libelf/elf_scn.c b/ext/libelf/elf_scn.c new file mode 100644 index 000000000..cf596bac2 --- /dev/null +++ b/ext/libelf/elf_scn.c @@ -0,0 +1,227 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <assert.h> +#include <errno.h> +#include <stddef.h> +#include <stdlib.h> + +#include "gelf.h" +#include "libelf.h" +#include "_libelf.h" + +/* + * Load an ELF section table and create a list of Elf_Scn structures. + */ +static int +_libelf_load_scn(Elf *e, void *ehdr) +{ + int ec, swapbytes; + size_t fsz, i, shnum; + uint64_t shoff; + char *src; + Elf32_Ehdr *eh32; + Elf64_Ehdr *eh64; + Elf_Scn *scn; + void (*xlator)(char *_d, char *_s, size_t _c, int _swap); + + assert(e != NULL); + assert(ehdr != NULL); + assert((e->e_flags & LIBELF_F_SHDRS_LOADED) == 0); + +#define CHECK_EHDR(E,EH) do { \ + if (fsz != (EH)->e_shentsize || \ + shoff + fsz * shnum > e->e_rawsize) { \ + LIBELF_SET_ERROR(HEADER, 0); \ + return (0); \ + } \ + } while (0) + + ec = e->e_class; + fsz = _libelf_fsize(ELF_T_SHDR, ec, e->e_version, (size_t) 1); + assert(fsz > 0); + + shnum = e->e_u.e_elf.e_nscn; + + if (ec == ELFCLASS32) { + eh32 = (Elf32_Ehdr *) ehdr; + shoff = (uint64_t) eh32->e_shoff; + CHECK_EHDR(e, eh32); + } else { + eh64 = (Elf64_Ehdr *) ehdr; + shoff = eh64->e_shoff; + CHECK_EHDR(e, eh64); + } + + xlator = _libelf_get_translator(ELF_T_SHDR, ELF_TOMEMORY, ec); + + swapbytes = e->e_byteorder != LIBELF_PRIVATE(byteorder); + src = e->e_rawfile + shoff; + + /* + * If the file is using extended numbering then section #0 + * would have already been read in. + */ + + i = 0; + if (!STAILQ_EMPTY(&e->e_u.e_elf.e_scn)) { + assert(STAILQ_FIRST(&e->e_u.e_elf.e_scn) == + STAILQ_LAST(&e->e_u.e_elf.e_scn, _Elf_Scn, s_next)); + + i = 1; + src += fsz; + } + + for (; i < shnum; i++, src += fsz) { + if ((scn = _libelf_allocate_scn(e, i)) == NULL) + return (0); + + (*xlator)((char *) &scn->s_shdr, src, (size_t) 1, swapbytes); + + if (ec == ELFCLASS32) { + scn->s_offset = scn->s_rawoff = + scn->s_shdr.s_shdr32.sh_offset; + scn->s_size = scn->s_shdr.s_shdr32.sh_size; + } else { + scn->s_offset = scn->s_rawoff = + scn->s_shdr.s_shdr64.sh_offset; + scn->s_size = scn->s_shdr.s_shdr64.sh_size; + } + } + + e->e_flags |= LIBELF_F_SHDRS_LOADED; + + return (1); +} + + +Elf_Scn * +elf_getscn(Elf *e, size_t index) +{ + int ec; + void *ehdr; + Elf_Scn *s; + + if (e == NULL || e->e_kind != ELF_K_ELF || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if ((ehdr = _libelf_ehdr(e, ec, 0)) == NULL) + return (NULL); + + if (e->e_cmd != ELF_C_WRITE && + (e->e_flags & LIBELF_F_SHDRS_LOADED) == 0 && + _libelf_load_scn(e, ehdr) == 0) + return (NULL); + + STAILQ_FOREACH(s, &e->e_u.e_elf.e_scn, s_next) + if (s->s_ndx == index) + return (s); + + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); +} + +size_t +elf_ndxscn(Elf_Scn *s) +{ + if (s == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (SHN_UNDEF); + } + return (s->s_ndx); +} + +Elf_Scn * +elf_newscn(Elf *e) +{ + int ec; + void *ehdr; + Elf_Scn *scn; + + if (e == NULL || e->e_kind != ELF_K_ELF) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64) { + LIBELF_SET_ERROR(CLASS, 0); + return (NULL); + } + + if ((ehdr = _libelf_ehdr(e, ec, 0)) == NULL) + return (NULL); + + /* + * The application may be asking for a new section descriptor + * on an ELF object opened with ELF_C_RDWR or ELF_C_READ. We + * need to bring in the existing section information before + * appending a new one to the list. + * + * Per the ELF(3) API, an application is allowed to open a + * file using ELF_C_READ, mess with its internal structure and + * use elf_update(...,ELF_C_NULL) to compute its new layout. + */ + if (e->e_cmd != ELF_C_WRITE && + (e->e_flags & LIBELF_F_SHDRS_LOADED) == 0 && + _libelf_load_scn(e, ehdr) == 0) + return (NULL); + + if (STAILQ_EMPTY(&e->e_u.e_elf.e_scn)) { + assert(e->e_u.e_elf.e_nscn == 0); + if ((scn = _libelf_allocate_scn(e, (size_t) SHN_UNDEF)) == + NULL) + return (NULL); + e->e_u.e_elf.e_nscn++; + } + + assert(e->e_u.e_elf.e_nscn > 0); + + if ((scn = _libelf_allocate_scn(e, e->e_u.e_elf.e_nscn)) == NULL) + return (NULL); + + e->e_u.e_elf.e_nscn++; + + (void) elf_flagscn(scn, ELF_C_SET, ELF_F_DIRTY); + + return (scn); +} + +Elf_Scn * +elf_nextscn(Elf *e, Elf_Scn *s) +{ + if (e == NULL || (e->e_kind != ELF_K_ELF) || + (s && s->s_elf != e)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + return (s == NULL ? elf_getscn(e, (size_t) 1) : + STAILQ_NEXT(s, s_next)); +} diff --git a/ext/libelf/elf_shnum.c b/ext/libelf/elf_shnum.c new file mode 100644 index 000000000..adc77af03 --- /dev/null +++ b/ext/libelf/elf_shnum.c @@ -0,0 +1,51 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <ar.h> +#include "libelf.h" + +#include "_libelf.h" + +int +elf_getshnum(Elf *e, size_t *shnum) +{ + void *eh; + int ec; + + if (e == NULL || e->e_kind != ELF_K_ELF || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if ((eh = _libelf_ehdr(e, ec, 0)) == NULL) + return (0); + + *shnum = e->e_u.e_elf.e_nscn; + + return (1); +} diff --git a/ext/libelf/elf_shstrndx.c b/ext/libelf/elf_shstrndx.c new file mode 100644 index 000000000..5b9cccda0 --- /dev/null +++ b/ext/libelf/elf_shstrndx.c @@ -0,0 +1,67 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <ar.h> +#include "libelf.h" + +#include "_libelf.h" + +int +elf_getshstrndx(Elf *e, size_t *strndx) +{ + void *eh; + int ec; + + if (e == NULL || e->e_kind != ELF_K_ELF || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if ((eh = _libelf_ehdr(e, ec, 0)) == NULL) + return (0); + + *strndx = e->e_u.e_elf.e_strndx; + + return (1); +} + +int +elf_setshstrndx(Elf *e, size_t strndx) +{ + void *eh; + int ec; + + if (e == NULL || e->e_kind != ELF_K_ELF || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64) || + ((eh = _libelf_ehdr(e, ec, 0)) == NULL)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + return (_libelf_setshstrndx(e, eh, ec, strndx)); +} diff --git a/ext/libelf/elf_strptr.c b/ext/libelf/elf_strptr.c new file mode 100644 index 000000000..6a05fa1d4 --- /dev/null +++ b/ext/libelf/elf_strptr.c @@ -0,0 +1,134 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <sys/param.h> +#ifdef __sun +#include <sys/sysmacros.h> +#endif + +#include <assert.h> +#include "gelf.h" + +#include "_libelf.h" + +/* + * Convert an ELF section#,offset pair to a string pointer. + */ + +char * +elf_strptr(Elf *e, size_t scndx, size_t offset) +{ + Elf_Scn *s; + Elf_Data *d; + size_t alignment, count; + GElf_Shdr shdr; + + if (e == NULL || e->e_kind != ELF_K_ELF) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if ((s = elf_getscn(e, scndx)) == NULL || + gelf_getshdr(s, &shdr) == NULL) + return (NULL); + + if (shdr.sh_type != SHT_STRTAB || + offset >= shdr.sh_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + d = NULL; + if (e->e_flags & ELF_F_LAYOUT) { + + /* + * The application is taking responsibility for the + * ELF object's layout, so we can directly translate + * an offset to a `char *' address using the `d_off' + * members of Elf_Data descriptors. + */ + while ((d = elf_getdata(s, d)) != NULL) { + + if (d->d_buf == 0 || d->d_size == 0) + continue; + + if (d->d_type != ELF_T_BYTE) { + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + + if (offset >= d->d_off && + offset < d->d_off + d->d_size) + return ((char *) d->d_buf + offset - d->d_off); + } + } else { + /* + * Otherwise, the `d_off' members are not useable and + * we need to compute offsets ourselves, taking into + * account 'holes' in coverage of the section introduced + * by alignment requirements. + */ + count = (size_t) 0; /* cumulative count of bytes seen */ + while ((d = elf_getdata(s, d)) != NULL && count <= offset) { + + if (d->d_buf == NULL || d->d_size == 0) + continue; + + if (d->d_type != ELF_T_BYTE) { + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + + if ((alignment = d->d_align) > 1) { + if ((alignment & (alignment - 1)) != 0) { + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + count = roundup(count, alignment); + } + + if (offset < count) { + /* offset starts in the 'hole' */ + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (offset < count + d->d_size) { + if (d->d_buf != NULL) + return ((char *) d->d_buf + + offset - count); + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + + count += d->d_size; + } + } + + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); +} diff --git a/ext/libelf/elf_types.m4 b/ext/libelf/elf_types.m4 new file mode 100644 index 000000000..a72923341 --- /dev/null +++ b/ext/libelf/elf_types.m4 @@ -0,0 +1,310 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/libelf/elf_types.m4,v 1.2 2006/12/18 05:40:01 jkoshy Exp $ + */ + +/* + * ELF types, defined in the "enum Elf_Type" API. + * + * The members of the list form a 3-tuple: (name, C-type-suffix, OSversion). + * + `name' is an Elf_Type symbol without the `ELF_T_' prefix. + * + `C-type-suffix' is the suffix for Elf32_ and Elf64_ type names. + * + `version' is the OS version the symbol first appeared in. + * + */ + +define(`ELF_TYPE_LIST', + ``ADDR, Addr, 600102', + `BYTE, Byte, 600102', + `CAP, Cap, 700025', + `DYN, Dyn, 600102', + `EHDR, Ehdr, 600102', + `HALF, Half, 600102', + `LWORD, Lword, 700025', + `MOVE, Move, 700025', + `MOVEP, MoveP, 700025', + `NOTE, Note, 600102', + `OFF, Off, 600102', + `PHDR, Phdr, 600102', + `REL, Rel, 600102', + `RELA, Rela, 600102', + `SHDR, Shdr, 600102', + `SWORD, Sword, 600102', + `SXWORD, Sxword, 700009', + `SYMINFO, Syminfo, 700025', + `SYM, Sym, 600102', + `VDEF, Verdef, 700009', + `VNEED, Verneed, 700009', + `WORD, Word, 600102', + `XWORD, Xword, 700009', + `NUM, _, _'') + +/* + * DEFINE_STRUCT(NAME,MEMBERLIST...) + * + * Map a type name to its members. + * + * Each member-list element comprises of pairs of (field name, type), + * in the sequence used in the file representation of `NAME'. + * + * Each member list element comprises a pair containing a field name + * and a basic type. Basic types include IDENT, HALF, WORD, LWORD, + * ADDR{32,64}, OFF{32,64}, SWORD, XWORD, SXWORD. + * + * The last element of a member list is the null element: `_,_'. + */ + +define(`DEFINE_STRUCT',`define(`$1_DEF',shift($@))dnl') + +DEFINE_STRUCT(`Elf32_Cap', + ``c_tag, WORD', + `c_un.c_val, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Cap', + ``c_tag, XWORD', + `c_un.c_val, XWORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Dyn', + ``d_tag, SWORD', + `d_un.d_ptr, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Dyn', + ``d_tag, SXWORD', + `d_un.d_ptr, XWORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Ehdr', + ``e_ident, IDENT', + `e_type, HALF', + `e_machine, HALF', + `e_version, WORD', + `e_entry, ADDR', + `e_phoff, OFF', + `e_shoff, OFF', + `e_flags, WORD', + `e_ehsize, HALF', + `e_phentsize, HALF', + `e_phnum, HALF', + `e_shentsize, HALF', + `e_shnum, HALF', + `e_shstrndx, HALF', + `_,_'') + +DEFINE_STRUCT(`Elf64_Ehdr', + ``e_ident, IDENT', + `e_type, HALF', + `e_machine, HALF', + `e_version, WORD', + `e_entry, ADDR', + `e_phoff, OFF', + `e_shoff, OFF', + `e_flags, WORD', + `e_ehsize, HALF', + `e_phentsize, HALF', + `e_phnum, HALF', + `e_shentsize, HALF', + `e_shnum, HALF', + `e_shstrndx, HALF', + `_,_'') + +DEFINE_STRUCT(`Elf32_Move', + ``m_value, LWORD', + `m_info, WORD', + `m_poffset, WORD', + `m_repeat, HALF', + `m_stride, HALF', + `_,_'') + +DEFINE_STRUCT(`Elf64_Move', + ``m_value, LWORD', + `m_info, XWORD', + `m_poffset, XWORD', + `m_repeat, HALF', + `m_stride, HALF', + `_,_'') + +DEFINE_STRUCT(`Elf32_Phdr', + ``p_type, WORD', + `p_offset, OFF', + `p_vaddr, ADDR', + `p_paddr, ADDR', + `p_filesz, WORD', + `p_memsz, WORD', + `p_flags, WORD', + `p_align, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Phdr', + ``p_type, WORD', + `p_flags, WORD', + `p_offset, OFF', + `p_vaddr, ADDR', + `p_paddr, ADDR', + `p_filesz, XWORD', + `p_memsz, XWORD', + `p_align, XWORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Rel', + ``r_offset, ADDR', + `r_info, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Rel', + ``r_offset, ADDR', + `r_info, XWORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Rela', + ``r_offset, ADDR', + `r_info, WORD', + `r_addend, SWORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Rela', + ``r_offset, ADDR', + `r_info, XWORD', + `r_addend, SXWORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Shdr', + ``sh_name, WORD', + `sh_type, WORD', + `sh_flags, WORD', + `sh_addr, ADDR', + `sh_offset, OFF', + `sh_size, WORD', + `sh_link, WORD', + `sh_info, WORD', + `sh_addralign, WORD', + `sh_entsize, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Shdr', + ``sh_name, WORD', + `sh_type, WORD', + `sh_flags, XWORD', + `sh_addr, ADDR', + `sh_offset, OFF', + `sh_size, XWORD', + `sh_link, WORD', + `sh_info, WORD', + `sh_addralign, XWORD', + `sh_entsize, XWORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Sym', + ``st_name, WORD', + `st_value, ADDR', + `st_size, WORD', + `st_info, BYTE', + `st_other, BYTE', + `st_shndx, HALF', + `_,_'') + +DEFINE_STRUCT(`Elf64_Sym', + ``st_name, WORD', + `st_info, BYTE', + `st_other, BYTE', + `st_shndx, HALF', + `st_value, ADDR', + `st_size, XWORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Syminfo', + ``si_boundto, HALF', + `si_flags, HALF', + `_,_'') + +DEFINE_STRUCT(`Elf64_Syminfo', + ``si_boundto, HALF', + `si_flags, HALF', + `_,_'') + +DEFINE_STRUCT(`Elf32_Verdaux', + ``vda_name, WORD', + `vda_next, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Verdaux', + ``vda_name, WORD', + `vda_next, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Verdef', + ``vd_version, HALF', + `vd_flags, HALF', + `vd_ndx, HALF', + `vd_cnt, HALF', + `vd_hash, WORD', + `vd_aux, WORD', + `vd_next, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Verdef', + ``vd_version, HALF', + `vd_flags, HALF', + `vd_ndx, HALF', + `vd_cnt, HALF', + `vd_hash, WORD', + `vd_aux, WORD', + `vd_next, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Verneed', + ``vn_version, HALF', + `vn_cnt, HALF', + `vn_file, WORD', + `vn_aux, WORD', + `vn_next, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Verneed', + ``vn_version, HALF', + `vn_cnt, HALF', + `vn_file, WORD', + `vn_aux, WORD', + `vn_next, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf32_Vernaux', + ``vna_hash, WORD', + `vna_flags, HALF', + `vna_other, HALF', + `vna_name, WORD', + `vna_next, WORD', + `_,_'') + +DEFINE_STRUCT(`Elf64_Vernaux', + ``vna_hash, WORD', + `vna_flags, HALF', + `vna_other, HALF', + `vna_name, WORD', + `vna_next, WORD', + `_,_'') diff --git a/ext/libelf/elf_update.c b/ext/libelf/elf_update.c new file mode 100644 index 000000000..6959d3c3e --- /dev/null +++ b/ext/libelf/elf_update.c @@ -0,0 +1,885 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + +#include <sys/mman.h> +#include <sys/param.h> +#ifdef __sun +#include <sys/sysmacros.h> +#endif + +#include <assert.h> +#include <errno.h> +#include "gelf.h" +#include "libelf.h" +#include <stdlib.h> +#include <string.h> +#include <unistd.h> + +#include "_libelf.h" + +/* + * Update the internal data structures associated with an ELF object. + * Returns the size in bytes the ELF object would occupy in its file + * representation. + * + * After a successful call to this function, the following structures + * are updated: + * + * - The ELF header is updated. + * - All sections are sorted in order of ascending addresses and their + * section header table entries updated. An error is signalled + * if an overlap was detected among sections. + * - All data descriptors associated with a section are sorted in order + * of ascending addresses. Overlaps, if detected, are signalled as + * errors. Other sanity checks for alignments, section types etc. are + * made. + * + * After a resync_elf() successfully returns, the ELF descriptor is + * ready for being handed over to _libelf_write_elf(). + * + * File alignments: + * PHDR - Addr + * SHDR - Addr + * + * XXX: how do we handle 'flags'. + */ + +/* + * Compute the extents of a section, by looking at the. + */ +static int +_libelf_compute_section_extents(Elf *e, Elf_Scn *s, off_t *rc) +{ + int ec; + Elf_Data *d, *td; + unsigned int elftype; + uint32_t sh_type; + uint64_t d_align; + uint64_t sh_align, sh_entsize, sh_offset, sh_size; + uint64_t scn_size, scn_alignment; + + /* + * We need to recompute library private data structures if one + * or more of the following is true: + * - The underlying Shdr structure has been marked `dirty'. Significant + * fields include: `sh_offset', `sh_type', `sh_size', `sh_addralign'. + * - The Elf_Data structures part of this section have been marked + * `dirty'. Affected members include `d_align', `d_offset', `d_type', + * and `d_size'. + * - The section as a whole is `dirty', e.g., it has been allocated + * using elf_newscn(), or if a new Elf_Data structure was added using + * elf_newdata(). + * + * Each of these conditions would result in the ELF_F_DIRTY bit being + * set on the section descriptor's `s_flags' field. + */ + + ec = e->e_class; + + if (ec == ELFCLASS32) { + sh_type = s->s_shdr.s_shdr32.sh_type; + sh_align = (uint64_t) s->s_shdr.s_shdr32.sh_addralign; + sh_entsize = (uint64_t) s->s_shdr.s_shdr32.sh_entsize; + sh_offset = (uint64_t) s->s_shdr.s_shdr32.sh_offset; + sh_size = (uint64_t) s->s_shdr.s_shdr32.sh_size; + } else { + sh_type = s->s_shdr.s_shdr64.sh_type; + sh_align = s->s_shdr.s_shdr64.sh_addralign; + sh_entsize = s->s_shdr.s_shdr64.sh_entsize; + sh_offset = s->s_shdr.s_shdr64.sh_offset; + sh_size = s->s_shdr.s_shdr64.sh_size; + } + + if (sh_type == SHT_NULL || sh_type == SHT_NOBITS) + return (1); + + if ((s->s_flags & ELF_F_DIRTY) == 0) { + if ((size_t) *rc < sh_offset + sh_size) + *rc = sh_offset + sh_size; + return (1); + } + + elftype = _libelf_xlate_shtype(sh_type); + if (elftype > ELF_T_LAST) { + LIBELF_SET_ERROR(SECTION, 0); + return (0); + } + + /* + * Compute the extent of the data descriptors associated with + * this section. + */ + scn_alignment = 0; + if (sh_align == 0) + sh_align = _libelf_falign(elftype, ec); + + /* Compute the section alignment. */ + STAILQ_FOREACH(d, &s->s_data, d_next) { + if (d->d_type != elftype) { + LIBELF_SET_ERROR(DATA, 0); + return (0); + } + if (d->d_version != e->e_version) { + LIBELF_SET_ERROR(VERSION, 0); + return (0); + } + if ((d_align = d->d_align) % sh_align) { + LIBELF_SET_ERROR(LAYOUT, 0); + return (0); + } + if (d_align == 0 || (d_align & (d_align - 1))) { + LIBELF_SET_ERROR(DATA, 0); + return (0); + } + if (d_align > scn_alignment) + scn_alignment = d_align; + } + + scn_size = 0L; + + STAILQ_FOREACH_SAFE(d, &s->s_data, d_next, td) { + if (e->e_flags & ELF_F_LAYOUT) { + if ((uint64_t) d->d_off + d->d_size > scn_size) + scn_size = d->d_off + d->d_size; + } else { + scn_size = roundup(scn_size, scn_alignment); + d->d_off = scn_size; + scn_size += d->d_size; + } + } + + /* + * If the application is requesting full control over the layout + * of the section, check its values for sanity. + */ + if (e->e_flags & ELF_F_LAYOUT) { + if (scn_alignment > sh_align || sh_offset % sh_align || + sh_size < scn_size) { + LIBELF_SET_ERROR(LAYOUT, 0); + return (0); + } + } else { + /* + * Otherwise compute the values in the section header. + */ + + if (scn_alignment > sh_align) + sh_align = scn_alignment; + + /* + * If the section entry size is zero, try and fill in an + * appropriate entry size. Per the elf(5) manual page + * sections without fixed-size entries should have their + * 'sh_entsize' field set to zero. + */ + if (sh_entsize == 0 && + (sh_entsize = _libelf_fsize(elftype, ec, e->e_version, + (size_t) 1)) == 1) + sh_entsize = 0; + + sh_size = scn_size; + sh_offset = roundup(*rc, sh_align); + + if (ec == ELFCLASS32) { + s->s_shdr.s_shdr32.sh_addralign = (uint32_t) sh_align; + s->s_shdr.s_shdr32.sh_entsize = (uint32_t) sh_entsize; + s->s_shdr.s_shdr32.sh_offset = (uint32_t) sh_offset; + s->s_shdr.s_shdr32.sh_size = (uint32_t) sh_size; + } else { + s->s_shdr.s_shdr64.sh_addralign = sh_align; + s->s_shdr.s_shdr64.sh_entsize = sh_entsize; + s->s_shdr.s_shdr64.sh_offset = sh_offset; + s->s_shdr.s_shdr64.sh_size = sh_size; + } + } + + if ((size_t) *rc < sh_offset + sh_size) + *rc = sh_offset + sh_size; + + s->s_size = sh_size; + s->s_offset = sh_offset; + return (1); +} + + +/* + * Insert a section in ascending order in the list + */ + +static int +_libelf_insert_section(Elf *e, Elf_Scn *s) +{ + Elf_Scn *t, *prevt; + uint64_t smax, smin, tmax, tmin; + + smin = s->s_offset; + smax = smin + s->s_size; + + prevt = NULL; + STAILQ_FOREACH(t, &e->e_u.e_elf.e_scn, s_next) { + tmin = t->s_offset; + tmax = tmin + t->s_size; + + /* check if there is an overlap */ + if (tmax < smin) { + prevt = t; + continue; + } else if (smax < tmin) + break; + else { + LIBELF_SET_ERROR(LAYOUT, 0); + return (0); + } + } + + if (prevt) + STAILQ_INSERT_AFTER(&e->e_u.e_elf.e_scn, prevt, s, s_next); + else + STAILQ_INSERT_HEAD(&e->e_u.e_elf.e_scn, s, s_next); + return (1); +} + +static off_t +_libelf_resync_sections(Elf *e, off_t rc) +{ + int ec; + off_t nrc; + size_t sh_type; + Elf_Scn *s, *ts; + + ec = e->e_class; + + /* + * Make a pass through sections, computing the extent of each + * section. Order in increasing order of addresses. + */ + + nrc = rc; + STAILQ_FOREACH(s, &e->e_u.e_elf.e_scn, s_next) + if (_libelf_compute_section_extents(e, s, &nrc) == 0) + return ((off_t) -1); + + STAILQ_FOREACH_SAFE(s, &e->e_u.e_elf.e_scn, s_next, ts) { + if (ec == ELFCLASS32) + sh_type = s->s_shdr.s_shdr32.sh_type; + else + sh_type = s->s_shdr.s_shdr64.sh_type; + + /* XXX Do we need the 'size' field of an SHT_NOBITS section */ + if (sh_type == SHT_NOBITS || sh_type == SHT_NULL) + continue; + + if (s->s_offset < (uint64_t) rc) { + if (s->s_offset + s->s_size < (uint64_t) rc) { + /* + * Try insert this section in the + * correct place in the list, + * detecting overlaps if any. + */ + STAILQ_REMOVE(&e->e_u.e_elf.e_scn, s, _Elf_Scn, + s_next); + if (_libelf_insert_section(e, s) == 0) + return ((off_t) -1); + } else { + LIBELF_SET_ERROR(LAYOUT, 0); + return ((off_t) -1); + } + } else + rc = s->s_offset + s->s_size; + } + + assert(nrc == rc); + + return (rc); +} + +static off_t +_libelf_resync_elf(Elf *e) +{ + int ec, eh_class, eh_type; + unsigned int eh_byteorder, eh_version; + size_t align, fsz; + size_t phnum, shnum; + off_t rc, phoff, shoff; + void *ehdr; + Elf32_Ehdr *eh32; + Elf64_Ehdr *eh64; + + rc = 0; + + ec = e->e_class; + + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + /* + * Prepare the EHDR. + */ + if ((ehdr = _libelf_ehdr(e, ec, 0)) == NULL) + return ((off_t) -1); + + eh32 = ehdr; + eh64 = ehdr; + + if (ec == ELFCLASS32) { + eh_byteorder = eh32->e_ident[EI_DATA]; + eh_class = eh32->e_ident[EI_CLASS]; + phoff = (uint64_t) eh32->e_phoff; + shoff = (uint64_t) eh32->e_shoff; + eh_type = eh32->e_type; + eh_version = eh32->e_version; + } else { + eh_byteorder = eh64->e_ident[EI_DATA]; + eh_class = eh64->e_ident[EI_CLASS]; + phoff = eh64->e_phoff; + shoff = eh64->e_shoff; + eh_type = eh64->e_type; + eh_version = eh64->e_version; + } + + if (eh_version == EV_NONE) + eh_version = EV_CURRENT; + + if (eh_version != e->e_version) { /* always EV_CURRENT */ + LIBELF_SET_ERROR(VERSION, 0); + return ((off_t) -1); + } + + if (eh_class != e->e_class) { + LIBELF_SET_ERROR(CLASS, 0); + return ((off_t) -1); + } + + if (e->e_cmd != ELF_C_WRITE && eh_byteorder != e->e_byteorder) { + LIBELF_SET_ERROR(HEADER, 0); + return ((off_t) -1); + } + + shnum = e->e_u.e_elf.e_nscn; + phnum = e->e_u.e_elf.e_nphdr; + + e->e_byteorder = eh_byteorder; + +#define INITIALIZE_EHDR(E,EC,V) do { \ + (E)->e_ident[EI_MAG0] = ELFMAG0; \ + (E)->e_ident[EI_MAG1] = ELFMAG1; \ + (E)->e_ident[EI_MAG2] = ELFMAG2; \ + (E)->e_ident[EI_MAG3] = ELFMAG3; \ + (E)->e_ident[EI_CLASS] = (EC); \ + (E)->e_ident[EI_VERSION] = (V); \ + (E)->e_ehsize = _libelf_fsize(ELF_T_EHDR, (EC), (V), \ + (size_t) 1); \ + (E)->e_phentsize = _libelf_fsize(ELF_T_PHDR, (EC), (V), \ + (size_t) 1); \ + (E)->e_shentsize = _libelf_fsize(ELF_T_SHDR, (EC), (V), \ + (size_t) 1); \ + } while (0) + + if (ec == ELFCLASS32) + INITIALIZE_EHDR(eh32, ec, eh_version); + else + INITIALIZE_EHDR(eh64, ec, eh_version); + + (void) elf_flagehdr(e, ELF_C_SET, ELF_F_DIRTY); + + rc += _libelf_fsize(ELF_T_EHDR, ec, eh_version, (size_t) 1); + + /* + * Compute the layout the program header table, if one is + * present. The program header table needs to be aligned to a + * `natural' boundary. + */ + if (phnum) { + fsz = _libelf_fsize(ELF_T_PHDR, ec, eh_version, phnum); + align = _libelf_falign(ELF_T_PHDR, ec); + + if (e->e_flags & ELF_F_LAYOUT) { + /* + * Check offsets for sanity. + */ + if (rc > phoff) { + LIBELF_SET_ERROR(HEADER, 0); + return ((off_t) -1); + } + + if (phoff % align) { + LIBELF_SET_ERROR(LAYOUT, 0); + return ((off_t) -1); + } + + } else + phoff = roundup(rc, align); + + rc = phoff + fsz; + } else + phoff = 0; + + /* + * Compute the layout of the sections associated with the + * file. + */ + + if ((rc = _libelf_resync_sections(e, rc)) < 0) + return ((off_t) -1); + + /* + * Compute the space taken up by the section header table, if + * one is needed. + */ + if (shnum) { + fsz = _libelf_fsize(ELF_T_SHDR, ec, eh_version, (size_t) 1); + align = _libelf_falign(ELF_T_SHDR, ec); + + if (e->e_flags & ELF_F_LAYOUT) { + if (rc > shoff) { + LIBELF_SET_ERROR(HEADER, 0); + return ((off_t) -1); + } + + if (shoff % align) { + LIBELF_SET_ERROR(LAYOUT, 0); + return ((off_t) -1); + } + } else + shoff = roundup(rc, align); + + rc = shoff + fsz * shnum; + } else + shoff = 0; + + /* + * Set the fields of the Executable Header that could potentially use + * extended numbering. + */ + _libelf_setphnum(e, ehdr, ec, phnum); + _libelf_setshnum(e, ehdr, ec, shnum); + + /* + * Update the `e_phoff' and `e_shoff' fields if the library is + * doing the layout. + */ + if ((e->e_flags & ELF_F_LAYOUT) == 0) { + if (ec == ELFCLASS32) { + eh32->e_phoff = (uint32_t) phoff; + eh32->e_shoff = (uint32_t) shoff; + } else { + eh64->e_phoff = (uint64_t) phoff; + eh64->e_shoff = (uint64_t) shoff; + } + } + + return (rc); +} + +/* + * Write out the contents of a section. + */ + +static off_t +_libelf_write_scn(Elf *e, char *nf, Elf_Scn *s, off_t rc) +{ + int ec; + size_t fsz, msz, nobjects; + uint32_t sh_type; + uint64_t sh_off; + int elftype; + Elf_Data *d, dst; + + if ((ec = e->e_class) == ELFCLASS32) + sh_type = s->s_shdr.s_shdr32.sh_type; + else + sh_type = s->s_shdr.s_shdr64.sh_type; + + /* + * Ignore sections that do not allocate space in the file. + */ + if (sh_type == SHT_NOBITS || sh_type == SHT_NULL) + return (rc); + + + elftype = _libelf_xlate_shtype(sh_type); + assert(elftype >= ELF_T_FIRST && elftype <= ELF_T_LAST); + + msz = _libelf_msize(elftype, ec, e->e_version); + + sh_off = s->s_offset; + assert(sh_off % _libelf_falign(elftype, ec) == 0); + + /* + * If the section has a `rawdata' descriptor, and the section + * contents have not been modified, use its contents directly. + * The `s_rawoff' member contains the offset into the original + * file, while `s_offset' contains its new location in the + * destination. + */ + + if (STAILQ_EMPTY(&s->s_data)) { + + if ((d = elf_rawdata(s, NULL)) == NULL) + return ((off_t) -1); + + STAILQ_FOREACH(d, &s->s_rawdata, d_next) { + if ((uint64_t) rc < sh_off + d->d_off) + (void) memset(nf + rc, + LIBELF_PRIVATE(fillchar), sh_off + + d->d_off - rc); + rc = sh_off + d->d_off; + + assert(d->d_buf != NULL); + assert(d->d_type == ELF_T_BYTE); + assert(d->d_version == e->e_version); + + (void) memcpy(nf + rc, + e->e_rawfile + s->s_rawoff + d->d_off, d->d_size); + + rc += d->d_size; + } + + return (rc); + } + + /* + * Iterate over the set of data descriptors for this section. + * The prior call to _libelf_resync_elf() would have setup the + * descriptors for this step. + */ + + dst.d_version = e->e_version; + + STAILQ_FOREACH(d, &s->s_data, d_next) { + + if ((uint64_t) rc < sh_off + d->d_off) + (void) memset(nf + rc, + LIBELF_PRIVATE(fillchar), sh_off + d->d_off - rc); + + rc = sh_off + d->d_off; + + assert(d->d_buf != NULL); + assert(d->d_type == (Elf_Type) elftype); + assert(d->d_version == e->e_version); + assert(d->d_size % msz == 0); + + nobjects = d->d_size / msz; + + fsz = _libelf_fsize(elftype, ec, e->e_version, nobjects); + + dst.d_buf = nf + rc; + dst.d_size = fsz; + + if (_libelf_xlate(&dst, d, e->e_byteorder, ec, ELF_TOFILE) == + NULL) + return ((off_t) -1); + + rc += fsz; + } + + return ((off_t) rc); +} + +/* + * Write out the file image. + * + * The original file could have been mapped in with an ELF_C_RDWR + * command and the application could have added new content or + * re-arranged its sections before calling elf_update(). Consequently + * its not safe to work `in place' on the original file. So we + * malloc() the required space for the updated ELF object and build + * the object there and write it out to the underlying file at the + * end. Note that the application may have opened the underlying file + * in ELF_C_RDWR and only retrieved/modified a few sections. We take + * care to avoid translating file sections unnecessarily. + * + * Gaps in the coverage of the file by the file's sections will be + * filled with the fill character set by elf_fill(3). + */ + +static off_t +_libelf_write_elf(Elf *e, off_t newsize) +{ + int ec; + off_t rc; + size_t fsz, msz, phnum, shnum; + uint64_t phoff, shoff; + void *ehdr; + char *newfile; + Elf_Data dst, src; + Elf_Scn *scn, *tscn; + Elf32_Ehdr *eh32; + Elf64_Ehdr *eh64; + + assert(e->e_kind == ELF_K_ELF); + assert(e->e_cmd != ELF_C_READ); + assert(e->e_fd >= 0); + + if ((newfile = malloc((size_t) newsize)) == NULL) { + LIBELF_SET_ERROR(RESOURCE, errno); + return ((off_t) -1); + } + + ec = e->e_class; + + ehdr = _libelf_ehdr(e, ec, 0); + assert(ehdr != NULL); + + phnum = e->e_u.e_elf.e_nphdr; + + if (ec == ELFCLASS32) { + eh32 = (Elf32_Ehdr *) ehdr; + + phoff = (uint64_t) eh32->e_phoff; + shnum = eh32->e_shnum; + shoff = (uint64_t) eh32->e_shoff; + } else { + eh64 = (Elf64_Ehdr *) ehdr; + + phoff = eh64->e_phoff; + shnum = eh64->e_shnum; + shoff = eh64->e_shoff; + } + + fsz = _libelf_fsize(ELF_T_EHDR, ec, e->e_version, (size_t) 1); + msz = _libelf_msize(ELF_T_EHDR, ec, e->e_version); + + (void) memset(&dst, 0, sizeof(dst)); + (void) memset(&src, 0, sizeof(src)); + + src.d_buf = ehdr; + src.d_size = msz; + src.d_type = ELF_T_EHDR; + src.d_version = dst.d_version = e->e_version; + + rc = 0; + + dst.d_buf = newfile + rc; + dst.d_size = fsz; + + if (_libelf_xlate(&dst, &src, e->e_byteorder, ec, ELF_TOFILE) == + NULL) + goto error; + + rc += fsz; + + /* + * Write the program header table if present. + */ + + if (phnum != 0 && phoff != 0) { + assert((unsigned) rc <= phoff); + + fsz = _libelf_fsize(ELF_T_PHDR, ec, e->e_version, phnum); + + assert(phoff % _libelf_falign(ELF_T_PHDR, ec) == 0); + assert(fsz > 0); + + src.d_version = dst.d_version = e->e_version; + src.d_type = ELF_T_PHDR; + + if (ec == ELFCLASS32) + src.d_buf = e->e_u.e_elf.e_phdr.e_phdr32; + else + src.d_buf = e->e_u.e_elf.e_phdr.e_phdr64; + + src.d_size = phnum * _libelf_msize(ELF_T_PHDR, ec, + e->e_version); + + dst.d_size = fsz; + + if ((uint64_t) rc < phoff) + (void) memset(newfile + rc, + LIBELF_PRIVATE(fillchar), phoff - rc); + + dst.d_buf = newfile + rc; + + if (_libelf_xlate(&dst, &src, e->e_byteorder, ec, ELF_TOFILE) == + NULL) + goto error; + + rc = phoff + fsz; + } + + /* + * Write out individual sections. + */ + + STAILQ_FOREACH(scn, &e->e_u.e_elf.e_scn, s_next) + if ((rc = _libelf_write_scn(e, newfile, scn, rc)) < 0) + goto error; + + /* + * Write out the section header table, if required. + */ + + if (shnum != 0 && shoff != 0) { + assert((unsigned) rc <= shoff); + + if ((uint64_t) rc < shoff) + (void) memset(newfile + rc, + LIBELF_PRIVATE(fillchar), shoff - rc); + + rc = shoff; + + assert(rc % _libelf_falign(ELF_T_SHDR, ec) == 0); + + src.d_type = ELF_T_SHDR; + src.d_size = _libelf_msize(ELF_T_SHDR, ec, e->e_version); + src.d_version = dst.d_version = e->e_version; + + fsz = _libelf_fsize(ELF_T_SHDR, ec, e->e_version, (size_t) 1); + + STAILQ_FOREACH(scn, &e->e_u.e_elf.e_scn, s_next) { + if (ec == ELFCLASS32) + src.d_buf = &scn->s_shdr.s_shdr32; + else + src.d_buf = &scn->s_shdr.s_shdr64; + + dst.d_size = fsz; + dst.d_buf = newfile + rc; + + if (_libelf_xlate(&dst, &src, e->e_byteorder, ec, + ELF_TOFILE) != &dst) + goto error; + + rc += fsz; + } + } + + /* + */ + + assert(rc == newsize); + + /* + * Write out the constructed contents and remap the file in + * read-only. + */ + + if (e->e_rawfile && munmap(e->e_rawfile, e->e_rawsize) < 0) { + LIBELF_SET_ERROR(IO, errno); + goto error; + } + + if (write(e->e_fd, newfile, (size_t) newsize) != newsize || + lseek(e->e_fd, (off_t) 0, SEEK_SET) < 0) { + LIBELF_SET_ERROR(IO, errno); + goto error; + } + + if (e->e_cmd != ELF_C_WRITE) { + if ((e->e_rawfile = mmap(NULL, (size_t) newsize, PROT_READ, + MAP_PRIVATE, e->e_fd, (off_t) 0)) == MAP_FAILED) { + LIBELF_SET_ERROR(IO, errno); + goto error; + } + e->e_rawsize = newsize; + } + + /* + * Reset flags, remove existing section descriptors and + * {E,P}HDR pointers so that a subsequent elf_get{e,p}hdr() + * and elf_getscn() will function correctly. + */ + + e->e_flags &= ~ELF_F_DIRTY; + + STAILQ_FOREACH_SAFE(scn, &e->e_u.e_elf.e_scn, s_next, tscn) + _libelf_release_scn(scn); + + if (ec == ELFCLASS32) { + free(e->e_u.e_elf.e_ehdr.e_ehdr32); + if (e->e_u.e_elf.e_phdr.e_phdr32) + free(e->e_u.e_elf.e_phdr.e_phdr32); + + e->e_u.e_elf.e_ehdr.e_ehdr32 = NULL; + e->e_u.e_elf.e_phdr.e_phdr32 = NULL; + } else { + free(e->e_u.e_elf.e_ehdr.e_ehdr64); + if (e->e_u.e_elf.e_phdr.e_phdr64) + free(e->e_u.e_elf.e_phdr.e_phdr64); + + e->e_u.e_elf.e_ehdr.e_ehdr64 = NULL; + e->e_u.e_elf.e_phdr.e_phdr64 = NULL; + } + + return (rc); + + error: + if (newfile) + free(newfile); + return ((off_t) -1); +} + +off_t +elf_update(Elf *e, Elf_Cmd c) +{ + int ec; + off_t rc; + + rc = (off_t) -1; + + if (e == NULL || e->e_kind != ELF_K_ELF || + (c != ELF_C_NULL && c != ELF_C_WRITE)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (rc); + } + + if ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64) { + LIBELF_SET_ERROR(CLASS, 0); + return (rc); + } + + if (e->e_version == EV_NONE) + e->e_version = EV_CURRENT; + + if (c == ELF_C_WRITE && e->e_cmd == ELF_C_READ) { + LIBELF_SET_ERROR(MODE, 0); + return (rc); + } + + if ((rc = _libelf_resync_elf(e)) < 0) + return (rc); + + if (c == ELF_C_NULL) + return (rc); + + if (e->e_cmd == ELF_C_READ) { + /* + * This descriptor was opened in read-only mode or by + * elf_memory(). + */ + if (e->e_fd) + LIBELF_SET_ERROR(MODE, 0); + else + LIBELF_SET_ERROR(ARGUMENT, 0); + return ((off_t) -1); + } + + if (e->e_fd < 0) { + LIBELF_SET_ERROR(SEQUENCE, 0); + return ((off_t) -1); + } + + return (_libelf_write_elf(e, rc)); +} diff --git a/ext/libelf/elf_version.c b/ext/libelf/elf_version.c new file mode 100644 index 000000000..e4c1e7d36 --- /dev/null +++ b/ext/libelf/elf_version.c @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "libelf.h" +#include "_libelf.h" + +unsigned int +elf_version(unsigned int v) +{ + unsigned int old; + + if ((old = LIBELF_PRIVATE(version)) == EV_NONE) + old = EV_CURRENT; + + if (v == EV_NONE) + return old; + if (v > EV_CURRENT) { + LIBELF_SET_ERROR(VERSION, 0); + return EV_NONE; + } + + LIBELF_PRIVATE(version) = v; + return (old); +} diff --git a/ext/libelf/gelf.h b/ext/libelf/gelf.h new file mode 100644 index 000000000..6ccb87f93 --- /dev/null +++ b/ext/libelf/gelf.h @@ -0,0 +1,113 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/libelf/gelf.h,v 1.3 2007/03/08 04:01:30 jkoshy Exp $ + */ + +#ifndef _GELF_H_ +#define _GELF_H_ + + +#include "libelf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef Elf64_Addr GElf_Addr; /* Addresses */ +typedef Elf64_Half GElf_Half; /* Half words (16 bit) */ +typedef Elf64_Off GElf_Off; /* Offsets */ +typedef Elf64_Sword GElf_Sword; /* Signed words (32 bit) */ +typedef Elf64_Sxword GElf_Sxword; /* Signed long words (64 bit) */ +typedef Elf64_Word GElf_Word; /* Unsigned words (32 bit) */ +typedef Elf64_Xword GElf_Xword; /* Unsigned long words (64 bit) */ + +typedef Elf64_Dyn GElf_Dyn; /* ".dynamic" section entries */ +typedef Elf64_Ehdr GElf_Ehdr; /* ELF header */ +typedef Elf64_Phdr GElf_Phdr; /* Program header */ +typedef Elf64_Shdr GElf_Shdr; /* Section header */ +typedef Elf64_Sym GElf_Sym; /* Symbol table entries */ +typedef Elf64_Rel GElf_Rel; /* Relocation entries */ +typedef Elf64_Rela GElf_Rela; /* Relocation entries with addend */ + +typedef Elf64_Cap GElf_Cap; /* SW/HW capabilities */ +typedef Elf64_Move GElf_Move; /* Move entries */ +typedef Elf64_Syminfo GElf_Syminfo; /* Symbol information */ + +#define GELF_M_INFO ELF64_M_INFO +#define GELF_M_SIZE ELF64_M_SIZE +#define GELF_M_SYM ELF64_M_SYM + +#define GELF_R_INFO ELF64_R_INFO +#define GELF_R_SYM ELF64_R_SYM +#define GELF_R_TYPE ELF64_R_TYPE +#define GELF_R_TYPE_DATA ELF64_R_TYPE_DATA +#define GELF_R_TYPE_ID ELF64_R_TYPE_ID +#define GELF_R_TYPE_INFO ELF64_R_TYPE_INFO + +#define GELF_ST_BIND ELF64_ST_BIND +#define GELF_ST_INFO ELF64_ST_INFO +#define GELF_ST_TYPE ELF64_ST_TYPE +#define GELF_ST_VISIBILITY ELF64_ST_VISIBILITY + +long gelf_checksum(Elf *_elf); +size_t gelf_fsize(Elf *_elf, Elf_Type _type, size_t _count, + unsigned int _version); +int gelf_getclass(Elf *_elf); +GElf_Dyn *gelf_getdyn(Elf_Data *_data, int _index, GElf_Dyn *_dst); +GElf_Ehdr *gelf_getehdr(Elf *_elf, GElf_Ehdr *_dst); +GElf_Phdr *gelf_getphdr(Elf *_elf, int _index, GElf_Phdr *_dst); +GElf_Rel *gelf_getrel(Elf_Data *_src, int _index, GElf_Rel *_dst); +GElf_Rela *gelf_getrela(Elf_Data *_src, int _index, GElf_Rela *_dst); +GElf_Shdr *gelf_getshdr(Elf_Scn *_scn, GElf_Shdr *_dst); +GElf_Sym *gelf_getsym(Elf_Data *_src, int _index, GElf_Sym *_dst); +GElf_Sym *gelf_getsymshndx(Elf_Data *_src, Elf_Data *_shindexsrc, + int _index, GElf_Sym *_dst, Elf32_Word *_shindexdst); +void * gelf_newehdr(Elf *_elf, int _class); +void * gelf_newphdr(Elf *_elf, size_t _phnum); +int gelf_update_dyn(Elf_Data *_dst, int _index, GElf_Dyn *_src); +int gelf_update_ehdr(Elf *_elf, GElf_Ehdr *_src); +int gelf_update_phdr(Elf *_elf, int _index, GElf_Phdr *_src); +int gelf_update_rel(Elf_Data *_dst, int _index, GElf_Rel *_src); +int gelf_update_rela(Elf_Data *_dst, int _index, GElf_Rela *_src); +int gelf_update_shdr(Elf_Scn *_dst, GElf_Shdr *_src); +int gelf_update_sym(Elf_Data *_dst, int _index, GElf_Sym *_src); +int gelf_update_symshndx(Elf_Data *_symdst, Elf_Data *_shindexdst, + int _index, GElf_Sym *_symsrc, Elf32_Word _shindexsrc); +Elf_Data *gelf_xlatetof(Elf *_elf, Elf_Data *_dst, const Elf_Data *_src, unsigned int _encode); +Elf_Data *gelf_xlatetom(Elf *_elf, Elf_Data *_dst, const Elf_Data *_src, unsigned int _encode); + +GElf_Cap *gelf_getcap(Elf_Data *_data, int _index, GElf_Cap *_cap); +GElf_Move *gelf_getmove(Elf_Data *_src, int _index, GElf_Move *_dst); +GElf_Syminfo *gelf_getsyminfo(Elf_Data *_src, int _index, GElf_Syminfo *_dst); +int gelf_update_cap(Elf_Data *_dst, int _index, GElf_Cap *_src); +int gelf_update_move(Elf_Data *_dst, int _index, GElf_Move *_src); +int gelf_update_syminfo(Elf_Data *_dst, int _index, GElf_Syminfo *_src); + +#ifdef __cplusplus +} +#endif + +#endif /* _GELF_H_ */ diff --git a/ext/libelf/gelf_checksum.c b/ext/libelf/gelf_checksum.c new file mode 100644 index 000000000..105cd2883 --- /dev/null +++ b/ext/libelf/gelf_checksum.c @@ -0,0 +1,54 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "gelf.h" +#include "libelf.h" + +#include "_libelf.h" + +long +elf32_checksum(Elf *e) +{ + return (_libelf_checksum(e, ELFCLASS32)); +} + +long +elf64_checksum(Elf *e) +{ + return (_libelf_checksum(e, ELFCLASS64)); +} + +long +gelf_checksum(Elf *e) +{ + int ec; + if (e == NULL || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0L); + } + return (_libelf_checksum(e, ec)); +} diff --git a/ext/libelf/gelf_dyn.c b/ext/libelf/gelf_dyn.c new file mode 100644 index 000000000..982068099 --- /dev/null +++ b/ext/libelf/gelf_dyn.c @@ -0,0 +1,140 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <assert.h> +#include <limits.h> + +#include "gelf.h" +#include "_libelf.h" + +GElf_Dyn * +gelf_getdyn(Elf_Data *d, int ndx, GElf_Dyn *dst) +{ + int ec; + Elf *e; + Elf_Scn *scn; + Elf32_Dyn *dyn32; + Elf64_Dyn *dyn64; + size_t msz; + uint32_t sh_type; + + if (d == NULL || ndx < 0 || dst == NULL || + (scn = d->d_scn) == NULL || + (e = scn->s_elf) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_DYN) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + msz = _libelf_msize(ELF_T_DYN, ec, e->e_version); + + assert(msz > 0); + + if (msz * ndx >= d->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (ec == ELFCLASS32) { + dyn32 = (Elf32_Dyn *) d->d_buf + ndx; + + dst->d_tag = dyn32->d_tag; + dst->d_un.d_val = (Elf64_Xword) dyn32->d_un.d_val; + + } else { + + dyn64 = (Elf64_Dyn *) d->d_buf + ndx; + + *dst = *dyn64; + } + + return (dst); +} + +int +gelf_update_dyn(Elf_Data *d, int ndx, GElf_Dyn *ds) +{ + int ec; + Elf *e; + Elf_Scn *scn; + Elf32_Dyn *dyn32; + Elf64_Dyn *dyn64; + size_t msz; + uint32_t sh_type; + + if (d == NULL || ndx < 0 || ds == NULL || + (scn = d->d_scn) == NULL || + (e = scn->s_elf) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_DYN) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + msz = _libelf_msize(ELF_T_DYN, ec, e->e_version); + assert(msz > 0); + + if (msz * ndx >= d->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (ec == ELFCLASS32) { + dyn32 = (Elf32_Dyn *) d->d_buf + ndx; + + LIBELF_COPY_S32(dyn32, ds, d_tag); + LIBELF_COPY_U32(dyn32, ds, d_un.d_val); + } else { + dyn64 = (Elf64_Dyn *) d->d_buf + ndx; + + *dyn64 = *ds; + } + + return (1); +} diff --git a/ext/libelf/gelf_ehdr.c b/ext/libelf/gelf_ehdr.c new file mode 100644 index 000000000..c410f4a15 --- /dev/null +++ b/ext/libelf/gelf_ehdr.c @@ -0,0 +1,164 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <limits.h> + +#include <assert.h> +#include "gelf.h" +#include "libelf.h" +#include <string.h> + +#include "_libelf.h" + +Elf32_Ehdr * +elf32_getehdr(Elf *e) +{ + return (_libelf_ehdr(e, ELFCLASS32, 0)); +} + +Elf64_Ehdr * +elf64_getehdr(Elf *e) +{ + return (_libelf_ehdr(e, ELFCLASS64, 0)); +} + +GElf_Ehdr * +gelf_getehdr(Elf *e, GElf_Ehdr *d) +{ + int ec; + Elf32_Ehdr *eh32; + Elf64_Ehdr *eh64; + + if (d == NULL || e == NULL || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (ec == ELFCLASS32) { + if ((eh32 = _libelf_ehdr(e, ELFCLASS32, 0)) == NULL) + return (NULL); + + (void) memcpy(d->e_ident, eh32->e_ident, sizeof(eh32->e_ident)); + d->e_type = eh32->e_type; + d->e_machine = eh32->e_machine; + d->e_version = eh32->e_version; + d->e_entry = eh32->e_entry; + d->e_phoff = eh32->e_phoff; + d->e_shoff = eh32->e_shoff; + d->e_flags = eh32->e_flags; + d->e_ehsize = eh32->e_ehsize; + d->e_phentsize = eh32->e_phentsize; + d->e_phnum = eh32->e_phnum; + d->e_shentsize = eh32->e_shentsize; + d->e_shnum = eh32->e_shnum; + d->e_shstrndx = eh32->e_shstrndx; + + return (d); + } + + assert(ec == ELFCLASS64); + + if ((eh64 = _libelf_ehdr(e, ELFCLASS64, 0)) == NULL) + return (NULL); + *d = *eh64; + + return (d); +} + +Elf32_Ehdr * +elf32_newehdr(Elf *e) +{ + return (_libelf_ehdr(e, ELFCLASS32, 1)); +} + +Elf64_Ehdr * +elf64_newehdr(Elf *e) +{ + return (_libelf_ehdr(e, ELFCLASS64, 1)); +} + +void * +gelf_newehdr(Elf *e, int ec) +{ + if (e != NULL && + (ec == ELFCLASS32 || ec == ELFCLASS64)) + return (_libelf_ehdr(e, ec, 1)); + + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); +} + +int +gelf_update_ehdr(Elf *e, GElf_Ehdr *s) +{ + int ec; + void *ehdr; + Elf32_Ehdr *eh32; + Elf64_Ehdr *eh64; + + if (s== NULL || e == NULL || e->e_kind != ELF_K_ELF || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (e->e_cmd == ELF_C_READ) { + LIBELF_SET_ERROR(MODE, 0); + return (0); + } + + if ((ehdr = _libelf_ehdr(e, ec, 0)) == NULL) + return (0); + + if (ec == ELFCLASS64) { + eh64 = (Elf64_Ehdr *) ehdr; + *eh64 = *s; + return (1); + } + + eh32 = (Elf32_Ehdr *) ehdr; + + (void) memcpy(eh32->e_ident, s->e_ident, sizeof(eh32->e_ident)); + + eh32->e_type = s->e_type; + eh32->e_machine = s->e_machine; + eh32->e_version = s->e_version; + LIBELF_COPY_U32(eh32, s, e_entry); + LIBELF_COPY_U32(eh32, s, e_phoff); + LIBELF_COPY_U32(eh32, s, e_shoff); + eh32->e_flags = s->e_flags; + eh32->e_ehsize = s->e_ehsize; + eh32->e_phentsize = s->e_phentsize; + eh32->e_phnum = s->e_phnum; + eh32->e_shentsize = s->e_shentsize; + eh32->e_shnum = s->e_shnum; + eh32->e_shstrndx = s->e_shstrndx; + + (void) elf_flagehdr(e, ELF_C_SET, ELF_F_DIRTY); + + return (1); +} diff --git a/ext/libelf/gelf_fsize.c b/ext/libelf/gelf_fsize.c new file mode 100644 index 000000000..06add0733 --- /dev/null +++ b/ext/libelf/gelf_fsize.c @@ -0,0 +1,58 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "gelf.h" +#include "libelf.h" + +#include "_libelf.h" + +size_t +elf32_fsize(Elf_Type t, size_t c, unsigned int v) +{ + return (_libelf_fsize(t, ELFCLASS32, v, c)); +} + +size_t +elf64_fsize(Elf_Type t, size_t c, unsigned int v) +{ + return (_libelf_fsize(t, ELFCLASS64, v, c)); +} + +size_t +gelf_fsize(Elf *e, Elf_Type t, size_t c, unsigned int v) +{ + + if (e == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (e->e_class == ELFCLASS32 || e->e_class == ELFCLASS64) + return (_libelf_fsize(t, e->e_class, v, c)); + + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); +} diff --git a/ext/libelf/gelf_getclass.c b/ext/libelf/gelf_getclass.c new file mode 100644 index 000000000..96f2007a6 --- /dev/null +++ b/ext/libelf/gelf_getclass.c @@ -0,0 +1,35 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "gelf.h" + +#include "_libelf.h" + +int +gelf_getclass(Elf *e) +{ + return (e != NULL ? e->e_class : ELFCLASSNONE); +} diff --git a/ext/libelf/gelf_phdr.c b/ext/libelf/gelf_phdr.c new file mode 100644 index 000000000..6125ec671 --- /dev/null +++ b/ext/libelf/gelf_phdr.c @@ -0,0 +1,175 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <limits.h> + +#include "gelf.h" +#include "libelf.h" + +#include "_libelf.h" + +Elf32_Phdr * +elf32_getphdr(Elf *e) +{ + return (_libelf_getphdr(e, ELFCLASS32)); +} + +Elf64_Phdr * +elf64_getphdr(Elf *e) +{ + return (_libelf_getphdr(e, ELFCLASS64)); +} + +GElf_Phdr * +gelf_getphdr(Elf *e, int index, GElf_Phdr *d) +{ + int ec; + Elf32_Ehdr *eh32; + Elf64_Ehdr *eh64; + Elf32_Phdr *ep32; + Elf64_Phdr *ep64; + + if (d == NULL || e == NULL || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64) || + (e->e_kind != ELF_K_ELF) || index < 0) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (ec == ELFCLASS32) { + if ((eh32 = _libelf_ehdr(e, ELFCLASS32, 0)) == NULL || + ((ep32 = _libelf_getphdr(e, ELFCLASS32)) == NULL)) + return (NULL); + + if (index >= eh32->e_phnum) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + ep32 += index; + + d->p_type = ep32->p_type; + d->p_offset = ep32->p_offset; + d->p_vaddr = (Elf64_Addr) ep32->p_vaddr; + d->p_paddr = (Elf64_Addr) ep32->p_paddr; + d->p_filesz = (Elf64_Xword) ep32->p_filesz; + d->p_memsz = (Elf64_Xword) ep32->p_memsz; + d->p_flags = ep32->p_flags; + d->p_align = (Elf64_Xword) ep32->p_align; + + } else { + if ((eh64 = _libelf_ehdr(e, ELFCLASS64, 0)) == NULL || + (ep64 = _libelf_getphdr(e, ELFCLASS64)) == NULL) + return (NULL); + + if (index >= eh64->e_phnum) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + ep64 += index; + + *d = *ep64; + } + + return (d); +} + +Elf32_Phdr * +elf32_newphdr(Elf *e, size_t count) +{ + return (_libelf_newphdr(e, ELFCLASS32, count)); +} + +Elf64_Phdr * +elf64_newphdr(Elf *e, size_t count) +{ + return (_libelf_newphdr(e, ELFCLASS64, count)); +} + +void * +gelf_newphdr(Elf *e, size_t count) +{ + if (e == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + return (_libelf_newphdr(e, e->e_class, count)); +} + +int +gelf_update_phdr(Elf *e, int ndx, GElf_Phdr *s) +{ + int ec, phnum; + void *ehdr; + Elf32_Phdr *ph32; + Elf64_Phdr *ph64; + + if (s == NULL || e == NULL || e->e_kind != ELF_K_ELF || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (e->e_cmd == ELF_C_READ) { + LIBELF_SET_ERROR(MODE, 0); + return (0); + } + + if ((ehdr = _libelf_ehdr(e, ec, 0)) == NULL) + return (0); + + if (ec == ELFCLASS32) + phnum = ((Elf32_Ehdr *) ehdr)->e_phnum; + else + phnum = ((Elf64_Ehdr *) ehdr)->e_phnum; + + if (ndx < 0 || ndx > phnum) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (ec == ELFCLASS64) { + ph64 = e->e_u.e_elf.e_phdr.e_phdr64 + ndx; + *ph64 = *s; + return (1); + } + + ph32 = e->e_u.e_elf.e_phdr.e_phdr32 + ndx; + + ph32->p_type = s->p_type; + ph32->p_flags = s->p_flags; + LIBELF_COPY_U32(ph32, s, p_offset); + LIBELF_COPY_U32(ph32, s, p_vaddr); + LIBELF_COPY_U32(ph32, s, p_paddr); + LIBELF_COPY_U32(ph32, s, p_filesz); + LIBELF_COPY_U32(ph32, s, p_memsz); + LIBELF_COPY_U32(ph32, s, p_align); + + (void) elf_flagphdr(e, ELF_C_SET, ELF_F_DIRTY); + + return (1); +} diff --git a/ext/libelf/gelf_rel.c b/ext/libelf/gelf_rel.c new file mode 100644 index 000000000..560613805 --- /dev/null +++ b/ext/libelf/gelf_rel.c @@ -0,0 +1,141 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <limits.h> + +#include <assert.h> +#include "gelf.h" + +#include "_libelf.h" + +GElf_Rel * +gelf_getrel(Elf_Data *d, int ndx, GElf_Rel *dst) +{ + int ec; + Elf *e; + Elf_Scn *scn; + Elf32_Rel *rel32; + Elf64_Rel *rel64; + size_t msz; + uint32_t sh_type; + + if (d == NULL || ndx < 0 || dst == NULL || + (scn = d->d_scn) == NULL || + (e = scn->s_elf) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_REL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + msz = _libelf_msize(ELF_T_REL, ec, e->e_version); + + assert(msz > 0); + + if (msz * ndx >= d->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (ec == ELFCLASS32) { + rel32 = (Elf32_Rel *) d->d_buf + ndx; + + dst->r_offset = (Elf64_Addr) rel32->r_offset; + dst->r_info = (Elf64_Xword) rel32->r_info; + + } else { + + rel64 = (Elf64_Rel *) d->d_buf + ndx; + + *dst = *rel64; + } + + return (dst); +} + +int +gelf_update_rel(Elf_Data *d, int ndx, GElf_Rel *dr) +{ + int ec; + Elf *e; + Elf_Scn *scn; + Elf32_Rel *rel32; + Elf64_Rel *rel64; + size_t msz; + uint32_t sh_type; + + if (d == NULL || ndx < 0 || dr == NULL || + (scn = d->d_scn) == NULL || + (e = scn->s_elf) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_REL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + msz = _libelf_msize(ELF_T_REL, ec, e->e_version); + assert(msz > 0); + + if (msz * ndx >= d->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (ec == ELFCLASS32) { + rel32 = (Elf32_Rel *) d->d_buf + ndx; + + LIBELF_COPY_U32(rel32, dr, r_offset); + LIBELF_COPY_U32(rel32, dr, r_info); + } else { + rel64 = (Elf64_Rel *) d->d_buf + ndx; + + *rel64 = *dr; + } + + return (1); +} diff --git a/ext/libelf/gelf_rela.c b/ext/libelf/gelf_rela.c new file mode 100644 index 000000000..fbd2a2cc8 --- /dev/null +++ b/ext/libelf/gelf_rela.c @@ -0,0 +1,143 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <limits.h> + +#include <assert.h> +#include "gelf.h" + +#include "_libelf.h" + +GElf_Rela * +gelf_getrela(Elf_Data *d, int ndx, GElf_Rela *dst) +{ + int ec; + Elf *e; + Elf_Scn *scn; + Elf32_Rela *rela32; + Elf64_Rela *rela64; + size_t msz; + uint32_t sh_type; + + if (d == NULL || ndx < 0 || dst == NULL || + (scn = d->d_scn) == NULL || + (e = scn->s_elf) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_RELA) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + msz = _libelf_msize(ELF_T_RELA, ec, e->e_version); + + assert(msz > 0); + + if (msz * ndx >= d->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (ec == ELFCLASS32) { + rela32 = (Elf32_Rela *) d->d_buf + ndx; + + dst->r_offset = (Elf64_Addr) rela32->r_offset; + dst->r_info = (Elf64_Xword) rela32->r_info; + dst->r_addend = (Elf64_Sxword) rela32->r_addend; + + } else { + + rela64 = (Elf64_Rela *) d->d_buf + ndx; + + *dst = *rela64; + } + + return (dst); +} + +int +gelf_update_rela(Elf_Data *d, int ndx, GElf_Rela *dr) +{ + int ec; + Elf *e; + Elf_Scn *scn; + Elf32_Rela *rela32; + Elf64_Rela *rela64; + size_t msz; + uint32_t sh_type; + + if (d == NULL || ndx < 0 || dr == NULL || + (scn = d->d_scn) == NULL || + (e = scn->s_elf) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_RELA) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + msz = _libelf_msize(ELF_T_RELA, ec, e->e_version); + assert(msz > 0); + + if (msz * ndx >= d->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (ec == ELFCLASS32) { + rela32 = (Elf32_Rela *) d->d_buf + ndx; + + LIBELF_COPY_U32(rela32, dr, r_offset); + LIBELF_COPY_U32(rela32, dr, r_info); + LIBELF_COPY_S32(rela32, dr, r_addend); + } else { + rela64 = (Elf64_Rela *) d->d_buf + ndx; + + *rela64 = *dr; + } + + return (1); +} diff --git a/ext/libelf/gelf_shdr.c b/ext/libelf/gelf_shdr.c new file mode 100644 index 000000000..16d6434f3 --- /dev/null +++ b/ext/libelf/gelf_shdr.c @@ -0,0 +1,128 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <limits.h> + +#include <assert.h> +#include "gelf.h" +#include "libelf.h" + +#include "_libelf.h" + +Elf32_Shdr * +elf32_getshdr(Elf_Scn *s) +{ + return (_libelf_getshdr(s, ELFCLASS32)); +} + +Elf64_Shdr * +elf64_getshdr(Elf_Scn *s) +{ + return (_libelf_getshdr(s, ELFCLASS64)); +} + +GElf_Shdr * +gelf_getshdr(Elf_Scn *s, GElf_Shdr *d) +{ + int ec; + void *sh; + Elf32_Shdr *sh32; + Elf64_Shdr *sh64; + + if (d == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if ((sh = _libelf_getshdr(s, ELFCLASSNONE)) == NULL) + return (NULL); + + ec = s->s_elf->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) { + sh32 = (Elf32_Shdr *) sh; + + d->sh_name = sh32->sh_name; + d->sh_type = sh32->sh_type; + d->sh_flags = (Elf64_Xword) sh32->sh_flags; + d->sh_addr = (Elf64_Addr) sh32->sh_addr; + d->sh_offset = (Elf64_Off) sh32->sh_offset; + d->sh_size = (Elf64_Xword) sh32->sh_size; + d->sh_link = sh32->sh_link; + d->sh_info = sh32->sh_info; + d->sh_addralign = (Elf64_Xword) sh32->sh_addralign; + d->sh_entsize = (Elf64_Xword) sh32->sh_entsize; + } else { + sh64 = (Elf64_Shdr *) sh; + *d = *sh64; + } + + return (d); +} + +int +gelf_update_shdr(Elf_Scn *scn, GElf_Shdr *s) +{ + int ec; + Elf *e; + Elf32_Shdr *sh32; + + + if (s == NULL || scn == NULL || (e = scn->s_elf) == NULL || + e->e_kind != ELF_K_ELF || + ((ec = e->e_class) != ELFCLASS32 && ec != ELFCLASS64)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (e->e_cmd == ELF_C_READ) { + LIBELF_SET_ERROR(MODE, 0); + return (0); + } + + if (ec == ELFCLASS64) { + scn->s_shdr.s_shdr64 = *s; + return (1); + } + + sh32 = &scn->s_shdr.s_shdr32; + + sh32->sh_name = s->sh_name; + sh32->sh_type = s->sh_type; + LIBELF_COPY_U32(sh32, s, sh_flags); + LIBELF_COPY_U32(sh32, s, sh_addr); + LIBELF_COPY_U32(sh32, s, sh_offset); + LIBELF_COPY_U32(sh32, s, sh_size); + sh32->sh_link = s->sh_link; + sh32->sh_info = s->sh_info; + LIBELF_COPY_U32(sh32, s, sh_addralign); + LIBELF_COPY_U32(sh32, s, sh_entsize); + + (void) elf_flagscn(scn, ELF_C_SET, ELF_F_DIRTY); + + return (1); +} diff --git a/ext/libelf/gelf_sym.c b/ext/libelf/gelf_sym.c new file mode 100644 index 000000000..78c8a087c --- /dev/null +++ b/ext/libelf/gelf_sym.c @@ -0,0 +1,151 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <limits.h> + +#include <assert.h> +#include "gelf.h" + +#include "_libelf.h" + +GElf_Sym * +gelf_getsym(Elf_Data *d, int ndx, GElf_Sym *dst) +{ + int ec; + Elf *e; + Elf_Scn *scn; + Elf32_Sym *sym32; + Elf64_Sym *sym64; + size_t msz; + uint32_t sh_type; + + if (d == NULL || ndx < 0 || dst == NULL || + (scn = d->d_scn) == NULL || + (e = scn->s_elf) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_SYM) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + msz = _libelf_msize(ELF_T_SYM, ec, e->e_version); + + assert(msz > 0); + + if (msz * ndx >= d->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (ec == ELFCLASS32) { + + sym32 = (Elf32_Sym *) d->d_buf + ndx; + + dst->st_name = sym32->st_name; + dst->st_value = (Elf64_Addr) sym32->st_value; + dst->st_size = (Elf64_Xword) sym32->st_size; + dst->st_info = ELF64_ST_INFO(ELF32_ST_BIND(sym32->st_info), + ELF32_ST_TYPE(sym32->st_info)); + dst->st_other = sym32->st_other; + dst->st_shndx = sym32->st_shndx; + } else { + + sym64 = (Elf64_Sym *) d->d_buf + ndx; + + *dst = *sym64; + } + + return (dst); +} + +int +gelf_update_sym(Elf_Data *d, int ndx, GElf_Sym *gs) +{ + int ec; + Elf *e; + Elf_Scn *scn; + Elf32_Sym *sym32; + Elf64_Sym *sym64; + size_t msz; + uint32_t sh_type; + + if (d == NULL || ndx < 0 || gs == NULL || + (scn = d->d_scn) == NULL || + (e = scn->s_elf) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_SYM) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + msz = _libelf_msize(ELF_T_SYM, ec, e->e_version); + assert(msz > 0); + + if (msz * ndx >= d->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + if (ec == ELFCLASS32) { + sym32 = (Elf32_Sym *) d->d_buf + ndx; + + sym32->st_name = gs->st_name; + sym32->st_info = gs->st_info; + sym32->st_other = gs->st_other; + sym32->st_shndx = gs->st_shndx; + + LIBELF_COPY_U32(sym32, gs, st_value); + LIBELF_COPY_U32(sym32, gs, st_size); + } else { + sym64 = (Elf64_Sym *) d->d_buf + ndx; + + *sym64 = *gs; + } + + return (1); +} diff --git a/ext/libelf/gelf_symshndx.c b/ext/libelf/gelf_symshndx.c new file mode 100644 index 000000000..ec948fd75 --- /dev/null +++ b/ext/libelf/gelf_symshndx.c @@ -0,0 +1,126 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <limits.h> + +#include <assert.h> +#include "gelf.h" + +#include "_libelf.h" + +GElf_Sym * +gelf_getsymshndx(Elf_Data *d, Elf_Data *id, int ndx, GElf_Sym *dst, + Elf32_Word *shindex) +{ + int ec; + Elf *e; + Elf_Scn *scn; + size_t msz; + uint32_t sh_type; + + if (gelf_getsym(d, ndx, dst) == 0) + return (NULL); + + if (id == NULL || (scn = id->d_scn) == NULL || + (e = scn->s_elf) == NULL || (e != d->d_scn->s_elf) || + shindex == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_WORD || + id->d_type != ELF_T_WORD) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + msz = _libelf_msize(ELF_T_WORD, ec, e->e_version); + + assert(msz > 0); + + if (msz * ndx >= id->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + *shindex = ((Elf32_Word *) id->d_buf)[ndx]; + + return (dst); +} + +int +gelf_update_symshndx(Elf_Data *d, Elf_Data *id, int ndx, GElf_Sym *gs, + Elf32_Word xindex) +{ + int ec; + Elf *e; + Elf_Scn *scn; + size_t msz; + uint32_t sh_type; + + if (gelf_update_sym(d, ndx, gs) == 0) + return (0); + + if (id == NULL || (scn = id->d_scn) == NULL || + (e = scn->s_elf) == NULL || (e != d->d_scn->s_elf)) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + ec = e->e_class; + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (ec == ELFCLASS32) + sh_type = scn->s_shdr.s_shdr32.sh_type; + else + sh_type = scn->s_shdr.s_shdr64.sh_type; + + if (_libelf_xlate_shtype(sh_type) != ELF_T_WORD || + d->d_type != ELF_T_WORD) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + msz = _libelf_msize(ELF_T_WORD, ec, e->e_version); + assert(msz > 0); + + if (msz * ndx >= id->d_size) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0); + } + + *(((Elf32_Word *) id->d_buf) + ndx) = xindex; + + return (1); +} diff --git a/ext/libelf/gelf_xlate.c b/ext/libelf/gelf_xlate.c new file mode 100644 index 000000000..8ab98ad55 --- /dev/null +++ b/ext/libelf/gelf_xlate.c @@ -0,0 +1,76 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "gelf.h" +#include "libelf.h" +#include <string.h> + +#include "_libelf.h" + + +Elf_Data * +elf32_xlatetof(Elf_Data *dst, const Elf_Data *src, unsigned int encoding) +{ + return _libelf_xlate(dst, src, encoding, ELFCLASS32, ELF_TOFILE); +} + +Elf_Data * +elf64_xlatetof(Elf_Data *dst, const Elf_Data *src, unsigned int encoding) +{ + return _libelf_xlate(dst, src, encoding, ELFCLASS64, ELF_TOFILE); +} + +Elf_Data * +elf32_xlatetom(Elf_Data *dst, const Elf_Data *src, unsigned int encoding) +{ + return _libelf_xlate(dst, src, encoding, ELFCLASS32, ELF_TOMEMORY); +} + +Elf_Data * +elf64_xlatetom(Elf_Data *dst, const Elf_Data *src, unsigned int encoding) +{ + return _libelf_xlate(dst, src, encoding, ELFCLASS64, ELF_TOMEMORY); +} + +Elf_Data * +gelf_xlatetom(Elf *e, Elf_Data *dst, const Elf_Data *src, unsigned int encoding) +{ + if (e != NULL) + return (_libelf_xlate(dst, src, encoding, e->e_class, + ELF_TOMEMORY)); + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); +} + +Elf_Data * +gelf_xlatetof(Elf *e, Elf_Data *dst, const Elf_Data *src, unsigned int encoding) +{ + if (e != NULL) + return (_libelf_xlate(dst, src, encoding, e->e_class, + ELF_TOFILE)); + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); +} diff --git a/ext/libelf/libelf.c b/ext/libelf/libelf.c new file mode 100644 index 000000000..73f25a210 --- /dev/null +++ b/ext/libelf/libelf.c @@ -0,0 +1,51 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> + +#include "libelf.h" +#include "_libelf.h" + +struct _libelf_globals * +_libelf_private() +{ + static int initialized = 0; + static struct _libelf_globals private; + + if (!initialized) { + uint32_t endian_test = ELFDATA2MSB << 24 | ELFDATA2LSB; + + private.libelf_arch = EM_NONE; + private.libelf_byteorder = *(char *)&endian_test; + private.libelf_class = ELFCLASSNONE; + private.libelf_error = 0; + private.libelf_fillchar = 0; + private.libelf_version = EV_NONE; + initialized = 1; + } + + return &private; +} diff --git a/ext/libelf/libelf.h b/ext/libelf/libelf.h new file mode 100644 index 000000000..51b9a851b --- /dev/null +++ b/ext/libelf/libelf.h @@ -0,0 +1,249 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/libelf/libelf.h,v 1.1 2006/11/11 17:16:33 jkoshy Exp $ + */ + +#ifndef _LIBELF_H_ +#define _LIBELF_H_ + +#include <sys/types.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#include "elf_queue.h" +#include "elf32.h" +#include "elf64.h" + +/* Library private data structures */ +typedef struct _Elf Elf; +typedef struct _Elf_Scn Elf_Scn; + +/* File types */ +typedef enum { + ELF_K_NONE = 0, + ELF_K_AR, /* `ar' archives */ + ELF_K_COFF, /* COFF files (unsupported) */ + ELF_K_ELF, /* ELF files */ + ELF_K_NUM +} Elf_Kind; + +#define ELF_K_FIRST ELF_K_NONE +#define ELF_K_LAST ELF_K_NUM + +/* Data types */ +typedef enum { + ELF_T_ADDR, + ELF_T_BYTE, + ELF_T_CAP, + ELF_T_DYN, + ELF_T_EHDR, + ELF_T_HALF, + ELF_T_LWORD, + ELF_T_MOVE, + ELF_T_MOVEP, + ELF_T_NOTE, + ELF_T_OFF, + ELF_T_PHDR, + ELF_T_REL, + ELF_T_RELA, + ELF_T_SHDR, + ELF_T_SWORD, + ELF_T_SXWORD, + ELF_T_SYMINFO, + ELF_T_SYM, + ELF_T_VDEF, + ELF_T_VNEED, + ELF_T_WORD, + ELF_T_XWORD, + ELF_T_NUM +} Elf_Type; + +#define ELF_T_FIRST ELF_T_ADDR +#define ELF_T_LAST ELF_T_XWORD + +/* Commands */ +typedef enum { + ELF_C_NULL = 0, + ELF_C_CLR, + ELF_C_FDDONE, + ELF_C_FDREAD, + ELF_C_RDWR, + ELF_C_READ, + ELF_C_SET, + ELF_C_WRITE, + ELF_C_NUM +} Elf_Cmd; + +#define ELF_C_FIRST ELF_C_NULL +#define ELF_C_LAST ELF_C_NUM + +/* + * An `Elf_Data' structure describes data in an + * ELF section. + */ +typedef struct _Elf_Data { + /* + * `Public' members that are part of the ELF(3) API. + */ + uint64_t d_align; + void *d_buf; + uint64_t d_off; + uint64_t d_size; + Elf_Type d_type; + unsigned int d_version; + + /* + * Members that are not part of the public API. + */ + Elf_Scn *d_scn; /* containing section */ + unsigned int d_flags; + STAILQ_ENTRY(_Elf_Data) d_next; +} Elf_Data; + +/* + * An `Elf_Arhdr' structure describes an archive + * header. + */ +typedef struct { + time_t ar_date; + char *ar_name; /* archive member name */ + gid_t ar_gid; + mode_t ar_mode; + char *ar_rawname; /* 'raw' member name */ + size_t ar_size; + uid_t ar_uid; +} Elf_Arhdr; + +/* + * An `Elf_Arsym' describes an entry in the archive + * symbol table. + */ +typedef struct { + off_t as_off; /* byte offset to member's header */ + unsigned long as_hash; /* elf_hash() value for name */ + char *as_name; /* null terminated symbol name */ +} Elf_Arsym; + +/* + * Error numbers. + */ + +enum Elf_Error { + ELF_E_NONE, /* No error */ + ELF_E_ARCHIVE, /* Malformed ar(1) archive */ + ELF_E_ARGUMENT, /* Invalid argument */ + ELF_E_CLASS, /* Mismatched ELF class */ + ELF_E_DATA, /* Invalid data descriptor */ + ELF_E_HEADER, /* Missing or malformed ELF header */ + ELF_E_IO, /* I/O error */ + ELF_E_LAYOUT, /* Layout constraint violation */ + ELF_E_MODE, /* Wrong mode for ELF descriptor */ + ELF_E_RANGE, /* Value out of range */ + ELF_E_RESOURCE, /* Resource exhaustion */ + ELF_E_SECTION, /* Invalid section descriptor */ + ELF_E_SEQUENCE, /* API calls out of sequence */ + ELF_E_UNIMPL, /* Feature is unimplemented */ + ELF_E_VERSION, /* Unknown API version */ + ELF_E_NUM /* Max error number */ +}; + +/* + * Flags defined by the API. + */ + +#define ELF_F_LAYOUT 0x001U /* application will layout the file */ +#define ELF_F_DIRTY 0x002U /* a section or ELF file is dirty */ + +Elf *elf_begin(int _fd, Elf_Cmd _cmd, Elf *_elf); +int elf_cntl(Elf *_elf, Elf_Cmd _cmd); +int elf_end(Elf *_elf); +const char *elf_errmsg(int _error); +int elf_errno(void); +void elf_fill(int _fill); +unsigned int elf_flagdata(Elf_Data *_data, Elf_Cmd _cmd, unsigned int _flags); +unsigned int elf_flagehdr(Elf *_elf, Elf_Cmd _cmd, unsigned int _flags); +unsigned int elf_flagelf(Elf *_elf, Elf_Cmd _cmd, unsigned int _flags); +unsigned int elf_flagphdr(Elf *_elf, Elf_Cmd _cmd, unsigned int _flags); +unsigned int elf_flagscn(Elf_Scn *_scn, Elf_Cmd _cmd, unsigned int _flags); +unsigned int elf_flagshdr(Elf_Scn *_scn, Elf_Cmd _cmd, unsigned int _flags); +Elf_Arhdr *elf_getarhdr(Elf *_elf); +Elf_Arsym *elf_getarsym(Elf *_elf, size_t *_ptr); +off_t elf_getbase(Elf *_elf); +Elf_Data *elf_getdata(Elf_Scn *, Elf_Data *); +char *elf_getident(Elf *_elf, size_t *_ptr); +int elf_getphnum(Elf *_elf, size_t *_dst); +Elf_Scn *elf_getscn(Elf *_elf, size_t _index); +int elf_getshnum(Elf *_elf, size_t *_dst); +int elf_getshstrndx(Elf *_elf, size_t *_dst); +unsigned long elf_hash(const char *_name); +Elf_Kind elf_kind(Elf *_elf); +Elf *elf_memory(char *_image, size_t _size); +size_t elf_ndxscn(Elf_Scn *_scn); +Elf_Data *elf_newdata(Elf_Scn *_scn); +Elf_Scn *elf_newscn(Elf *_elf); +Elf_Scn *elf_nextscn(Elf *_elf, Elf_Scn *_scn); +Elf_Cmd elf_next(Elf *_elf); +off_t elf_rand(Elf *_elf, off_t _off); +Elf_Data *elf_rawdata(Elf_Scn *_scn, Elf_Data *_data); +char *elf_rawfile(Elf *_elf, size_t *_size); +int elf_setshstrndx(Elf *_elf, size_t _shnum); +char *elf_strptr(Elf *_elf, size_t _section, size_t _offset); +off_t elf_update(Elf *_elf, Elf_Cmd _cmd); +unsigned int elf_version(unsigned int _version); + +long elf32_checksum(Elf *_elf); +size_t elf32_fsize(Elf_Type _type, size_t _count, + unsigned int _version); +Elf32_Ehdr *elf32_getehdr(Elf *_elf); +Elf32_Phdr *elf32_getphdr(Elf *_elf); +Elf32_Shdr *elf32_getshdr(Elf_Scn *_scn); +Elf32_Ehdr *elf32_newehdr(Elf *_elf); +Elf32_Phdr *elf32_newphdr(Elf *_elf, size_t _count); +Elf_Data *elf32_xlatetof(Elf_Data *_dst, const Elf_Data *_src, + unsigned int _enc); +Elf_Data *elf32_xlatetom(Elf_Data *_dst, const Elf_Data *_src, + unsigned int _enc); + +long elf64_checksum(Elf *_elf); +size_t elf64_fsize(Elf_Type _type, size_t _count, + unsigned int _version); +Elf64_Ehdr *elf64_getehdr(Elf *_elf); +Elf64_Phdr *elf64_getphdr(Elf *_elf); +Elf64_Shdr *elf64_getshdr(Elf_Scn *_scn); +Elf64_Ehdr *elf64_newehdr(Elf *_elf); +Elf64_Phdr *elf64_newphdr(Elf *_elf, size_t _count); +Elf_Data *elf64_xlatetof(Elf_Data *_dst, const Elf_Data *_src, + unsigned int _enc); +Elf_Data *elf64_xlatetom(Elf_Data *_dst, const Elf_Data *_src, + unsigned int _enc); + +#ifdef __cplusplus +} +#endif + +#endif /* _LIBELF_H_ */ diff --git a/ext/libelf/libelf_align.c b/ext/libelf/libelf_align.c new file mode 100644 index 000000000..af44ecdb9 --- /dev/null +++ b/ext/libelf/libelf_align.c @@ -0,0 +1,130 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/types.h> + +//#include <machine/elf.h> +//#include <machine/endian.h> + +#include "libelf.h" + +#include "_libelf.h" + +struct align { + int a32; + int a64; +}; + +#ifdef __GNUC__ +#define MALIGN(N) { \ + .a32 = __alignof__(Elf32_##N), \ + .a64 = __alignof__(Elf64_##N) \ + } +#define MALIGN64(V) { \ + .a32 = 0, \ + .a64 = __alignof__(Elf64_##V) \ + } +#else +#error Need the __alignof__ builtin. +#endif +#define UNSUPPORTED() { \ + .a32 = 0, \ + .a64 = 0 \ + } + +static struct align malign[ELF_T_NUM] = { + [ELF_T_ADDR] = MALIGN(Addr), + [ELF_T_BYTE] = { .a32 = 1, .a64 = 1 }, + [ELF_T_CAP] = MALIGN(Cap), + [ELF_T_DYN] = MALIGN(Dyn), + [ELF_T_EHDR] = MALIGN(Ehdr), + [ELF_T_HALF] = MALIGN(Half), + [ELF_T_LWORD] = MALIGN(Lword), + [ELF_T_MOVE] = MALIGN(Move), + [ELF_T_MOVEP] = UNSUPPORTED(), + [ELF_T_NOTE] = MALIGN(Nhdr), + [ELF_T_OFF] = MALIGN(Off), + [ELF_T_PHDR] = MALIGN(Phdr), + [ELF_T_REL] = MALIGN(Rel), + [ELF_T_RELA] = MALIGN(Rela), + [ELF_T_SHDR] = MALIGN(Shdr), + [ELF_T_SWORD] = MALIGN(Sword), + [ELF_T_SXWORD] = MALIGN64(Sxword), + [ELF_T_SYM] = MALIGN(Sym), + [ELF_T_SYMINFO] = MALIGN(Syminfo), + [ELF_T_VDEF] = MALIGN(Verdef), + [ELF_T_VNEED] = MALIGN(Verneed), + [ELF_T_WORD] = MALIGN(Word), + [ELF_T_XWORD] = MALIGN64(Xword) +}; + +int +_libelf_malign(Elf_Type t, int elfclass) +{ + if (t >= ELF_T_NUM || (int) t < 0) + return (0); + + return (elfclass == ELFCLASS32 ? malign[t].a32 : + malign[t].a64); +} + +#define FALIGN(A32,A64) { .a32 = (A32), .a64 = (A64) } + +static struct align falign[ELF_T_NUM] = { + [ELF_T_ADDR] = FALIGN(4,8), + [ELF_T_BYTE] = FALIGN(1,1), + [ELF_T_CAP] = FALIGN(4,8), + [ELF_T_DYN] = FALIGN(4,8), + [ELF_T_EHDR] = FALIGN(4,8), + [ELF_T_HALF] = FALIGN(2,2), + [ELF_T_LWORD] = FALIGN(8,8), + [ELF_T_MOVE] = FALIGN(8,8), + [ELF_T_MOVEP] = UNSUPPORTED(), + [ELF_T_NOTE] = FALIGN(4,4), + [ELF_T_OFF] = FALIGN(4,8), + [ELF_T_PHDR] = FALIGN(4,8), + [ELF_T_REL] = FALIGN(4,8), + [ELF_T_RELA] = FALIGN(4,8), + [ELF_T_SHDR] = FALIGN(4,8), + [ELF_T_SWORD] = FALIGN(4,4), + [ELF_T_SXWORD] = FALIGN(0,8), + [ELF_T_SYM] = FALIGN(4,8), + [ELF_T_SYMINFO] = FALIGN(2,2), + [ELF_T_VDEF] = FALIGN(4,4), + [ELF_T_VNEED] = FALIGN(4,4), + [ELF_T_WORD] = FALIGN(4,4), + [ELF_T_XWORD] = FALIGN(0,8) +}; + +int +_libelf_falign(Elf_Type t, int elfclass) +{ + if (t >= ELF_T_NUM || (int) t < 0) + return (0); + + return (elfclass == ELFCLASS32 ? falign[t].a32 : + falign[t].a64); +} diff --git a/ext/libelf/libelf_allocate.c b/ext/libelf/libelf_allocate.c new file mode 100644 index 000000000..9e1280c47 --- /dev/null +++ b/ext/libelf/libelf_allocate.c @@ -0,0 +1,206 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Internal APIs + */ + +#include <errno.h> + +#include <assert.h> +#include "libelf.h" +#include <stdlib.h> +#include <string.h> + +#include "_libelf.h" + +Elf * +_libelf_allocate_elf(void) +{ + Elf *e; + + if ((e = malloc(sizeof(*e))) == NULL) { + LIBELF_SET_ERROR(RESOURCE, errno); + return NULL; + } + + e->e_activations = 1; + e->e_arhdr = NULL; + e->e_byteorder = ELFDATANONE; + e->e_class = ELFCLASSNONE; + e->e_cmd = ELF_C_NULL; + e->e_fd = -1; + e->e_flags = 0; + e->e_kind = ELF_K_NONE; + e->e_parent = NULL; + e->e_rawfile = NULL; + e->e_rawsize = 0; + e->e_version = LIBELF_PRIVATE(version); + + (void) memset(&e->e_u, 0, sizeof(e->e_u)); + + return (e); +} + +void +_libelf_init_elf(Elf *e, Elf_Kind kind) +{ + assert(e != NULL); + assert(e->e_kind == ELF_K_NONE); + + e->e_kind = kind; + + switch (kind) { + case ELF_K_ELF: + STAILQ_INIT(&e->e_u.e_elf.e_scn); + break; + default: + break; + } +} + +#define FREE(P) do { \ + if (P) \ + free(P); \ + } while (0) + + +Elf * +_libelf_release_elf(Elf *e) +{ + switch (e->e_kind) { + case ELF_K_AR: + FREE(e->e_u.e_ar.e_symtab); + break; + + case ELF_K_ELF: + switch (e->e_class) { + case ELFCLASS32: + FREE(e->e_u.e_elf.e_ehdr.e_ehdr32); + FREE(e->e_u.e_elf.e_phdr.e_phdr32); + break; + case ELFCLASS64: + FREE(e->e_u.e_elf.e_ehdr.e_ehdr64); + FREE(e->e_u.e_elf.e_phdr.e_phdr64); + break; + } + + assert(STAILQ_EMPTY(&e->e_u.e_elf.e_scn)); + + if (e->e_arhdr) { + FREE(e->e_arhdr->ar_name); + FREE(e->e_arhdr->ar_rawname); + free(e->e_arhdr); + } + + break; + + default: + break; + } + + free(e); + + return (NULL); +} + +Elf_Data * +_libelf_allocate_data(Elf_Scn *s) +{ + Elf_Data *d; + + if ((d = calloc((size_t) 1, sizeof(Elf_Data))) == NULL) { + LIBELF_SET_ERROR(RESOURCE, 0); + return (NULL); + } + + d->d_scn = s; + + return (d); +} + +Elf_Data * +_libelf_release_data(Elf_Data *d) +{ + + if (d->d_flags & LIBELF_F_MALLOCED) + free(d->d_buf); + + free(d); + + return (NULL); +} + +Elf_Scn * +_libelf_allocate_scn(Elf *e, size_t ndx) +{ + Elf_Scn *s; + + if ((s = calloc((size_t) 1, sizeof(Elf_Scn))) == NULL) { + LIBELF_SET_ERROR(RESOURCE, errno); + return (NULL); + } + + s->s_elf = e; + s->s_ndx = ndx; + + STAILQ_INIT(&s->s_data); + STAILQ_INIT(&s->s_rawdata); + + STAILQ_INSERT_TAIL(&e->e_u.e_elf.e_scn, s, s_next); + + return (s); +} + +Elf_Scn * +_libelf_release_scn(Elf_Scn *s) +{ + Elf *e; + Elf_Data *d, *td; + + assert(s != NULL); + + STAILQ_FOREACH_SAFE(d, &s->s_data, d_next, td) { + STAILQ_REMOVE(&s->s_data, d, _Elf_Data, d_next); + d = _libelf_release_data(d); + } + + STAILQ_FOREACH_SAFE(d, &s->s_rawdata, d_next, td) { + assert((d->d_flags & LIBELF_F_MALLOCED) == 0); + STAILQ_REMOVE(&s->s_rawdata, d, _Elf_Data, d_next); + d = _libelf_release_data(d); + } + + e = s->s_elf; + + assert(e != NULL); + + STAILQ_REMOVE(&e->e_u.e_elf.e_scn, s, _Elf_Scn, s_next); + + free(s); + + return (NULL); +} diff --git a/ext/libelf/libelf_ar.c b/ext/libelf/libelf_ar.c new file mode 100644 index 000000000..01e162455 --- /dev/null +++ b/ext/libelf/libelf_ar.c @@ -0,0 +1,481 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS `AS IS' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <ar.h> +#include <assert.h> +#include <ctype.h> +#include "libelf.h" +#include <stdlib.h> +#include <string.h> + +#include "_libelf.h" + +#define LIBELF_NALLOC_SIZE 16 + +/* + * `ar' archive handling. + * + * `ar' archives start with signature `ARMAG'. Each archive member is + * preceded by a header containing meta-data for the member. This + * header is described in <ar.h> (struct ar_hdr). The header always + * starts on an even address. File data is padded with "\n" + * characters to keep this invariant. + * + * Special considerations for `ar' archives: + * + * The `ar' header only has space for a 16 character file name. File + * names are terminated with a '/', so this effectively leaves 15 + * characters for the actual file name. In order to accomodate longer + * file names, names may be stored in a separate 'string table' and + * referenced indirectly by a member header. The string table itself + * appears as an archive member with name "// ". An indirect file name + * in an `ar' header matches the pattern "/[0-9]*". The digits form a + * decimal number that corresponds to a byte offset into the string + * table where the actual file name of the object starts. Strings in + * the string table are padded to start on even addresses. + * + * Archives may also have a symbol table (see ranlib(1)), mapping + * program symbols to object files inside the archive. A symbol table + * uses a file name of "/ " in its archive header. The symbol table + * is structured as: + * - a 4-byte count of entries stored as a binary value, MSB first + * - 'n' 4-byte offsets, stored as binary values, MSB first + * - 'n' NUL-terminated strings, for ELF symbol names, stored unpadded. + * + * If the symbol table and string table are is present in an archive + * they must be the very first objects and in that order. + */ + +/* + * Convert a string bounded by `start' and `start+sz' (exclusive) to a + * number in the specified base. + */ +static int +_libelf_ar_get_number(char *s, size_t sz, int base, size_t *ret) +{ + int c, v; + size_t r; + char *e; + + assert(base <= 10); + + e = s + sz; + + /* skip leading blanks */ + for (;s < e && (c = *s) == ' '; s++) + ; + + r = 0L; + for (;s < e; s++) { + if ((c = *s) == ' ') + break; + if (c < '0' || c > '9') + return (0); + v = c - '0'; + if (v >= base) /* Illegal digit. */ + break; + r *= base; + r += v; + } + + *ret = r; + + return (1); +} + +/* + * Retrieve a string from a name field. If `rawname' is set, leave + * ar(1) control characters in. + */ +static char * +_libelf_ar_get_string(const char *buf, size_t bufsize, int rawname) +{ + const char *q; + char *r; + size_t sz; + + if (rawname) + sz = bufsize + 1; + else { + /* Skip back over trailing blanks. */ + for (q = buf + bufsize - 1; q >= buf && *q == ' '; --q) + ; + + if (q < buf) { + /* + * If the input buffer only had blanks in it, + * return a zero-length string. + */ + buf = ""; + sz = 1; + } else { + /* + * Remove the trailing '/' character, but only + * if the name isn't one of the special names + * "/" and "//". + */ + if (q > buf + 1 || + (q == (buf + 1) && *buf != '/')) + q--; + + sz = q - buf + 2; /* Space for a trailing NUL. */ + } + } + + if ((r = malloc(sz)) == NULL) { + LIBELF_SET_ERROR(RESOURCE, 0); + return (NULL); + } + + (void) strncpy(r, buf, sz); + r[sz - 1] = '\0'; + + return (r); +} + +/* + * Retrieve the full name of the archive member. + */ +static char * +_libelf_ar_get_name(char *buf, size_t bufsize, Elf *e) +{ + char c, *q, *r, *s; + size_t len; + size_t offset; + + assert(e->e_kind == ELF_K_AR); + + if (buf[0] == '/' && (c = buf[1]) >= '0' && c <= '9') { + /* + * The value in field ar_name is a decimal offset into + * the archive string table where the actual name + * resides. + */ + if (_libelf_ar_get_number(buf + 1, bufsize - 1, 10, + &offset) == 0) { + LIBELF_SET_ERROR(ARCHIVE, 0); + return (NULL); + } + + if (offset > e->e_u.e_ar.e_rawstrtabsz) { + LIBELF_SET_ERROR(ARCHIVE, 0); + return (NULL); + } + + s = q = e->e_u.e_ar.e_rawstrtab + offset; + r = e->e_u.e_ar.e_rawstrtab + e->e_u.e_ar.e_rawstrtabsz; + + for (s = q; s < r && *s != '/'; s++) + ; + len = s - q + 1; /* space for the trailing NUL */ + + if ((s = malloc(len)) == NULL) { + LIBELF_SET_ERROR(RESOURCE, 0); + return (NULL); + } + + (void) strncpy(s, q, len); + s[len - 1] = '\0'; + + return (s); + } + + /* + * Normal 'name' + */ + return (_libelf_ar_get_string(buf, bufsize, 0)); +} + + +Elf_Arhdr * +_libelf_ar_gethdr(Elf *e) +{ + Elf *parent; + struct ar_hdr *arh; + Elf_Arhdr *eh; + size_t n; + + if ((parent = e->e_parent) == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + arh = (struct ar_hdr *) ((uintptr_t) e->e_rawfile - sizeof(struct ar_hdr)); + + assert((uintptr_t) arh >= (uintptr_t) parent->e_rawfile + SARMAG); + assert((uintptr_t) arh <= (uintptr_t) parent->e_rawfile + parent->e_rawsize - + sizeof(struct ar_hdr)); + + if ((eh = malloc(sizeof(Elf_Arhdr))) == NULL) { + LIBELF_SET_ERROR(RESOURCE, 0); + return (NULL); + } + + e->e_arhdr = eh; + eh->ar_name = eh->ar_rawname = NULL; + + if ((eh->ar_name = _libelf_ar_get_name(arh->ar_name, sizeof(arh->ar_name), + parent)) == NULL) + goto error; + + if (_libelf_ar_get_number(arh->ar_uid, sizeof(arh->ar_uid), 10, &n) == 0) + goto error; + eh->ar_uid = (uid_t) n; + + if (_libelf_ar_get_number(arh->ar_gid, sizeof(arh->ar_gid), 10, &n) == 0) + goto error; + eh->ar_gid = (gid_t) n; + + if (_libelf_ar_get_number(arh->ar_mode, sizeof(arh->ar_mode), 8, &n) == 0) + goto error; + eh->ar_mode = (mode_t) n; + + if (_libelf_ar_get_number(arh->ar_size, sizeof(arh->ar_size), 10, &n) == 0) + goto error; + eh->ar_size = n; + + if ((eh->ar_rawname = _libelf_ar_get_string(arh->ar_name, + sizeof(arh->ar_name), 1)) == NULL) + goto error; + + return (eh); + + error: + if (eh) { + if (eh->ar_name) + free(eh->ar_name); + if (eh->ar_rawname) + free(eh->ar_rawname); + free(eh); + } + e->e_arhdr = NULL; + + return (NULL); +} + +Elf * +_libelf_ar_open_member(int fd, Elf_Cmd c, Elf *elf) +{ + Elf *e; + off_t next; + struct ar_hdr *arh; + size_t sz; + + assert(elf->e_kind == ELF_K_AR); + + next = elf->e_u.e_ar.e_next; + + /* + * `next' is only set to zero by elf_next() when the last + * member of an archive is processed. + */ + if (next == (off_t) 0) + return (NULL); + + assert((next & 1) == 0); + + arh = (struct ar_hdr *) (elf->e_rawfile + next); + + if (_libelf_ar_get_number(arh->ar_size, sizeof(arh->ar_size), 10, &sz) == 0) { + LIBELF_SET_ERROR(ARCHIVE, 0); + return (NULL); + } + + assert(sz > 0); + + arh++; /* skip over archive member header */ + + if ((e = elf_memory((char *) arh, sz)) == NULL) + return (NULL); + + e->e_fd = fd; + e->e_cmd = c; + + elf->e_u.e_ar.e_nchildren++; + e->e_parent = elf; + + return (e); +} + +Elf * +_libelf_ar_open(Elf *e) +{ + int i; + char *s, *end; + size_t sz; + struct ar_hdr arh; + + e->e_kind = ELF_K_AR; + e->e_u.e_ar.e_nchildren = 0; + e->e_u.e_ar.e_next = (off_t) -1; + + /* + * Look for special members. + */ + + s = e->e_rawfile + SARMAG; + end = e->e_rawfile + e->e_rawsize; + + assert(e->e_rawsize > 0); + + /* + * Look for magic names "/ " and "// " in the first two entries + * of the archive. + */ + for (i = 0; i < 2; i++) { + + if (s + sizeof(arh) > end) { + LIBELF_SET_ERROR(ARCHIVE, 0); + return (NULL); + } + + (void) memcpy(&arh, s, sizeof(arh)); + + if (arh.ar_fmag[0] != '`' || arh.ar_fmag[1] != '\n') { + LIBELF_SET_ERROR(ARCHIVE, 0); + return (NULL); + } + + if (arh.ar_name[0] != '/') /* not a special symbol */ + break; + + if (_libelf_ar_get_number(arh.ar_size, sizeof(arh.ar_size), 10, &sz) == 0) { + LIBELF_SET_ERROR(ARCHIVE, 0); + return (NULL); + } + + assert(sz > 0); + + s += sizeof(arh); + + if (arh.ar_name[1] == ' ') { /* "/ " => symbol table */ + + e->e_u.e_ar.e_rawsymtab = s; + e->e_u.e_ar.e_rawsymtabsz = sz; + + } else if (arh.ar_name[1] == '/' && arh.ar_name[2] == ' ') { + + /* "// " => string table for long file names */ + e->e_u.e_ar.e_rawstrtab = s; + e->e_u.e_ar.e_rawstrtabsz = sz; + } + + sz = LIBELF_ADJUST_AR_SIZE(sz); + + s += sz; + } + + e->e_u.e_ar.e_next = (off_t) (s - e->e_rawfile); + + return (e); +} + +/* + * An ar(1) symbol table has the following layout: + * + * The first 4 bytes are a binary count of the number of entries in the + * symbol table, stored MSB-first. + * + * Then there are 'n' 4-byte binary offsets, also stored MSB first. + * + * Following this, there are 'n' null-terminated strings. + */ + +#define GET_WORD(P, V) do { \ + (V) = 0; \ + (V) = (P)[0]; (V) <<= 8; \ + (V) += (P)[1]; (V) <<= 8; \ + (V) += (P)[2]; (V) <<= 8; \ + (V) += (P)[3]; \ + } while (0) + +#define INTSZ 4 + +Elf_Arsym * +_libelf_ar_process_symtab(Elf *e, size_t *count) +{ + size_t n, nentries, off; + Elf_Arsym *symtab, *sym; + char *p, *s, *end; + + assert(e != NULL); + assert(count != NULL); + + if (e->e_u.e_ar.e_rawsymtabsz < INTSZ) { + LIBELF_SET_ERROR(ARCHIVE, 0); + return (NULL); + } + + p = e->e_u.e_ar.e_rawsymtab; + end = p + e->e_u.e_ar.e_rawsymtabsz; + + GET_WORD(p, nentries); + p += INTSZ; + + if (nentries == 0 || p + nentries * INTSZ >= end) { + LIBELF_SET_ERROR(ARCHIVE, 0); + return (NULL); + } + + /* Allocate space for a nentries + a sentinel. */ + if ((symtab = malloc(sizeof(Elf_Arsym) * (nentries+1))) == NULL) { + LIBELF_SET_ERROR(RESOURCE, 0); + return (NULL); + } + + s = p + (nentries * INTSZ); /* start of the string table. */ + + for (n = nentries, sym = symtab; n > 0; n--) { + off = 0; + + GET_WORD(p, off); + + sym->as_off = off; + sym->as_hash = elf_hash(s); + sym->as_name = s; + + p += INTSZ; + sym++; + + for (; s < end && *s++ != '\0';) /* skip to next string */ + ; + if (s > end) { + LIBELF_SET_ERROR(ARCHIVE, 0); + free(symtab); + return (NULL); + } + } + + /* Fill up the sentinel entry. */ + sym->as_name = NULL; + sym->as_hash = ~0UL; + sym->as_off = (off_t) 0; + + *count = e->e_u.e_ar.e_symtabsz = nentries + 1; + e->e_u.e_ar.e_symtab = symtab; + + return (symtab); +} diff --git a/ext/libelf/libelf_checksum.c b/ext/libelf/libelf_checksum.c new file mode 100644 index 000000000..143517592 --- /dev/null +++ b/ext/libelf/libelf_checksum.c @@ -0,0 +1,96 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "gelf.h" + +#include "_libelf.h" + +static unsigned long +_libelf_sum(unsigned long c, const unsigned char *s, size_t size) +{ + if (s == NULL || size == 0) + return (c); + + while (size--) + c += *s++; + + return (c); +} + +unsigned long +_libelf_checksum(Elf *e, int elfclass) +{ + size_t shn; + Elf_Scn *scn; + Elf_Data *d; + unsigned long checksum; + GElf_Ehdr eh; + GElf_Shdr shdr; + + if (e == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (0L); + } + + if (e->e_class != elfclass) { + LIBELF_SET_ERROR(CLASS, 0); + return (0L); + } + + if (gelf_getehdr(e, &eh) == NULL) + return (0); + + /* + * Iterate over all sections in the ELF file, computing the + * checksum along the way. + * + * The first section is always SHN_UNDEF and can be skipped. + * Non-allocatable sections are skipped, as are sections that + * could be affected by utilities such as strip(1). + */ + + checksum = 0; + for (shn = 1; shn < e->e_u.e_elf.e_nscn; shn++) { + if ((scn = elf_getscn(e, shn)) == NULL) + return (0); + if (gelf_getshdr(scn, &shdr) == NULL) + return (0); + if ((shdr.sh_flags & SHF_ALLOC) == 0 || + shdr.sh_type == SHT_DYNAMIC || + shdr.sh_type == SHT_DYNSYM) + continue; + + d = NULL; + while ((d = elf_rawdata(scn, d)) != NULL) + checksum = _libelf_sum(checksum, + (unsigned char *) d->d_buf, d->d_size); + } + + /* + * Return a 16-bit checksum compatible with Solaris. + */ + return (((checksum >> 16) & 0xFFFFUL) + (checksum & 0xFFFFUL)); +} diff --git a/ext/libelf/libelf_convert.m4 b/ext/libelf/libelf_convert.m4 new file mode 100644 index 000000000..1f21dbe4c --- /dev/null +++ b/ext/libelf/libelf_convert.m4 @@ -0,0 +1,657 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/types.h> + +#include <assert.h> +#include <string.h> + +#include "elf32.h" +#include "elf64.h" +#include "libelf.h" +#include "_libelf.h" + +/* WARNING: GENERATED FROM __file__. */ + +/* + * Macros to swap various integral quantities. + */ + +#define SWAP_HALF(X) do { \ + uint16_t _x = (uint16_t) (X); \ + uint16_t _t = _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + (X) = _t; \ + } while (0) +#define SWAP_WORD(X) do { \ + uint32_t _x = (uint32_t) (X); \ + uint32_t _t = _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + (X) = _t; \ + } while (0) +#define SWAP_ADDR32(X) SWAP_WORD(X) +#define SWAP_OFF32(X) SWAP_WORD(X) +#define SWAP_SWORD(X) SWAP_WORD(X) +#define SWAP_WORD64(X) do { \ + uint64_t _x = (uint64_t) (X); \ + uint64_t _t = _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + _t <<= 8; _x >>= 8; _t |= _x & 0xFF; \ + (X) = _t; \ + } while (0) +#define SWAP_ADDR64(X) SWAP_WORD64(X) +#define SWAP_LWORD(X) SWAP_WORD64(X) +#define SWAP_OFF64(X) SWAP_WORD64(X) +#define SWAP_SXWORD(X) SWAP_WORD64(X) +#define SWAP_XWORD(X) SWAP_WORD64(X) + +/* + * Write out various integral values. The destination pointer could + * be unaligned. Values are written out in native byte order. The + * destination pointer is incremented after the write. + */ +#define WRITE_BYTE(P,X) do { \ + unsigned char *const _p = (unsigned char *) (P); \ + _p[0] = (unsigned char) (X); \ + (P) = _p + 1; \ + } while (0) +#define WRITE_HALF(P,X) do { \ + uint16_t _t = (X); \ + unsigned char *const _p = (unsigned char *) (P); \ + unsigned const char *const _q = (unsigned char *) &_t; \ + _p[0] = _q[0]; \ + _p[1] = _q[1]; \ + (P) = _p + 2; \ + } while (0) +#define WRITE_WORD(P,X) do { \ + uint32_t _t = (X); \ + unsigned char *const _p = (unsigned char *) (P); \ + unsigned const char *const _q = (unsigned char *) &_t; \ + _p[0] = _q[0]; \ + _p[1] = _q[1]; \ + _p[2] = _q[2]; \ + _p[3] = _q[3]; \ + (P) = _p + 4; \ + } while (0) +#define WRITE_ADDR32(P,X) WRITE_WORD(P,X) +#define WRITE_OFF32(P,X) WRITE_WORD(P,X) +#define WRITE_SWORD(P,X) WRITE_WORD(P,X) +#define WRITE_WORD64(P,X) do { \ + uint64_t _t = (X); \ + unsigned char *const _p = (unsigned char *) (P); \ + unsigned const char *const _q = (unsigned char *) &_t; \ + _p[0] = _q[0]; \ + _p[1] = _q[1]; \ + _p[2] = _q[2]; \ + _p[3] = _q[3]; \ + _p[4] = _q[4]; \ + _p[5] = _q[5]; \ + _p[6] = _q[6]; \ + _p[7] = _q[7]; \ + (P) = _p + 8; \ + } while (0) +#define WRITE_ADDR64(P,X) WRITE_WORD64(P,X) +#define WRITE_LWORD(P,X) WRITE_WORD64(P,X) +#define WRITE_OFF64(P,X) WRITE_WORD64(P,X) +#define WRITE_SXWORD(P,X) WRITE_WORD64(P,X) +#define WRITE_XWORD(P,X) WRITE_WORD64(P,X) +#define WRITE_IDENT(P,X) do { \ + (void) memcpy((P), (X), sizeof((X))); \ + (P) = (P) + EI_NIDENT; \ + } while (0) + +/* + * Read in various integral values. The source pointer could be + * unaligned. Values are read in in native byte order. The source + * pointer is incremented appropriately. + */ + +#define READ_BYTE(P,X) do { \ + const unsigned char *const _p = \ + (const unsigned char *) (P); \ + (X) = _p[0]; \ + (P) = (P) + 1; \ + } while (0) +#define READ_HALF(P,X) do { \ + uint16_t _t; \ + unsigned char *const _q = (unsigned char *) &_t; \ + const unsigned char *const _p = \ + (const unsigned char *) (P); \ + _q[0] = _p[0]; \ + _q[1] = _p[1]; \ + (P) = (P) + 2; \ + (X) = _t; \ + } while (0) +#define READ_WORD(P,X) do { \ + uint32_t _t; \ + unsigned char *const _q = (unsigned char *) &_t; \ + const unsigned char *const _p = \ + (const unsigned char *) (P); \ + _q[0] = _p[0]; \ + _q[1] = _p[1]; \ + _q[2] = _p[2]; \ + _q[3] = _p[3]; \ + (P) = (P) + 4; \ + (X) = _t; \ + } while (0) +#define READ_ADDR32(P,X) READ_WORD(P,X) +#define READ_OFF32(P,X) READ_WORD(P,X) +#define READ_SWORD(P,X) READ_WORD(P,X) +#define READ_WORD64(P,X) do { \ + uint64_t _t; \ + unsigned char *const _q = (unsigned char *) &_t; \ + const unsigned char *const _p = \ + (const unsigned char *) (P); \ + _q[0] = _p[0]; \ + _q[1] = _p[1]; \ + _q[2] = _p[2]; \ + _q[3] = _p[3]; \ + _q[4] = _p[4]; \ + _q[5] = _p[5]; \ + _q[6] = _p[6]; \ + _q[7] = _p[7]; \ + (P) = (P) + 8; \ + (X) = _t; \ + } while (0) +#define READ_ADDR64(P,X) READ_WORD64(P,X) +#define READ_LWORD(P,X) READ_WORD64(P,X) +#define READ_OFF64(P,X) READ_WORD64(P,X) +#define READ_SXWORD(P,X) READ_WORD64(P,X) +#define READ_XWORD(P,X) READ_WORD64(P,X) +#define READ_IDENT(P,X) do { \ + (void) memcpy((X), (P), sizeof((X))); \ + (P) = (P) + EI_NIDENT; \ + } while (0) + +#define ROUNDUP2(V,N) (V) = ((((V) + (N) - 1)) & ~((N) - 1)) + +divert(-1) + +/* + * Generate conversion routines for converting between in-memory and + * file representations of Elf data structures. + * + * `In-memory' representations of an Elf data structure use natural + * alignments and native byte ordering. This allows arithmetic and + * casting to work as expected. On the other hand the `file' + * representation of an ELF data structure could be packed tighter + * than its `in-memory' representation, and could be of a differing + * byte order. An additional complication is that `ar' only pads data + * to even addresses and so ELF archive member data being read from + * inside an `ar' archive could end up at misaligned memory addresses. + * + * Consequently, casting the `char *' pointers that point to memory + * representations (i.e., source pointers for the *_tof() functions + * and the destination pointers for the *_tom() functions), is safe, + * as these pointers should be correctly aligned for the memory type + * already. However, pointers to file representations have to be + * treated as being potentially unaligned and no casting can be done. + */ + +include(SRCDIR`/elf_types.m4') + +/* + * `IGNORE'_* flags turn off generation of template code. + */ + +define(`IGNORE', + `define(IGNORE_$1`'32, 1) + define(IGNORE_$1`'64, 1)') + +IGNORE(MOVEP) +IGNORE(NOTE) + +define(IGNORE_BYTE, 1) /* 'lator, leave 'em bytes alone */ +define(IGNORE_NOTE, 1) +define(IGNORE_SXWORD32, 1) +define(IGNORE_XWORD32, 1) + +/* + * `BASE'_XXX flags cause class agnostic template functions + * to be generated. + */ + +define(`BASE_BYTE', 1) +define(`BASE_HALF', 1) +define(`BASE_NOTE', 1) +define(`BASE_WORD', 1) +define(`BASE_LWORD', 1) +define(`BASE_SWORD', 1) +define(`BASE_XWORD', 1) +define(`BASE_SXWORD', 1) + +/* + * `SIZEDEP'_XXX flags cause 32/64 bit variants to be generated + * for each primitive type. + */ + +define(`SIZEDEP_ADDR', 1) +define(`SIZEDEP_OFF', 1) + +/* + * `Primitive' ELF types are those that are an alias for an integral + * type. They have no internal structure. These can be copied using + * a `memcpy()', and byteswapped in straightforward way. + * + * Macro use: + * `$1': Name of the ELF type. + * `$2': C structure name suffix + * `$3': ELF class specifier for symbols, one of [`', `32', `64'] + * `$4': ELF class specifier for types, one of [`32', `64'] + */ +define(`MAKEPRIM_TO_F',` +static void +libelf_cvt_$1$3_tof(char *dst, char *src, size_t count, int byteswap) +{ + Elf$4_$2 t, *s = (Elf$4_$2 *) (uintptr_t) src; + size_t c; + + if (dst == src && !byteswap) + return; + + if (!byteswap) { + (void) memcpy(dst, src, count * sizeof(*s)); + return; + } + + for (c = 0; c < count; c++) { + t = *s++; + SWAP_$1$3(t); + WRITE_$1$3(dst,t); + } +} +') + +define(`MAKEPRIM_TO_M',` +static void +libelf_cvt_$1$3_tom(char *dst, char *src, size_t count, int byteswap) +{ + Elf$4_$2 t, *d = (Elf$4_$2 *) (uintptr_t) dst; + size_t c; + + if (dst == src && !byteswap) + return; + + if (!byteswap) { + (void) memcpy(dst, src, count * sizeof(*d)); + return; + } + + for (c = 0; c < count; c++) { + READ_$1$3(src,t); + SWAP_$1$3(t); + *d++ = t; + } +} +') + +define(`SWAP_FIELD', + `ifdef(`IGNORE_'$2,`', + `ifelse(BASE_$2,1, + `SWAP_$2(t.$1); + ', + `ifelse($2,BYTE,`', + `ifelse($2,IDENT,`', + `SWAP_$2'SZ()`(t.$1); + ')')')')') +define(`SWAP_MEMBERS', + `ifelse($#,1,`/**/', + `SWAP_FIELD($1)SWAP_MEMBERS(shift($@))')') + +define(`SWAP_STRUCT', + `pushdef(`SZ',$2)/* Swap an Elf$2_$1 */ + SWAP_MEMBERS(Elf$2_$1_DEF)popdef(`SZ')') + +define(`WRITE_FIELD', + `ifelse(BASE_$2,1, + `WRITE_$2(dst,t.$1); + ', + `ifelse($2,IDENT, + `WRITE_$2(dst,t.$1); + ', + `WRITE_$2'SZ()`(dst,t.$1); + ')')') +define(`WRITE_MEMBERS', + `ifelse($#,1,`/**/', + `WRITE_FIELD($1)WRITE_MEMBERS(shift($@))')') + +define(`WRITE_STRUCT', + `pushdef(`SZ',$2)/* Write an Elf$2_$1 */ + WRITE_MEMBERS(Elf$2_$1_DEF)popdef(`SZ')') + +define(`READ_FIELD', + `ifelse(BASE_$2,1, + `READ_$2(s,t.$1); + ', + `ifelse($2,IDENT, + `READ_$2(s,t.$1); + ', + `READ_$2'SZ()`(s,t.$1); + ')')') + +define(`READ_MEMBERS', + `ifelse($#,1,`/**/', + `READ_FIELD($1)READ_MEMBERS(shift($@))')') + +define(`READ_STRUCT', + `pushdef(`SZ',$2)/* Read an Elf$2_$1 */ + READ_MEMBERS(Elf$2_$1_DEF)popdef(`SZ')') + +/* + * Converters for non-integral ELF data structures. + * + * When converting data to file representation, the source pointer + * will be naturally aligned for a data structure's in-memory + * representation. When converting data to memory, the destination + * pointer will be similarly aligned. + * + * For in-place conversions, when converting to file representations, + * the source buffer is large enough to hold `file' data. When + * converting from file to memory, we need to be careful to work + * `backwards', to avoid overwriting unconverted data. + * + * Macro use: + * `$1': Name of the ELF type. + * `$2': C structure name suffix. + * `$3': ELF class specifier, one of [`', `32', `64'] + */ + +define(`MAKE_TO_F', + `ifdef(`IGNORE_'$1$3,`',` +static void +libelf_cvt$3_$1_tof(char *dst, char *src, size_t count, int byteswap) +{ + Elf$3_$2 t, *s; + size_t c; + + s = (Elf$3_$2 *) (uintptr_t) src; + for (c = 0; c < count; c++) { + t = *s++; + if (byteswap) { + SWAP_STRUCT($2,$3) + } + WRITE_STRUCT($2,$3) + } +} +')') + +define(`MAKE_TO_M', + `ifdef(`IGNORE_'$1$3,`',` +static void +libelf_cvt$3_$1_tom(char *dst, char *src, size_t count, int byteswap) +{ + Elf$3_$2 t, *d; + unsigned char *s,*s0; + size_t fsz; + + fsz = elf$3_fsize(ELF_T_$1, (size_t) 1, EV_CURRENT); + d = ((Elf$3_$2 *) (uintptr_t) dst) + (count - 1); + s0 = (unsigned char *) src + (count - 1) * fsz; + + while (count--) { + s = s0; + READ_STRUCT($2,$3) + if (byteswap) { + SWAP_STRUCT($2,$3) + } + *d-- = t; s0 -= fsz; + } +} +')') + +/* + * Make type convertor functions from the type definition + * of the ELF type: + * - if the type is a base (i.e., `primitive') type: + * - if it is marked as to be ignored (i.e., `IGNORE_'TYPE) + * is defined, we skip the code generation step. + * - if the type is declared as `SIZEDEP', then 32 and 64 bit + * variants of the conversion functions are generated. + * - otherwise a 32 bit variant is generated. + * - if the type is a structure type, we generate 32 and 64 bit + * variants of the conversion functions. + */ + +define(`MAKE_TYPE_CONVERTER', + `ifdef(`BASE'_$1, + `ifdef(`IGNORE_'$1,`', + `MAKEPRIM_TO_F($1,$2,`',64) + MAKEPRIM_TO_M($1,$2,`',64)')', + `ifdef(`SIZEDEP_'$1, + `MAKEPRIM_TO_F($1,$2,32,32)dnl + MAKEPRIM_TO_M($1,$2,32,32)dnl + MAKEPRIM_TO_F($1,$2,64,64)dnl + MAKEPRIM_TO_M($1,$2,64,64)', + `MAKE_TO_F($1,$2,32)dnl + MAKE_TO_F($1,$2,64)dnl + MAKE_TO_M($1,$2,32)dnl + MAKE_TO_M($1,$2,64)')') +') + +define(`MAKE_TYPE_CONVERTERS', + `ifelse($#,1,`', + `MAKE_TYPE_CONVERTER($1)MAKE_TYPE_CONVERTERS(shift($@))')') + +divert(0) + +/* + * Sections of type ELF_T_BYTE are never byteswapped, consequently a + * simple memcpy suffices for both directions of conversion. + */ + +static void +libelf_cvt_BYTE_tox(char *dst, char *src, size_t count, int byteswap) +{ + (void) byteswap; + if (dst != src) + (void) memcpy(dst, src, count); +} + +/* + * Elf_Note structures comprise a fixed size header followed by variable + * length strings. The fixed size header needs to be byte swapped, but + * not the strings. + * + * Argument `count' denotes the total number of bytes to be converted. + */ +static void +libelf_cvt_NOTE_tom(char *dst, char *src, size_t count, int byteswap) +{ + uint32_t namesz, descsz, type; + Elf_Note *en; + size_t sz; + + if (dst == src && !byteswap) + return; + + if (!byteswap) { + (void) memcpy(dst, src, count); + return; + } + + while (count > sizeof(Elf_Note)) { + + READ_WORD(src, namesz); + READ_WORD(src, descsz); + READ_WORD(src, type); + + if (byteswap) { + SWAP_WORD(namesz); + SWAP_WORD(descsz); + SWAP_WORD(type); + } + + en = (Elf_Note *) (uintptr_t) dst; + en->n_namesz = namesz; + en->n_descsz = descsz; + en->n_type = type; + + dst += sizeof(Elf_Note); + + ROUNDUP2(namesz, 4); + ROUNDUP2(descsz, 4); + + sz = namesz + descsz; + + if (count < sz) + sz = count; + + (void) memcpy(dst, src, sz); + + src += sz; + dst += sz; + count -= sz; + } +} + +static void +libelf_cvt_NOTE_tof(char *dst, char *src, size_t count, int byteswap) +{ + uint32_t namesz, descsz, type; + Elf_Note *en; + size_t sz; + + if (dst == src && !byteswap) + return; + + if (!byteswap) { + (void) memcpy(dst, src, count); + return; + } + + while (count > sizeof(Elf_Note)) { + + en = (Elf_Note *) (uintptr_t) src; + namesz = en->n_namesz; + descsz = en->n_descsz; + type = en->n_type; + + if (byteswap) { + SWAP_WORD(namesz); + SWAP_WORD(descsz); + SWAP_WORD(type); + } + + + WRITE_WORD(dst, namesz); + WRITE_WORD(dst, descsz); + WRITE_WORD(dst, type); + + src += sizeof(Elf_Note); + + ROUNDUP2(namesz, 4); + ROUNDUP2(descsz, 4); + + sz = namesz + descsz; + + if (count < sz) + sz = count; + + (void) memcpy(dst, src, sz); + + src += sz; + dst += sz; + count -= sz; + } +} + +MAKE_TYPE_CONVERTERS(ELF_TYPE_LIST) + +struct converters { + void (*tof32)(char *dst, char *src, size_t cnt, int byteswap); + void (*tom32)(char *dst, char *src, size_t cnt, int byteswap); + void (*tof64)(char *dst, char *src, size_t cnt, int byteswap); + void (*tom64)(char *dst, char *src, size_t cnt, int byteswap); +}; + +divert(-1) +define(`CONV', + `ifdef(`IGNORE_'$1$2, + `.$3$2 = NULL', + `ifdef(`BASE_'$1, + `ifdef(`IGNORE_'$1, + `.$3$2 = NULL', + `.$3$2 = libelf_cvt_$1_$3')', + `ifdef(`SIZEDEP_'$1, + `.$3$2 = libelf_cvt_$1$2_$3', + `.$3$2 = libelf_cvt$2_$1_$3')')')') + +define(`CONVERTER_NAME', + `[ELF_T_$1] = { + CONV($1,32,tof), CONV($1,32,tom), + CONV($1,64,tof), CONV($1,64,tom) },')') + +define(`CONVERTER_NAMES', + `ifelse($#,1,`', + `CONVERTER_NAME($1)CONVERTER_NAMES(shift($@))')') + +undefine(`IGNORE_BYTE32') +undefine(`IGNORE_BYTE64') +divert(0) + +static struct converters cvt[ELF_T_NUM] = { +CONVERTER_NAMES(ELF_TYPE_LIST) + + /* + * Types that needs hand-coded converters follow. + */ + + [ELF_T_BYTE] = { + .tof32 = libelf_cvt_BYTE_tox, + .tom32 = libelf_cvt_BYTE_tox, + .tof64 = libelf_cvt_BYTE_tox, + .tom64 = libelf_cvt_BYTE_tox + }, + [ELF_T_NOTE] = { + .tof32 = libelf_cvt_NOTE_tof, + .tom32 = libelf_cvt_NOTE_tom, + .tof64 = libelf_cvt_NOTE_tof, + .tom64 = libelf_cvt_NOTE_tom + } +}; + +void (*_libelf_get_translator(Elf_Type t, int direction, int elfclass)) + (char *_dst, char *_src, size_t _cnt, int _byteswap) +{ + assert(elfclass == ELFCLASS32 || elfclass == ELFCLASS64); + assert(direction == ELF_TOFILE || direction == ELF_TOMEMORY); + + if (t >= ELF_T_NUM || + (elfclass != ELFCLASS32 && elfclass != ELFCLASS64) || + (direction != ELF_TOFILE && direction != ELF_TOMEMORY)) + return (NULL); + + return ((elfclass == ELFCLASS32) ? + (direction == ELF_TOFILE ? cvt[t].tof32 : cvt[t].tom32) : + (direction == ELF_TOFILE ? cvt[t].tof64 : cvt[t].tom64)); +} diff --git a/ext/libelf/libelf_data.c b/ext/libelf/libelf_data.c new file mode 100644 index 000000000..49c65754b --- /dev/null +++ b/ext/libelf/libelf_data.c @@ -0,0 +1,78 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "libelf.h" + +#include "_libelf.h" + +int +_libelf_xlate_shtype(uint32_t sht) +{ + switch (sht) { + case SHT_DYNAMIC: + return (ELF_T_DYN); + case SHT_DYNSYM: + return (ELF_T_SYM); + case SHT_FINI_ARRAY: + return (ELF_T_ADDR); + case SHT_GROUP: + return (ELF_T_WORD); + case SHT_HASH: + return (ELF_T_WORD); + case SHT_INIT_ARRAY: + return (ELF_T_ADDR); + case SHT_NOBITS: + return (ELF_T_BYTE); + case SHT_NOTE: + return (ELF_T_NOTE); + case SHT_PREINIT_ARRAY: + return (ELF_T_ADDR); + case SHT_PROGBITS: + return (ELF_T_BYTE); + case SHT_REL: + return (ELF_T_REL); + case SHT_RELA: + return (ELF_T_RELA); + case SHT_STRTAB: + return (ELF_T_BYTE); + case SHT_SYMTAB: + return (ELF_T_SYM); + case SHT_SYMTAB_SHNDX: + return (ELF_T_WORD); + case SHT_GNU_verdef: /* == SHT_SUNW_verdef */ + return (ELF_T_VDEF); + case SHT_GNU_verneed: /* == SHT_SUNW_verneed */ + return (ELF_T_VNEED); + case SHT_GNU_versym: /* == SHT_SUNW_versym */ + return (-1); /* XXX */ + case SHT_SUNW_move: + return (ELF_T_MOVE); + case SHT_SUNW_syminfo: + return (ELF_T_SYMINFO); + default: + return (-1); + } +} diff --git a/ext/libelf/libelf_ehdr.c b/ext/libelf/libelf_ehdr.c new file mode 100644 index 000000000..c90394681 --- /dev/null +++ b/ext/libelf/libelf_ehdr.c @@ -0,0 +1,201 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/libelf/libelf_ehdr.c,v 1.2 2006/12/25 02:22:22 jkoshy Exp $ + */ + +#include <assert.h> +#include "gelf.h" +#include "libelf.h" +#include <stdlib.h> + +#include "_libelf.h" + +/* + * Retrieve counts for sections, phdrs and the section string table index + * from section header #0 of the ELF object. + */ +static int +_libelf_load_extended(Elf *e, int ec, uint64_t shoff, uint16_t phnum, + uint16_t strndx) +{ + Elf_Scn *scn; + size_t fsz; + void (*xlator)(char *_d, char *_s, size_t _c, int _swap); + uint32_t shtype; + + assert(STAILQ_EMPTY(&e->e_u.e_elf.e_scn)); + + fsz = _libelf_fsize(ELF_T_SHDR, ec, e->e_version, 1); + assert(fsz > 0); + + if (e->e_rawsize < shoff + fsz) { /* raw file too small */ + LIBELF_SET_ERROR(HEADER, 0); + return (0); + } + + if ((scn = _libelf_allocate_scn(e, (size_t) 0)) == NULL) + return (0); + + xlator = _libelf_get_translator(ELF_T_SHDR, ELF_TOMEMORY, ec); + (*xlator)((char *) &scn->s_shdr, e->e_rawfile + shoff, (size_t) 1, + e->e_byteorder != LIBELF_PRIVATE(byteorder)); + +#define GET_SHDR_MEMBER(M) ((ec == ELFCLASS32) ? scn->s_shdr.s_shdr32.M : \ + scn->s_shdr.s_shdr64.M) + + if ((shtype = GET_SHDR_MEMBER(sh_type)) != SHT_NULL) { + LIBELF_SET_ERROR(SECTION, 0); + return (0); + } + + e->e_u.e_elf.e_nscn = GET_SHDR_MEMBER(sh_size); + e->e_u.e_elf.e_nphdr = (phnum != PN_XNUM) ? phnum : + GET_SHDR_MEMBER(sh_info); + e->e_u.e_elf.e_strndx = (strndx != SHN_XINDEX) ? strndx : + GET_SHDR_MEMBER(sh_link); +#undef GET_SHDR_MEMBER + + return (1); +} + +#define EHDR_INIT(E,SZ) do { \ + Elf##SZ##_Ehdr *eh = (E); \ + eh->e_ident[EI_MAG0] = ELFMAG0; \ + eh->e_ident[EI_MAG1] = ELFMAG1; \ + eh->e_ident[EI_MAG2] = ELFMAG2; \ + eh->e_ident[EI_MAG3] = ELFMAG3; \ + eh->e_ident[EI_CLASS] = ELFCLASS##SZ; \ + eh->e_ident[EI_DATA] = ELFDATANONE; \ + eh->e_ident[EI_VERSION] = LIBELF_PRIVATE(version); \ + eh->e_machine = EM_NONE; \ + eh->e_type = ELF_K_NONE; \ + eh->e_version = LIBELF_PRIVATE(version); \ + } while (0) + +void * +_libelf_ehdr(Elf *e, int ec, int allocate) +{ + void *ehdr; + size_t fsz, msz; + uint16_t phnum, shnum, strndx; + uint64_t shoff; + void (*xlator)(char *_d, char *_s, size_t _c, int _swap); + + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (e == NULL || e->e_kind != ELF_K_ELF) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (e->e_class != ELFCLASSNONE && e->e_class != ec) { + LIBELF_SET_ERROR(CLASS, 0); + return (NULL); + } + + if (e->e_version != EV_CURRENT) { + LIBELF_SET_ERROR(VERSION, 0); + return (NULL); + } + + if (e->e_class == ELFCLASSNONE) + e->e_class = ec; + + if (ec == ELFCLASS32) + ehdr = (void *) e->e_u.e_elf.e_ehdr.e_ehdr32; + else + ehdr = (void *) e->e_u.e_elf.e_ehdr.e_ehdr64; + + if (ehdr != NULL) /* already have a translated ehdr */ + return (ehdr); + + fsz = _libelf_fsize(ELF_T_EHDR, ec, e->e_version, (size_t) 1); + assert(fsz > 0); + + if (e->e_cmd != ELF_C_WRITE && e->e_rawsize < fsz) { + LIBELF_SET_ERROR(HEADER, 0); + return (NULL); + } + + msz = _libelf_msize(ELF_T_EHDR, ec, EV_CURRENT); + + assert(msz > 0); + + if ((ehdr = calloc((size_t) 1, msz)) == NULL) { + LIBELF_SET_ERROR(RESOURCE, 0); + return (NULL); + } + + if (ec == ELFCLASS32) { + e->e_u.e_elf.e_ehdr.e_ehdr32 = ehdr; + EHDR_INIT(ehdr,32); + } else { + e->e_u.e_elf.e_ehdr.e_ehdr64 = ehdr; + EHDR_INIT(ehdr,64); + } + + if (allocate) + e->e_flags |= ELF_F_DIRTY; + + if (e->e_cmd == ELF_C_WRITE) + return (ehdr); + + xlator = _libelf_get_translator(ELF_T_EHDR, ELF_TOMEMORY, ec); + (*xlator)(ehdr, e->e_rawfile, (size_t) 1, + e->e_byteorder != LIBELF_PRIVATE(byteorder)); + + /* + * If extended numbering is being used, read the correct + * number of sections and program header entries. + */ + if (ec == ELFCLASS32) { + phnum = ((Elf32_Ehdr *) ehdr)->e_phnum; + shnum = ((Elf32_Ehdr *) ehdr)->e_shnum; + shoff = ((Elf32_Ehdr *) ehdr)->e_shoff; + strndx = ((Elf32_Ehdr *) ehdr)->e_shstrndx; + } else { + phnum = ((Elf64_Ehdr *) ehdr)->e_phnum; + shnum = ((Elf64_Ehdr *) ehdr)->e_shnum; + shoff = ((Elf64_Ehdr *) ehdr)->e_shoff; + strndx = ((Elf64_Ehdr *) ehdr)->e_shstrndx; + } + + if (shnum >= SHN_LORESERVE || + (shoff == 0LL && (shnum != 0 || phnum == PN_XNUM || + strndx == SHN_XINDEX))) { + LIBELF_SET_ERROR(HEADER, 0); + return (NULL); + } + + if (shnum != 0 || shoff == 0LL) { /* not using extended numbering */ + e->e_u.e_elf.e_nphdr = phnum; + e->e_u.e_elf.e_nscn = shnum; + e->e_u.e_elf.e_strndx = strndx; + } else if (_libelf_load_extended(e, ec, shoff, phnum, strndx) == 0) + return (NULL); + + return (ehdr); +} diff --git a/ext/libelf/libelf_extended.c b/ext/libelf/libelf_extended.c new file mode 100644 index 000000000..01363aafe --- /dev/null +++ b/ext/libelf/libelf_extended.c @@ -0,0 +1,133 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <assert.h> +#include "libelf.h" + +#include "_libelf.h" + +/* + * Retrieve section #0, allocating a new section if needed. + */ +static Elf_Scn * +_libelf_getscn0(Elf *e) +{ + Elf_Scn *s; + + if ((s = STAILQ_FIRST(&e->e_u.e_elf.e_scn)) != NULL) + return (s); + + return (_libelf_allocate_scn(e, (size_t) SHN_UNDEF)); +} + +int +_libelf_setshnum(Elf *e, void *eh, int ec, size_t shnum) +{ + Elf_Scn *scn; + + if (shnum >= SHN_LORESERVE) { + if ((scn = _libelf_getscn0(e)) == NULL) + return (0); + + assert(scn->s_ndx == SHN_UNDEF); + + if (ec == ELFCLASS32) + scn->s_shdr.s_shdr32.sh_size = shnum; + else + scn->s_shdr.s_shdr64.sh_size = shnum; + + (void) elf_flagshdr(scn, ELF_C_SET, ELF_F_DIRTY); + + shnum = 0; + } + + if (ec == ELFCLASS32) + ((Elf32_Ehdr *) eh)->e_shnum = shnum; + else + ((Elf64_Ehdr *) eh)->e_shnum = shnum; + + + return (1); +} + +int +_libelf_setshstrndx(Elf *e, void *eh, int ec, size_t shstrndx) +{ + Elf_Scn *scn; + + if (shstrndx >= SHN_LORESERVE) { + if ((scn = _libelf_getscn0(e)) == NULL) + return (0); + + assert(scn->s_ndx == SHN_UNDEF); + + if (ec == ELFCLASS32) + scn->s_shdr.s_shdr32.sh_link = shstrndx; + else + scn->s_shdr.s_shdr64.sh_link = shstrndx; + + (void) elf_flagshdr(scn, ELF_C_SET, ELF_F_DIRTY); + + shstrndx = SHN_XINDEX; + } + + if (ec == ELFCLASS32) + ((Elf32_Ehdr *) eh)->e_shstrndx = shstrndx; + else + ((Elf64_Ehdr *) eh)->e_shstrndx = shstrndx; + + return (1); +} + +int +_libelf_setphnum(Elf *e, void *eh, int ec, size_t phnum) +{ + Elf_Scn *scn; + + if (phnum >= PN_XNUM) { + if ((scn = _libelf_getscn0(e)) == NULL) + return (0); + + assert(scn->s_ndx == SHN_UNDEF); + + if (ec == ELFCLASS32) + scn->s_shdr.s_shdr32.sh_info = phnum; + else + scn->s_shdr.s_shdr64.sh_info = phnum; + + (void) elf_flagshdr(scn, ELF_C_SET, ELF_F_DIRTY); + + phnum = PN_XNUM; + } + + if (ec == ELFCLASS32) + ((Elf32_Ehdr *) eh)->e_phnum = phnum; + else + ((Elf64_Ehdr *) eh)->e_phnum = phnum; + + return (1); +} + diff --git a/ext/libelf/libelf_fsize.m4 b/ext/libelf/libelf_fsize.m4 new file mode 100644 index 000000000..fa4657b34 --- /dev/null +++ b/ext/libelf/libelf_fsize.m4 @@ -0,0 +1,151 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/libelf/libelf_fsize.m4,v 1.2 2006/12/18 05:40:01 jkoshy Exp $ + */ + +#include "libelf.h" +#include "_libelf.h" + +/* + * Create an array of file sizes from the elf_type definitions + */ + +divert(-1) +include(SRCDIR`/elf_types.m4') + +/* + * Translations from structure definitions to the size of their file + * representations. + */ + +/* `Basic' types */ +define(`BYTE_SIZE', 1) +define(`IDENT_SIZE', `EI_NIDENT') +define(`NOTE_SIZE', 1) /* Elf_Note structures have variable length. */ + +/* Currently unimplemented types */ +define(`MOVEP_SIZE', 0) + +/* Overrides for 32 bit types that do not exist */ +define(`XWORD_SIZE32', 0) +define(`SXWORD_SIZE32', 0) + +/* + * FSZ{32,64} define the sizes of 32 and 64 bit file structures respectively. + */ + +define(`FSZ32',`_FSZ32($1_DEF)') +define(`_FSZ32', + `ifelse($#,1,0, + `_BSZ32($1)+_FSZ32(shift($@))')') +define(`_BSZ32',`$2_SIZE32') + +define(`FSZ64',`_FSZ64($1_DEF)') +define(`_FSZ64', + `ifelse($#,1,0, + `_BSZ64($1)+_FSZ64(shift($@))')') +define(`_BSZ64',`$2_SIZE64') + +/* + * DEFINE_ELF_FSIZES(TYPE,NAME) + * + * Shorthand for defining for 32 and 64 versions + * of elf type TYPE. + * + * If TYPE`'_SIZE is defined, use its value for both 32 bit and 64 bit + * sizes. + * + * Otherwise, look for a explicit 32/64 bit size definition for TYPE, + * TYPE`'_SIZE32 or TYPE`'_SIZE64. If this definition is present, there + * is nothing further to do. + * + * Otherwise, if an Elf{32,64}_`'NAME structure definition is known, + * compute an expression that adds up the sizes of the structure's + * constituents. + * + * If such a structure definition is not known, treat TYPE as a primitive + * (i.e., integral) type and use sizeof(Elf{32,64}_`'NAME) to get its + * file representation size. + */ + +define(`DEFINE_ELF_FSIZE', + `ifdef($1`_SIZE', + `define($1_SIZE32,$1_SIZE) + define($1_SIZE64,$1_SIZE)', + `ifdef($1`_SIZE32',`', + `ifdef(`Elf32_'$2`_DEF', + `define($1_SIZE32,FSZ32(Elf32_$2))', + `define($1_SIZE32,`sizeof(Elf32_'$2`)')')') + ifdef($1`_SIZE64',`', + `ifdef(`Elf64_'$2`_DEF', + `define($1_SIZE64,FSZ64(Elf64_$2))', + `define($1_SIZE64,`sizeof(Elf64_'$2`)')')')')') + +define(`DEFINE_ELF_FSIZES', + `ifelse($#,1,`', + `DEFINE_ELF_FSIZE($1) + DEFINE_ELF_FSIZES(shift($@))')') + +DEFINE_ELF_FSIZES(ELF_TYPE_LIST) +DEFINE_ELF_FSIZE(`IDENT',`') # `IDENT' is a pseudo type + +define(`FSIZE', + `[ELF_T_$1] = { .fsz32 = $1_SIZE32, .fsz64 = $1_SIZE64 },') +define(`FSIZES', + `ifelse($#,1,`', + `FSIZE($1) +FSIZES(shift($@))')') + +divert(0) + +struct fsize { + size_t fsz32; + size_t fsz64; +}; + +static struct fsize fsize[ELF_T_NUM] = { +FSIZES(ELF_TYPE_LIST) +}; + +size_t +_libelf_fsize(Elf_Type t, int ec, unsigned int v, size_t c) +{ + size_t sz; + + sz = 0; + if (v != EV_CURRENT) + LIBELF_SET_ERROR(VERSION, 0); + else if ((int) t < ELF_T_FIRST || t > ELF_T_LAST) + LIBELF_SET_ERROR(ARGUMENT, 0); + else { + sz = ec == ELFCLASS64 ? fsize[t].fsz64 : fsize[t].fsz32; + if (sz == 0) + LIBELF_SET_ERROR(UNIMPL, 0); + } + + return (sz*c); +} + diff --git a/ext/libelf/libelf_msize.m4 b/ext/libelf/libelf_msize.m4 new file mode 100644 index 000000000..cca31679b --- /dev/null +++ b/ext/libelf/libelf_msize.m4 @@ -0,0 +1,101 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/types.h> + +#include <assert.h> +#include <string.h> + +#include "elf32.h" +#include "elf64.h" +#include "libelf.h" +#include "_libelf.h" + +/* WARNING: GENERATED FROM __file__. */ + +struct msize { + size_t msz32; + size_t msz64; +}; + +divert(-1) +include(SRCDIR`/elf_types.m4') + +define(BYTE_SIZE, 1) +define(NOTE_SIZE, 1) + +/* + * Unimplemented types. + */ +define(MOVEP_SIZE, 0) +define(SXWORD_SIZE32, 0) +define(XWORD_SIZE32, 0) + +define(`DEFINE_ELF_MSIZE', + `ifdef($1`_SIZE', + `define($1_SIZE32,$1_SIZE) + define($1_SIZE64,$1_SIZE)', + `ifdef($1`_SIZE32',`', + `define($1_SIZE32,sizeof(Elf32_$2))') + ifdef($1`_SIZE64',`', + `define($1_SIZE64,sizeof(Elf64_$2))')')') +define(`DEFINE_ELF_MSIZES', + `ifelse($#,1,`', + `DEFINE_ELF_MSIZE($1) + DEFINE_ELF_MSIZES(shift($@))')') + +DEFINE_ELF_MSIZES(ELF_TYPE_LIST) + +define(`MSIZE', + `[ELF_T_$1] = { .msz32 = $1_SIZE32, .msz64 = $1_SIZE64 },') +define(`MSIZES', + `ifelse($#,1,`', + `MSIZE($1) +MSIZES(shift($@))')') + +divert(0) + +static struct msize msize[ELF_T_NUM] = { +MSIZES(ELF_TYPE_LIST) +}; + +size_t +_libelf_msize(Elf_Type t, int elfclass, unsigned int version) +{ + size_t sz; + + assert(elfclass == ELFCLASS32 || elfclass == ELFCLASS64); + assert((signed) t >= ELF_T_FIRST && t <= ELF_T_LAST); + + if (version != EV_CURRENT) { + LIBELF_SET_ERROR(VERSION, 0); + return (0); + } + + sz = (elfclass == ELFCLASS32) ? msize[t].msz32 : msize[t].msz64; + + return (sz); +} diff --git a/ext/libelf/libelf_phdr.c b/ext/libelf/libelf_phdr.c new file mode 100644 index 000000000..1d7e90bca --- /dev/null +++ b/ext/libelf/libelf_phdr.c @@ -0,0 +1,154 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD: src/lib/libelf/libelf_phdr.c,v 1.2 2006/12/25 02:22:22 jkoshy Exp $ + */ + +#include <assert.h> +#include <stdlib.h> + +#include "gelf.h" +#include "libelf.h" +#include "_libelf.h" + +void * +_libelf_getphdr(Elf *e, int ec) +{ + size_t phnum, phentsize; + size_t fsz, msz; + uint64_t phoff; + Elf32_Ehdr *eh32; + Elf64_Ehdr *eh64; + void *ehdr, *phdr; + void (*xlator)(char *_d, char *_s, size_t _c, int _swap); + + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + + if (e == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if ((phdr = (ec == ELFCLASS32 ? + (void *) e->e_u.e_elf.e_phdr.e_phdr32 : + (void *) e->e_u.e_elf.e_phdr.e_phdr64)) != NULL) + return (phdr); + + /* + * Check the PHDR related fields in the EHDR for sanity. + */ + + if ((ehdr = _libelf_ehdr(e, ec, 0)) == NULL) + return (NULL); + + phnum = e->e_u.e_elf.e_nphdr; + + if (ec == ELFCLASS32) { + eh32 = (Elf32_Ehdr *) ehdr; + phentsize = eh32->e_phentsize; + phoff = (uint64_t) eh32->e_phoff; + } else { + eh64 = (Elf64_Ehdr *) ehdr; + phentsize = eh64->e_phentsize; + phoff = (uint64_t) eh64->e_phoff; + } + + fsz = gelf_fsize(e, ELF_T_PHDR, phnum, e->e_version); + + assert(fsz > 0); + + if ((uint64_t) e->e_rawsize < (phoff + fsz)) { + LIBELF_SET_ERROR(HEADER, 0); + return (NULL); + } + + msz = _libelf_msize(ELF_T_PHDR, ec, EV_CURRENT); + + assert(msz > 0); + + if ((phdr = calloc(phnum, msz)) == NULL) { + LIBELF_SET_ERROR(RESOURCE, 0); + return (NULL); + } + + if (ec == ELFCLASS32) + e->e_u.e_elf.e_phdr.e_phdr32 = phdr; + else + e->e_u.e_elf.e_phdr.e_phdr64 = phdr; + + + xlator = _libelf_get_translator(ELF_T_PHDR, ELF_TOMEMORY, ec); + (*xlator)(phdr, e->e_rawfile + phoff, phnum, + e->e_byteorder != LIBELF_PRIVATE(byteorder)); + + return (phdr); +} + +void * +_libelf_newphdr(Elf *e, int ec, size_t count) +{ + void *ehdr, *newphdr, *oldphdr; + size_t msz; + + if (e == NULL) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if ((ehdr = _libelf_ehdr(e, ec, 0)) == NULL) { + LIBELF_SET_ERROR(SEQUENCE, 0); + return (NULL); + } + + assert(e->e_class == ec); + assert(ec == ELFCLASS32 || ec == ELFCLASS64); + assert(e->e_version == EV_CURRENT); + + msz = _libelf_msize(ELF_T_PHDR, ec, e->e_version); + + assert(msz > 0); + + newphdr = NULL; + if (count > 0 && (newphdr = calloc(count, msz)) == NULL) { + LIBELF_SET_ERROR(RESOURCE, 0); + return (NULL); + } + + if (ec == ELFCLASS32) { + if ((oldphdr = (void *) e->e_u.e_elf.e_phdr.e_phdr32) != NULL) + free(oldphdr); + e->e_u.e_elf.e_phdr.e_phdr32 = (Elf32_Phdr *) newphdr; + } else { + if ((oldphdr = (void *) e->e_u.e_elf.e_phdr.e_phdr64) != NULL) + free(oldphdr); + e->e_u.e_elf.e_phdr.e_phdr64 = (Elf64_Phdr *) newphdr; + } + + e->e_u.e_elf.e_nphdr = count; + + elf_flagphdr(e, ELF_C_SET, ELF_F_DIRTY); + + return (newphdr); +} diff --git a/ext/libelf/libelf_shdr.c b/ext/libelf/libelf_shdr.c new file mode 100644 index 000000000..c1e140719 --- /dev/null +++ b/ext/libelf/libelf_shdr.c @@ -0,0 +1,51 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "gelf.h" +#include "libelf.h" +#include "_libelf.h" + +void * +_libelf_getshdr(Elf_Scn *s, int ec) +{ + Elf *e; + + if (s == NULL || (e = s->s_elf) == NULL || + e->e_kind != ELF_K_ELF) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + if (ec == ELFCLASSNONE) + ec = e->e_class; + + if (ec != e->e_class) { + LIBELF_SET_ERROR(CLASS, 0); + return (NULL); + } + + return ((void *) &s->s_shdr); +} diff --git a/ext/libelf/libelf_xlate.c b/ext/libelf/libelf_xlate.c new file mode 100644 index 000000000..c5fea208d --- /dev/null +++ b/ext/libelf/libelf_xlate.c @@ -0,0 +1,141 @@ +/*- + * Copyright (c) 2006 Joseph Koshy + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <assert.h> + +#include "libelf.h" +#include "_libelf.h" + +/* + * Translate to/from the file representation of ELF objects. + * + * Translation could potentially involve the following + * transformations: + * + * - an endianness conversion, + * - a change of layout, as the file representation of ELF objects + * can differ from their in-memory representation. + * - a change in representation due to a layout version change. + */ + +Elf_Data * +_libelf_xlate(Elf_Data *dst, const Elf_Data *src, unsigned int encoding, + int elfclass, int direction) +{ + size_t cnt, dsz, fsz, msz; + uintptr_t sb, se, db, de; + + if (encoding == ELFDATANONE) + encoding = LIBELF_PRIVATE(byteorder); + + if ((encoding != ELFDATA2LSB && encoding != ELFDATA2MSB) || + dst == NULL || src == NULL || dst == src) { + LIBELF_SET_ERROR(ARGUMENT, 0); + return (NULL); + } + + assert(elfclass == ELFCLASS32 || elfclass == ELFCLASS64); + assert(direction == ELF_TOFILE || direction == ELF_TOMEMORY); + + if (dst->d_version != src->d_version) { + LIBELF_SET_ERROR(UNIMPL, 0); + return (NULL); + } + + if (src->d_buf == NULL || dst->d_buf == NULL || + src->d_size == 0) { + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + + if ((int) src->d_type < 0 || src->d_type >= ELF_T_NUM) { + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + + if ((fsz = (elfclass == ELFCLASS32 ? elf32_fsize : elf64_fsize)(src->d_type, + (size_t) 1, src->d_version)) == 0) + return (NULL); + + msz = _libelf_msize(src->d_type, elfclass, src->d_version); + + assert(msz > 0); + + if (src->d_size % (direction == ELF_TOMEMORY ? fsz : msz)) { + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + + /* + * Determine the number of objects that need to be converted, and + * the space required for the converted objects in the destination + * buffer. + */ + if (direction == ELF_TOMEMORY) { + cnt = src->d_size / fsz; + dsz = cnt * msz; + } else { + cnt = src->d_size / msz; + dsz = cnt * fsz; + } + + if (dst->d_size < dsz) { + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + + sb = (uintptr_t) src->d_buf; + se = sb + src->d_size; + db = (uintptr_t) dst->d_buf; + de = db + dst->d_size; + + /* + * Check for overlapping buffers. Note that db == sb is + * allowed. + */ + if (db != sb && de > sb && se > db) { + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + + if ((direction == ELF_TOMEMORY ? db : sb) % + _libelf_malign(src->d_type, elfclass)) { + LIBELF_SET_ERROR(DATA, 0); + return (NULL); + } + + dst->d_type = src->d_type; + dst->d_size = dsz; + + if (db == sb && encoding == LIBELF_PRIVATE(byteorder) && + fsz == msz) + return (dst); /* nothing more to do */ + + (_libelf_get_translator(src->d_type, direction, elfclass))(dst->d_buf, + src->d_buf, cnt, encoding != LIBELF_PRIVATE(byteorder)); + + return (dst); +} diff --git a/ext/ply/ANNOUNCE b/ext/ply/ANNOUNCE new file mode 100644 index 000000000..f40902021 --- /dev/null +++ b/ext/ply/ANNOUNCE @@ -0,0 +1,48 @@ +February 19, 2007 + + Announcing : PLY-2.3 (Python Lex-Yacc) + + http://www.dabeaz.com/ply + +I'm pleased to announce a significant new update to PLY---a 100% Python +implementation of the common parsing tools lex and yacc. PLY-2.3 is +a minor bug fix release, but also features improved performance. + +If you are new to PLY, here are a few highlights: + +- PLY is closely modeled after traditional lex/yacc. If you know how + to use these or similar tools in other languages, you will find + PLY to be comparable. + +- PLY provides very extensive error reporting and diagnostic + information to assist in parser construction. The original + implementation was developed for instructional purposes. As + a result, the system tries to identify the most common types + of errors made by novice users. + +- PLY provides full support for empty productions, error recovery, + precedence rules, and ambiguous grammars. + +- Parsing is based on LR-parsing which is fast, memory efficient, + better suited to large grammars, and which has a number of nice + properties when dealing with syntax errors and other parsing + problems. Currently, PLY can build its parsing tables using + either SLR or LALR(1) algorithms. + +- PLY can be used to build parsers for large programming languages. + Although it is not ultra-fast due to its Python implementation, + PLY can be used to parse grammars consisting of several hundred + rules (as might be found for a language like C). The lexer and LR + parser are also reasonably efficient when parsing normal + sized programs. + +More information about PLY can be obtained on the PLY webpage at: + + http://www.dabeaz.com/ply + +PLY is freely available and is licensed under the terms of the Lesser +GNU Public License (LGPL). + +Cheers, + +David Beazley (http://www.dabeaz.com)
\ No newline at end of file diff --git a/ext/ply/CHANGES b/ext/ply/CHANGES index 9c7334066..d88f3e5d6 100644 --- a/ext/ply/CHANGES +++ b/ext/ply/CHANGES @@ -1,3 +1,582 @@ +Version 2.3 +----------------------------- +02/20/07: beazley + Fixed a bug with character literals if the literal '.' appeared as the + last symbol of a grammar rule. Reported by Ales Smrcka. + +02/19/07: beazley + Warning messages are now redirected to stderr instead of being printed + to standard output. + +02/19/07: beazley + Added a warning message to lex.py if it detects a literal backslash + character inside the t_ignore declaration. This is to help + problems that might occur if someone accidentally defines t_ignore + as a Python raw string. For example: + + t_ignore = r' \t' + + The idea for this is from an email I received from David Cimimi who + reported bizarre behavior in lexing as a result of defining t_ignore + as a raw string by accident. + +02/18/07: beazley + Performance improvements. Made some changes to the internal + table organization and LR parser to improve parsing performance. + +02/18/07: beazley + Automatic tracking of line number and position information must now be + enabled by a special flag to parse(). For example: + + yacc.parse(data,tracking=True) + + In many applications, it's just not that important to have the + parser automatically track all line numbers. By making this an + optional feature, it allows the parser to run significantly faster + (more than a 20% speed increase in many cases). Note: positional + information is always available for raw tokens---this change only + applies to positional information associated with nonterminal + grammar symbols. + *** POTENTIAL INCOMPATIBILITY *** + +02/18/07: beazley + Yacc no longer supports extended slices of grammar productions. + However, it does support regular slices. For example: + + def p_foo(p): + '''foo: a b c d e''' + p[0] = p[1:3] + + This change is a performance improvement to the parser--it streamlines + normal access to the grammar values since slices are now handled in + a __getslice__() method as opposed to __getitem__(). + +02/12/07: beazley + Fixed a bug in the handling of token names when combined with + start conditions. Bug reported by Todd O'Bryan. + +Version 2.2 +------------------------------ +11/01/06: beazley + Added lexpos() and lexspan() methods to grammar symbols. These + mirror the same functionality of lineno() and linespan(). For + example: + + def p_expr(p): + 'expr : expr PLUS expr' + p.lexpos(1) # Lexing position of left-hand-expression + p.lexpos(1) # Lexing position of PLUS + start,end = p.lexspan(3) # Lexing range of right hand expression + +11/01/06: beazley + Minor change to error handling. The recommended way to skip characters + in the input is to use t.lexer.skip() as shown here: + + def t_error(t): + print "Illegal character '%s'" % t.value[0] + t.lexer.skip(1) + + The old approach of just using t.skip(1) will still work, but won't + be documented. + +10/31/06: beazley + Discarded tokens can now be specified as simple strings instead of + functions. To do this, simply include the text "ignore_" in the + token declaration. For example: + + t_ignore_cppcomment = r'//.*' + + Previously, this had to be done with a function. For example: + + def t_ignore_cppcomment(t): + r'//.*' + pass + + If start conditions/states are being used, state names should appear + before the "ignore_" text. + +10/19/06: beazley + The Lex module now provides support for flex-style start conditions + as described at http://www.gnu.org/software/flex/manual/html_chapter/flex_11.html. + Please refer to this document to understand this change note. Refer to + the PLY documentation for PLY-specific explanation of how this works. + + To use start conditions, you first need to declare a set of states in + your lexer file: + + states = ( + ('foo','exclusive'), + ('bar','inclusive') + ) + + This serves the same role as the %s and %x specifiers in flex. + + One a state has been declared, tokens for that state can be + declared by defining rules of the form t_state_TOK. For example: + + t_PLUS = '\+' # Rule defined in INITIAL state + t_foo_NUM = '\d+' # Rule defined in foo state + t_bar_NUM = '\d+' # Rule defined in bar state + + t_foo_bar_NUM = '\d+' # Rule defined in both foo and bar + t_ANY_NUM = '\d+' # Rule defined in all states + + In addition to defining tokens for each state, the t_ignore and t_error + specifications can be customized for specific states. For example: + + t_foo_ignore = " " # Ignored characters for foo state + def t_bar_error(t): + # Handle errors in bar state + + With token rules, the following methods can be used to change states + + def t_TOKNAME(t): + t.lexer.begin('foo') # Begin state 'foo' + t.lexer.push_state('foo') # Begin state 'foo', push old state + # onto a stack + t.lexer.pop_state() # Restore previous state + t.lexer.current_state() # Returns name of current state + + These methods mirror the BEGIN(), yy_push_state(), yy_pop_state(), and + yy_top_state() functions in flex. + + The use of start states can be used as one way to write sub-lexers. + For example, the lexer or parser might instruct the lexer to start + generating a different set of tokens depending on the context. + + example/yply/ylex.py shows the use of start states to grab C/C++ + code fragments out of traditional yacc specification files. + + *** NEW FEATURE *** Suggested by Daniel Larraz with whom I also + discussed various aspects of the design. + +10/19/06: beazley + Minor change to the way in which yacc.py was reporting shift/reduce + conflicts. Although the underlying LALR(1) algorithm was correct, + PLY was under-reporting the number of conflicts compared to yacc/bison + when precedence rules were in effect. This change should make PLY + report the same number of conflicts as yacc. + +10/19/06: beazley + Modified yacc so that grammar rules could also include the '-' + character. For example: + + def p_expr_list(p): + 'expression-list : expression-list expression' + + Suggested by Oldrich Jedlicka. + +10/18/06: beazley + Attribute lexer.lexmatch added so that token rules can access the re + match object that was generated. For example: + + def t_FOO(t): + r'some regex' + m = t.lexer.lexmatch + # Do something with m + + + This may be useful if you want to access named groups specified within + the regex for a specific token. Suggested by Oldrich Jedlicka. + +10/16/06: beazley + Changed the error message that results if an illegal character + is encountered and no default error function is defined in lex. + The exception is now more informative about the actual cause of + the error. + +Version 2.1 +------------------------------ +10/02/06: beazley + The last Lexer object built by lex() can be found in lex.lexer. + The last Parser object built by yacc() can be found in yacc.parser. + +10/02/06: beazley + New example added: examples/yply + + This example uses PLY to convert Unix-yacc specification files to + PLY programs with the same grammar. This may be useful if you + want to convert a grammar from bison/yacc to use with PLY. + +10/02/06: beazley + Added support for a start symbol to be specified in the yacc + input file itself. Just do this: + + start = 'name' + + where 'name' matches some grammar rule. For example: + + def p_name(p): + 'name : A B C' + ... + + This mirrors the functionality of the yacc %start specifier. + +09/30/06: beazley + Some new examples added.: + + examples/GardenSnake : A simple indentation based language similar + to Python. Shows how you might handle + whitespace. Contributed by Andrew Dalke. + + examples/BASIC : An implementation of 1964 Dartmouth BASIC. + Contributed by Dave against his better + judgement. + +09/28/06: beazley + Minor patch to allow named groups to be used in lex regular + expression rules. For example: + + t_QSTRING = r'''(?P<quote>['"]).*?(?P=quote)''' + + Patch submitted by Adam Ring. + +09/28/06: beazley + LALR(1) is now the default parsing method. To use SLR, use + yacc.yacc(method="SLR"). Note: there is no performance impact + on parsing when using LALR(1) instead of SLR. However, constructing + the parsing tables will take a little longer. + +09/26/06: beazley + Change to line number tracking. To modify line numbers, modify + the line number of the lexer itself. For example: + + def t_NEWLINE(t): + r'\n' + t.lexer.lineno += 1 + + This modification is both cleanup and a performance optimization. + In past versions, lex was monitoring every token for changes in + the line number. This extra processing is unnecessary for a vast + majority of tokens. Thus, this new approach cleans it up a bit. + + *** POTENTIAL INCOMPATIBILITY *** + You will need to change code in your lexer that updates the line + number. For example, "t.lineno += 1" becomes "t.lexer.lineno += 1" + +09/26/06: beazley + Added the lexing position to tokens as an attribute lexpos. This + is the raw index into the input text at which a token appears. + This information can be used to compute column numbers and other + details (e.g., scan backwards from lexpos to the first newline + to get a column position). + +09/25/06: beazley + Changed the name of the __copy__() method on the Lexer class + to clone(). This is used to clone a Lexer object (e.g., if + you're running different lexers at the same time). + +09/21/06: beazley + Limitations related to the use of the re module have been eliminated. + Several users reported problems with regular expressions exceeding + more than 100 named groups. To solve this, lex.py is now capable + of automatically splitting its master regular regular expression into + smaller expressions as needed. This should, in theory, make it + possible to specify an arbitrarily large number of tokens. + +09/21/06: beazley + Improved error checking in lex.py. Rules that match the empty string + are now rejected (otherwise they cause the lexer to enter an infinite + loop). An extra check for rules containing '#' has also been added. + Since lex compiles regular expressions in verbose mode, '#' is interpreted + as a regex comment, it is critical to use '\#' instead. + +09/18/06: beazley + Added a @TOKEN decorator function to lex.py that can be used to + define token rules where the documentation string might be computed + in some way. + + digit = r'([0-9])' + nondigit = r'([_A-Za-z])' + identifier = r'(' + nondigit + r'(' + digit + r'|' + nondigit + r')*)' + + from ply.lex import TOKEN + + @TOKEN(identifier) + def t_ID(t): + # Do whatever + + The @TOKEN decorator merely sets the documentation string of the + associated token function as needed for lex to work. + + Note: An alternative solution is the following: + + def t_ID(t): + # Do whatever + + t_ID.__doc__ = identifier + + Note: Decorators require the use of Python 2.4 or later. If compatibility + with old versions is needed, use the latter solution. + + The need for this feature was suggested by Cem Karan. + +09/14/06: beazley + Support for single-character literal tokens has been added to yacc. + These literals must be enclosed in quotes. For example: + + def p_expr(p): + "expr : expr '+' expr" + ... + + def p_expr(p): + 'expr : expr "-" expr' + ... + + In addition to this, it is necessary to tell the lexer module about + literal characters. This is done by defining the variable 'literals' + as a list of characters. This should be defined in the module that + invokes the lex.lex() function. For example: + + literals = ['+','-','*','/','(',')','='] + + or simply + + literals = '+=*/()=' + + It is important to note that literals can only be a single character. + When the lexer fails to match a token using its normal regular expression + rules, it will check the current character against the literal list. + If found, it will be returned with a token type set to match the literal + character. Otherwise, an illegal character will be signalled. + + +09/14/06: beazley + Modified PLY to install itself as a proper Python package called 'ply'. + This will make it a little more friendly to other modules. This + changes the usage of PLY only slightly. Just do this to import the + modules + + import ply.lex as lex + import ply.yacc as yacc + + Alternatively, you can do this: + + from ply import * + + Which imports both the lex and yacc modules. + Change suggested by Lee June. + +09/13/06: beazley + Changed the handling of negative indices when used in production rules. + A negative production index now accesses already parsed symbols on the + parsing stack. For example, + + def p_foo(p): + "foo: A B C D" + print p[1] # Value of 'A' symbol + print p[2] # Value of 'B' symbol + print p[-1] # Value of whatever symbol appears before A + # on the parsing stack. + + p[0] = some_val # Sets the value of the 'foo' grammer symbol + + This behavior makes it easier to work with embedded actions within the + parsing rules. For example, in C-yacc, it is possible to write code like + this: + + bar: A { printf("seen an A = %d\n", $1); } B { do_stuff; } + + In this example, the printf() code executes immediately after A has been + parsed. Within the embedded action code, $1 refers to the A symbol on + the stack. + + To perform this equivalent action in PLY, you need to write a pair + of rules like this: + + def p_bar(p): + "bar : A seen_A B" + do_stuff + + def p_seen_A(p): + "seen_A :" + print "seen an A =", p[-1] + + The second rule "seen_A" is merely a empty production which should be + reduced as soon as A is parsed in the "bar" rule above. The use + of the negative index p[-1] is used to access whatever symbol appeared + before the seen_A symbol. + + This feature also makes it possible to support inherited attributes. + For example: + + def p_decl(p): + "decl : scope name" + + def p_scope(p): + """scope : GLOBAL + | LOCAL""" + p[0] = p[1] + + def p_name(p): + "name : ID" + if p[-1] == "GLOBAL": + # ... + else if p[-1] == "LOCAL": + #... + + In this case, the name rule is inheriting an attribute from the + scope declaration that precedes it. + + *** POTENTIAL INCOMPATIBILITY *** + If you are currently using negative indices within existing grammar rules, + your code will break. This should be extremely rare if non-existent in + most cases. The argument to various grammar rules is not usually not + processed in the same way as a list of items. + +Version 2.0 +------------------------------ +09/07/06: beazley + Major cleanup and refactoring of the LR table generation code. Both SLR + and LALR(1) table generation is now performed by the same code base with + only minor extensions for extra LALR(1) processing. + +09/07/06: beazley + Completely reimplemented the entire LALR(1) parsing engine to use the + DeRemer and Pennello algorithm for calculating lookahead sets. This + significantly improves the performance of generating LALR(1) tables + and has the added feature of actually working correctly! If you + experienced weird behavior with LALR(1) in prior releases, this should + hopefully resolve all of those problems. Many thanks to + Andrew Waters and Markus Schoepflin for submitting bug reports + and helping me test out the revised LALR(1) support. + +Version 1.8 +------------------------------ +08/02/06: beazley + Fixed a problem related to the handling of default actions in LALR(1) + parsing. If you experienced subtle and/or bizarre behavior when trying + to use the LALR(1) engine, this may correct those problems. Patch + contributed by Russ Cox. Note: This patch has been superceded by + revisions for LALR(1) parsing in Ply-2.0. + +08/02/06: beazley + Added support for slicing of productions in yacc. + Patch contributed by Patrick Mezard. + +Version 1.7 +------------------------------ +03/02/06: beazley + Fixed infinite recursion problem ReduceToTerminals() function that + would sometimes come up in LALR(1) table generation. Reported by + Markus Schoepflin. + +03/01/06: beazley + Added "reflags" argument to lex(). For example: + + lex.lex(reflags=re.UNICODE) + + This can be used to specify optional flags to the re.compile() function + used inside the lexer. This may be necessary for special situations such + as processing Unicode (e.g., if you want escapes like \w and \b to consult + the Unicode character property database). The need for this suggested by + Andreas Jung. + +03/01/06: beazley + Fixed a bug with an uninitialized variable on repeated instantiations of parser + objects when the write_tables=0 argument was used. Reported by Michael Brown. + +03/01/06: beazley + Modified lex.py to accept Unicode strings both as the regular expressions for + tokens and as input. Hopefully this is the only change needed for Unicode support. + Patch contributed by Johan Dahl. + +03/01/06: beazley + Modified the class-based interface to work with new-style or old-style classes. + Patch contributed by Michael Brown (although I tweaked it slightly so it would work + with older versions of Python). + +Version 1.6 +------------------------------ +05/27/05: beazley + Incorporated patch contributed by Christopher Stawarz to fix an extremely + devious bug in LALR(1) parser generation. This patch should fix problems + numerous people reported with LALR parsing. + +05/27/05: beazley + Fixed problem with lex.py copy constructor. Reported by Dave Aitel, Aaron Lav, + and Thad Austin. + +05/27/05: beazley + Added outputdir option to yacc() to control output directory. Contributed + by Christopher Stawarz. + +05/27/05: beazley + Added rununit.py test script to run tests using the Python unittest module. + Contributed by Miki Tebeka. + +Version 1.5 +------------------------------ +05/26/04: beazley + Major enhancement. LALR(1) parsing support is now working. + This feature was implemented by Elias Ioup (ezioup@alumni.uchicago.edu) + and optimized by David Beazley. To use LALR(1) parsing do + the following: + + yacc.yacc(method="LALR") + + Computing LALR(1) parsing tables takes about twice as long as + the default SLR method. However, LALR(1) allows you to handle + more complex grammars. For example, the ANSI C grammar + (in example/ansic) has 13 shift-reduce conflicts with SLR, but + only has 1 shift-reduce conflict with LALR(1). + +05/20/04: beazley + Added a __len__ method to parser production lists. Can + be used in parser rules like this: + + def p_somerule(p): + """a : B C D + | E F" + if (len(p) == 3): + # Must have been first rule + elif (len(p) == 2): + # Must be second rule + + Suggested by Joshua Gerth and others. + +Version 1.4 +------------------------------ +04/23/04: beazley + Incorporated a variety of patches contributed by Eric Raymond. + These include: + + 0. Cleans up some comments so they don't wrap on an 80-column display. + 1. Directs compiler errors to stderr where they belong. + 2. Implements and documents automatic line counting when \n is ignored. + 3. Changes the way progress messages are dumped when debugging is on. + The new format is both less verbose and conveys more information than + the old, including shift and reduce actions. + +04/23/04: beazley + Added a Python setup.py file to simply installation. Contributed + by Adam Kerrison. + +04/23/04: beazley + Added patches contributed by Adam Kerrison. + + - Some output is now only shown when debugging is enabled. This + means that PLY will be completely silent when not in debugging mode. + + - An optional parameter "write_tables" can be passed to yacc() to + control whether or not parsing tables are written. By default, + it is true, but it can be turned off if you don't want the yacc + table file. Note: disabling this will cause yacc() to regenerate + the parsing table each time. + +04/23/04: beazley + Added patches contributed by David McNab. This patch addes two + features: + + - The parser can be supplied as a class instead of a module. + For an example of this, see the example/classcalc directory. + + - Debugging output can be directed to a filename of the user's + choice. Use + + yacc(debugfile="somefile.out") + + Version 1.3 ------------------------------ 12/10/02: jmdyck diff --git a/ext/ply/README b/ext/ply/README index 35b458d4c..6e246c2bd 100644 --- a/ext/ply/README +++ b/ext/ply/README @@ -1,14 +1,8 @@ -PLY (Python Lex-Yacc) Version 1.2 (November 27, 2002) +PLY (Python Lex-Yacc) Version 2.3 (February 18, 2007) -David M. Beazley -Department of Computer Science -University of Chicago -Chicago, IL 60637 -beazley@cs.uchicago.edu +David M. Beazley (dave@dabeaz.com) -Copyright (C) 2001 David M. Beazley - -$Header: /home/stever/bk/newmem2/ext/ply/README 1.1 03/06/06 14:53:34-00:00 stever@ $ +Copyright (C) 2001-2007 David M. Beazley This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public @@ -52,11 +46,10 @@ Python, there are several reasons why you might want to consider PLY: Currently, PLY builds its parsing tables using the SLR algorithm which is slightly weaker than LALR(1) used in traditional yacc. - - Like John Aycock's excellent SPARK toolkit, PLY uses Python - reflection to build lexers and parsers. This greatly simplifies - the task of parser construction since it reduces the number of files - and eliminates the need to run a separate lex/yacc tool before - running your program. + - PLY uses Python introspection features to build lexers and parsers. + This greatly simplifies the task of parser construction since it reduces + the number of files and eliminates the need to run a separate lex/yacc + tool before running your program. - PLY can be used to build parsers for "real" programming languages. Although it is not ultra-fast due to its Python implementation, @@ -77,51 +70,79 @@ common usability problems. How to Use ========== -PLY consists of two files : lex.py and yacc.py. To use the system, -simply copy these files to your project and import them like standard -Python modules. +PLY consists of two files : lex.py and yacc.py. These are contained +within the 'ply' directory which may also be used as a Python package. +To use PLY, simply copy the 'ply' directory to your project and import +lex and yacc from the associated 'ply' package. For example: + + import ply.lex as lex + import ply.yacc as yacc + +Alternatively, you can copy just the files lex.py and yacc.py +individually and use them as modules. For example: + + import lex + import yacc + +The file setup.py can be used to install ply using distutils. The file doc/ply.html contains complete documentation on how to use the system. The example directory contains several different examples including a -PLY specification for ANSI C as given in K&R 2nd Ed. Note: To use -the examples, you will need to copy the lex.py and yacc.py files to -the example directory. +PLY specification for ANSI C as given in K&R 2nd Ed. A simple example is found at the end of this document Requirements ============ -PLY requires the use of Python 2.0 or greater. It should work on -just about any platform. +PLY requires the use of Python 2.1 or greater. However, you should +use the latest Python release if possible. It should work on just +about any platform. PLY has been tested with both CPython and Jython. +However, it does not seem to work with IronPython. Resources ========= - More information about PLY can be obtained on the PLY webpage at: - http://systems.cs.uchicago.edu/ply + http://www.dabeaz.com/ply For a detailed overview of parsing theory, consult the excellent book "Compilers : Principles, Techniques, and Tools" by Aho, Sethi, and Ullman. The topics found in "Lex & Yacc" by Levine, Mason, and Brown may also be useful. -Given that this is the first release, I welcome your comments on how -to improve the current implementation. See the TODO file for things that -still need to be done. +A Google group for PLY can be found at + + http://groups.google.com/group/ply-hack Acknowledgments =============== - A special thanks is in order for all of the students in CS326 who suffered through about 25 different versions of these tools :-). +The CHANGES file acknowledges those who have contributed patches. + +Elias Ioup did the first implementation of LALR(1) parsing in PLY-1.x. +Andrew Waters and Markus Schoepflin were instrumental in reporting bugs +and testing a revised LALR(1) implementation for PLY-2.0. + +Special Note for PLY-2.x +======================== +PLY-2.0 is the first in a series of PLY releases that will be adding a +variety of significant new features. The first release in this series +(Ply-2.0) should be 100% compatible with all previous Ply-1.x releases +except for the fact that Ply-2.0 features a correct implementation of +LALR(1) table generation. + +If you have suggestions for improving PLY in future 2.x releases, please +contact me. - Dave + Example ======= -Here is a simple example showing a PLY implementation of a calculator with variables. +Here is a simple example showing a PLY implementation of a calculator +with variables. # ----------------------------------------------------------------------------- # calc.py @@ -160,14 +181,14 @@ t_ignore = " \t" def t_newline(t): r'\n+' - t.lineno += t.value.count("\n") + t.lexer.lineno += t.value.count("\n") def t_error(t): print "Illegal character '%s'" % t.value[0] - t.skip(1) + t.lexer.skip(1) # Build the lexer -import lex +import ply.lex as lex lex.lex() # Precedence rules for the arithmetic operators @@ -180,48 +201,48 @@ precedence = ( # dictionary of names (for storing variables) names = { } -def p_statement_assign(t): +def p_statement_assign(p): 'statement : NAME EQUALS expression' - names[t[1]] = t[3] + names[p[1]] = p[3] -def p_statement_expr(t): +def p_statement_expr(p): 'statement : expression' - print t[1] + print p[1] -def p_expression_binop(t): +def p_expression_binop(p): '''expression : expression PLUS expression | expression MINUS expression | expression TIMES expression | expression DIVIDE expression''' - if t[2] == '+' : t[0] = t[1] + t[3] - elif t[2] == '-': t[0] = t[1] - t[3] - elif t[2] == '*': t[0] = t[1] * t[3] - elif t[2] == '/': t[0] = t[1] / t[3] + if p[2] == '+' : p[0] = p[1] + p[3] + elif p[2] == '-': p[0] = p[1] - p[3] + elif p[2] == '*': p[0] = p[1] * p[3] + elif p[2] == '/': p[0] = p[1] / p[3] -def p_expression_uminus(t): +def p_expression_uminus(p): 'expression : MINUS expression %prec UMINUS' - t[0] = -t[2] + p[0] = -p[2] -def p_expression_group(t): +def p_expression_group(p): 'expression : LPAREN expression RPAREN' - t[0] = t[2] + p[0] = p[2] -def p_expression_number(t): +def p_expression_number(p): 'expression : NUMBER' - t[0] = t[1] + p[0] = p[1] -def p_expression_name(t): +def p_expression_name(p): 'expression : NAME' try: - t[0] = names[t[1]] + p[0] = names[p[1]] except LookupError: - print "Undefined name '%s'" % t[1] - t[0] = 0 + print "Undefined name '%s'" % p[1] + p[0] = 0 -def p_error(t): - print "Syntax error at '%s'" % t.value +def p_error(p): + print "Syntax error at '%s'" % p.value -import yacc +import ply.yacc as yacc yacc.yacc() while 1: @@ -232,16 +253,24 @@ while 1: yacc.parse(s) +Bug Reports and Patches +======================= +Because of the extremely specialized and advanced nature of PLY, I +rarely spend much time working on it unless I receive very specific +bug-reports and/or patches to fix problems. I also try to incorporate +submitted feature requests and enhancements into each new version. To +contact me about bugs and/or new features, please send email to +dave@dabeaz.com. +In addition there is a Google group for discussing PLY related issues at + http://groups.google.com/group/ply-hack + +-- Dave - - - - diff --git a/ext/ply/TODO b/ext/ply/TODO index b2978150d..7139d53d1 100644 --- a/ext/ply/TODO +++ b/ext/ply/TODO @@ -1,22 +1,14 @@ The PLY to-do list: -$Header: /home/stever/bk/newmem2/ext/ply/TODO 1.1 03/06/06 14:53:34-00:00 stever@ $ +1. More interesting parsing examples. -1. Create a Python package using distutils - -2. More interesting parsing examples. - -3. Work on the ANSI C grammar so that it can actually parse C programs. To do this, +2. Work on the ANSI C grammar so that it can actually parse C programs. To do this, some extra code needs to be added to the lexer to deal with typedef names and enumeration constants. -4. Get LALR(1) to work. Hard, but not impossible. - -5. More tests in the test directory. - -6. Performance improvements and cleanup in yacc.py. +3. More tests in the test directory. -7. More documentation. +4. Performance improvements and cleanup in yacc.py. -8. Lots and lots of cleanup. +5. More documentation (?). diff --git a/ext/ply/doc/makedoc.py b/ext/ply/doc/makedoc.py new file mode 100644 index 000000000..3eed9bd74 --- /dev/null +++ b/ext/ply/doc/makedoc.py @@ -0,0 +1,194 @@ +#!/usr/local/bin/python + +############################################################################### +# Takes a chapter as input and adds internal links and numbering to all +# of the H1, H2, H3, H4 and H5 sections. +# +# Every heading HTML tag (H1, H2 etc) is given an autogenerated name to link +# to. However, if the name is not an autogenerated name from a previous run, +# it will be kept. If it is autogenerated, it might change on subsequent runs +# of this program. Thus if you want to create links to one of the headings, +# then change the heading link name to something that does not look like an +# autogenerated link name. +############################################################################### + +import sys +import re +import string + +############################################################################### +# Functions +############################################################################### + +# Regexs for <a name="..."></a> +alink = re.compile(r"<a *name *= *\"(.*)\"></a>", re.IGNORECASE) +heading = re.compile(r"(_nn\d)", re.IGNORECASE) + +def getheadingname(m): + autogeneratedheading = True; + if m.group(1) != None: + amatch = alink.match(m.group(1)) + if amatch: + # A non-autogenerated heading - keep it + headingname = amatch.group(1) + autogeneratedheading = heading.match(headingname) + if autogeneratedheading: + # The heading name was either non-existent or autogenerated, + # We can create a new heading / change the existing heading + headingname = "%s_nn%d" % (filenamebase, nameindex) + return headingname + +############################################################################### +# Main program +############################################################################### + +if len(sys.argv) != 2: + print "usage: makedoc.py filename" + sys.exit(1) + +filename = sys.argv[1] +filenamebase = string.split(filename,".")[0] + +section = 0 +subsection = 0 +subsubsection = 0 +subsubsubsection = 0 +nameindex = 0 + +name = "" + +# Regexs for <h1>,... <h5> sections + +h1 = re.compile(r".*?<H1>(<a.*a>)*[\d\.\s]*(.*?)</H1>", re.IGNORECASE) +h2 = re.compile(r".*?<H2>(<a.*a>)*[\d\.\s]*(.*?)</H2>", re.IGNORECASE) +h3 = re.compile(r".*?<H3>(<a.*a>)*[\d\.\s]*(.*?)</H3>", re.IGNORECASE) +h4 = re.compile(r".*?<H4>(<a.*a>)*[\d\.\s]*(.*?)</H4>", re.IGNORECASE) +h5 = re.compile(r".*?<H5>(<a.*a>)*[\d\.\s]*(.*?)</H5>", re.IGNORECASE) + +data = open(filename).read() # Read data +open(filename+".bak","w").write(data) # Make backup + +lines = data.splitlines() +result = [ ] # This is the result of postprocessing the file +index = "<!-- INDEX -->\n<div class=\"sectiontoc\">\n" # index contains the index for adding at the top of the file. Also printed to stdout. + +skip = 0 +skipspace = 0 + +for s in lines: + if s == "<!-- INDEX -->": + if not skip: + result.append("@INDEX@") + skip = 1 + else: + skip = 0 + continue; + if skip: + continue + + if not s and skipspace: + continue + + if skipspace: + result.append("") + result.append("") + skipspace = 0 + + m = h2.match(s) + if m: + prevheadingtext = m.group(2) + nameindex += 1 + section += 1 + headingname = getheadingname(m) + result.append("""<H2><a name="%s"></a>%d. %s</H2>""" % (headingname,section, prevheadingtext)) + + if subsubsubsection: + index += "</ul>\n" + if subsubsection: + index += "</ul>\n" + if subsection: + index += "</ul>\n" + if section == 1: + index += "<ul>\n" + + index += """<li><a href="#%s">%s</a>\n""" % (headingname,prevheadingtext) + subsection = 0 + subsubsection = 0 + subsubsubsection = 0 + skipspace = 1 + continue + m = h3.match(s) + if m: + prevheadingtext = m.group(2) + nameindex += 1 + subsection += 1 + headingname = getheadingname(m) + result.append("""<H3><a name="%s"></a>%d.%d %s</H3>""" % (headingname,section, subsection, prevheadingtext)) + + if subsubsubsection: + index += "</ul>\n" + if subsubsection: + index += "</ul>\n" + if subsection == 1: + index += "<ul>\n" + + index += """<li><a href="#%s">%s</a>\n""" % (headingname,prevheadingtext) + subsubsection = 0 + skipspace = 1 + continue + m = h4.match(s) + if m: + prevheadingtext = m.group(2) + nameindex += 1 + subsubsection += 1 + subsubsubsection = 0 + headingname = getheadingname(m) + result.append("""<H4><a name="%s"></a>%d.%d.%d %s</H4>""" % (headingname,section, subsection, subsubsection, prevheadingtext)) + + if subsubsubsection: + index += "</ul>\n" + if subsubsection == 1: + index += "<ul>\n" + + index += """<li><a href="#%s">%s</a>\n""" % (headingname,prevheadingtext) + skipspace = 1 + continue + m = h5.match(s) + if m: + prevheadingtext = m.group(2) + nameindex += 1 + subsubsubsection += 1 + headingname = getheadingname(m) + result.append("""<H5><a name="%s"></a>%d.%d.%d.%d %s</H5>""" % (headingname,section, subsection, subsubsection, subsubsubsection, prevheadingtext)) + + if subsubsubsection == 1: + index += "<ul>\n" + + index += """<li><a href="#%s">%s</a>\n""" % (headingname,prevheadingtext) + skipspace = 1 + continue + + result.append(s) + +if subsubsubsection: + index += "</ul>\n" + +if subsubsection: + index += "</ul>\n" + +if subsection: + index += "</ul>\n" + +if section: + index += "</ul>\n" + +index += "</div>\n<!-- INDEX -->\n" + +data = "\n".join(result) + +data = data.replace("@INDEX@",index) + "\n"; + +# Write the file back out +open(filename,"w").write(data) + + diff --git a/ext/ply/doc/ply.html b/ext/ply/doc/ply.html index 2596066fe..dba0c6288 100644 --- a/ext/ply/doc/ply.html +++ b/ext/ply/doc/ply.html @@ -5,70 +5,131 @@ <body bgcolor="#ffffff"> <h1>PLY (Python Lex-Yacc)</h1> - + <b> David M. Beazley <br> -Department of Computer Science <br> -University of Chicago <br> -Chicago, IL 60637 <br> -beazley@cs.uchicago.edu <br> +dave@dabeaz.com<br> </b> <p> -Documentation version: $Header: /home/stever/bk/newmem2/ext/ply/doc/ply.html 1.1 03/06/06 14:53:34-00:00 stever@ $ +<b>PLY Version: 2.3</b> +<p> + +<!-- INDEX --> +<div class="sectiontoc"> +<ul> +<li><a href="#ply_nn1">Introduction</a> +<li><a href="#ply_nn2">PLY Overview</a> +<li><a href="#ply_nn3">Lex</a> +<ul> +<li><a href="#ply_nn4">Lex Example</a> +<li><a href="#ply_nn5">The tokens list</a> +<li><a href="#ply_nn6">Specification of tokens</a> +<li><a href="#ply_nn7">Token values</a> +<li><a href="#ply_nn8">Discarded tokens</a> +<li><a href="#ply_nn9">Line numbers and positional information</a> +<li><a href="#ply_nn10">Ignored characters</a> +<li><a href="#ply_nn11">Literal characters</a> +<li><a href="#ply_nn12">Error handling</a> +<li><a href="#ply_nn13">Building and using the lexer</a> +<li><a href="#ply_nn14">The @TOKEN decorator</a> +<li><a href="#ply_nn15">Optimized mode</a> +<li><a href="#ply_nn16">Debugging</a> +<li><a href="#ply_nn17">Alternative specification of lexers</a> +<li><a href="#ply_nn18">Maintaining state</a> +<li><a href="#ply_nn19">Duplicating lexers</a> +<li><a href="#ply_nn20">Internal lexer state</a> +<li><a href="#ply_nn21">Conditional lexing and start conditions</a> +<li><a href="#ply_nn21">Miscellaneous Issues</a> +</ul> +<li><a href="#ply_nn22">Parsing basics</a> +<li><a href="#ply_nn23">Yacc reference</a> +<ul> +<li><a href="#ply_nn24">An example</a> +<li><a href="#ply_nn25">Combining Grammar Rule Functions</a> +<li><a href="#ply_nn26">Character Literals</a> +<li><a href="#ply_nn26">Empty Productions</a> +<li><a href="#ply_nn28">Changing the starting symbol</a> +<li><a href="#ply_nn27">Dealing With Ambiguous Grammars</a> +<li><a href="#ply_nn28">The parser.out file</a> +<li><a href="#ply_nn29">Syntax Error Handling</a> +<ul> +<li><a href="#ply_nn30">Recovery and resynchronization with error rules</a> +<li><a href="#ply_nn31">Panic mode recovery</a> +<li><a href="#ply_nn32">General comments on error handling</a> +</ul> +<li><a href="#ply_nn33">Line Number and Position Tracking</a> +<li><a href="#ply_nn34">AST Construction</a> +<li><a href="#ply_nn35">Embedded Actions</a> +<li><a href="#ply_nn36">Yacc implementation notes</a> +</ul> +<li><a href="#ply_nn37">Parser and Lexer State Management</a> +<li><a href="#ply_nn38">Using Python's Optimized Mode</a> +<li><a href="#ply_nn39">Where to go from here?</a> +</ul> +</div> +<!-- INDEX --> + -<h2>Introduction</h2> -PLY is a Python-only implementation of the popular compiler -construction tools lex and yacc. The implementation borrows ideas -from a number of previous efforts; most notably John Aycock's SPARK -toolkit. However, the overall flavor of the implementation is more -closely modeled after the C version of lex and yacc. The other -significant feature of PLY is that it provides extensive input -validation and error reporting--much more so than other Python parsing -tools. + + + +<H2><a name="ply_nn1"></a>1. Introduction</H2> + + +PLY is a pure-Python implementation of the popular compiler +construction tools lex and yacc. The main goal of PLY is to stay +fairly faithful to the way in which traditional lex/yacc tools work. +This includes supporting LALR(1) parsing as well as providing +extensive input validation, error reporting, and diagnostics. Thus, +if you've used yacc in another programming language, it should be +relatively straightforward to use PLY. <p> -Early versions of PLY were developed to support the Introduction to -Compilers Course at the University of Chicago. In this course, +Early versions of PLY were developed to support an Introduction to +Compilers Course I taught in 2001 at the University of Chicago. In this course, students built a fully functional compiler for a simple Pascal-like language. Their compiler, implemented entirely in Python, had to include lexical analysis, parsing, type checking, type inference, nested scoping, and code generation for the SPARC processor. Approximately 30 different compiler implementations were completed in -this course. Most of PLY's interface and operation has been motivated by common +this course. Most of PLY's interface and operation has been influenced by common usability problems encountered by students. <p> -Because PLY was primarily developed as an instructional tool, you will -find it to be <em>MUCH</em> more picky about token and grammar rule -specification than most other Python parsing tools. In part, this +Since PLY was primarily developed as an instructional tool, you will +find it to be fairly picky about token and grammar rule +specification. In part, this added formality is meant to catch common programming mistakes made by novice users. However, advanced users will also find such features to be useful when building complicated grammars for real programming -languages. It should also be noted that PLY does not provide much in the way -of bells and whistles (e.g., automatic construction of abstract syntax trees, -tree traversal, etc.). Instead, you will find a bare-bones, yet +languages. It should also be noted that PLY does not provide much in +the way of bells and whistles (e.g., automatic construction of +abstract syntax trees, tree traversal, etc.). Nor would I consider it +to be a parsing framework. Instead, you will find a bare-bones, yet fully capable lex/yacc implementation written entirely in Python. <p> The rest of this document assumes that you are somewhat familar with -parsing theory, syntax directed translation, and automatic tools such -as lex and yacc. If you are unfamilar with these topics, you will -probably want to consult an introductory text such as "Compilers: -Principles, Techniques, and Tools", by Aho, Sethi, and Ullman. "Lex -and Yacc" by John Levine may also be handy. +parsing theory, syntax directed translation, and the use of compiler +construction tools such as lex and yacc in other programming +languages. If you are unfamilar with these topics, you will probably +want to consult an introductory text such as "Compilers: Principles, +Techniques, and Tools", by Aho, Sethi, and Ullman. O'Reilly's "Lex +and Yacc" by John Levine may also be handy. In fact, the O'Reilly book can be +used as a reference for PLY as the concepts are virtually identical. + +<H2><a name="ply_nn2"></a>2. PLY Overview</H2> -<h2>PLY Overview</h2> -PLY consists of two separate tools; <tt>lex.py</tt> and -<tt>yacc.py</tt>. <tt>lex.py</tt> is used to break input text into a +PLY consists of two separate modules; <tt>lex.py</tt> and +<tt>yacc.py</tt>, both of which are found in a Python package +called <tt>ply</tt>. The <tt>lex.py</tt> module is used to break input text into a collection of tokens specified by a collection of regular expression rules. <tt>yacc.py</tt> is used to recognize language syntax that has -been specified in the form of a context free grammar. Currently, -<tt>yacc.py</tt> uses LR parsing and generates its parsing tables -using the SLR algorithm. LALR(1) parsing may be supported in a future -release. +been specified in the form of a context free grammar. <tt>yacc.py</tt> uses LR parsing and generates its parsing tables +using either the LALR(1) (the default) or SLR table generation algorithms. <p> The two tools are meant to work together. Specifically, @@ -78,32 +139,77 @@ input stream. <tt>yacc.py</tt> calls this repeatedly to retrieve tokens and invoke grammar rules. The output of <tt>yacc.py</tt> is often an Abstract Syntax Tree (AST). However, this is entirely up to the user. If desired, <tt>yacc.py</tt> can also be used to implement -simple one-pass compilers. +simple one-pass compilers. <p> Like its Unix counterpart, <tt>yacc.py</tt> provides most of the features you expect including extensive error checking, grammar validation, support for empty productions, error tokens, and ambiguity -resolution via precedence rules. The primary difference between -<tt>yacc.py</tt> and <tt>yacc</tt> is the use of SLR parsing instead -of LALR(1). Although this slightly restricts the types of grammars -than can be successfully parsed, it is sufficiently powerful to handle most -kinds of normal programming language constructs. +resolution via precedence rules. In fact, everything that is possible in traditional yacc +should be supported in PLY. <p> -Finally, it is important to note that PLY relies on reflection -(introspection) to build its lexers and parsers. Unlike traditional -lex/yacc which require a special input file that is converted into a -separate source file, the specifications given to PLY <em>are</em> -valid Python programs. This means that there are no extra source -files nor is there a special compiler construction step (e.g., running -yacc to generate Python code for the compiler). +The primary difference between +<tt>yacc.py</tt> and Unix <tt>yacc</tt> is that <tt>yacc.py</tt> +doesn't involve a separate code-generation process. +Instead, PLY relies on reflection (introspection) +to build its lexers and parsers. Unlike traditional lex/yacc which +require a special input file that is converted into a separate source +file, the specifications given to PLY <em>are</em> valid Python +programs. This means that there are no extra source files nor is +there a special compiler construction step (e.g., running yacc to +generate Python code for the compiler). Since the generation of the +parsing tables is relatively expensive, PLY caches the results and +saves them to a file. If no changes are detected in the input source, +the tables are read from the cache. Otherwise, they are regenerated. + +<H2><a name="ply_nn3"></a>3. Lex</H2> + + +<tt>lex.py</tt> is used to tokenize an input string. For example, suppose +you're writing a programming language and a user supplied the following input string: + +<blockquote> +<pre> +x = 3 + 42 * (s - t) +</pre> +</blockquote> -<h2>Lex Example</h2> +A tokenizer splits the string into individual tokens -<tt>lex.py</tt> is used to write tokenizers. To do this, each token -must be defined by a regular expression rule. The following file -implements a very simple lexer for tokenizing simple integer expressions: +<blockquote> +<pre> +'x','=', '3', '+', '42', '*', '(', 's', '-', 't', ')' +</pre> +</blockquote> + +Tokens are usually given names to indicate what they are. For example: + +<blockquote> +<pre> +'ID','EQUALS','NUMBER','PLUS','NUMBER','TIMES', +'LPAREN','ID','MINUS','ID','RPAREN' +</pre> +</blockquote> + +More specifically, the input is broken into pairs of token types and values. For example: + +<blockquote> +<pre> +('ID','x'), ('EQUALS','='), ('NUMBER','3'), +('PLUS','+'), ('NUMBER','42), ('TIMES','*'), +('LPAREN','('), ('ID','s'), ('MINUS','-'), +('ID','t'), ('RPAREN',')' +</pre> +</blockquote> + +The identification of tokens is typically done by writing a series of regular expression +rules. The next section shows how this is done using <tt>lex.py</tt>. + +<H3><a name="ply_nn4"></a>3.1 Lex Example</H3> + + +The following example shows how <tt>lex.py</tt> is used to write a simple tokenizer. <blockquote> <pre> @@ -113,7 +219,7 @@ implements a very simple lexer for tokenizing simple integer expressions: # tokenizer for a simple expression evaluator for # numbers and +,-,*,/ # ------------------------------------------------------------ -import lex +import ply.lex as lex # List of token names. This is always required tokens = ( @@ -147,7 +253,7 @@ def t_NUMBER(t): # Define a rule so we can track line numbers def t_newline(t): r'\n+' - t.lineno += len(t.value) + t.lexer.lineno += len(t.value) # A string containing ignored characters (spaces and tabs) t_ignore = ' \t' @@ -155,11 +261,18 @@ t_ignore = ' \t' # Error handling rule def t_error(t): print "Illegal character '%s'" % t.value[0] - t.skip(1) + t.lexer.skip(1) # Build the lexer lex.lex() +</pre> +</blockquote> +To use the lexer, you first need to feed it some input text using its <tt>input()</tt> method. After that, repeated calls to <tt>token()</tt> produce tokens. The following code shows how this works: + +<blockquote> +<pre> + # Test it out data = ''' 3 + 4 * 10 @@ -177,11 +290,76 @@ while 1: </pre> </blockquote> -In the example, the <tt>tokens</tt> list defines all of the possible -token names that can be produced by the lexer. This list is always required -and is used to perform a variety of validation checks. Following the <tt>tokens</tt> -list, regular expressions are written for each token. Each of these -rules are defined by making declarations with a special prefix <tt>t_</tt> to indicate that it +When executed, the example will produce the following output: + +<blockquote> +<pre> +$ python example.py +LexToken(NUMBER,3,2,1) +LexToken(PLUS,'+',2,3) +LexToken(NUMBER,4,2,5) +LexToken(TIMES,'*',2,7) +LexToken(NUMBER,10,2,10) +LexToken(PLUS,'+',3,14) +LexToken(MINUS,'-',3,16) +LexToken(NUMBER,20,3,18) +LexToken(TIMES,'*',3,20) +LexToken(NUMBER,2,3,21) +</pre> +</blockquote> + +The tokens returned by <tt>lex.token()</tt> are instances +of <tt>LexToken</tt>. This object has +attributes <tt>tok.type</tt>, <tt>tok.value</tt>, +<tt>tok.lineno</tt>, and <tt>tok.lexpos</tt>. The following code shows an example of +accessing these attributes: + +<blockquote> +<pre> +# Tokenize +while 1: + tok = lex.token() + if not tok: break # No more input + print tok.type, tok.value, tok.line, tok.lexpos +</pre> +</blockquote> + +The <tt>tok.type</tt> and <tt>tok.value</tt> attributes contain the +type and value of the token itself. +<tt>tok.line</tt> and <tt>tok.lexpos</tt> contain information about +the location of the token. <tt>tok.lexpos</tt> is the index of the +token relative to the start of the input text. + +<H3><a name="ply_nn5"></a>3.2 The tokens list</H3> + + +All lexers must provide a list <tt>tokens</tt> that defines all of the possible token +names that can be produced by the lexer. This list is always required +and is used to perform a variety of validation checks. The tokens list is also used by the +<tt>yacc.py</tt> module to identify terminals. + +<p> +In the example, the following code specified the token names: + +<blockquote> +<pre> +tokens = ( + 'NUMBER', + 'PLUS', + 'MINUS', + 'TIMES', + 'DIVIDE', + 'LPAREN', + 'RPAREN', +) +</pre> +</blockquote> + +<H3><a name="ply_nn6"></a>3.3 Specification of tokens</H3> + + +Each token is specified by writing a regular expression rule. Each of these rules are +are defined by making declarations with a special prefix <tt>t_</tt> to indicate that it defines a token. For simple tokens, the regular expression can be specified as strings such as this (note: Python raw strings are used since they are the most convenient way to write regular expression strings): @@ -194,7 +372,8 @@ t_PLUS = r'\+' In this case, the name following the <tt>t_</tt> must exactly match one of the names supplied in <tt>tokens</tt>. If some kind of action needs to be performed, -a token rule can be specified as a function. For example: +a token rule can be specified as a function. For example, this rule matches numbers and +converts the string into a Python integer. <blockquote> <pre> @@ -209,21 +388,157 @@ def t_NUMBER(t): </pre> </blockquote> -In this case, the regular expression rule is specified in the function documentation string. +When a function is used, the regular expression rule is specified in the function documentation string. The function always takes a single argument which is an instance of -<tt>LexToken</tt>. This object has attributes of <tt>t.type</tt> which is the token type, -<tt>t.value</tt> which is the lexeme, and <tt>t.lineno</tt> which is the current line number. +<tt>LexToken</tt>. This object has attributes of <tt>t.type</tt> which is the token type (as a string), +<tt>t.value</tt> which is the lexeme (the actual text matched), <tt>t.lineno</tt> which is the current line number, and <tt>t.lexpos</tt> which +is the position of the token relative to the beginning of the input text. By default, <tt>t.type</tt> is set to the name following the <tt>t_</tt> prefix. The action function can modify the contents of the <tt>LexToken</tt> object as appropriate. However, when it is done, the resulting token should be returned. If no value is returned by the action function, the token is simply discarded and the next token read. <p> -The rule <tt>t_newline()</tt> illustrates a regular expression rule -for a discarded token. In this case, a rule is written to match -newlines so that proper line number tracking can be performed. -By returning no value, the function causes the newline character to be -discarded. +Internally, <tt>lex.py</tt> uses the <tt>re</tt> module to do its patten matching. When building the master regular expression, +rules are added in the following order: +<p> +<ol> +<li>All tokens defined by functions are added in the same order as they appear in the lexer file. +<li>Tokens defined by strings are added next by sorting them in order of decreasing regular expression length (longer expressions +are added first). +</ol> +<p> +Without this ordering, it can be difficult to correctly match certain types of tokens. For example, if you +wanted to have separate tokens for "=" and "==", you need to make sure that "==" is checked first. By sorting regular +expressions in order of decreasing length, this problem is solved for rules defined as strings. For functions, +the order can be explicitly controlled since rules appearing first are checked first. + +<p> +To handle reserved words, it is usually easier to just match an identifier and do a special name lookup in a function +like this: + +<blockquote> +<pre> +reserved = { + 'if' : 'IF', + 'then' : 'THEN', + 'else' : 'ELSE', + 'while' : 'WHILE', + ... +} + +def t_ID(t): + r'[a-zA-Z_][a-zA-Z_0-9]*' + t.type = reserved.get(t.value,'ID') # Check for reserved words + return t +</pre> +</blockquote> + +This approach greatly reduces the number of regular expression rules and is likely to make things a little faster. + +<p> +<b>Note:</b> You should avoid writing individual rules for reserved words. For example, if you write rules like this, + +<blockquote> +<pre> +t_FOR = r'for' +t_PRINT = r'print' +</pre> +</blockquote> + +those rules will be triggered for identifiers that include those words as a prefix such as "forget" or "printed". This is probably not +what you want. + +<H3><a name="ply_nn7"></a>3.4 Token values</H3> + + +When tokens are returned by lex, they have a value that is stored in the <tt>value</tt> attribute. Normally, the value is the text +that was matched. However, the value can be assigned to any Python object. For instance, when lexing identifiers, you may +want to return both the identifier name and information from some sort of symbol table. To do this, you might write a rule like this: + +<blockquote> +<pre> +def t_ID(t): + ... + # Look up symbol table information and return a tuple + t.value = (t.value, symbol_lookup(t.value)) + ... + return t +</pre> +</blockquote> + +It is important to note that storing data in other attribute names is <em>not</em> recommended. The <tt>yacc.py</tt> module only exposes the +contents of the <tt>value</tt> attribute. Thus, accessing other attributes may be unnecessarily awkward. + +<H3><a name="ply_nn8"></a>3.5 Discarded tokens</H3> + + +To discard a token, such as a comment, simply define a token rule that returns no value. For example: + +<blockquote> +<pre> +def t_COMMENT(t): + r'\#.*' + pass + # No return value. Token discarded +</pre> +</blockquote> + +Alternatively, you can include the prefix "ignore_" in the token declaration to force a token to be ignored. For example: + +<blockquote> +<pre> +t_ignore_COMMENT = r'\#.*' +</pre> +</blockquote> + +Be advised that if you are ignoring many different kinds of text, you may still want to use functions since these provide more precise +control over the order in which regular expressions are matched (i.e., functions are matched in order of specification whereas strings are +sorted by regular expression length). + +<H3><a name="ply_nn9"></a>3.6 Line numbers and positional information</H3> + + +<p>By default, <tt>lex.py</tt> knows nothing about line numbers. This is because <tt>lex.py</tt> doesn't know anything +about what constitutes a "line" of input (e.g., the newline character or even if the input is textual data). +To update this information, you need to write a special rule. In the example, the <tt>t_newline()</tt> rule shows how to do this. + +<blockquote> +<pre> +# Define a rule so we can track line numbers +def t_newline(t): + r'\n+' + t.lexer.lineno += len(t.value) +</pre> +</blockquote> +Within the rule, the <tt>lineno</tt> attribute of the underlying lexer <tt>t.lexer</tt> is updated. +After the line number is updated, the token is simply discarded since nothing is returned. + +<p> +<tt>lex.py</tt> does not perform and kind of automatic column tracking. However, it does record positional +information related to each token in the <tt>lexpos</tt> attribute. Using this, it is usually possible to compute +column information as a separate step. For instance, just count backwards until you reach a newline. + +<blockquote> +<pre> +# Compute column. +# input is the input text string +# token is a token instance +def find_column(input,token): + i = token.lexpos + while i > 0: + if input[i] == '\n': break + i -= 1 + column = (token.lexpos - i)+1 + return column +</pre> +</blockquote> + +Since column information is often only useful in the context of error handling, calculating the column +position can be performed when needed as opposed to doing it for each token. + +<H3><a name="ply_nn10"></a>3.7 Ignored characters</H3> + <p> The special <tt>t_ignore</tt> rule is reserved by <tt>lex.py</tt> for characters @@ -234,12 +549,55 @@ similar to <tt>t_newline()</tt>, the use of <tt>t_ignore</tt> provides substanti lexing performance because it is handled as a special case and is checked in a much more efficient manner than the normal regular expression rules. +<H3><a name="ply_nn11"></a>3.8 Literal characters</H3> + + +<p> +Literal characters can be specified by defining a variable <tt>literals</tt> in your lexing module. For example: + +<blockquote> +<pre> +literals = [ '+','-','*','/' ] +</pre> +</blockquote> + +or alternatively + +<blockquote> +<pre> +literals = "+-*/" +</pre> +</blockquote> + +A literal character is simply a single character that is returned "as is" when encountered by the lexer. Literals are checked +after all of the defined regular expression rules. Thus, if a rule starts with one of the literal characters, it will always +take precedence. +<p> +When a literal token is returned, both its <tt>type</tt> and <tt>value</tt> attributes are set to the character itself. For example, <tt>'+'</tt>. + +<H3><a name="ply_nn12"></a>3.9 Error handling</H3> + + <p> Finally, the <tt>t_error()</tt> function is used to handle lexing errors that occur when illegal characters are detected. In this case, the <tt>t.value</tt> attribute contains the -rest of the input string that has not been tokenized. In the example, we simply print -the offending character and skip ahead one character by calling <tt>t.skip(1)</tt>. +rest of the input string that has not been tokenized. In the example, the error function +was defined as follows: + +<blockquote> +<pre> +# Error handling rule +def t_error(t): + print "Illegal character '%s'" % t.value[0] + t.lexer.skip(1) +</pre> +</blockquote> + +In this case, we simply print the offending character and skip ahead one character by calling <tt>t.lexer.skip(1)</tt>. + +<H3><a name="ply_nn13"></a>3.10 Building and using the lexer</H3> + <p> To build the lexer, the function <tt>lex.lex()</tt> is used. This function @@ -253,193 +611,733 @@ be used to control the lexer. None if the end of the input text has been reached. </ul> -The code at the bottom of the example shows how the lexer is actually used. When executed, -the following output will be produced: +If desired, the lexer can also be used as an object. The <tt>lex()</tt> returns a <tt>Lexer</tt> object that +can be used for this purpose. For example: <blockquote> <pre> -$ python example.py -LexToken(NUMBER,3,2) -LexToken(PLUS,'+',2) -LexToken(NUMBER,4,2) -LexToken(TIMES,'*',2) -LexToken(NUMBER,10,2) -LexToken(PLUS,'+',3) -LexToken(MINUS,'-',3) -LexToken(NUMBER,20,3) -LexToken(TIMES,'*',3) -LexToken(NUMBER,2,3) +lexer = lex.lex() +lexer.input(sometext) +while 1: + tok = lexer.token() + if not tok: break + print tok </pre> </blockquote> -<h2>Lex Implementation Notes</h2> - -<ul> -<li><tt>lex.py</tt> uses the <tt>re</tt> module to do its patten matching. When building the master regular expression, -rules are added in the following order: <p> -<ol> -<li>All tokens defined by functions are added in the same order as they appear in the lexer file. -<li>Tokens defined by strings are added by sorting them in order of decreasing regular expression length (longer expressions -are added first). -</ol> +This latter technique should be used if you intend to use multiple lexers in your application. Simply define each +lexer in its own module and use the object returned by <tt>lex()</tt> as appropriate. + <p> -Without this ordering, it can be difficult to correctly match certain types of tokens. For example, if you -wanted to have separate tokens for "=" and "==", you need to make sure that "==" is checked first. By sorting regular -expressions in order of decreasing length, this problem is solved for rules defined as strings. For functions, -the order can be explicitly controlled since rules appearing first are checked first. +Note: The global functions <tt>lex.input()</tt> and <tt>lex.token()</tt> are bound to the <tt>input()</tt> +and <tt>token()</tt> methods of the last lexer created by the lex module. -<P> -<li>The lexer requires input to be supplied as a single input string. Since most machines have more than enough memory, this -rarely presents a performance concern. However, it means that the lexer currently can't be used with streaming data -such as open files or sockets. This limitation is primarily a side-effect of using the <tt>re</tt> module. +<H3><a name="ply_nn14"></a>3.11 The @TOKEN decorator</H3> -<p> -<li> -To handle reserved words, it is usually easier to just match an identifier and do a special name lookup in a function -like this: + +In some applications, you may want to define build tokens from as a series of +more complex regular expression rules. For example: <blockquote> <pre> -reserved = { - 'if' : 'IF', - 'then' : 'THEN', - 'else' : 'ELSE', - 'while' : 'WHILE', - ... -} +digit = r'([0-9])' +nondigit = r'([_A-Za-z])' +identifier = r'(' + nondigit + r'(' + digit + r'|' + nondigit + r')*)' def t_ID(t): - r'[a-zA-Z_][a-zA-Z_0-9]*' - t.type = reserved.get(t.value,'ID') # Check for reserved words - return t + # want docstring to be identifier above. ????? + ... </pre> </blockquote> -<p> -<li>The lexer requires tokens to be defined as class instances with <tt>t.type</tt>, <tt>t.value</tt>, and <tt>t.lineno</tt> -attributes. By default, tokens are created as instances of the <tt>LexToken</tt> class defined internally to <tt>lex.py</tt>. -If desired, you can create new kinds of tokens provided that they have the three required attributes. However, -in practice, it is probably safer to stick with the default. - -<p> -<li>The only safe attribute for assigning token properties is <tt>t.value</tt>. In some cases, you may want to attach -a number of different properties to a token (e.g., symbol table entries for identifiers). To do this, replace <tt>t.value</tt> -with a tuple or class instance. For example: +In this case, we want the regular expression rule for <tt>ID</tt> to be one of the variables above. However, there is no +way to directly specify this using a normal documentation string. To solve this problem, you can use the <tt>@TOKEN</tt> +decorator. For example: <blockquote> <pre> +from ply.lex import TOKEN + +@TOKEN(identifier) def t_ID(t): ... - # For identifiers, create a (lexeme, symtab) tuple - t.value = (t.value, symbol_lookup(t.value)) - ... - return t </pre> </blockquote> -Although allowed, do NOT assign additional attributes to the token object. For example, +This will attach <tt>identifier</tt> to the docstring for <tt>t_ID()</tt> allowing <tt>lex.py</tt> to work normally. An alternative +approach this problem is to set the docstring directly like this: + <blockquote> <pre> def t_ID(t): ... - # Bad implementation of above - t.symtab = symbol_lookup(t.value) - ... + +t_ID.__doc__ = identifier +</pre> +</blockquote> + +<b>NOTE:</b> Use of <tt>@TOKEN</tt> requires Python-2.4 or newer. If you're concerned about backwards compatibility with older +versions of Python, use the alternative approach of setting the docstring directly. + +<H3><a name="ply_nn15"></a>3.12 Optimized mode</H3> + + +For improved performance, it may be desirable to use Python's +optimized mode (e.g., running Python with the <tt>-O</tt> +option). However, doing so causes Python to ignore documentation +strings. This presents special problems for <tt>lex.py</tt>. To +handle this case, you can create your lexer using +the <tt>optimize</tt> option as follows: + +<blockquote> +<pre> +lexer = lex.lex(optimize=1) </pre> </blockquote> -The reason you don't want to do this is that the <tt>yacc.py</tt> -module only provides public access to the <tt>t.value</tt> attribute of each token. -Therefore, any other attributes you assign are inaccessible (if you are familiar -with the internals of C lex/yacc, <tt>t.value</tt> is the same as <tt>yylval.tok</tt>). +Next, run Python in its normal operating mode. When you do +this, <tt>lex.py</tt> will write a file called <tt>lextab.py</tt> to +the current directory. This file contains all of the regular +expression rules and tables used during lexing. On subsequent +executions, +<tt>lextab.py</tt> will simply be imported to build the lexer. This +approach substantially improves the startup time of the lexer and it +works in Python's optimized mode. <p> -<li>To track line numbers, the lexer internally maintains a line -number variable. Each token automatically gets the value of the -current line number in the <tt>t.lineno</tt> attribute. To modify the -current line number, simply change the <tt>t.lineno</tt> attribute -in a function rule (as previously shown for -<tt>t_newline()</tt>). Even if the resulting token is discarded, -changes to the line number remain in effect for subsequent tokens. +To change the name of the lexer-generated file, use the <tt>lextab</tt> keyword argument. For example: + +<blockquote> +<pre> +lexer = lex.lex(optimize=1,lextab="footab") +</pre> +</blockquote> + +When running in optimized mode, it is important to note that lex disables most error checking. Thus, this is really only recommended +if you're sure everything is working correctly and you're ready to start releasing production code. + +<H3><a name="ply_nn16"></a>3.13 Debugging</H3> + + +For the purpose of debugging, you can run <tt>lex()</tt> in a debugging mode as follows: + +<blockquote> +<pre> +lexer = lex.lex(debug=1) +</pre> +</blockquote> + +This will result in a large amount of debugging information to be printed including all of the added rules and the master +regular expressions. + +In addition, <tt>lex.py</tt> comes with a simple main function which +will either tokenize input read from standard input or from a file specified +on the command line. To use it, simply put this in your lexer: + +<blockquote> +<pre> +if __name__ == '__main__': + lex.runmain() +</pre> +</blockquote> + +<H3><a name="ply_nn17"></a>3.14 Alternative specification of lexers</H3> + + +As shown in the example, lexers are specified all within one Python module. If you want to +put token rules in a different module from the one in which you invoke <tt>lex()</tt>, use the +<tt>module</tt> keyword argument. <p> -<li>To support multiple scanners in the same application, the <tt>lex.lex()</tt> function -actually returns a special <tt>Lexer</tt> object. This object has two methods -<tt>input()</tt> and <tt>token()</tt> that can be used to supply input and get tokens. For example: +For example, you might have a dedicated module that just contains +the token rules: + +<blockquote> +<pre> +# module: tokrules.py +# This module just contains the lexing rules + +# List of token names. This is always required +tokens = ( + 'NUMBER', + 'PLUS', + 'MINUS', + 'TIMES', + 'DIVIDE', + 'LPAREN', + 'RPAREN', +) + +# Regular expression rules for simple tokens +t_PLUS = r'\+' +t_MINUS = r'-' +t_TIMES = r'\*' +t_DIVIDE = r'/' +t_LPAREN = r'\(' +t_RPAREN = r'\)' + +# A regular expression rule with some action code +def t_NUMBER(t): + r'\d+' + try: + t.value = int(t.value) + except ValueError: + print "Line %d: Number %s is too large!" % (t.lineno,t.value) + t.value = 0 + return t + +# Define a rule so we can track line numbers +def t_newline(t): + r'\n+' + t.lexer.lineno += len(t.value) + +# A string containing ignored characters (spaces and tabs) +t_ignore = ' \t' + +# Error handling rule +def t_error(t): + print "Illegal character '%s'" % t.value[0] + t.lexer.skip(1) +</pre> +</blockquote> + +Now, if you wanted to build a tokenizer from these rules from within a different module, you would do the following (shown for Python interactive mode): <blockquote> <pre> +>>> import tokrules +>>> <b>lexer = lex.lex(module=tokrules)</b> +>>> lexer.input("3 + 4") +>>> lexer.token() +LexToken(NUMBER,3,1,1,0) +>>> lexer.token() +LexToken(PLUS,'+',1,2) +>>> lexer.token() +LexToken(NUMBER,4,1,4) +>>> lexer.token() +None +>>> +</pre> +</blockquote> + +The <tt>object</tt> option can be used to define lexers as a class instead of a module. For example: + +<blockquote> +<pre> +import ply.lex as lex + +class MyLexer: + # List of token names. This is always required + tokens = ( + 'NUMBER', + 'PLUS', + 'MINUS', + 'TIMES', + 'DIVIDE', + 'LPAREN', + 'RPAREN', + ) + + # Regular expression rules for simple tokens + t_PLUS = r'\+' + t_MINUS = r'-' + t_TIMES = r'\*' + t_DIVIDE = r'/' + t_LPAREN = r'\(' + t_RPAREN = r'\)' + + # A regular expression rule with some action code + # Note addition of self parameter since we're in a class + def t_NUMBER(self,t): + r'\d+' + try: + t.value = int(t.value) + except ValueError: + print "Line %d: Number %s is too large!" % (t.lineno,t.value) + t.value = 0 + return t + + # Define a rule so we can track line numbers + def t_newline(self,t): + r'\n+' + t.lexer.lineno += len(t.value) + + # A string containing ignored characters (spaces and tabs) + t_ignore = ' \t' + + # Error handling rule + def t_error(self,t): + print "Illegal character '%s'" % t.value[0] + t.lexer.skip(1) + + <b># Build the lexer + def build(self,**kwargs): + self.lexer = lex.lex(object=self, **kwargs)</b> + + # Test it output + def test(self,data): + self.lexer.input(data) + while 1: + tok = lexer.token() + if not tok: break + print tok + +# Build the lexer and try it out +m = MyLexer() +m.build() # Build the lexer +m.test("3 + 4") # Test it +</pre> +</blockquote> + +For reasons that are subtle, you should <em>NOT</em> invoke <tt>lex.lex()</tt> inside the <tt>__init__()</tt> method of your class. If you +do, it may cause bizarre behavior if someone tries to duplicate a lexer object. Keep reading. + +<H3><a name="ply_nn18"></a>3.15 Maintaining state</H3> + + +In your lexer, you may want to maintain a variety of state information. This might include mode settings, symbol tables, and other details. There are a few +different ways to handle this situation. First, you could just keep some global variables: + +<blockquote> +<pre> +num_count = 0 +def t_NUMBER(t): + r'\d+' + global num_count + num_count += 1 + try: + t.value = int(t.value) + except ValueError: + print "Line %d: Number %s is too large!" % (t.lineno,t.value) + t.value = 0 + return t +</pre> +</blockquote> + +Alternatively, you can store this information inside the Lexer object created by <tt>lex()</tt>. To this, you can use the <tt>lexer</tt> attribute +of tokens passed to the various rules. For example: + +<blockquote> +<pre> +def t_NUMBER(t): + r'\d+' + t.lexer.num_count += 1 # Note use of lexer attribute + try: + t.value = int(t.value) + except ValueError: + print "Line %d: Number %s is too large!" % (t.lineno,t.value) + t.value = 0 + return t + lexer = lex.lex() -lexer.input(sometext) -while 1: - tok = lexer.token() - if not tok: break - print tok +lexer.num_count = 0 # Set the initial count </pre> </blockquote> -The functions <tt>lex.input()</tt> and <tt>lex.token()</tt> are bound to the <tt>input()</tt> -and <tt>token()</tt> methods of the last lexer created by the lex module. +This latter approach has the advantage of storing information inside +the lexer itself---something that may be useful if multiple instances +of the same lexer have been created. However, it may also feel kind +of "hacky" to the purists. Just to put their mind at some ease, all +internal attributes of the lexer (with the exception of <tt>lineno</tt>) have names that are prefixed +by <tt>lex</tt> (e.g., <tt>lexdata</tt>,<tt>lexpos</tt>, etc.). Thus, +it should be perfectly safe to store attributes in the lexer that +don't have names starting with that prefix. + +<p> +A third approach is to define the lexer as a class as shown in the previous example: +<blockquote> +<pre> +class MyLexer: + ... + def t_NUMBER(self,t): + r'\d+' + self.num_count += 1 + try: + t.value = int(t.value) + except ValueError: + print "Line %d: Number %s is too large!" % (t.lineno,t.value) + t.value = 0 + return t + + def build(self, **kwargs): + self.lexer = lex.lex(object=self,**kwargs) + + def __init__(self): + self.num_count = 0 + +# Create a lexer +m = MyLexer() +lexer = lex.lex(object=m) +</pre> +</blockquote> + +The class approach may be the easiest to manage if your application is going to be creating multiple instances of the same lexer and +you need to manage a lot of state. + +<H3><a name="ply_nn19"></a>3.16 Duplicating lexers</H3> + + +<b>NOTE: I am thinking about deprecating this feature. Post comments on <a href="http://groups.google.com/group/ply-hack">ply-hack@googlegroups.com</a> or send me a private email at dave@dabeaz.com.</b> <p> -<li>To reduce compiler startup time and improve performance, the lexer can be built in optimized mode as follows: +If necessary, a lexer object can be quickly duplicated by invoking its <tt>clone()</tt> method. For example: <blockquote> <pre> -lex.lex(optimize=1) +lexer = lex.lex() +... +newlexer = lexer.clone() </pre> </blockquote> -When used, most error checking and validation is disabled. This provides a slight performance -gain while tokenizing and tends to chop a few tenths of a second off startup time. Since it disables -error checking, this mode is not the default and is not recommended during development. However, once -you have your compiler fully working, it is usually safe to disable the error checks. +When a lexer is cloned, the copy is identical to the original lexer, +including any input text. However, once created, different text can be +fed to the clone which can be used independently. This capability may +be useful in situations when you are writing a parser/compiler that +involves recursive or reentrant processing. For instance, if you +needed to scan ahead in the input for some reason, you could create a +clone and use it to look ahead. <p> -<li>You can enable some additional debugging by building the lexer like this: +The advantage of using <tt>clone()</tt> instead of reinvoking <tt>lex()</tt> is +that it is significantly faster. Namely, it is not necessary to re-examine all of the +token rules, build a regular expression, and construct internal tables. All of this +information can simply be reused in the new lexer. + +<p> +Special considerations need to be made when cloning a lexer that is defined as a class. Previous sections +showed an example of a class <tt>MyLexer</tt>. If you have the following code: <blockquote> <pre> -lex.lex(debug=1) +m = MyLexer() +a = lex.lex(object=m) # Create a lexer + +b = a.clone() # Clone the lexer </pre> </blockquote> +Then both <tt>a</tt> and <tt>b</tt> are going to be bound to the same +object <tt>m</tt>. If the object <tt>m</tt> contains internal state +related to lexing, this sharing may lead to quite a bit of confusion. To fix this, +the <tt>clone()</tt> method accepts an optional argument that can be used to supply a new object. This +can be used to clone the lexer and bind it to a new instance. For example: + +<blockquote> +<pre> +m = MyLexer() # Create a lexer +a = lex.lex(object=m) + +# Create a clone +n = MyLexer() # New instance of MyLexer +b = a.clone(n) # New lexer bound to n +</pre> +</blockquote> + +It may make sense to encapsulate all of this inside a method: + +<blockquote> +<pre> +class MyLexer: + ... + def clone(self): + c = MyLexer() # Create a new instance of myself + # Copy attributes from self to c as appropriate + ... + # Clone the lexer + c.lexer = self.lexer.clone(c) + return c +</pre> +</blockquote> + +The fact that a new instance of <tt>MyLexer</tt> may be created while cloning a lexer is the reason why you should never +invoke <tt>lex.lex()</tt> inside <tt>__init__()</tt>. If you do, the lexer will be rebuilt from scratch and you lose +all of the performance benefits of using <tt>clone()</tt> in the first place. + +<H3><a name="ply_nn20"></a>3.17 Internal lexer state</H3> + + +A Lexer object <tt>lexer</tt> has a number of internal attributes that may be useful in certain +situations. + <p> -<li>To help you debug your lexer, <tt>lex.py</tt> comes with a simple main program which will either -tokenize input read from standard input or from a file. To use it, simply put this in your lexer: +<tt>lexer.lexpos</tt> +<blockquote> +This attribute is an integer that contains the current position within the input text. If you modify +the value, it will change the result of the next call to <tt>token()</tt>. Within token rule functions, this points +to the first character <em>after</em> the matched text. If the value is modified within a rule, the next returned token will be +matched at the new position. +</blockquote> + +<p> +<tt>lexer.lineno</tt> +<blockquote> +The current value of the line number attribute stored in the lexer. This can be modified as needed to +change the line number. +</blockquote> + +<p> +<tt>lexer.lexdata</tt> +<blockquote> +The current input text stored in the lexer. This is the string passed with the <tt>input()</tt> method. It +would probably be a bad idea to modify this unless you really know what you're doing. +</blockquote> + +<P> +<tt>lexer.lexmatch</tt> +<blockquote> +This is the raw <tt>Match</tt> object returned by the Python <tt>re.match()</tt> function (used internally by PLY) for the +current token. If you have written a regular expression that contains named groups, you can use this to retrieve those values. +</blockquote> + +<H3><a name="ply_nn21"></a>3.18 Conditional lexing and start conditions</H3> + + +In advanced parsing applications, it may be useful to have different +lexing states. For instance, you may want the occurrence of a certain +token or syntactic construct to trigger a different kind of lexing. +PLY supports a feature that allows the underlying lexer to be put into +a series of different states. Each state can have its own tokens, +lexing rules, and so forth. The implementation is based largely on +the "start condition" feature of GNU flex. Details of this can be found +at <a +href="http://www.gnu.org/software/flex/manual/html_chapter/flex_11.html">http://www.gnu.org/software/flex/manual/html_chapter/flex_11.html.</a>. + +<p> +To define a new lexing state, it must first be declared. This is done by including a "states" declaration in your +lex file. For example: <blockquote> <pre> -if __name__ == '__main__': - lex.runmain() +states = ( + ('foo','exclusive'), + ('bar','inclusive'), +) </pre> </blockquote> -Then, run you lexer as a main program such as <tt>python mylex.py</tt> +This declaration declares two states, <tt>'foo'</tt> +and <tt>'bar'</tt>. States may be of two types; <tt>'exclusive'</tt> +and <tt>'inclusive'</tt>. An exclusive state completely overrides the +default behavior of the lexer. That is, lex will only return tokens +and apply rules defined specifically for that state. An inclusive +state adds additional tokens and rules to the default set of rules. +Thus, lex will return both the tokens defined by default in addition +to those defined for the inclusive state. + +<p> +Once a state has been declared, tokens and rules are declared by including the +state name in token/rule declaration. For example: + +<blockquote> +<pre> +t_foo_NUMBER = r'\d+' # Token 'NUMBER' in state 'foo' +t_bar_ID = r'[a-zA-Z_][a-zA-Z0-9_]*' # Token 'ID' in state 'bar' + +def t_foo_newline(t): + r'\n' + t.lexer.lineno += 1 +</pre> +</blockquote> + +A token can be declared in multiple states by including multiple state names in the declaration. For example: + +<blockquote> +<pre> +t_foo_bar_NUMBER = r'\d+' # Defines token 'NUMBER' in both state 'foo' and 'bar' +</pre> +</blockquote> + +Alternative, a token can be declared in all states using the 'ANY' in the name. + +<blockquote> +<pre> +t_ANY_NUMBER = r'\d+' # Defines a token 'NUMBER' in all states +</pre> +</blockquote> + +If no state name is supplied, as is normally the case, the token is associated with a special state <tt>'INITIAL'</tt>. For example, +these two declarations are identical: + +<blockquote> +<pre> +t_NUMBER = r'\d+' +t_INITIAL_NUMBER = r'\d+' +</pre> +</blockquote> + +<p> +States are also associated with the special <tt>t_ignore</tt> and <tt>t_error()</tt> declarations. For example, if a state treats +these differently, you can declare: + +<blockquote> +<pre> +t_foo_ignore = " \t\n" # Ignored characters for state 'foo' + +def t_bar_error(t): # Special error handler for state 'bar' + pass +</pre> +</blockquote> + +By default, lexing operates in the <tt>'INITIAL'</tt> state. This state includes all of the normally defined tokens. +For users who aren't using different states, this fact is completely transparent. If, during lexing or parsing, you want to change +the lexing state, use the <tt>begin()</tt> method. For example: + +<blockquote> +<pre> +def t_begin_foo(t): + r'start_foo' + t.lexer.begin('foo') # Starts 'foo' state +</pre> +</blockquote> + +To get out of a state, you use <tt>begin()</tt> to switch back to the initial state. For example: + +<blockquote> +<pre> +def t_foo_end(t): + r'end_foo' + t.lexer.begin('INITIAL') # Back to the initial state +</pre> +</blockquote> + +The management of states can also be done with a stack. For example: + +<blockquote> +<pre> +def t_begin_foo(t): + r'start_foo' + t.lexer.push_state('foo') # Starts 'foo' state + +def t_foo_end(t): + r'end_foo' + t.lexer.pop_state() # Back to the previous state +</pre> +</blockquote> + +<p> +The use of a stack would be useful in situations where there are many ways of entering a new lexing state and you merely want to go back +to the previous state afterwards. + +<P> +An example might help clarify. Suppose you were writing a parser and you wanted to grab sections of arbitrary C code enclosed by +curly braces. That is, whenever you encounter a starting brace '{', you want to read all of the enclosed code up to the ending brace '}' +and return it as a string. Doing this with a normal regular expression rule is nearly (if not actually) impossible. This is because braces can +be nested and can be included in comments and strings. Thus, simply matching up to the first matching '}' character isn't good enough. Here is how +you might use lexer states to do this: + +<blockquote> +<pre> +# Declare the state +states = ( + ('ccode','exclusive'), +) + +# Match the first {. Enter ccode state. +def t_ccode(t): + r'\{' + t.lexer.code_start = t.lexer.lexpos # Record the starting position + t.lexer.level = 1 # Initial brace level + t.lexer.begin('ccode') # Enter 'ccode' state + +# Rules for the ccode state +def t_ccode_lbrace(t): + r'\{' + t.lexer.level +=1 + +def t_ccode_rbrace(t): + r'\}' + t.lexer.level -=1 + + # If closing brace, return the code fragment + if t.lexer.level == 0: + t.value = t.lexer.lexdata[t.lexer.code_start:t.lexer.lexpos+1] + t.type = "CCODE" + t.lexer.lineno += t.value.count('\n') + t.lexer.begin('INITIAL') + return t + +# C or C++ comment (ignore) +def t_ccode_comment(t): + r'(/\*(.|\n)*?*/)|(//.*)' + pass + +# C string +def t_ccode_string(t): + r'\"([^\\\n]|(\\.))*?\"' + +# C character literal +def t_ccode_char(t): + r'\'([^\\\n]|(\\.))*?\'' + +# Any sequence of non-whitespace characters (not braces, strings) +def t_ccode_nonspace(t): + r'[^\s\{\}\'\"]+' + +# Ignored characters (whitespace) +t_ccode_ignore = " \t\n" + +# For bad characters, we just skip over it +def t_ccode_error(t): + t.lexer.skip(1) +</pre> +</blockquote> + +In this example, the occurrence of the first '{' causes the lexer to record the starting position and enter a new state <tt>'ccode'</tt>. A collection of rules then match +various parts of the input that follow (comments, strings, etc.). All of these rules merely discard the token (by not returning a value). +However, if the closing right brace is encountered, the rule <tt>t_ccode_rbrace</tt> collects all of the code (using the earlier recorded starting +position), stores it, and returns a token 'CCODE' containing all of that text. When returning the token, the lexing state is restored back to its +initial state. + +<H3><a name="ply_nn21"></a>3.19 Miscellaneous Issues</H3> + + +<P> +<li>The lexer requires input to be supplied as a single input string. Since most machines have more than enough memory, this +rarely presents a performance concern. However, it means that the lexer currently can't be used with streaming data +such as open files or sockets. This limitation is primarily a side-effect of using the <tt>re</tt> module. + +<p> +<li>The lexer should work properly with both Unicode strings given as token and pattern matching rules as +well as for input text. + +<p> +<li>If you need to supply optional flags to the re.compile() function, use the reflags option to lex. For example: + +<blockquote> +<pre> +lex.lex(reflags=re.UNICODE) +</pre> +</blockquote> <p> <li>Since the lexer is written entirely in Python, its performance is largely determined by that of the Python <tt>re</tt> module. Although the lexer has been written to be as efficient as possible, it's not -blazingly fast when used on very large input files. Sorry. If +blazingly fast when used on very large input files. If performance is concern, you might consider upgrading to the most recent version of Python, creating a hand-written lexer, or offloading -the lexer into a C extension module. In defense of <tt>lex.py</tt>, -it's performance is not <em>that</em> bad when used on reasonably -sized input files. For instance, lexing a 4700 line C program with -32000 input tokens takes about 20 seconds on a 200 Mhz PC. Obviously, -it will run much faster on a more speedy machine. +the lexer into a C extension module. +<p> +If you are going to create a hand-written lexer and you plan to use it with <tt>yacc.py</tt>, +it only needs to conform to the following requirements: + +<ul> +<li>It must provide a <tt>token()</tt> method that returns the next token or <tt>None</tt> if no more +tokens are available. +<li>The <tt>token()</tt> method must return an object <tt>tok</tt> that has <tt>type</tt> and <tt>value</tt> attributes. </ul> -<h2>Parsing basics</h2> +<H2><a name="ply_nn22"></a>4. Parsing basics</H2> + <tt>yacc.py</tt> is used to parse language syntax. Before showing an example, there are a few important bits of background that must be -mentioned. First, <tt>syntax</tt> is usually specified in terms of a -context free grammar (CFG). For example, if you wanted to parse +mentioned. First, <em>syntax</em> is usually specified in terms of a BNF grammar. +For example, if you wanted to parse simple arithmetic expressions, you might first write an unambiguous grammar specification like this: @@ -458,7 +1356,11 @@ factor : NUMBER </pre> </blockquote> -Next, the semantic behavior of a language is often specified using a +In the grammar, symbols such as <tt>NUMBER</tt>, <tt>+</tt>, <tt>-</tt>, <tt>*</tt>, and <tt>/</tt> are known +as <em>terminals</em> and correspond to raw input tokens. Identifiers such as <tt>term</tt> and <tt>factor</tt> refer to more +complex rules, typically comprised of a collection of tokens. These identifiers are known as <em>non-terminals</em>. +<P> +The semantic behavior of a language is often specified using a technique known as syntax directed translation. In syntax directed translation, attributes are attached to each symbol in a given grammar rule along with an action. Whenever a particular grammar rule is @@ -483,7 +1385,12 @@ factor : NUMBER factor.val = int(NUMBER.lexval) </pre> </blockquote> -Finally, Yacc uses a parsing technique known as LR-parsing or shift-reduce parsing. LR parsing is a +A good way to think about syntax directed translation is to simply think of each symbol in the grammar as some +kind of object. The semantics of the language are then expressed as a collection of methods/operations on these +objects. + +<p> +Yacc uses a parsing technique known as LR-parsing or shift-reduce parsing. LR parsing is a bottom up technique that tries to recognize the right-hand-side of various grammar rules. Whenever a valid right-hand-side is found in the input, the appropriate action code is triggered and the grammar symbols are replaced by the grammar symbol on the left-hand-side. @@ -534,12 +1441,18 @@ appropriate action is triggered (if defined). If the input token can't be shift any grammar rules, a syntax error has occurred and the parser must take some kind of recovery step (or bail out). <p> -It is important to note that the underlying implementation is actually built around a large finite-state machine -and some tables. The construction of these tables is quite complicated and beyond the scope of this discussion. +It is important to note that the underlying implementation is built around a large finite-state machine that is encoded +in a collection of tables. The construction of these tables is quite complicated and beyond the scope of this discussion. However, subtle details of this process explain why, in the example above, the parser chooses to shift a token onto the stack in step 9 rather than reducing the rule <tt>expr : expr + term</tt>. -<h2>Yacc example</h2> +<H2><a name="ply_nn23"></a>5. Yacc reference</H2> + + +This section describes how to use write parsers in PLY. + +<H3><a name="ply_nn24"></a>5.1 An example</H3> + Suppose you wanted to make a grammar for simple arithmetic expressions as previously described. Here is how you would do it with <tt>yacc.py</tt>: @@ -548,50 +1461,53 @@ how you would do it with <tt>yacc.py</tt>: <pre> # Yacc example -import yacc +import ply.yacc as yacc # Get the token map from the lexer. This is required. from calclex import tokens -def p_expression_plus(t): +def p_expression_plus(p): 'expression : expression PLUS term' - t[0] = t[1] + t[3] + p[0] = p[1] + p[3] -def p_expression_minus(t): +def p_expression_minus(p): 'expression : expression MINUS term' - t[0] = t[1] - t[3] + p[0] = p[1] - p[3] -def p_expression_term(t): +def p_expression_term(p): 'expression : term' - t[0] = t[1] + p[0] = p[1] -def p_term_times(t): +def p_term_times(p): 'term : term TIMES factor' - t[0] = t[1] * t[3] + p[0] = p[1] * p[3] -def p_term_div(t): +def p_term_div(p): 'term : term DIVIDE factor' - t[0] = t[1] / t[3] + p[0] = p[1] / p[3] -def p_term_factor(t): +def p_term_factor(p): 'term : factor' - t[0] = t[1] + p[0] = p[1] -def p_factor_num(t): +def p_factor_num(p): 'factor : NUMBER' - t[0] = t[1] + p[0] = p[1] -def p_factor_expr(t): +def p_factor_expr(p): 'factor : LPAREN expression RPAREN' - t[0] = t[2] + p[0] = p[2] # Error rule for syntax errors -def p_error(t): +def p_error(p): print "Syntax error in input!" # Build the parser yacc.yacc() +# Use this if you want to build the parser using SLR instead of LALR +# yacc.yacc(method="SLR") + while 1: try: s = raw_input('calc > ') @@ -604,39 +1520,45 @@ while 1: </blockquote> In this example, each grammar rule is defined by a Python function where the docstring to that function contains the -appropriate context-free grammar specification (an idea borrowed from John Aycock's SPARK toolkit). Each function accepts a single -argument <tt>t</tt> that is a sequence containing the values of each grammar symbol in the corresponding rule. The values of -<tt>t[i]</tt> are mapped to grammar symbols as shown here: +appropriate context-free grammar specification. Each function accepts a single +argument <tt>p</tt> that is a sequence containing the values of each grammar symbol in the corresponding rule. The values of +<tt>p[i]</tt> are mapped to grammar symbols as shown here: <blockquote> <pre> -def p_expression_plus(t): +def p_expression_plus(p): 'expression : expression PLUS term' # ^ ^ ^ ^ - # t[0] t[1] t[2] t[3] + # p[0] p[1] p[2] p[3] - t[0] = t[1] + t[3] + p[0] = p[1] + p[3] </pre> </blockquote> -For tokens, the "value" in the corresponding <tt>t[i]</tt> is the -<em>same</em> as the value of the <tt>t.value</tt> attribute assigned +For tokens, the "value" of the corresponding <tt>p[i]</tt> is the +<em>same</em> as the <tt>p.value</tt> attribute assigned in the lexer module. For non-terminals, the value is determined by -whatever is placed in <tt>t[0]</tt> when rules are reduced. This +whatever is placed in <tt>p[0]</tt> when rules are reduced. This value can be anything at all. However, it probably most common for the value to be a simple Python type, a tuple, or an instance. In this example, we are relying on the fact that the <tt>NUMBER</tt> token stores an integer value in its value field. All of the other rules simply perform various types of integer operations and store the result. +<P> +Note: The use of negative indices have a special meaning in yacc---specially <tt>p[-1]</tt> does +not have the same value as <tt>p[3]</tt> in this example. Please see the section on "Embedded Actions" for further +details. + <p> The first rule defined in the yacc specification determines the starting grammar symbol (in this case, a rule for <tt>expression</tt> appears first). Whenever the starting rule is reduced by the parser and no more input is available, parsing stops and the final value is returned (this value will be whatever the top-most rule -placed in <tt>t[0]</tt>). +placed in <tt>p[0]</tt>). Note: an alternative starting symbol can be specified using the <tt>start</tt> keyword argument to +<tt>yacc()</tt>. -<p>The <tt>p_error(t)</tt> rule is defined to catch syntax errors. See the error handling section +<p>The <tt>p_error(p)</tt> rule is defined to catch syntax errors. See the error handling section below for more detail. <p> @@ -648,7 +1570,7 @@ such as this: <blockquote> <pre> $ python calcparse.py -yacc: Generating SLR parsing table... +yacc: Generating LALR parsing table... calc > </pre> </blockquote> @@ -660,7 +1582,7 @@ debugging file called <tt>parser.out</tt> is created. On subsequent executions, <tt>yacc</tt> will reload the table from <tt>parsetab.py</tt> unless it has detected a change in the underlying grammar (in which case the tables and <tt>parsetab.py</tt> file are -regenerated). +regenerated). Note: The names of parser output files can be changed if necessary. See the notes that follow later. <p> If any errors are detected in your grammar specification, <tt>yacc.py</tt> will produce @@ -677,20 +1599,21 @@ diagnostic messages and possibly raise an exception. Some of the errors that ca The next few sections now discuss a few finer points of grammar construction. -<h2>Combining Grammar Rule Functions</h2> +<H3><a name="ply_nn25"></a>5.2 Combining Grammar Rule Functions</H3> + When grammar rules are similar, they can be combined into a single function. For example, consider the two rules in our earlier example: <blockquote> <pre> -def p_expression_plus(t): +def p_expression_plus(p): 'expression : expression PLUS term' - t[0] = t[1] + t[3] + p[0] = p[1] + p[3] def p_expression_minus(t): 'expression : expression MINUS term' - t[0] = t[1] - t[3] + p[0] = p[1] - p[3] </pre> </blockquote> @@ -698,13 +1621,13 @@ Instead of writing two functions, you might write a single function like this: <blockquote> <pre> -def p_expression(t): +def p_expression(p): '''expression : expression PLUS term | expression MINUS term''' - if t[2] == '+': - t[0] = t[1] + t[3] - elif t[2] == '-': - t[0] = t[1] - t[3] + if p[2] == '+': + p[0] = p[1] + p[3] + elif p[2] == '-': + p[0] = p[1] - p[3] </pre> </blockquote> @@ -713,33 +1636,82 @@ have also been legal (although possibly confusing) to write this: <blockquote> <pre> -def p_binary_operators(t): +def p_binary_operators(p): '''expression : expression PLUS term | expression MINUS term term : term TIMES factor | term DIVIDE factor''' - if t[2] == '+': - t[0] = t[1] + t[3] - elif t[2] == '-': - t[0] = t[1] - t[3] - elif t[2] == '*': - t[0] = t[1] * t[3] - elif t[2] == '/': - t[0] = t[1] / t[3] + if p[2] == '+': + p[0] = p[1] + p[3] + elif p[2] == '-': + p[0] = p[1] - p[3] + elif p[2] == '*': + p[0] = p[1] * p[3] + elif p[2] == '/': + p[0] = p[1] / p[3] </pre> </blockquote> When combining grammar rules into a single function, it is usually a good idea for all of the rules to have a similar structure (e.g., the same number of terms). Otherwise, the corresponding action code may be more -complicated than necessary. +complicated than necessary. However, it is possible to handle simple cases using len(). For example: + +<blockquote> +<pre> +def p_expressions(p): + '''expression : expression MINUS expression + | MINUS expression''' + if (len(p) == 4): + p[0] = p[1] - p[3] + elif (len(p) == 3): + p[0] = -p[2] +</pre> +</blockquote> + +<H3><a name="ply_nn26"></a>5.3 Character Literals</H3> + + +If desired, a grammar may contain tokens defined as single character literals. For example: + +<blockquote> +<pre> +def p_binary_operators(p): + '''expression : expression '+' term + | expression '-' term + term : term '*' factor + | term '/' factor''' + if p[2] == '+': + p[0] = p[1] + p[3] + elif p[2] == '-': + p[0] = p[1] - p[3] + elif p[2] == '*': + p[0] = p[1] * p[3] + elif p[2] == '/': + p[0] = p[1] / p[3] +</pre> +</blockquote> + +A character literal must be enclosed in quotes such as <tt>'+'</tt>. In addition, if literals are used, they must be declared in the +corresponding <tt>lex</tt> file through the use of a special <tt>literals</tt> declaration. + +<blockquote> +<pre> +# Literals. Should be placed in module given to lex() +literals = ['+','-','*','/' ] +</pre> +</blockquote> + +<b>Character literals are limited to a single character</b>. Thus, it is not legal to specify literals such as <tt>'<='</tt> or <tt>'=='</tt>. For this, use +the normal lexing rules (e.g., define a rule such as <tt>t_EQ = r'=='</tt>). + +<H3><a name="ply_nn26"></a>5.4 Empty Productions</H3> -<h2>Empty Productions</h2> <tt>yacc.py</tt> can handle empty productions by defining a rule like this: <blockquote> <pre> -def p_empty(t): +def p_empty(p): 'empty :' pass </pre> @@ -749,14 +1721,47 @@ Now to use the empty production, simply use 'empty' as a symbol. For example: <blockquote> <pre> -def p_optitem(t): +def p_optitem(p): 'optitem : item' ' | empty' ... </pre> </blockquote> -<h2>Dealing With Ambiguous Grammars</h2> +Note: You can write empty rules anywhere by simply specifying an empty right hand side. However, I personally find that +writing an "empty" rule and using "empty" to denote an empty production is easier to read. + +<H3><a name="ply_nn28"></a>5.5 Changing the starting symbol</H3> + + +Normally, the first rule found in a yacc specification defines the starting grammar rule (top level rule). To change this, simply +supply a <tt>start</tt> specifier in your file. For example: + +<blockquote> +<pre> +start = 'foo' + +def p_bar(p): + 'bar : A B' + +# This is the starting rule due to the start specifier above +def p_foo(p): + 'foo : bar X' +... +</pre> +</blockquote> + +The use of a <tt>start</tt> specifier may be useful during debugging since you can use it to have yacc build a subset of +a larger grammar. For this purpose, it is also possible to specify a starting symbol as an argument to <tt>yacc()</tt>. For example: + +<blockquote> +<pre> +yacc.yacc(start='foo') +</pre> +</blockquote> + +<H3><a name="ply_nn27"></a>5.6 Dealing With Ambiguous Grammars</H3> + The expression grammar given in the earlier example has been written in a special format to eliminate ambiguity. However, in many situations, it is extremely difficult or awkward to write grammars in this format. A @@ -775,7 +1780,7 @@ expression : expression PLUS expression Unfortunately, this grammar specification is ambiguous. For example, if you are parsing the string "3 * 4 + 5", there is no way to tell how the operators are supposed to be grouped. -For example, does this expression mean "(3 * 4) + 5" or is it "3 * (4+5)"? +For example, does the expression mean "(3 * 4) + 5" or is it "3 * (4+5)"? <p> When an ambiguous grammar is given to <tt>yacc.py</tt> it will print messages about "shift/reduce conflicts" @@ -796,7 +1801,7 @@ Step Symbol Stack Input Tokens Action </pre> </blockquote> -In this case, when the parser reaches step 6, it has two options. One is the reduce the +In this case, when the parser reaches step 6, it has two options. One is to reduce the rule <tt>expr : expr * expr</tt> on the stack. The other option is to shift the token <tt>+</tt> on the stack. Both options are perfectly legal from the rules of the context-free-grammar. @@ -806,7 +1811,7 @@ By default, all shift/reduce conflicts are resolved in favor of shifting. There example, the parser will always shift the <tt>+</tt> instead of reducing. Although this strategy works in many cases (including the ambiguous if-then-else), it is not enough for arithmetic expressions. In fact, in the above example, the decision to shift <tt>+</tt> is completely wrong---we should have -reduced <tt>expr * expr</tt> since multiplication has higher precedence than addition. +reduced <tt>expr * expr</tt> since multiplication has higher mathematical precedence than addition. <p>To resolve ambiguity, especially in expression grammars, <tt>yacc.py</tt> allows individual tokens to be assigned a precedence level and associativity. This is done by adding a variable @@ -823,25 +1828,37 @@ precedence = ( This declaration specifies that <tt>PLUS</tt>/<tt>MINUS</tt> have the same precedence level and are left-associative and that -<tt>TIMES</tt>/<tt>DIVIDE</tt> have the same precedence and are left-associative. -Furthermore, the declaration specifies that <tt>TIMES</tt>/<tt>DIVIDE</tt> have higher +<tt>TIMES</tt>/<tt>DIVIDE</tt> have the same precedence and are left-associative. +Within the <tt>precedence</tt> declaration, tokens are ordered from lowest to highest precedence. Thus, +this declaration specifies that <tt>TIMES</tt>/<tt>DIVIDE</tt> have higher precedence than <tt>PLUS</tt>/<tt>MINUS</tt> (since they appear later in the precedence specification). <p> -The precedence specification is used to attach a numerical precedence value and associativity direction -to each grammar rule. This is always determined by the precedence of the right-most terminal symbol. Therefore, -if PLUS/MINUS had a precedence of 1 and TIMES/DIVIDE had a precedence of 2, the grammar rules -would have precedence values as follows: +The precedence specification works by associating a numerical precedence level value and associativity direction to +the listed tokens. For example, in the above example you get: <blockquote> <pre> -expression : expression PLUS expression # prec = 1, left - | expression MINUS expression # prec = 1, left - | expression TIMES expression # prec = 2, left - | expression DIVIDE expression # prec = 2, left - | LPAREN expression RPAREN # prec = unknown - | NUMBER # prec = unknown +PLUS : level = 1, assoc = 'left' +MINUS : level = 1, assoc = 'left' +TIMES : level = 2, assoc = 'left' +DIVIDE : level = 2, assoc = 'left' +</pre> +</blockquote> + +These values are then used to attach a numerical precedence value and associativity direction +to each grammar rule. <em>This is always determined by looking at the precedence of the right-most terminal symbol.</em> +For example: + +<blockquote> +<pre> +expression : expression PLUS expression # level = 1, left + | expression MINUS expression # level = 1, left + | expression TIMES expression # level = 2, left + | expression DIVIDE expression # level = 2, left + | LPAREN expression RPAREN # level = None (not specified) + | NUMBER # level = None (not specified) </pre> </blockquote> @@ -858,6 +1875,11 @@ rule is reduced for left associativity, whereas the token is shifted for right a favor of shifting (the default). </ol> +For example, if "expression PLUS expression" has been parsed and the next token +is "TIMES", the action is going to be a shift because "TIMES" has a higher precedence level than "PLUS". On the other +hand, if "expression TIMES expression" has been parsed and the next token is "PLUS", the action +is going to be reduce because "PLUS" has a lower precedence than "TIMES." + <p> When shift/reduce conflicts are resolved using the first three techniques (with the help of precedence rules), <tt>yacc.py</tt> will report no errors or conflicts in the grammar. @@ -883,9 +1905,9 @@ Now, in the grammar file, we can write our unary minus rule like this: <blockquote> <pre> -def p_expr_uminus(t): +def p_expr_uminus(p): 'expression : MINUS expression %prec UMINUS' - t[0] = -t[2] + p[0] = -p[2] </pre> </blockquote> @@ -893,9 +1915,15 @@ In this case, <tt>%prec UMINUS</tt> overrides the default rule precedence--setti of UMINUS in the precedence specifier. <p> +At first, the use of UMINUS in this example may appear very confusing. +UMINUS is not an input token or a grammer rule. Instead, you should +think of it as the name of a special marker in the precedence table. When you use the <tt>%prec</tt> qualifier, you're simply +telling yacc that you want the precedence of the expression to be the same as for this special marker instead of the usual precedence. + +<p> It is also possible to specify non-associativity in the <tt>precedence</tt> table. This would be used when you <em>don't</em> want operations to chain together. For example, suppose -you wanted to support a comparison operators like <tt><</tt> and <tt>></tt> but you didn't want to allow +you wanted to support comparison operators like <tt><</tt> and <tt>></tt> but you didn't want to allow combinations like <tt>a < b < c</tt>. To do this, simply specify a rule like this: <blockquote> @@ -910,6 +1938,10 @@ precedence = ( </blockquote> <p> +If you do this, the occurrence of input text such as <tt> a < b < c</tt> will result in a syntax error. However, simple +expressions such as <tt>a < b</tt> will still be fine. + +<p> Reduce/reduce conflicts are caused when there are multiple grammar rules that can be applied to a given set of symbols. This kind of conflict is almost always bad and is always resolved by picking the @@ -941,11 +1973,17 @@ expression : NUMBER </blockquote> For example, if you wrote "a = 5", the parser can't figure out if this -is supposed to reduced as <tt>assignment : ID EQUALS NUMBER</tt> or +is supposed to be reduced as <tt>assignment : ID EQUALS NUMBER</tt> or whether it's supposed to reduce the 5 as an expression and then reduce the rule <tt>assignment : ID EQUALS expression</tt>. -<h2>The parser.out file</h2> +<p> +It should be noted that reduce/reduce conflicts are notoriously difficult to spot +simply looking at the input grammer. To locate these, it is usually easier to look at the +<tt>parser.out</tt> debugging file with an appropriately high level of caffeination. + +<H3><a name="ply_nn28"></a>5.7 The parser.out file</H3> + Tracking down shift/reduce and reduce/reduce conflicts is one of the finer pleasures of using an LR parsing algorithm. To assist in debugging, <tt>yacc.py</tt> creates a debugging file called @@ -981,7 +2019,7 @@ Nonterminals, with rules where they appear expression : 1 1 2 2 3 3 4 4 6 0 -Parsing method: SLR +Parsing method: LALR state 0 @@ -1220,7 +2258,8 @@ By looking at these rules (and with a little practice), you can usually track do of most parsing conflicts. It should also be stressed that not all shift-reduce conflicts are bad. However, the only way to be sure that they are resolved correctly is to look at <tt>parser.out</tt>. -<h2>Syntax Error Handling</h2> +<H3><a name="ply_nn29"></a>5.8 Syntax Error Handling</H3> + When a syntax error occurs during parsing, the error is immediately detected (i.e., the parser does not read any more tokens beyond the @@ -1259,14 +2298,15 @@ shifted onto the parsing stack. parser can successfully shift a new symbol or reduce a rule involving <tt>error</tt>. </ol> -<h4>Recovery and resynchronization with error rules</h4> +<H4><a name="ply_nn30"></a>5.8.1 Recovery and resynchronization with error rules</H4> + The most well-behaved approach for handling syntax errors is to write grammar rules that include the <tt>error</tt> token. For example, suppose your language had a grammar rule for a print statement like this: <blockquote> <pre> -def p_statement_print(t): +def p_statement_print(p): 'statement : PRINT expr SEMI' ... </pre> @@ -1276,7 +2316,7 @@ To account for the possibility of a bad expression, you might write an additiona <blockquote> <pre> -def p_statement_print_error(t): +def p_statement_print_error(p): 'statement : PRINT error SEMI' print "Syntax error in print statement. Bad expression" @@ -1300,7 +2340,7 @@ on the right in an error rule. For example: <blockquote> <pre> -def p_statement_print_error(t): +def p_statement_print_error(p): 'statement : PRINT error' print "Syntax error in print statement. Bad expression" </pre> @@ -1310,7 +2350,8 @@ This is because the first bad token encountered will cause the rule to be reduced--which may make it difficult to recover if more bad tokens immediately follow. -<h4>Panic mode recovery</h4> +<H4><a name="ply_nn31"></a>5.8.2 Panic mode recovery</H4> + An alternative error recovery scheme is to enter a panic mode recovery in which tokens are discarded to a point where the parser might be able to recover in some sensible manner. @@ -1322,7 +2363,7 @@ parser in its initial state. <blockquote> <pre> -def p_error(t): +def p_error(p): print "Whoa. You are seriously hosed." # Read ahead looking for a closing '}' while 1: @@ -1337,8 +2378,8 @@ This function simply discards the bad token and tells the parser that the error <blockquote> <pre> -def p_error(t): - print "Syntax error at token", t.type +def p_error(p): + print "Syntax error at token", p.type # Just discard the token and tell the parser it's okay. yacc.errok() </pre> @@ -1370,7 +2411,7 @@ useful if trying to synchronize on special characters. For example: <blockquote> <pre> -def p_error(t): +def p_error(p): # Read ahead looking for a terminating ";" while 1: tok = yacc.token() # Get the next token @@ -1382,47 +2423,110 @@ def p_error(t): </pre> </blockquote> -<h4>General comments on error handling</h4> +<H4><a name="ply_nn32"></a>5.8.3 General comments on error handling</H4> + For normal types of languages, error recovery with error rules and resynchronization characters is probably the most reliable technique. This is because you can instrument the grammar to catch errors at selected places where it is relatively easy to recover and continue parsing. Panic mode recovery is really only useful in certain specialized applications where you might want to discard huge portions of the input text to find a valid restart point. -<h2>Line Number Tracking</h2> +<H3><a name="ply_nn33"></a>5.9 Line Number and Position Tracking</H3> -<tt>yacc.py</tt> automatically tracks line numbers for all of the grammar symbols and tokens it processes. To retrieve the line -numbers, two functions are used in grammar rules: +Position tracking is often a tricky problem when writing compilers. By default, PLY tracks the line number and position of +all tokens. This information is available using the following functions: <ul> -<li><tt>t.lineno(num)</tt>. Return the starting line number for symbol <em>num</em> -<li><tt>t.linespan(num)</tt>. Return a tuple (startline,endline) with the starting and ending line number for symbol <em>num</em>. +<li><tt>p.lineno(num)</tt>. Return the line number for symbol <em>num</em> +<li><tt>p.lexpos(num)</tt>. Return the lexing position for symbol <em>num</em> </ul> For example: <blockquote> <pre> -def t_expression(t): +def p_expression(p): 'expression : expression PLUS expression' - t.lineno(1) # Line number of the left expression - t.lineno(2) # line number of the PLUS operator - t.lineno(3) # line number of the right expression + line = p.lineno(2) # line number of the PLUS token + index = p.lexpos(2) # Position of the PLUS token +</pre> +</blockquote> + +As an optional feature, <tt>yacc.py</tt> can automatically track line numbers and positions for all of the grammar symbols +as well. However, this +extra tracking requires extra processing and can significantly slow down parsing. Therefore, it must be enabled by passing the +<tt>tracking=True</tt> option to <tt>yacc.parse()</tt>. For example: + +<blockquote> +<pre> +yacc.parse(data,tracking=True) +</pre> +</blockquote> + +Once enabled, the <tt>lineno()</tt> and <tt>lexpos()</tt> methods work for all grammar symbols. In addition, two +additional methods can be used: + +<ul> +<li><tt>p.linespan(num)</tt>. Return a tuple (startline,endline) with the starting and ending line number for symbol <em>num</em>. +<li><tt>p.lexspan(num)</tt>. Return a tuple (start,end) with the starting and ending positions for symbol <em>num</em>. +</ul> + +For example: + +<blockquote> +<pre> +def p_expression(p): + 'expression : expression PLUS expression' + p.lineno(1) # Line number of the left expression + p.lineno(2) # line number of the PLUS operator + p.lineno(3) # line number of the right expression ... - start,end = t.linespan(3) # Start,end lines of the right expression + start,end = p.linespan(3) # Start,end lines of the right expression + starti,endi = p.lexspan(3) # Start,end positions of right expression + +</pre> +</blockquote> +Note: The <tt>lexspan()</tt> function only returns the range of values up to the start of the last grammar symbol. + +<p> +Although it may be convenient for PLY to track position information on +all grammar symbols, this is often unnecessary. For example, if you +are merely using line number information in an error message, you can +often just key off of a specific token in the grammar rule. For +example: + +<blockquote> +<pre> +def p_bad_func(p): + 'funccall : fname LPAREN error RPAREN' + # Line number reported from LPAREN token + print "Bad function call at line", p.lineno(2) </pre> </blockquote> -Since line numbers are managed internally by the parser, there is usually no need to modify the line -numbers. However, if you want to save the line numbers in a parse-tree node, you will need to make your own -private copy. +<p> +Similarly, you may get better parsing performance if you only propagate line number +information where it's needed. For example: + +<blockquote> +<pre> +def p_fname(p): + 'fname : ID' + p[0] = (p[1],p.lineno(1)) +</pre> +</blockquote> + +Finally, it should be noted that PLY does not store position information after a rule has been +processed. If it is important for you to retain this information in an abstract syntax tree, you +must make your own copy. + +<H3><a name="ply_nn34"></a>5.10 AST Construction</H3> -<h2>AST Construction</h2> <tt>yacc.py</tt> provides no special functions for constructing an abstract syntax tree. However, such construction is easy enough to do on your own. Simply create a data structure for abstract syntax tree nodes -and assign nodes to <tt>t[0]</tt> in each rule. +and assign nodes to <tt>p[0]</tt> in each rule. For example: @@ -1442,21 +2546,21 @@ class Number(Expr): self.type = "number" self.value = value -def p_expression_binop(t): +def p_expression_binop(p): '''expression : expression PLUS expression | expression MINUS expression | expression TIMES expression | expression DIVIDE expression''' - t[0] = BinOp(t[1],t[2],t[3]) + p[0] = BinOp(p[1],p[2],p[3]) -def p_expression_group(t): +def p_expression_group(p): 'expression : LPAREN expression RPAREN' - t[0] = t[2] + p[0] = p[2] -def p_expression_number(t): +def p_expression_number(p): 'expression : NUMBER' - t[0] = Number(t[1]) + p[0] = Number(p[1]) </pre> </blockquote> @@ -1474,19 +2578,144 @@ class Node: self.children = [ ] self.leaf = leaf -def p_expression_binop(t): +def p_expression_binop(p): '''expression : expression PLUS expression | expression MINUS expression | expression TIMES expression | expression DIVIDE expression''' - t[0] = Node("binop", [t[1],t[3]], t[2]) + p[0] = Node("binop", [p[1],p[3]], p[2]) +</pre> +</blockquote> + +<H3><a name="ply_nn35"></a>5.11 Embedded Actions</H3> + + +The parsing technique used by yacc only allows actions to be executed at the end of a rule. For example, +suppose you have a rule like this: + +<blockquote> +<pre> +def p_foo(p): + "foo : A B C D" + print "Parsed a foo", p[1],p[2],p[3],p[4] +</pre> +</blockquote> + +<p> +In this case, the supplied action code only executes after all of the +symbols <tt>A</tt>, <tt>B</tt>, <tt>C</tt>, and <tt>D</tt> have been +parsed. Sometimes, however, it is useful to execute small code +fragments during intermediate stages of parsing. For example, suppose +you wanted to perform some action immediately after <tt>A</tt> has +been parsed. To do this, you can write a empty rule like this: + +<blockquote> +<pre> +def p_foo(p): + "foo : A seen_A B C D" + print "Parsed a foo", p[1],p[3],p[4],p[5] + print "seen_A returned", p[2] + +def p_seen_A(p): + "seen_A :" + print "Saw an A = ", p[-1] # Access grammar symbol to left + p[0] = some_value # Assign value to seen_A + +</pre> +</blockquote> + +<p> +In this example, the empty <tt>seen_A</tt> rule executes immediately +after <tt>A</tt> is shifted onto the parsing stack. Within this +rule, <tt>p[-1]</tt> refers to the symbol on the stack that appears +immediately to the left of the <tt>seen_A</tt> symbol. In this case, +it would be the value of <tt>A</tt> in the <tt>foo</tt> rule +immediately above. Like other rules, a value can be returned from an +embedded action by simply assigning it to <tt>p[0]</tt> + +<p> +The use of embedded actions can sometimes introduce extra shift/reduce conflicts. For example, +this grammar has no conflicts: + +<blockquote> +<pre> +def p_foo(p): + """foo : abcd + | abcx""" + +def p_abcd(p): + "abcd : A B C D" + +def p_abcx(p): + "abcx : A B C X" +</pre> +</blockquote> + +However, if you insert an embedded action into one of the rules like this, + +<blockquote> +<pre> +def p_foo(p): + """foo : abcd + | abcx""" + +def p_abcd(p): + "abcd : A B C D" + +def p_abcx(p): + "abcx : A B seen_AB C X" + +def p_seen_AB(p): + "seen_AB :" +</pre> +</blockquote> + +an extra shift-reduce conflict will be introduced. This conflict is caused by the fact that the same symbol <tt>C</tt> appears next in +both the <tt>abcd</tt> and <tt>abcx</tt> rules. The parser can either shift the symbol (<tt>abcd</tt> rule) or reduce the empty rule <tt>seen_AB</tt> (<tt>abcx</tt> rule). + +<p> +A common use of embedded rules is to control other aspects of parsing +such as scoping of local variables. For example, if you were parsing C code, you might +write code like this: + +<blockquote> +<pre> +def p_statements_block(p): + "statements: LBRACE new_scope statements RBRACE""" + # Action code + ... + pop_scope() # Return to previous scope + +def p_new_scope(p): + "new_scope :" + # Create a new scope for local variables + s = new_scope() + push_scope(s) + ... </pre> </blockquote> -<h2>Yacc implementation notes</h2> +In this case, the embedded action <tt>new_scope</tt> executes immediately after a <tt>LBRACE</tt> (<tt>{</tt>) symbol is parsed. This might +adjust internal symbol tables and other aspects of the parser. Upon completion of the rule <tt>statements_block</tt>, code might undo the operations performed in the embedded action (e.g., <tt>pop_scope()</tt>). + +<H3><a name="ply_nn36"></a>5.12 Yacc implementation notes</H3> + <ul> +<li>The default parsing method is LALR. To use SLR instead, run yacc() as follows: + +<blockquote> +<pre> +yacc.yacc(method="SLR") +</pre> +</blockquote> +Note: LALR table generation takes approximately twice as long as SLR table generation. There is no +difference in actual parsing performance---the same code is used in both cases. LALR is preferred when working +with more complicated grammars since it is more powerful. + +<p> + <li>By default, <tt>yacc.py</tt> relies on <tt>lex.py</tt> for tokenizing. However, an alternative tokenizer can be supplied as follows: @@ -1517,6 +2746,25 @@ yacc.yacc(tabmodule="foo") </pre> </blockquote> +<p> +<li>To change the directory in which the <tt>parsetab.py</tt> file (and other output files) are written, use: +<blockquote> +<pre> +yacc.yacc(tabmodule="foo",outputdir="somedirectory") +</pre> +</blockquote> + +<p> +<li>To prevent yacc from generating any kind of parser table file, use: +<blockquote> +<pre> +yacc.yacc(write_tables=0) +</pre> +</blockquote> + +Note: If you disable table generation, yacc() will regenerate the parsing tables +each time it runs (which may take awhile depending on how large your grammar is). + <P> <li>To print copious amounts of debugging during parsing, use: @@ -1527,6 +2775,15 @@ yacc.parse(debug=1) </blockquote> <p> +<li>To redirect the debugging output to a filename of your choosing, use: + +<blockquote> +<pre> +yacc.parse(debug=1, debugfile="debugging.out") +</pre> +</blockquote> + +<p> <li>The <tt>yacc.yacc()</tt> function really returns a parser object. If you want to support multiple parsers in the same application, do this: @@ -1541,7 +2798,7 @@ p.parse() Note: The function <tt>yacc.parse()</tt> is bound to the last parser that was generated. <p> -<li>Since the generation of the SLR tables is relatively expensive, previously generated tables are +<li>Since the generation of the LALR tables is relatively expensive, previously generated tables are cached and reused if possible. The decision to regenerate the tables is determined by taking an MD5 checksum of all grammar rules and precedence rules. Only in the event of a mismatch are the tables regenerated. @@ -1551,11 +2808,12 @@ and several hundred states. For more complex languages such as C, table generat machine. Please be patient. <p> -<li>Since LR parsing is mostly driven by tables, the performance of the parser is largely independent of the -size of the grammar. The biggest bottlenecks will be the lexer and the complexity of your grammar rules. +<li>Since LR parsing is driven by tables, the performance of the parser is largely independent of the +size of the grammar. The biggest bottlenecks will be the lexer and the complexity of the code in your grammar rules. </ul> -<h2>Parser and Lexer State Management</h2> +<H2><a name="ply_nn37"></a>6. Parser and Lexer State Management</H2> + In advanced parsing applications, you may want to have multiple parsers and lexers. Furthermore, the parser may want to control the @@ -1573,6 +2831,14 @@ parser = yacc.yacc() # Return parser object </pre> </blockquote> +To attach the lexer and parser together, make sure you use the <tt>lexer</tt> argumemnt to parse. For example: + +<blockquote> +<pre> +parser.parse(text,lexer=lexer) +</pre> +</blockquote> + Within lexer and parser rules, these objects are also available. In the lexer, the "lexer" attribute of a token refers to the lexer object in use. For example: @@ -1590,11 +2856,11 @@ and parser objects respectively. <blockquote> <pre> -def p_expr_plus(t): +def p_expr_plus(p): 'expr : expr PLUS expr' ... - print t.parser # Show parser object - print t.lexer # Show lexer object + print p.parser # Show parser object + print p.lexer # Show lexer object </pre> </blockquote> @@ -1602,7 +2868,8 @@ If necessary, arbitrary attributes can be attached to the lexer or parser object For example, if you wanted to have different parsing modes, you could attach a mode attribute to the parser object and look at it later. -<h2>Using Python's Optimized Mode</h2> +<H2><a name="ply_nn38"></a>7. Using Python's Optimized Mode</H2> + Because PLY uses information from doc-strings, parsing and lexing information must be gathered while running the Python interpreter in @@ -1626,7 +2893,8 @@ Beware: running PLY in optimized mode disables a lot of error checking. You should only do this when your project has stabilized and you don't need to do any debugging. -<h2>Where to go from here?</h2> +<H2><a name="ply_nn39"></a>8. Where to go from here?</H2> + The <tt>examples</tt> directory of the PLY distribution contains several simple examples. Please consult a compilers textbook for the theory and underlying implementation details or LR parsing. diff --git a/ext/ply/example/BASIC/README b/ext/ply/example/BASIC/README new file mode 100644 index 000000000..be24a3005 --- /dev/null +++ b/ext/ply/example/BASIC/README @@ -0,0 +1,79 @@ +Inspired by a September 14, 2006 Salon article "Why Johnny Can't Code" by +David Brin (http://www.salon.com/tech/feature/2006/09/14/basic/index.html), +I thought that a fully working BASIC interpreter might be an interesting, +if not questionable, PLY example. Uh, okay, so maybe it's just a bad idea, +but in any case, here it is. + +In this example, you'll find a rough implementation of 1964 Dartmouth BASIC +as described in the manual at: + + http://www.bitsavers.org/pdf/dartmouth/BASIC_Oct64.pdf + +See also: + + http://en.wikipedia.org/wiki/Dartmouth_BASIC + +This dialect is downright primitive---there are no string variables +and no facilities for interactive input. Moreover, subroutines and functions +are brain-dead even more than they usually are for BASIC. Of course, +the GOTO statement is provided. + +Nevertheless, there are a few interesting aspects of this example: + + - It illustrates a fully working interpreter including lexing, parsing, + and interpretation of instructions. + + - The parser shows how to catch and report various kinds of parsing + errors in a more graceful way. + + - The example both parses files (supplied on command line) and + interactive input entered line by line. + + - It shows how you might represent parsed information. In this case, + each BASIC statement is encoded into a Python tuple containing the + statement type and parameters. These tuples are then stored in + a dictionary indexed by program line numbers. + + - Even though it's just BASIC, the parser contains more than 80 + rules and 150 parsing states. Thus, it's a little more meaty than + the calculator example. + +To use the example, run it as follows: + + % python basic.py hello.bas + HELLO WORLD + % + +or use it interactively: + + % python basic.py + [BASIC] 10 PRINT "HELLO WORLD" + [BASIC] 20 END + [BASIC] RUN + HELLO WORLD + [BASIC] + +The following files are defined: + + basic.py - High level script that controls everything + basiclex.py - BASIC tokenizer + basparse.py - BASIC parser + basinterp.py - BASIC interpreter that runs parsed programs. + +In addition, a number of sample BASIC programs (.bas suffix) are +provided. These were taken out of the Dartmouth manual. + +Disclaimer: I haven't spent a ton of time testing this and it's likely that +I've skimped here and there on a few finer details (e.g., strictly enforcing +variable naming rules). However, the interpreter seems to be able to run +the examples in the BASIC manual. + +Have fun! + +-Dave + + + + + + diff --git a/ext/ply/example/BASIC/basic.py b/ext/ply/example/BASIC/basic.py new file mode 100644 index 000000000..3a07acdbf --- /dev/null +++ b/ext/ply/example/BASIC/basic.py @@ -0,0 +1,68 @@ +# An implementation of Dartmouth BASIC (1964) +# + +import sys +sys.path.insert(0,"../..") + +import basiclex +import basparse +import basinterp + +# If a filename has been specified, we try to run it. +# If a runtime error occurs, we bail out and enter +# interactive mode below +if len(sys.argv) == 2: + data = open(sys.argv[1]).read() + prog = basparse.parse(data) + if not prog: raise SystemExit + b = basinterp.BasicInterpreter(prog) + try: + b.run() + raise SystemExit + except RuntimeError: + pass + +else: + b = basinterp.BasicInterpreter({}) + +# Interactive mode. This incrementally adds/deletes statements +# from the program stored in the BasicInterpreter object. In +# addition, special commands 'NEW','LIST',and 'RUN' are added. +# Specifying a line number with no code deletes that line from +# the program. + +while 1: + try: + line = raw_input("[BASIC] ") + except EOFError: + raise SystemExit + if not line: continue + line += "\n" + prog = basparse.parse(line) + if not prog: continue + + keys = prog.keys() + if keys[0] > 0: + b.add_statements(prog) + else: + stat = prog[keys[0]] + if stat[0] == 'RUN': + try: + b.run() + except RuntimeError: + pass + elif stat[0] == 'LIST': + b.list() + elif stat[0] == 'BLANK': + b.del_line(stat[1]) + elif stat[0] == 'NEW': + b.new() + + + + + + + + + diff --git a/ext/ply/example/BASIC/basiclex.py b/ext/ply/example/BASIC/basiclex.py new file mode 100644 index 000000000..727383f2b --- /dev/null +++ b/ext/ply/example/BASIC/basiclex.py @@ -0,0 +1,74 @@ +# An implementation of Dartmouth BASIC (1964) + +from ply import * + +keywords = ( + 'LET','READ','DATA','PRINT','GOTO','IF','THEN','FOR','NEXT','TO','STEP', + 'END','STOP','DEF','GOSUB','DIM','REM','RETURN','RUN','LIST','NEW', +) + +tokens = keywords + ( + 'EQUALS','PLUS','MINUS','TIMES','DIVIDE','POWER', + 'LPAREN','RPAREN','LT','LE','GT','GE','NE', + 'COMMA','SEMI', 'INTEGER','FLOAT', 'STRING', + 'ID','NEWLINE' +) + +t_ignore = ' \t' + +def t_REM(t): + r'REM .*' + return t + +def t_ID(t): + r'[A-Z][A-Z0-9]*' + if t.value in keywords: + t.type = t.value + return t + +t_EQUALS = r'=' +t_PLUS = r'\+' +t_MINUS = r'-' +t_TIMES = r'\*' +t_POWER = r'\^' +t_DIVIDE = r'/' +t_LPAREN = r'\(' +t_RPAREN = r'\)' +t_LT = r'<' +t_LE = r'<=' +t_GT = r'>' +t_GE = r'>=' +t_NE = r'<>' +t_COMMA = r'\,' +t_SEMI = r';' +t_INTEGER = r'\d+' +t_FLOAT = r'((\d*\.\d+)(E[\+-]?\d+)?|([1-9]\d*E[\+-]?\d+))' +t_STRING = r'\".*?\"' + +def t_NEWLINE(t): + r'\n' + t.lexer.lineno += 1 + return t + +def t_error(t): + print "Illegal character", t.value[0] + t.lexer.skip(1) + +lex.lex() + + + + + + + + + + + + + + + + + diff --git a/ext/ply/example/BASIC/basinterp.py b/ext/ply/example/BASIC/basinterp.py new file mode 100644 index 000000000..5850457cb --- /dev/null +++ b/ext/ply/example/BASIC/basinterp.py @@ -0,0 +1,440 @@ +# This file provides the runtime support for running a basic program +# Assumes the program has been parsed using basparse.py + +import sys +import math +import random + +class BasicInterpreter: + + # Initialize the interpreter. prog is a dictionary + # containing (line,statement) mappings + def __init__(self,prog): + self.prog = prog + + self.functions = { # Built-in function table + 'SIN' : lambda z: math.sin(self.eval(z)), + 'COS' : lambda z: math.cos(self.eval(z)), + 'TAN' : lambda z: math.tan(self.eval(z)), + 'ATN' : lambda z: math.atan(self.eval(z)), + 'EXP' : lambda z: math.exp(self.eval(z)), + 'ABS' : lambda z: abs(self.eval(z)), + 'LOG' : lambda z: math.log(self.eval(z)), + 'SQR' : lambda z: math.sqrt(self.eval(z)), + 'INT' : lambda z: int(self.eval(z)), + 'RND' : lambda z: random.random() + } + + # Collect all data statements + def collect_data(self): + self.data = [] + for lineno in self.stat: + if self.prog[lineno][0] == 'DATA': + self.data = self.data + self.prog[lineno][1] + self.dc = 0 # Initialize the data counter + + # Check for end statements + def check_end(self): + has_end = 0 + for lineno in self.stat: + if self.prog[lineno][0] == 'END' and not has_end: + has_end = lineno + if not has_end: + print "NO END INSTRUCTION" + self.error = 1 + if has_end != lineno: + print "END IS NOT LAST" + self.error = 1 + + # Check loops + def check_loops(self): + for pc in range(len(self.stat)): + lineno = self.stat[pc] + if self.prog[lineno][0] == 'FOR': + forinst = self.prog[lineno] + loopvar = forinst[1] + for i in range(pc+1,len(self.stat)): + if self.prog[self.stat[i]][0] == 'NEXT': + nextvar = self.prog[self.stat[i]][1] + if nextvar != loopvar: continue + self.loopend[pc] = i + break + else: + print "FOR WITHOUT NEXT AT LINE" % self.stat[pc] + self.error = 1 + + # Evaluate an expression + def eval(self,expr): + etype = expr[0] + if etype == 'NUM': return expr[1] + elif etype == 'GROUP': return self.eval(expr[1]) + elif etype == 'UNARY': + if expr[1] == '-': return -self.eval(expr[2]) + elif etype == 'BINOP': + if expr[1] == '+': return self.eval(expr[2])+self.eval(expr[3]) + elif expr[1] == '-': return self.eval(expr[2])-self.eval(expr[3]) + elif expr[1] == '*': return self.eval(expr[2])*self.eval(expr[3]) + elif expr[1] == '/': return float(self.eval(expr[2]))/self.eval(expr[3]) + elif expr[1] == '^': return abs(self.eval(expr[2]))**self.eval(expr[3]) + elif etype == 'VAR': + var,dim1,dim2 = expr[1] + if not dim1 and not dim2: + if self.vars.has_key(var): + return self.vars[var] + else: + print "UNDEFINED VARIABLE", var, "AT LINE", self.stat[self.pc] + raise RuntimeError + # May be a list lookup or a function evaluation + if dim1 and not dim2: + if self.functions.has_key(var): + # A function + return self.functions[var](dim1) + else: + # A list evaluation + if self.lists.has_key(var): + dim1val = self.eval(dim1) + if dim1val < 1 or dim1val > len(self.lists[var]): + print "LIST INDEX OUT OF BOUNDS AT LINE", self.stat[self.pc] + raise RuntimeError + return self.lists[var][dim1val-1] + if dim1 and dim2: + if self.tables.has_key(var): + dim1val = self.eval(dim1) + dim2val = self.eval(dim2) + if dim1val < 1 or dim1val > len(self.tables[var]) or dim2val < 1 or dim2val > len(self.tables[var][0]): + print "TABLE INDEX OUT OUT BOUNDS AT LINE", self.stat[self.pc] + raise RuntimeError + return self.tables[var][dim1val-1][dim2val-1] + print "UNDEFINED VARIABLE", var, "AT LINE", self.stat[self.pc] + raise RuntimeError + + # Evaluate a relational expression + def releval(self,expr): + etype = expr[1] + lhs = self.eval(expr[2]) + rhs = self.eval(expr[3]) + if etype == '<': + if lhs < rhs: return 1 + else: return 0 + + elif etype == '<=': + if lhs <= rhs: return 1 + else: return 0 + + elif etype == '>': + if lhs > rhs: return 1 + else: return 0 + + elif etype == '>=': + if lhs >= rhs: return 1 + else: return 0 + + elif etype == '=': + if lhs == rhs: return 1 + else: return 0 + + elif etype == '<>': + if lhs != rhs: return 1 + else: return 0 + + # Assignment + def assign(self,target,value): + var, dim1, dim2 = target + if not dim1 and not dim2: + self.vars[var] = self.eval(value) + elif dim1 and not dim2: + # List assignment + dim1val = self.eval(dim1) + if not self.lists.has_key(var): + self.lists[var] = [0]*10 + + if dim1val > len(self.lists[var]): + print "DIMENSION TOO LARGE AT LINE", self.stat[self.pc] + raise RuntimeError + self.lists[var][dim1val-1] = self.eval(value) + elif dim1 and dim2: + dim1val = self.eval(dim1) + dim2val = self.eval(dim2) + if not self.tables.has_key(var): + temp = [0]*10 + v = [] + for i in range(10): v.append(temp[:]) + self.tables[var] = v + # Variable already exists + if dim1val > len(self.tables[var]) or dim2val > len(self.tables[var][0]): + print "DIMENSION TOO LARGE AT LINE", self.stat[self.pc] + raise RuntimeError + self.tables[var][dim1val-1][dim2val-1] = self.eval(value) + + # Change the current line number + def goto(self,linenum): + if not self.prog.has_key(linenum): + print "UNDEFINED LINE NUMBER %d AT LINE %d" % (linenum, self.stat[self.pc]) + raise RuntimeError + self.pc = self.stat.index(linenum) + + # Run it + def run(self): + self.vars = { } # All variables + self.lists = { } # List variables + self.tables = { } # Tables + self.loops = [ ] # Currently active loops + self.loopend= { } # Mapping saying where loops end + self.gosub = None # Gosub return point (if any) + self.error = 0 # Indicates program error + + self.stat = self.prog.keys() # Ordered list of all line numbers + self.stat.sort() + self.pc = 0 # Current program counter + + # Processing prior to running + + self.collect_data() # Collect all of the data statements + self.check_end() + self.check_loops() + + if self.error: raise RuntimeError + + while 1: + line = self.stat[self.pc] + instr = self.prog[line] + + op = instr[0] + + # END and STOP statements + if op == 'END' or op == 'STOP': + break # We're done + + # GOTO statement + elif op == 'GOTO': + newline = instr[1] + self.goto(newline) + continue + + # PRINT statement + elif op == 'PRINT': + plist = instr[1] + out = "" + for label,val in plist: + if out: + out += ' '*(15 - (len(out) % 15)) + out += label + if val: + if label: out += " " + eval = self.eval(val) + out += str(eval) + sys.stdout.write(out) + end = instr[2] + if not (end == ',' or end == ';'): + sys.stdout.write("\n") + if end == ',': sys.stdout.write(" "*(15-(len(out) % 15))) + if end == ';': sys.stdout.write(" "*(3-(len(out) % 3))) + + # LET statement + elif op == 'LET': + target = instr[1] + value = instr[2] + self.assign(target,value) + + # READ statement + elif op == 'READ': + for target in instr[1]: + if self.dc < len(self.data): + value = ('NUM',self.data[self.dc]) + self.assign(target,value) + self.dc += 1 + else: + # No more data. Program ends + return + elif op == 'IF': + relop = instr[1] + newline = instr[2] + if (self.releval(relop)): + self.goto(newline) + continue + + elif op == 'FOR': + loopvar = instr[1] + initval = instr[2] + finval = instr[3] + stepval = instr[4] + + # Check to see if this is a new loop + if not self.loops or self.loops[-1][0] != self.pc: + # Looks like a new loop. Make the initial assignment + newvalue = initval + self.assign((loopvar,None,None),initval) + if not stepval: stepval = ('NUM',1) + stepval = self.eval(stepval) # Evaluate step here + self.loops.append((self.pc,stepval)) + else: + # It's a repeat of the previous loop + # Update the value of the loop variable according to the step + stepval = ('NUM',self.loops[-1][1]) + newvalue = ('BINOP','+',('VAR',(loopvar,None,None)),stepval) + + if self.loops[-1][1] < 0: relop = '>=' + else: relop = '<=' + if not self.releval(('RELOP',relop,newvalue,finval)): + # Loop is done. Jump to the NEXT + self.pc = self.loopend[self.pc] + self.loops.pop() + else: + self.assign((loopvar,None,None),newvalue) + + elif op == 'NEXT': + if not self.loops: + print "NEXT WITHOUT FOR AT LINE",line + return + + nextvar = instr[1] + self.pc = self.loops[-1][0] + loopinst = self.prog[self.stat[self.pc]] + forvar = loopinst[1] + if nextvar != forvar: + print "NEXT DOESN'T MATCH FOR AT LINE", line + return + continue + elif op == 'GOSUB': + newline = instr[1] + if self.gosub: + print "ALREADY IN A SUBROUTINE AT LINE", line + return + self.gosub = self.stat[self.pc] + self.goto(newline) + continue + + elif op == 'RETURN': + if not self.gosub: + print "RETURN WITHOUT A GOSUB AT LINE",line + return + self.goto(self.gosub) + self.gosub = None + + elif op == 'FUNC': + fname = instr[1] + pname = instr[2] + expr = instr[3] + def eval_func(pvalue,name=pname,self=self,expr=expr): + self.assign((pname,None,None),pvalue) + return self.eval(expr) + self.functions[fname] = eval_func + + elif op == 'DIM': + for vname,x,y in instr[1]: + if y == 0: + # Single dimension variable + self.lists[vname] = [0]*x + else: + # Double dimension variable + temp = [0]*y + v = [] + for i in range(x): + v.append(temp[:]) + self.tables[vname] = v + + self.pc += 1 + + # Utility functions for program listing + def expr_str(self,expr): + etype = expr[0] + if etype == 'NUM': return str(expr[1]) + elif etype == 'GROUP': return "(%s)" % self.expr_str(expr[1]) + elif etype == 'UNARY': + if expr[1] == '-': return "-"+str(expr[2]) + elif etype == 'BINOP': + return "%s %s %s" % (self.expr_str(expr[2]),expr[1],self.expr_str(expr[3])) + elif etype == 'VAR': + return self.var_str(expr[1]) + + def relexpr_str(self,expr): + return "%s %s %s" % (self.expr_str(expr[2]),expr[1],self.expr_str(expr[3])) + + def var_str(self,var): + varname,dim1,dim2 = var + if not dim1 and not dim2: return varname + if dim1 and not dim2: return "%s(%s)" % (varname, self.expr_str(dim1)) + return "%s(%s,%s)" % (varname, self.expr_str(dim1),self.expr_str(dim2)) + + # Create a program listing + def list(self): + stat = self.prog.keys() # Ordered list of all line numbers + stat.sort() + for line in stat: + instr = self.prog[line] + op = instr[0] + if op in ['END','STOP','RETURN']: + print line, op + continue + elif op == 'REM': + print line, instr[1] + elif op == 'PRINT': + print line, op, + first = 1 + for p in instr[1]: + if not first: print ",", + if p[0] and p[1]: print '"%s"%s' % (p[0],self.expr_str(p[1])), + elif p[1]: print self.expr_str(p[1]), + else: print '"%s"' % (p[0],), + first = 0 + if instr[2]: print instr[2] + else: print + elif op == 'LET': + print line,"LET",self.var_str(instr[1]),"=",self.expr_str(instr[2]) + elif op == 'READ': + print line,"READ", + first = 1 + for r in instr[1]: + if not first: print ",", + print self.var_str(r), + first = 0 + print "" + elif op == 'IF': + print line,"IF %s THEN %d" % (self.relexpr_str(instr[1]),instr[2]) + elif op == 'GOTO' or op == 'GOSUB': + print line, op, instr[1] + elif op == 'FOR': + print line,"FOR %s = %s TO %s" % (instr[1],self.expr_str(instr[2]),self.expr_str(instr[3])), + if instr[4]: print "STEP %s" % (self.expr_str(instr[4])), + print + elif op == 'NEXT': + print line,"NEXT", instr[1] + elif op == 'FUNC': + print line,"DEF %s(%s) = %s" % (instr[1],instr[2],self.expr_str(instr[3])) + elif op == 'DIM': + print line,"DIM", + first = 1 + for vname,x,y in instr[1]: + if not first: print ",", + first = 0 + if y == 0: + print "%s(%d)" % (vname,x), + else: + print "%s(%d,%d)" % (vname,x,y), + + print + elif op == 'DATA': + print line,"DATA", + first = 1 + for v in instr[1]: + if not first: print ",", + first = 0 + print v, + print + + # Erase the current program + def new(self): + self.prog = {} + + # Insert statements + def add_statements(self,prog): + for line,stat in prog.items(): + self.prog[line] = stat + + # Delete a statement + def del_line(self,lineno): + try: + del self.prog[lineno] + except KeyError: + pass + diff --git a/ext/ply/example/BASIC/basparse.py b/ext/ply/example/BASIC/basparse.py new file mode 100644 index 000000000..930af9a22 --- /dev/null +++ b/ext/ply/example/BASIC/basparse.py @@ -0,0 +1,424 @@ +# An implementation of Dartmouth BASIC (1964) +# + +from ply import * +import basiclex + +tokens = basiclex.tokens + +precedence = ( + ('left', 'PLUS','MINUS'), + ('left', 'TIMES','DIVIDE'), + ('left', 'POWER'), + ('right','UMINUS') +) + +#### A BASIC program is a series of statements. We represent the program as a +#### dictionary of tuples indexed by line number. + +def p_program(p): + '''program : program statement + | statement''' + + if len(p) == 2 and p[1]: + p[0] = { } + line,stat = p[1] + p[0][line] = stat + elif len(p) ==3: + p[0] = p[1] + if not p[0]: p[0] = { } + if p[2]: + line,stat = p[2] + p[0][line] = stat + +#### This catch-all rule is used for any catastrophic errors. In this case, +#### we simply return nothing + +def p_program_error(p): + '''program : error''' + p[0] = None + p.parser.error = 1 + +#### Format of all BASIC statements. + +def p_statement(p): + '''statement : INTEGER command NEWLINE''' + if isinstance(p[2],str): + print p[2],"AT LINE", p[1] + p[0] = None + p.parser.error = 1 + else: + lineno = int(p[1]) + p[0] = (lineno,p[2]) + +#### Interactive statements. + +def p_statement_interactive(p): + '''statement : RUN NEWLINE + | LIST NEWLINE + | NEW NEWLINE''' + p[0] = (0, (p[1],0)) + +#### Blank line number +def p_statement_blank(p): + '''statement : INTEGER NEWLINE''' + p[0] = (0,('BLANK',int(p[1]))) + +#### Error handling for malformed statements + +def p_statement_bad(p): + '''statement : INTEGER error NEWLINE''' + print "MALFORMED STATEMENT AT LINE", p[1] + p[0] = None + p.parser.error = 1 + +#### Blank line + +def p_statement_newline(p): + '''statement : NEWLINE''' + p[0] = None + +#### LET statement + +def p_command_let(p): + '''command : LET variable EQUALS expr''' + p[0] = ('LET',p[2],p[4]) + +def p_command_let_bad(p): + '''command : LET variable EQUALS error''' + p[0] = "BAD EXPRESSION IN LET" + +#### READ statement + +def p_command_read(p): + '''command : READ varlist''' + p[0] = ('READ',p[2]) + +def p_command_read_bad(p): + '''command : READ error''' + p[0] = "MALFORMED VARIABLE LIST IN READ" + +#### DATA statement + +def p_command_data(p): + '''command : DATA numlist''' + p[0] = ('DATA',p[2]) + +def p_command_data_bad(p): + '''command : DATA error''' + p[0] = "MALFORMED NUMBER LIST IN DATA" + +#### PRINT statement + +def p_command_print(p): + '''command : PRINT plist optend''' + p[0] = ('PRINT',p[2],p[3]) + +def p_command_print_bad(p): + '''command : PRINT error''' + p[0] = "MALFORMED PRINT STATEMENT" + +#### Optional ending on PRINT. Either a comma (,) or semicolon (;) + +def p_optend(p): + '''optend : COMMA + | SEMI + |''' + if len(p) == 2: + p[0] = p[1] + else: + p[0] = None + +#### PRINT statement with no arguments + +def p_command_print_empty(p): + '''command : PRINT''' + p[0] = ('PRINT',[],None) + +#### GOTO statement + +def p_command_goto(p): + '''command : GOTO INTEGER''' + p[0] = ('GOTO',int(p[2])) + +def p_command_goto_bad(p): + '''command : GOTO error''' + p[0] = "INVALID LINE NUMBER IN GOTO" + +#### IF-THEN statement + +def p_command_if(p): + '''command : IF relexpr THEN INTEGER''' + p[0] = ('IF',p[2],int(p[4])) + +def p_command_if_bad(p): + '''command : IF error THEN INTEGER''' + p[0] = "BAD RELATIONAL EXPRESSION" + +def p_command_if_bad2(p): + '''command : IF relexpr THEN error''' + p[0] = "INVALID LINE NUMBER IN THEN" + +#### FOR statement + +def p_command_for(p): + '''command : FOR ID EQUALS expr TO expr optstep''' + p[0] = ('FOR',p[2],p[4],p[6],p[7]) + +def p_command_for_bad_initial(p): + '''command : FOR ID EQUALS error TO expr optstep''' + p[0] = "BAD INITIAL VALUE IN FOR STATEMENT" + +def p_command_for_bad_final(p): + '''command : FOR ID EQUALS expr TO error optstep''' + p[0] = "BAD FINAL VALUE IN FOR STATEMENT" + +def p_command_for_bad_step(p): + '''command : FOR ID EQUALS expr TO expr STEP error''' + p[0] = "MALFORMED STEP IN FOR STATEMENT" + +#### Optional STEP qualifier on FOR statement + +def p_optstep(p): + '''optstep : STEP expr + | empty''' + if len(p) == 3: + p[0] = p[2] + else: + p[0] = None + +#### NEXT statement + +def p_command_next(p): + '''command : NEXT ID''' + + p[0] = ('NEXT',p[2]) + +def p_command_next_bad(p): + '''command : NEXT error''' + p[0] = "MALFORMED NEXT" + +#### END statement + +def p_command_end(p): + '''command : END''' + p[0] = ('END',) + +#### REM statement + +def p_command_rem(p): + '''command : REM''' + p[0] = ('REM',p[1]) + +#### STOP statement + +def p_command_stop(p): + '''command : STOP''' + p[0] = ('STOP',) + +#### DEF statement + +def p_command_def(p): + '''command : DEF ID LPAREN ID RPAREN EQUALS expr''' + p[0] = ('FUNC',p[2],p[4],p[7]) + +def p_command_def_bad_rhs(p): + '''command : DEF ID LPAREN ID RPAREN EQUALS error''' + p[0] = "BAD EXPRESSION IN DEF STATEMENT" + +def p_command_def_bad_arg(p): + '''command : DEF ID LPAREN error RPAREN EQUALS expr''' + p[0] = "BAD ARGUMENT IN DEF STATEMENT" + +#### GOSUB statement + +def p_command_gosub(p): + '''command : GOSUB INTEGER''' + p[0] = ('GOSUB',int(p[2])) + +def p_command_gosub_bad(p): + '''command : GOSUB error''' + p[0] = "INVALID LINE NUMBER IN GOSUB" + +#### RETURN statement + +def p_command_return(p): + '''command : RETURN''' + p[0] = ('RETURN',) + +#### DIM statement + +def p_command_dim(p): + '''command : DIM dimlist''' + p[0] = ('DIM',p[2]) + +def p_command_dim_bad(p): + '''command : DIM error''' + p[0] = "MALFORMED VARIABLE LIST IN DIM" + +#### List of variables supplied to DIM statement + +def p_dimlist(p): + '''dimlist : dimlist COMMA dimitem + | dimitem''' + if len(p) == 4: + p[0] = p[1] + p[0].append(p[3]) + else: + p[0] = [p[1]] + +#### DIM items + +def p_dimitem_single(p): + '''dimitem : ID LPAREN INTEGER RPAREN''' + p[0] = (p[1],eval(p[3]),0) + +def p_dimitem_double(p): + '''dimitem : ID LPAREN INTEGER COMMA INTEGER RPAREN''' + p[0] = (p[1],eval(p[3]),eval(p[5])) + +#### Arithmetic expressions + +def p_expr_binary(p): + '''expr : expr PLUS expr + | expr MINUS expr + | expr TIMES expr + | expr DIVIDE expr + | expr POWER expr''' + + p[0] = ('BINOP',p[2],p[1],p[3]) + +def p_expr_number(p): + '''expr : INTEGER + | FLOAT''' + p[0] = ('NUM',eval(p[1])) + +def p_expr_variable(p): + '''expr : variable''' + p[0] = ('VAR',p[1]) + +def p_expr_group(p): + '''expr : LPAREN expr RPAREN''' + p[0] = ('GROUP',p[2]) + +def p_expr_unary(p): + '''expr : MINUS expr %prec UMINUS''' + p[0] = ('UNARY','-',p[2]) + +#### Relational expressions + +def p_relexpr(p): + '''relexpr : expr LT expr + | expr LE expr + | expr GT expr + | expr GE expr + | expr EQUALS expr + | expr NE expr''' + p[0] = ('RELOP',p[2],p[1],p[3]) + +#### Variables + +def p_variable(p): + '''variable : ID + | ID LPAREN expr RPAREN + | ID LPAREN expr COMMA expr RPAREN''' + if len(p) == 2: + p[0] = (p[1],None,None) + elif len(p) == 5: + p[0] = (p[1],p[3],None) + else: + p[0] = (p[1],p[3],p[5]) + +#### Builds a list of variable targets as a Python list + +def p_varlist(p): + '''varlist : varlist COMMA variable + | variable''' + if len(p) > 2: + p[0] = p[1] + p[0].append(p[3]) + else: + p[0] = [p[1]] + + +#### Builds a list of numbers as a Python list + +def p_numlist(p): + '''numlist : numlist COMMA number + | number''' + + if len(p) > 2: + p[0] = p[1] + p[0].append(p[3]) + else: + p[0] = [p[1]] + +#### A number. May be an integer or a float + +def p_number(p): + '''number : INTEGER + | FLOAT''' + p[0] = eval(p[1]) + +#### A signed number. + +def p_number_signed(p): + '''number : MINUS INTEGER + | MINUS FLOAT''' + p[0] = eval("-"+p[2]) + +#### List of targets for a print statement +#### Returns a list of tuples (label,expr) + +def p_plist(p): + '''plist : plist COMMA pitem + | pitem''' + if len(p) > 3: + p[0] = p[1] + p[0].append(p[3]) + else: + p[0] = [p[1]] + +def p_item_string(p): + '''pitem : STRING''' + p[0] = (p[1][1:-1],None) + +def p_item_string_expr(p): + '''pitem : STRING expr''' + p[0] = (p[1][1:-1],p[2]) + +def p_item_expr(p): + '''pitem : expr''' + p[0] = ("",p[1]) + +#### Empty + +def p_empty(p): + '''empty : ''' + +#### Catastrophic error handler +def p_error(p): + if not p: + print "SYNTAX ERROR AT EOF" + +bparser = yacc.yacc() + +def parse(data): + bparser.error = 0 + p = bparser.parse(data) + if bparser.error: return None + return p + + + + + + + + + + + + + + diff --git a/ext/ply/example/BASIC/dim.bas b/ext/ply/example/BASIC/dim.bas new file mode 100644 index 000000000..87bd95b32 --- /dev/null +++ b/ext/ply/example/BASIC/dim.bas @@ -0,0 +1,14 @@ +5 DIM A(50,15) +10 FOR I = 1 TO 50 +20 FOR J = 1 TO 15 +30 LET A(I,J) = I + J +35 REM PRINT I,J, A(I,J) +40 NEXT J +50 NEXT I +100 FOR I = 1 TO 50 +110 FOR J = 1 TO 15 +120 PRINT A(I,J), +130 NEXT J +140 PRINT +150 NEXT I +999 END diff --git a/ext/ply/example/BASIC/func.bas b/ext/ply/example/BASIC/func.bas new file mode 100644 index 000000000..447ee16a9 --- /dev/null +++ b/ext/ply/example/BASIC/func.bas @@ -0,0 +1,5 @@ +10 DEF FDX(X) = 2*X +20 FOR I = 0 TO 100 +30 PRINT FDX(I) +40 NEXT I +50 END diff --git a/ext/ply/example/BASIC/gcd.bas b/ext/ply/example/BASIC/gcd.bas new file mode 100644 index 000000000..d0b774608 --- /dev/null +++ b/ext/ply/example/BASIC/gcd.bas @@ -0,0 +1,22 @@ +10 PRINT "A","B","C","GCD" +20 READ A,B,C +30 LET X = A +40 LET Y = B +50 GOSUB 200 +60 LET X = G +70 LET Y = C +80 GOSUB 200 +90 PRINT A, B, C, G +100 GOTO 20 +110 DATA 60, 90, 120 +120 DATA 38456, 64872, 98765 +130 DATA 32, 384, 72 +200 LET Q = INT(X/Y) +210 LET R = X - Q*Y +220 IF R = 0 THEN 300 +230 LET X = Y +240 LET Y = R +250 GOTO 200 +300 LET G = Y +310 RETURN +999 END diff --git a/ext/ply/example/BASIC/gosub.bas b/ext/ply/example/BASIC/gosub.bas new file mode 100644 index 000000000..99737b16f --- /dev/null +++ b/ext/ply/example/BASIC/gosub.bas @@ -0,0 +1,13 @@ +100 LET X = 3 +110 GOSUB 400 +120 PRINT U, V, W +200 LET X = 5 +210 GOSUB 400 +220 LET Z = U + 2*V + 3*W +230 PRINT Z +240 GOTO 999 +400 LET U = X*X +410 LET V = X*X*X +420 LET W = X*X*X*X + X*X*X + X*X + X +430 RETURN +999 END diff --git a/ext/ply/example/BASIC/hello.bas b/ext/ply/example/BASIC/hello.bas new file mode 100644 index 000000000..cc6f0b0b5 --- /dev/null +++ b/ext/ply/example/BASIC/hello.bas @@ -0,0 +1,4 @@ +5 REM HELLO WORLD PROGAM +10 PRINT "HELLO WORLD" +99 END + diff --git a/ext/ply/example/BASIC/linear.bas b/ext/ply/example/BASIC/linear.bas new file mode 100644 index 000000000..56c08220b --- /dev/null +++ b/ext/ply/example/BASIC/linear.bas @@ -0,0 +1,17 @@ +1 REM ::: SOLVE A SYSTEM OF LINEAR EQUATIONS +2 REM ::: A1*X1 + A2*X2 = B1 +3 REM ::: A3*X1 + A4*X2 = B2 +4 REM -------------------------------------- +10 READ A1, A2, A3, A4 +15 LET D = A1 * A4 - A3 * A2 +20 IF D = 0 THEN 65 +30 READ B1, B2 +37 LET X1 = (B1*A4 - B2*A2) / D +42 LET X2 = (A1*B2 - A3*B1) / D +55 PRINT X1, X2 +60 GOTO 30 +65 PRINT "NO UNIQUE SOLUTION" +70 DATA 1, 2, 4 +80 DATA 2, -7, 5 +85 DATA 1, 3, 4, -7 +90 END diff --git a/ext/ply/example/BASIC/maxsin.bas b/ext/ply/example/BASIC/maxsin.bas new file mode 100644 index 000000000..b96901530 --- /dev/null +++ b/ext/ply/example/BASIC/maxsin.bas @@ -0,0 +1,12 @@ +5 PRINT "X VALUE", "SINE", "RESOLUTION" +10 READ D +20 LET M = -1 +30 FOR X = 0 TO 3 STEP D +40 IF SIN(X) <= M THEN 80 +50 LET X0 = X +60 LET M = SIN(X) +80 NEXT X +85 PRINT X0, M, D +90 GOTO 10 +100 DATA .1, .01, .001 +110 END diff --git a/ext/ply/example/BASIC/powers.bas b/ext/ply/example/BASIC/powers.bas new file mode 100644 index 000000000..a454dc3e2 --- /dev/null +++ b/ext/ply/example/BASIC/powers.bas @@ -0,0 +1,13 @@ +5 PRINT "THIS PROGRAM COMPUTES AND PRINTS THE NTH POWERS" +6 PRINT "OF THE NUMBERS LESS THAN OR EQUAL TO N FOR VARIOUS" +7 PRINT "N FROM 1 THROUGH 7" +8 PRINT +10 FOR N = 1 TO 7 +15 PRINT "N = "N +20 FOR I = 1 TO N +30 PRINT I^N, +40 NEXT I +50 PRINT +60 PRINT +70 NEXT N +80 END diff --git a/ext/ply/example/BASIC/rand.bas b/ext/ply/example/BASIC/rand.bas new file mode 100644 index 000000000..4ff7a1467 --- /dev/null +++ b/ext/ply/example/BASIC/rand.bas @@ -0,0 +1,4 @@ +10 FOR I = 1 TO 20 +20 PRINT INT(10*RND(0)) +30 NEXT I +40 END diff --git a/ext/ply/example/BASIC/sales.bas b/ext/ply/example/BASIC/sales.bas new file mode 100644 index 000000000..a39aefb76 --- /dev/null +++ b/ext/ply/example/BASIC/sales.bas @@ -0,0 +1,20 @@ +10 FOR I = 1 TO 3 +20 READ P(I) +30 NEXT I +40 FOR I = 1 TO 3 +50 FOR J = 1 TO 5 +60 READ S(I,J) +70 NEXT J +80 NEXT I +90 FOR J = 1 TO 5 +100 LET S = 0 +110 FOR I = 1 TO 3 +120 LET S = S + P(I) * S(I,J) +130 NEXT I +140 PRINT "TOTAL SALES FOR SALESMAN"J, "$"S +150 NEXT J +200 DATA 1.25, 4.30, 2.50 +210 DATA 40, 20, 37, 29, 42 +220 DATA 10, 16, 3, 21, 8 +230 DATA 35, 47, 29, 16, 33 +300 END diff --git a/ext/ply/example/BASIC/sears.bas b/ext/ply/example/BASIC/sears.bas new file mode 100644 index 000000000..5ced3974e --- /dev/null +++ b/ext/ply/example/BASIC/sears.bas @@ -0,0 +1,18 @@ +1 REM :: THIS PROGRAM COMPUTES HOW MANY TIMES YOU HAVE TO FOLD +2 REM :: A PIECE OF PAPER SO THAT IT IS TALLER THAN THE +3 REM :: SEARS TOWER. +4 REM :: S = HEIGHT OF TOWER (METERS) +5 REM :: T = THICKNESS OF PAPER (MILLIMETERS) +10 LET S = 442 +20 LET T = 0.1 +30 REM CONVERT T TO METERS +40 LET T = T * .001 +50 LET F = 1 +60 LET H = T +100 IF H > S THEN 200 +120 LET H = 2 * H +125 LET F = F + 1 +130 GOTO 100 +200 PRINT "NUMBER OF FOLDS ="F +220 PRINT "FINAL HEIGHT ="H +999 END diff --git a/ext/ply/example/BASIC/sqrt1.bas b/ext/ply/example/BASIC/sqrt1.bas new file mode 100644 index 000000000..6673a9152 --- /dev/null +++ b/ext/ply/example/BASIC/sqrt1.bas @@ -0,0 +1,5 @@ +10 LET X = 0 +20 LET X = X + 1 +30 PRINT X, SQR(X) +40 IF X < 100 THEN 20 +50 END diff --git a/ext/ply/example/BASIC/sqrt2.bas b/ext/ply/example/BASIC/sqrt2.bas new file mode 100644 index 000000000..862d85ef2 --- /dev/null +++ b/ext/ply/example/BASIC/sqrt2.bas @@ -0,0 +1,4 @@ +10 FOR X = 1 TO 100 +20 PRINT X, SQR(X) +30 NEXT X +40 END diff --git a/ext/ply/example/GardenSnake/GardenSnake.py b/ext/ply/example/GardenSnake/GardenSnake.py new file mode 100644 index 000000000..ffa550fc6 --- /dev/null +++ b/ext/ply/example/GardenSnake/GardenSnake.py @@ -0,0 +1,709 @@ +# GardenSnake - a parser generator demonstration program +# +# This implements a modified version of a subset of Python: +# - only 'def', 'return' and 'if' statements +# - 'if' only has 'then' clause (no elif nor else) +# - single-quoted strings only, content in raw format +# - numbers are decimal.Decimal instances (not integers or floats) +# - no print statment; use the built-in 'print' function +# - only < > == + - / * implemented (and unary + -) +# - assignment and tuple assignment work +# - no generators of any sort +# - no ... well, no quite a lot + +# Why? I'm thinking about a new indentation-based configuration +# language for a project and wanted to figure out how to do it. Once +# I got that working I needed a way to test it out. My original AST +# was dumb so I decided to target Python's AST and compile it into +# Python code. Plus, it's pretty cool that it only took a day or so +# from sitting down with Ply to having working code. + +# This uses David Beazley's Ply from http://www.dabeaz.com/ply/ + +# This work is hereby released into the Public Domain. To view a copy of +# the public domain dedication, visit +# http://creativecommons.org/licenses/publicdomain/ or send a letter to +# Creative Commons, 543 Howard Street, 5th Floor, San Francisco, +# California, 94105, USA. +# +# Portions of this work are derived from Python's Grammar definition +# and may be covered under the Python copyright and license +# +# Andrew Dalke / Dalke Scientific Software, LLC +# 30 August 2006 / Cape Town, South Africa + +# Changelog: +# 30 August - added link to CC license; removed the "swapcase" encoding + +# Modifications for inclusion in PLY distribution +import sys +sys.path.insert(0,"../..") +from ply import * + +##### Lexer ###### +#import lex +import decimal + +tokens = ( + 'DEF', + 'IF', + 'NAME', + 'NUMBER', # Python decimals + 'STRING', # single quoted strings only; syntax of raw strings + 'LPAR', + 'RPAR', + 'COLON', + 'EQ', + 'ASSIGN', + 'LT', + 'GT', + 'PLUS', + 'MINUS', + 'MULT', + 'DIV', + 'RETURN', + 'WS', + 'NEWLINE', + 'COMMA', + 'SEMICOLON', + 'INDENT', + 'DEDENT', + 'ENDMARKER', + ) + +#t_NUMBER = r'\d+' +# taken from decmial.py but without the leading sign +def t_NUMBER(t): + r"""(\d+(\.\d*)?|\.\d+)([eE][-+]? \d+)?""" + t.value = decimal.Decimal(t.value) + return t + +def t_STRING(t): + r"'([^\\']+|\\'|\\\\)*'" # I think this is right ... + t.value=t.value[1:-1].decode("string-escape") # .swapcase() # for fun + return t + +t_COLON = r':' +t_EQ = r'==' +t_ASSIGN = r'=' +t_LT = r'<' +t_GT = r'>' +t_PLUS = r'\+' +t_MINUS = r'-' +t_MULT = r'\*' +t_DIV = r'/' +t_COMMA = r',' +t_SEMICOLON = r';' + +# Ply nicely documented how to do this. + +RESERVED = { + "def": "DEF", + "if": "IF", + "return": "RETURN", + } + +def t_NAME(t): + r'[a-zA-Z_][a-zA-Z0-9_]*' + t.type = RESERVED.get(t.value, "NAME") + return t + +# Putting this before t_WS let it consume lines with only comments in +# them so the latter code never sees the WS part. Not consuming the +# newline. Needed for "if 1: #comment" +def t_comment(t): + r"[ ]*\043[^\n]*" # \043 is '#' + pass + + +# Whitespace +def t_WS(t): + r' [ ]+ ' + if t.lexer.at_line_start and t.lexer.paren_count == 0: + return t + +# Don't generate newline tokens when inside of parenthesis, eg +# a = (1, +# 2, 3) +def t_newline(t): + r'\n+' + t.lexer.lineno += len(t.value) + t.type = "NEWLINE" + if t.lexer.paren_count == 0: + return t + +def t_LPAR(t): + r'\(' + t.lexer.paren_count += 1 + return t + +def t_RPAR(t): + r'\)' + # check for underflow? should be the job of the parser + t.lexer.paren_count -= 1 + return t + + +def t_error(t): + raise SyntaxError("Unknown symbol %r" % (t.value[0],)) + print "Skipping", repr(t.value[0]) + t.lexer.skip(1) + +## I implemented INDENT / DEDENT generation as a post-processing filter + +# The original lex token stream contains WS and NEWLINE characters. +# WS will only occur before any other tokens on a line. + +# I have three filters. One tags tokens by adding two attributes. +# "must_indent" is True if the token must be indented from the +# previous code. The other is "at_line_start" which is True for WS +# and the first non-WS/non-NEWLINE on a line. It flags the check so +# see if the new line has changed indication level. + +# Python's syntax has three INDENT states +# 0) no colon hence no need to indent +# 1) "if 1: go()" - simple statements have a COLON but no need for an indent +# 2) "if 1:\n go()" - complex statements have a COLON NEWLINE and must indent +NO_INDENT = 0 +MAY_INDENT = 1 +MUST_INDENT = 2 + +# only care about whitespace at the start of a line +def track_tokens_filter(lexer, tokens): + lexer.at_line_start = at_line_start = True + indent = NO_INDENT + saw_colon = False + for token in tokens: + token.at_line_start = at_line_start + + if token.type == "COLON": + at_line_start = False + indent = MAY_INDENT + token.must_indent = False + + elif token.type == "NEWLINE": + at_line_start = True + if indent == MAY_INDENT: + indent = MUST_INDENT + token.must_indent = False + + elif token.type == "WS": + assert token.at_line_start == True + at_line_start = True + token.must_indent = False + + else: + # A real token; only indent after COLON NEWLINE + if indent == MUST_INDENT: + token.must_indent = True + else: + token.must_indent = False + at_line_start = False + indent = NO_INDENT + + yield token + lexer.at_line_start = at_line_start + +def _new_token(type, lineno): + tok = lex.LexToken() + tok.type = type + tok.value = None + tok.lineno = lineno + return tok + +# Synthesize a DEDENT tag +def DEDENT(lineno): + return _new_token("DEDENT", lineno) + +# Synthesize an INDENT tag +def INDENT(lineno): + return _new_token("INDENT", lineno) + + +# Track the indentation level and emit the right INDENT / DEDENT events. +def indentation_filter(tokens): + # A stack of indentation levels; will never pop item 0 + levels = [0] + token = None + depth = 0 + prev_was_ws = False + for token in tokens: +## if 1: +## print "Process", token, +## if token.at_line_start: +## print "at_line_start", +## if token.must_indent: +## print "must_indent", +## print + + # WS only occurs at the start of the line + # There may be WS followed by NEWLINE so + # only track the depth here. Don't indent/dedent + # until there's something real. + if token.type == "WS": + assert depth == 0 + depth = len(token.value) + prev_was_ws = True + # WS tokens are never passed to the parser + continue + + if token.type == "NEWLINE": + depth = 0 + if prev_was_ws or token.at_line_start: + # ignore blank lines + continue + # pass the other cases on through + yield token + continue + + # then it must be a real token (not WS, not NEWLINE) + # which can affect the indentation level + + prev_was_ws = False + if token.must_indent: + # The current depth must be larger than the previous level + if not (depth > levels[-1]): + raise IndentationError("expected an indented block") + + levels.append(depth) + yield INDENT(token.lineno) + + elif token.at_line_start: + # Must be on the same level or one of the previous levels + if depth == levels[-1]: + # At the same level + pass + elif depth > levels[-1]: + raise IndentationError("indentation increase but not in new block") + else: + # Back up; but only if it matches a previous level + try: + i = levels.index(depth) + except ValueError: + raise IndentationError("inconsistent indentation") + for _ in range(i+1, len(levels)): + yield DEDENT(token.lineno) + levels.pop() + + yield token + + ### Finished processing ### + + # Must dedent any remaining levels + if len(levels) > 1: + assert token is not None + for _ in range(1, len(levels)): + yield DEDENT(token.lineno) + + +# The top-level filter adds an ENDMARKER, if requested. +# Python's grammar uses it. +def filter(lexer, add_endmarker = True): + token = None + tokens = iter(lexer.token, None) + tokens = track_tokens_filter(lexer, tokens) + for token in indentation_filter(tokens): + yield token + + if add_endmarker: + lineno = 1 + if token is not None: + lineno = token.lineno + yield _new_token("ENDMARKER", lineno) + +# Combine Ply and my filters into a new lexer + +class IndentLexer(object): + def __init__(self, debug=0, optimize=0, lextab='lextab', reflags=0): + self.lexer = lex.lex(debug=debug, optimize=optimize, lextab=lextab, reflags=reflags) + self.token_stream = None + def input(self, s, add_endmarker=True): + self.lexer.paren_count = 0 + self.lexer.input(s) + self.token_stream = filter(self.lexer, add_endmarker) + def token(self): + try: + return self.token_stream.next() + except StopIteration: + return None + +########## Parser (tokens -> AST) ###### + +# also part of Ply +#import yacc + +# I use the Python AST +from compiler import ast + +# Helper function +def Assign(left, right): + names = [] + if isinstance(left, ast.Name): + # Single assignment on left + return ast.Assign([ast.AssName(left.name, 'OP_ASSIGN')], right) + elif isinstance(left, ast.Tuple): + # List of things - make sure they are Name nodes + names = [] + for child in left.getChildren(): + if not isinstance(child, ast.Name): + raise SyntaxError("that assignment not supported") + names.append(child.name) + ass_list = [ast.AssName(name, 'OP_ASSIGN') for name in names] + return ast.Assign([ast.AssTuple(ass_list)], right) + else: + raise SyntaxError("Can't do that yet") + + +# The grammar comments come from Python's Grammar/Grammar file + +## NB: compound_stmt in single_input is followed by extra NEWLINE! +# file_input: (NEWLINE | stmt)* ENDMARKER +def p_file_input_end(p): + """file_input_end : file_input ENDMARKER""" + p[0] = ast.Stmt(p[1]) +def p_file_input(p): + """file_input : file_input NEWLINE + | file_input stmt + | NEWLINE + | stmt""" + if isinstance(p[len(p)-1], basestring): + if len(p) == 3: + p[0] = p[1] + else: + p[0] = [] # p == 2 --> only a blank line + else: + if len(p) == 3: + p[0] = p[1] + p[2] + else: + p[0] = p[1] + + +# funcdef: [decorators] 'def' NAME parameters ':' suite +# ignoring decorators +def p_funcdef(p): + "funcdef : DEF NAME parameters COLON suite" + p[0] = ast.Function(None, p[2], tuple(p[3]), (), 0, None, p[5]) + +# parameters: '(' [varargslist] ')' +def p_parameters(p): + """parameters : LPAR RPAR + | LPAR varargslist RPAR""" + if len(p) == 3: + p[0] = [] + else: + p[0] = p[2] + + +# varargslist: (fpdef ['=' test] ',')* ('*' NAME [',' '**' NAME] | '**' NAME) | +# highly simplified +def p_varargslist(p): + """varargslist : varargslist COMMA NAME + | NAME""" + if len(p) == 4: + p[0] = p[1] + p[3] + else: + p[0] = [p[1]] + +# stmt: simple_stmt | compound_stmt +def p_stmt_simple(p): + """stmt : simple_stmt""" + # simple_stmt is a list + p[0] = p[1] + +def p_stmt_compound(p): + """stmt : compound_stmt""" + p[0] = [p[1]] + +# simple_stmt: small_stmt (';' small_stmt)* [';'] NEWLINE +def p_simple_stmt(p): + """simple_stmt : small_stmts NEWLINE + | small_stmts SEMICOLON NEWLINE""" + p[0] = p[1] + +def p_small_stmts(p): + """small_stmts : small_stmts SEMICOLON small_stmt + | small_stmt""" + if len(p) == 4: + p[0] = p[1] + [p[3]] + else: + p[0] = [p[1]] + +# small_stmt: expr_stmt | print_stmt | del_stmt | pass_stmt | flow_stmt | +# import_stmt | global_stmt | exec_stmt | assert_stmt +def p_small_stmt(p): + """small_stmt : flow_stmt + | expr_stmt""" + p[0] = p[1] + +# expr_stmt: testlist (augassign (yield_expr|testlist) | +# ('=' (yield_expr|testlist))*) +# augassign: ('+=' | '-=' | '*=' | '/=' | '%=' | '&=' | '|=' | '^=' | +# '<<=' | '>>=' | '**=' | '//=') +def p_expr_stmt(p): + """expr_stmt : testlist ASSIGN testlist + | testlist """ + if len(p) == 2: + # a list of expressions + p[0] = ast.Discard(p[1]) + else: + p[0] = Assign(p[1], p[3]) + +def p_flow_stmt(p): + "flow_stmt : return_stmt" + p[0] = p[1] + +# return_stmt: 'return' [testlist] +def p_return_stmt(p): + "return_stmt : RETURN testlist" + p[0] = ast.Return(p[2]) + + +def p_compound_stmt(p): + """compound_stmt : if_stmt + | funcdef""" + p[0] = p[1] + +def p_if_stmt(p): + 'if_stmt : IF test COLON suite' + p[0] = ast.If([(p[2], p[4])], None) + +def p_suite(p): + """suite : simple_stmt + | NEWLINE INDENT stmts DEDENT""" + if len(p) == 2: + p[0] = ast.Stmt(p[1]) + else: + p[0] = ast.Stmt(p[3]) + + +def p_stmts(p): + """stmts : stmts stmt + | stmt""" + if len(p) == 3: + p[0] = p[1] + p[2] + else: + p[0] = p[1] + +## No using Python's approach because Ply supports precedence + +# comparison: expr (comp_op expr)* +# arith_expr: term (('+'|'-') term)* +# term: factor (('*'|'/'|'%'|'//') factor)* +# factor: ('+'|'-'|'~') factor | power +# comp_op: '<'|'>'|'=='|'>='|'<='|'<>'|'!='|'in'|'not' 'in'|'is'|'is' 'not' + +def make_lt_compare((left, right)): + return ast.Compare(left, [('<', right),]) +def make_gt_compare((left, right)): + return ast.Compare(left, [('>', right),]) +def make_eq_compare((left, right)): + return ast.Compare(left, [('==', right),]) + + +binary_ops = { + "+": ast.Add, + "-": ast.Sub, + "*": ast.Mul, + "/": ast.Div, + "<": make_lt_compare, + ">": make_gt_compare, + "==": make_eq_compare, +} +unary_ops = { + "+": ast.UnaryAdd, + "-": ast.UnarySub, + } +precedence = ( + ("left", "EQ", "GT", "LT"), + ("left", "PLUS", "MINUS"), + ("left", "MULT", "DIV"), + ) + +def p_comparison(p): + """comparison : comparison PLUS comparison + | comparison MINUS comparison + | comparison MULT comparison + | comparison DIV comparison + | comparison LT comparison + | comparison EQ comparison + | comparison GT comparison + | PLUS comparison + | MINUS comparison + | power""" + if len(p) == 4: + p[0] = binary_ops[p[2]]((p[1], p[3])) + elif len(p) == 3: + p[0] = unary_ops[p[1]](p[2]) + else: + p[0] = p[1] + +# power: atom trailer* ['**' factor] +# trailers enables function calls. I only allow one level of calls +# so this is 'trailer' +def p_power(p): + """power : atom + | atom trailer""" + if len(p) == 2: + p[0] = p[1] + else: + if p[2][0] == "CALL": + p[0] = ast.CallFunc(p[1], p[2][1], None, None) + else: + raise AssertionError("not implemented") + +def p_atom_name(p): + """atom : NAME""" + p[0] = ast.Name(p[1]) + +def p_atom_number(p): + """atom : NUMBER + | STRING""" + p[0] = ast.Const(p[1]) + +def p_atom_tuple(p): + """atom : LPAR testlist RPAR""" + p[0] = p[2] + +# trailer: '(' [arglist] ')' | '[' subscriptlist ']' | '.' NAME +def p_trailer(p): + "trailer : LPAR arglist RPAR" + p[0] = ("CALL", p[2]) + +# testlist: test (',' test)* [','] +# Contains shift/reduce error +def p_testlist(p): + """testlist : testlist_multi COMMA + | testlist_multi """ + if len(p) == 2: + p[0] = p[1] + else: + # May need to promote singleton to tuple + if isinstance(p[1], list): + p[0] = p[1] + else: + p[0] = [p[1]] + # Convert into a tuple? + if isinstance(p[0], list): + p[0] = ast.Tuple(p[0]) + +def p_testlist_multi(p): + """testlist_multi : testlist_multi COMMA test + | test""" + if len(p) == 2: + # singleton + p[0] = p[1] + else: + if isinstance(p[1], list): + p[0] = p[1] + [p[3]] + else: + # singleton -> tuple + p[0] = [p[1], p[3]] + + +# test: or_test ['if' or_test 'else' test] | lambdef +# as I don't support 'and', 'or', and 'not' this works down to 'comparison' +def p_test(p): + "test : comparison" + p[0] = p[1] + + + +# arglist: (argument ',')* (argument [',']| '*' test [',' '**' test] | '**' test) +# XXX INCOMPLETE: this doesn't allow the trailing comma +def p_arglist(p): + """arglist : arglist COMMA argument + | argument""" + if len(p) == 4: + p[0] = p[1] + [p[3]] + else: + p[0] = [p[1]] + +# argument: test [gen_for] | test '=' test # Really [keyword '='] test +def p_argument(p): + "argument : test" + p[0] = p[1] + +def p_error(p): + #print "Error!", repr(p) + raise SyntaxError(p) + + +class GardenSnakeParser(object): + def __init__(self, lexer = None): + if lexer is None: + lexer = IndentLexer() + self.lexer = lexer + self.parser = yacc.yacc(start="file_input_end") + + def parse(self, code): + self.lexer.input(code) + result = self.parser.parse(lexer = self.lexer) + return ast.Module(None, result) + + +###### Code generation ###### + +from compiler import misc, syntax, pycodegen + +class GardenSnakeCompiler(object): + def __init__(self): + self.parser = GardenSnakeParser() + def compile(self, code, filename="<string>"): + tree = self.parser.parse(code) + #print tree + misc.set_filename(filename, tree) + syntax.check(tree) + gen = pycodegen.ModuleCodeGenerator(tree) + code = gen.getCode() + return code + +####### Test code ####### + +compile = GardenSnakeCompiler().compile + +code = r""" + +print('LET\'S TRY THIS \\OUT') + +#Comment here +def x(a): + print('called with',a) + if a == 1: + return 2 + if a*2 > 10: return 999 / 4 + # Another comment here + + return a+2*3 + +ints = (1, 2, + 3, 4, +5) +print('mutiline-expression', ints) + +t = 4+1/3*2+6*(9-5+1) +print('predence test; should be 34+2/3:', t, t==(34+2/3)) + +print('numbers', 1,2,3,4,5) +if 1: + 8 + a=9 + print(x(a)) + +print(x(1)) +print(x(2)) +print(x(8),'3') +print('this is decimal', 1/5) +print('BIG DECIMAL', 1.234567891234567e12345) + +""" + +# Set up the GardenSnake run-time environment +def print_(*args): + print "-->", " ".join(map(str,args)) + +globals()["print"] = print_ + +compiled_code = compile(code) + +exec compiled_code in globals() +print "Done" diff --git a/ext/ply/example/GardenSnake/README b/ext/ply/example/GardenSnake/README new file mode 100644 index 000000000..4d8be2db0 --- /dev/null +++ b/ext/ply/example/GardenSnake/README @@ -0,0 +1,5 @@ +This example is Andrew Dalke's GardenSnake language. It shows how to process an +indentation-like language like Python. Further details can be found here: + +http://dalkescientific.com/writings/diary/archive/2006/08/30/gardensnake_language.html + diff --git a/ext/ply/example/README b/ext/ply/example/README new file mode 100644 index 000000000..63519b557 --- /dev/null +++ b/ext/ply/example/README @@ -0,0 +1,10 @@ +Simple examples: + calc - Simple calculator + classcalc - Simple calculate defined as a class + +Complex examples + ansic - ANSI C grammar from K&R + BASIC - A small BASIC interpreter + GardenSnake - A simple python-like language + yply - Converts Unix yacc files to PLY programs. + diff --git a/ext/ply/example/ansic/clex.py b/ext/ply/example/ansic/clex.py index afd995208..12441a60b 100644 --- a/ext/ply/example/ansic/clex.py +++ b/ext/ply/example/ansic/clex.py @@ -4,7 +4,10 @@ # A lexer for ANSI C. # ---------------------------------------------------------------------- -import lex +import sys +sys.path.insert(0,"../..") + +import ply.lex as lex # Reserved words reserved = ( @@ -53,7 +56,7 @@ t_ignore = ' \t\x0c' # Newlines def t_NEWLINE(t): r'\n+' - t.lineno += t.value.count("\n") + t.lexer.lineno += t.value.count("\n") # Operators t_PLUS = r'\+' @@ -64,7 +67,7 @@ t_MOD = r'%' t_OR = r'\|' t_AND = r'&' t_NOT = r'~' -t_XOR = r'^' +t_XOR = r'\^' t_LSHIFT = r'<<' t_RSHIFT = r'>>' t_LOR = r'\|\|' @@ -149,7 +152,7 @@ def t_preprocessor(t): def t_error(t): print "Illegal character %s" % repr(t.value[0]) - t.skip(1) + t.lexer.skip(1) lexer = lex.lex(optimize=1) if __name__ == "__main__": diff --git a/ext/ply/example/ansic/cparse.py b/ext/ply/example/ansic/cparse.py index ddfd5c72b..d474378c8 100644 --- a/ext/ply/example/ansic/cparse.py +++ b/ext/ply/example/ansic/cparse.py @@ -4,8 +4,9 @@ # Simple parser for ANSI C. Based on the grammar in K&R, 2nd Ed. # ----------------------------------------------------------------------------- -import yacc +import sys import clex +import ply.yacc as yacc # Get the token map tokens = clex.tokens @@ -852,7 +853,10 @@ def p_error(t): import profile # Build the grammar -profile.run("yacc.yacc()") + +yacc.yacc(method='LALR') + +#profile.run("yacc.yacc(method='LALR')") diff --git a/ext/ply/example/calc/calc.py b/ext/ply/example/calc/calc.py index aeb23c246..987ce8019 100644 --- a/ext/ply/example/calc/calc.py +++ b/ext/ply/example/calc/calc.py @@ -5,21 +5,17 @@ # "Lex and Yacc", p. 63. # ----------------------------------------------------------------------------- +import sys +sys.path.insert(0,"../..") + tokens = ( 'NAME','NUMBER', - 'PLUS','MINUS','TIMES','DIVIDE','EQUALS', - 'LPAREN','RPAREN', ) +literals = ['=','+','-','*','/', '(',')'] + # Tokens -t_PLUS = r'\+' -t_MINUS = r'-' -t_TIMES = r'\*' -t_DIVIDE = r'/' -t_EQUALS = r'=' -t_LPAREN = r'\(' -t_RPAREN = r'\)' t_NAME = r'[a-zA-Z_][a-zA-Z0-9_]*' def t_NUMBER(t): @@ -35,69 +31,69 @@ t_ignore = " \t" def t_newline(t): r'\n+' - t.lineno += t.value.count("\n") + t.lexer.lineno += t.value.count("\n") def t_error(t): print "Illegal character '%s'" % t.value[0] - t.skip(1) + t.lexer.skip(1) # Build the lexer -import lex +import ply.lex as lex lex.lex() # Parsing rules precedence = ( - ('left','PLUS','MINUS'), - ('left','TIMES','DIVIDE'), + ('left','+','-'), + ('left','*','/'), ('right','UMINUS'), ) # dictionary of names names = { } -def p_statement_assign(t): - 'statement : NAME EQUALS expression' - names[t[1]] = t[3] +def p_statement_assign(p): + 'statement : NAME "=" expression' + names[p[1]] = p[3] -def p_statement_expr(t): +def p_statement_expr(p): 'statement : expression' - print t[1] - -def p_expression_binop(t): - '''expression : expression PLUS expression - | expression MINUS expression - | expression TIMES expression - | expression DIVIDE expression''' - if t[2] == '+' : t[0] = t[1] + t[3] - elif t[2] == '-': t[0] = t[1] - t[3] - elif t[2] == '*': t[0] = t[1] * t[3] - elif t[2] == '/': t[0] = t[1] / t[3] - -def p_expression_uminus(t): - 'expression : MINUS expression %prec UMINUS' - t[0] = -t[2] - -def p_expression_group(t): - 'expression : LPAREN expression RPAREN' - t[0] = t[2] - -def p_expression_number(t): - 'expression : NUMBER' - t[0] = t[1] - -def p_expression_name(t): - 'expression : NAME' + print p[1] + +def p_expression_binop(p): + '''expression : expression '+' expression + | expression '-' expression + | expression '*' expression + | expression '/' expression''' + if p[2] == '+' : p[0] = p[1] + p[3] + elif p[2] == '-': p[0] = p[1] - p[3] + elif p[2] == '*': p[0] = p[1] * p[3] + elif p[2] == '/': p[0] = p[1] / p[3] + +def p_expression_uminus(p): + "expression : '-' expression %prec UMINUS" + p[0] = -p[2] + +def p_expression_group(p): + "expression : '(' expression ')'" + p[0] = p[2] + +def p_expression_number(p): + "expression : NUMBER" + p[0] = p[1] + +def p_expression_name(p): + "expression : NAME" try: - t[0] = names[t[1]] + p[0] = names[p[1]] except LookupError: - print "Undefined name '%s'" % t[1] - t[0] = 0 + print "Undefined name '%s'" % p[1] + p[0] = 0 -def p_error(t): - print "Syntax error at '%s'" % t.value +def p_error(p): + print "Syntax error at '%s'" % p.value -import yacc +import ply.yacc as yacc yacc.yacc() while 1: @@ -105,4 +101,5 @@ while 1: s = raw_input('calc > ') except EOFError: break + if not s: continue yacc.parse(s) diff --git a/ext/ply/example/classcalc/calc.py b/ext/ply/example/classcalc/calc.py new file mode 100644 index 000000000..b2f3f70f1 --- /dev/null +++ b/ext/ply/example/classcalc/calc.py @@ -0,0 +1,152 @@ +#!/usr/bin/env python + +# ----------------------------------------------------------------------------- +# calc.py +# +# A simple calculator with variables. This is from O'Reilly's +# "Lex and Yacc", p. 63. +# +# Class-based example contributed to PLY by David McNab +# ----------------------------------------------------------------------------- + +import sys +sys.path.insert(0,"../..") + +import readline +import ply.lex as lex +import ply.yacc as yacc +import os + +class Parser: + """ + Base class for a lexer/parser that has the rules defined as methods + """ + tokens = () + precedence = () + + def __init__(self, **kw): + self.debug = kw.get('debug', 0) + self.names = { } + try: + modname = os.path.split(os.path.splitext(__file__)[0])[1] + "_" + self.__class__.__name__ + except: + modname = "parser"+"_"+self.__class__.__name__ + self.debugfile = modname + ".dbg" + self.tabmodule = modname + "_" + "parsetab" + #print self.debugfile, self.tabmodule + + # Build the lexer and parser + lex.lex(module=self, debug=self.debug) + yacc.yacc(module=self, + debug=self.debug, + debugfile=self.debugfile, + tabmodule=self.tabmodule) + + def run(self): + while 1: + try: + s = raw_input('calc > ') + except EOFError: + break + if not s: continue + yacc.parse(s) + + +class Calc(Parser): + + tokens = ( + 'NAME','NUMBER', + 'PLUS','MINUS','EXP', 'TIMES','DIVIDE','EQUALS', + 'LPAREN','RPAREN', + ) + + # Tokens + + t_PLUS = r'\+' + t_MINUS = r'-' + t_EXP = r'\*\*' + t_TIMES = r'\*' + t_DIVIDE = r'/' + t_EQUALS = r'=' + t_LPAREN = r'\(' + t_RPAREN = r'\)' + t_NAME = r'[a-zA-Z_][a-zA-Z0-9_]*' + + def t_NUMBER(self, t): + r'\d+' + try: + t.value = int(t.value) + except ValueError: + print "Integer value too large", t.value + t.value = 0 + #print "parsed number %s" % repr(t.value) + return t + + t_ignore = " \t" + + def t_newline(self, t): + r'\n+' + t.lexer.lineno += t.value.count("\n") + + def t_error(self, t): + print "Illegal character '%s'" % t.value[0] + t.lexer.skip(1) + + # Parsing rules + + precedence = ( + ('left','PLUS','MINUS'), + ('left','TIMES','DIVIDE'), + ('left', 'EXP'), + ('right','UMINUS'), + ) + + def p_statement_assign(self, p): + 'statement : NAME EQUALS expression' + self.names[p[1]] = p[3] + + def p_statement_expr(self, p): + 'statement : expression' + print p[1] + + def p_expression_binop(self, p): + """ + expression : expression PLUS expression + | expression MINUS expression + | expression TIMES expression + | expression DIVIDE expression + | expression EXP expression + """ + #print [repr(p[i]) for i in range(0,4)] + if p[2] == '+' : p[0] = p[1] + p[3] + elif p[2] == '-': p[0] = p[1] - p[3] + elif p[2] == '*': p[0] = p[1] * p[3] + elif p[2] == '/': p[0] = p[1] / p[3] + elif p[2] == '**': p[0] = p[1] ** p[3] + + def p_expression_uminus(self, p): + 'expression : MINUS expression %prec UMINUS' + p[0] = -p[2] + + def p_expression_group(self, p): + 'expression : LPAREN expression RPAREN' + p[0] = p[2] + + def p_expression_number(self, p): + 'expression : NUMBER' + p[0] = p[1] + + def p_expression_name(self, p): + 'expression : NAME' + try: + p[0] = self.names[p[1]] + except LookupError: + print "Undefined name '%s'" % p[1] + p[0] = 0 + + def p_error(self, p): + print "Syntax error at '%s'" % p.value + +if __name__ == '__main__': + calc = Calc() + calc.run() diff --git a/ext/ply/example/cleanup.sh b/ext/ply/example/cleanup.sh new file mode 100644 index 000000000..3e115f41c --- /dev/null +++ b/ext/ply/example/cleanup.sh @@ -0,0 +1,2 @@ +#!/bin/sh +rm -f */*.pyc */parsetab.py */parser.out */*~ */*.class diff --git a/ext/ply/example/hedit/hedit.py b/ext/ply/example/hedit/hedit.py index f00427bf5..494f4fde5 100644 --- a/ext/ply/example/hedit/hedit.py +++ b/ext/ply/example/hedit/hedit.py @@ -14,6 +14,10 @@ # such tokens # ----------------------------------------------------------------------------- +import sys +sys.path.insert(0,"../..") + + tokens = ( 'H_EDIT_DESCRIPTOR', ) @@ -34,10 +38,10 @@ def t_H_EDIT_DESCRIPTOR(t): def t_error(t): print "Illegal character '%s'" % t.value[0] - t.skip(1) + t.lexer.skip(1) # Build the lexer -import lex +import ply.lex as lex lex.lex() lex.runmain() diff --git a/ext/ply/example/newclasscalc/calc.py b/ext/ply/example/newclasscalc/calc.py new file mode 100644 index 000000000..7f29bc821 --- /dev/null +++ b/ext/ply/example/newclasscalc/calc.py @@ -0,0 +1,155 @@ +#!/usr/bin/env python + +# ----------------------------------------------------------------------------- +# calc.py +# +# A simple calculator with variables. This is from O'Reilly's +# "Lex and Yacc", p. 63. +# +# Class-based example contributed to PLY by David McNab. +# +# Modified to use new-style classes. Test case. +# ----------------------------------------------------------------------------- + +import sys +sys.path.insert(0,"../..") + +import readline +import ply.lex as lex +import ply.yacc as yacc +import os + +class Parser(object): + """ + Base class for a lexer/parser that has the rules defined as methods + """ + tokens = () + precedence = () + + + def __init__(self, **kw): + self.debug = kw.get('debug', 0) + self.names = { } + try: + modname = os.path.split(os.path.splitext(__file__)[0])[1] + "_" + self.__class__.__name__ + except: + modname = "parser"+"_"+self.__class__.__name__ + self.debugfile = modname + ".dbg" + self.tabmodule = modname + "_" + "parsetab" + #print self.debugfile, self.tabmodule + + # Build the lexer and parser + lex.lex(module=self, debug=self.debug) + yacc.yacc(module=self, + debug=self.debug, + debugfile=self.debugfile, + tabmodule=self.tabmodule) + + def run(self): + while 1: + try: + s = raw_input('calc > ') + except EOFError: + break + if not s: continue + yacc.parse(s) + + +class Calc(Parser): + + tokens = ( + 'NAME','NUMBER', + 'PLUS','MINUS','EXP', 'TIMES','DIVIDE','EQUALS', + 'LPAREN','RPAREN', + ) + + # Tokens + + t_PLUS = r'\+' + t_MINUS = r'-' + t_EXP = r'\*\*' + t_TIMES = r'\*' + t_DIVIDE = r'/' + t_EQUALS = r'=' + t_LPAREN = r'\(' + t_RPAREN = r'\)' + t_NAME = r'[a-zA-Z_][a-zA-Z0-9_]*' + + def t_NUMBER(self, t): + r'\d+' + try: + t.value = int(t.value) + except ValueError: + print "Integer value too large", t.value + t.value = 0 + #print "parsed number %s" % repr(t.value) + return t + + t_ignore = " \t" + + def t_newline(self, t): + r'\n+' + t.lexer.lineno += t.value.count("\n") + + def t_error(self, t): + print "Illegal character '%s'" % t.value[0] + t.lexer.skip(1) + + # Parsing rules + + precedence = ( + ('left','PLUS','MINUS'), + ('left','TIMES','DIVIDE'), + ('left', 'EXP'), + ('right','UMINUS'), + ) + + def p_statement_assign(self, p): + 'statement : NAME EQUALS expression' + self.names[p[1]] = p[3] + + def p_statement_expr(self, p): + 'statement : expression' + print p[1] + + def p_expression_binop(self, p): + """ + expression : expression PLUS expression + | expression MINUS expression + | expression TIMES expression + | expression DIVIDE expression + | expression EXP expression + """ + #print [repr(p[i]) for i in range(0,4)] + if p[2] == '+' : p[0] = p[1] + p[3] + elif p[2] == '-': p[0] = p[1] - p[3] + elif p[2] == '*': p[0] = p[1] * p[3] + elif p[2] == '/': p[0] = p[1] / p[3] + elif p[2] == '**': p[0] = p[1] ** p[3] + + def p_expression_uminus(self, p): + 'expression : MINUS expression %prec UMINUS' + p[0] = -p[2] + + def p_expression_group(self, p): + 'expression : LPAREN expression RPAREN' + p[0] = p[2] + + def p_expression_number(self, p): + 'expression : NUMBER' + p[0] = p[1] + + def p_expression_name(self, p): + 'expression : NAME' + try: + p[0] = self.names[p[1]] + except LookupError: + print "Undefined name '%s'" % p[1] + p[0] = 0 + + def p_error(self, p): + print "Syntax error at '%s'" % p.value + +if __name__ == '__main__': + calc = Calc() + calc.run() diff --git a/ext/ply/example/optcalc/calc.py b/ext/ply/example/optcalc/calc.py index fa66cda5b..3a0ee6c9b 100644 --- a/ext/ply/example/optcalc/calc.py +++ b/ext/ply/example/optcalc/calc.py @@ -5,6 +5,9 @@ # "Lex and Yacc", p. 63. # ----------------------------------------------------------------------------- +import sys +sys.path.insert(0,"../..") + tokens = ( 'NAME','NUMBER', 'PLUS','MINUS','TIMES','DIVIDE','EQUALS', @@ -35,14 +38,14 @@ t_ignore = " \t" def t_newline(t): r'\n+' - t.lineno += t.value.count("\n") + t.lexer.lineno += t.value.count("\n") def t_error(t): print "Illegal character '%s'" % t.value[0] - t.skip(1) + t.lexer.skip(1) # Build the lexer -import lex +import ply.lex as lex lex.lex(optimize=1) # Parsing rules @@ -98,7 +101,7 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc +import ply.yacc as yacc yacc.yacc(optimize=1) while 1: diff --git a/ext/ply/example/unicalc/calc.py b/ext/ply/example/unicalc/calc.py new file mode 100644 index 000000000..d1f59f748 --- /dev/null +++ b/ext/ply/example/unicalc/calc.py @@ -0,0 +1,114 @@ +# ----------------------------------------------------------------------------- +# calc.py +# +# A simple calculator with variables. This is from O'Reilly's +# "Lex and Yacc", p. 63. +# +# This example uses unicode strings for tokens, docstrings, and input. +# ----------------------------------------------------------------------------- + +import sys +sys.path.insert(0,"../..") + +tokens = ( + 'NAME','NUMBER', + 'PLUS','MINUS','TIMES','DIVIDE','EQUALS', + 'LPAREN','RPAREN', + ) + +# Tokens + +t_PLUS = ur'\+' +t_MINUS = ur'-' +t_TIMES = ur'\*' +t_DIVIDE = ur'/' +t_EQUALS = ur'=' +t_LPAREN = ur'\(' +t_RPAREN = ur'\)' +t_NAME = ur'[a-zA-Z_][a-zA-Z0-9_]*' + +def t_NUMBER(t): + ur'\d+' + try: + t.value = int(t.value) + except ValueError: + print "Integer value too large", t.value + t.value = 0 + return t + +t_ignore = u" \t" + +def t_newline(t): + ur'\n+' + t.lexer.lineno += t.value.count("\n") + +def t_error(t): + print "Illegal character '%s'" % t.value[0] + t.lexer.skip(1) + +# Build the lexer +import ply.lex as lex +lex.lex() + +# Parsing rules + +precedence = ( + ('left','PLUS','MINUS'), + ('left','TIMES','DIVIDE'), + ('right','UMINUS'), + ) + +# dictionary of names +names = { } + +def p_statement_assign(p): + 'statement : NAME EQUALS expression' + names[p[1]] = p[3] + +def p_statement_expr(p): + 'statement : expression' + print p[1] + +def p_expression_binop(p): + '''expression : expression PLUS expression + | expression MINUS expression + | expression TIMES expression + | expression DIVIDE expression''' + if p[2] == u'+' : p[0] = p[1] + p[3] + elif p[2] == u'-': p[0] = p[1] - p[3] + elif p[2] == u'*': p[0] = p[1] * p[3] + elif p[2] == u'/': p[0] = p[1] / p[3] + +def p_expression_uminus(p): + 'expression : MINUS expression %prec UMINUS' + p[0] = -p[2] + +def p_expression_group(p): + 'expression : LPAREN expression RPAREN' + p[0] = p[2] + +def p_expression_number(p): + 'expression : NUMBER' + p[0] = p[1] + +def p_expression_name(p): + 'expression : NAME' + try: + p[0] = names[p[1]] + except LookupError: + print "Undefined name '%s'" % p[1] + p[0] = 0 + +def p_error(p): + print "Syntax error at '%s'" % p.value + +import ply.yacc as yacc +yacc.yacc() + +while 1: + try: + s = raw_input('calc > ') + except EOFError: + break + if not s: continue + yacc.parse(unicode(s)) diff --git a/ext/ply/example/yply/README b/ext/ply/example/yply/README new file mode 100644 index 000000000..bfadf3643 --- /dev/null +++ b/ext/ply/example/yply/README @@ -0,0 +1,41 @@ +yply.py + +This example implements a program yply.py that converts a UNIX-yacc +specification file into a PLY-compatible program. To use, simply +run it like this: + + % python yply.py [-nocode] inputfile.y >myparser.py + +The output of this program is Python code. In the output, +any C code in the original file is included, but is commented out. +If you use the -nocode option, then all of the C code in the +original file is just discarded. + +To use the resulting grammer with PLY, you'll need to edit the +myparser.py file. Within this file, some stub code is included that +can be used to test the construction of the parsing tables. However, +you'll need to do more editing to make a workable parser. + +Disclaimer: This just an example I threw together in an afternoon. +It might have some bugs. However, it worked when I tried it on +a yacc-specified C++ parser containing 442 rules and 855 parsing +states. + +Comments: + +1. This example does not parse specification files meant for lex/flex. + You'll need to specify the tokenizer on your own. + +2. This example shows a number of interesting PLY features including + + - Parsing of literal text delimited by nested parentheses + - Some interaction between the parser and the lexer. + - Use of literals in the grammar specification + - One pass compilation. The program just emits the result, + there is no intermediate parse tree. + +3. This program could probably be cleaned up and enhanced a lot. + It would be great if someone wanted to work on this (hint). + +-Dave + diff --git a/ext/ply/example/yply/ylex.py b/ext/ply/example/yply/ylex.py new file mode 100644 index 000000000..61bc0c7ef --- /dev/null +++ b/ext/ply/example/yply/ylex.py @@ -0,0 +1,112 @@ +# lexer for yacc-grammars +# +# Author: David Beazley (dave@dabeaz.com) +# Date : October 2, 2006 + +import sys +sys.path.append("../..") + +from ply import * + +tokens = ( + 'LITERAL','SECTION','TOKEN','LEFT','RIGHT','PREC','START','TYPE','NONASSOC','UNION','CODE', + 'ID','QLITERAL','NUMBER', +) + +states = (('code','exclusive'),) + +literals = [ ';', ',', '<', '>', '|',':' ] +t_ignore = ' \t' + +t_TOKEN = r'%token' +t_LEFT = r'%left' +t_RIGHT = r'%right' +t_NONASSOC = r'%nonassoc' +t_PREC = r'%prec' +t_START = r'%start' +t_TYPE = r'%type' +t_UNION = r'%union' +t_ID = r'[a-zA-Z_][a-zA-Z_0-9]*' +t_QLITERAL = r'''(?P<quote>['"]).*?(?P=quote)''' +t_NUMBER = r'\d+' + +def t_SECTION(t): + r'%%' + if getattr(t.lexer,"lastsection",0): + t.value = t.lexer.lexdata[t.lexpos+2:] + t.lexer.lexpos = len(t.lexer.lexdata) + else: + t.lexer.lastsection = 0 + return t + +# Comments +def t_ccomment(t): + r'/\*(.|\n)*?\*/' + t.lineno += t.value.count('\n') + +t_ignore_cppcomment = r'//.*' + +def t_LITERAL(t): + r'%\{(.|\n)*?%\}' + t.lexer.lineno += t.value.count("\n") + return t + +def t_NEWLINE(t): + r'\n' + t.lexer.lineno += 1 + +def t_code(t): + r'\{' + t.lexer.codestart = t.lexpos + t.lexer.level = 1 + t.lexer.begin('code') + +def t_code_ignore_string(t): + r'\"([^\\\n]|(\\.))*?\"' + +def t_code_ignore_char(t): + r'\'([^\\\n]|(\\.))*?\'' + +def t_code_ignore_comment(t): + r'/\*(.|\n)*?\*/' + +def t_code_ignore_cppcom(t): + r'//.*' + +def t_code_lbrace(t): + r'\{' + t.lexer.level += 1 + +def t_code_rbrace(t): + r'\}' + t.lexer.level -= 1 + if t.lexer.level == 0: + t.type = 'CODE' + t.value = t.lexer.lexdata[t.lexer.codestart:t.lexpos+1] + t.lexer.begin('INITIAL') + t.lexer.lineno += t.value.count('\n') + return t + +t_code_ignore_nonspace = r'[^\s\}\'\"\{]+' +t_code_ignore_whitespace = r'\s+' +t_code_ignore = "" + +def t_code_error(t): + raise RuntimeError + +def t_error(t): + print "%d: Illegal character '%s'" % (t.lineno, t.value[0]) + print t.value + t.lexer.skip(1) + +lex.lex() + +if __name__ == '__main__': + lex.runmain() + + + + + + + diff --git a/ext/ply/example/yply/yparse.py b/ext/ply/example/yply/yparse.py new file mode 100644 index 000000000..a4e46bef7 --- /dev/null +++ b/ext/ply/example/yply/yparse.py @@ -0,0 +1,217 @@ +# parser for Unix yacc-based grammars +# +# Author: David Beazley (dave@dabeaz.com) +# Date : October 2, 2006 + +import ylex +tokens = ylex.tokens + +from ply import * + +tokenlist = [] +preclist = [] + +emit_code = 1 + +def p_yacc(p): + '''yacc : defsection rulesection''' + +def p_defsection(p): + '''defsection : definitions SECTION + | SECTION''' + p.lexer.lastsection = 1 + print "tokens = ", repr(tokenlist) + print + print "precedence = ", repr(preclist) + print + print "# -------------- RULES ----------------" + print + +def p_rulesection(p): + '''rulesection : rules SECTION''' + + print "# -------------- RULES END ----------------" + print_code(p[2],0) + +def p_definitions(p): + '''definitions : definitions definition + | definition''' + +def p_definition_literal(p): + '''definition : LITERAL''' + print_code(p[1],0) + +def p_definition_start(p): + '''definition : START ID''' + print "start = '%s'" % p[2] + +def p_definition_token(p): + '''definition : toktype opttype idlist optsemi ''' + for i in p[3]: + if i[0] not in "'\"": + tokenlist.append(i) + if p[1] == '%left': + preclist.append(('left',) + tuple(p[3])) + elif p[1] == '%right': + preclist.append(('right',) + tuple(p[3])) + elif p[1] == '%nonassoc': + preclist.append(('nonassoc',)+ tuple(p[3])) + +def p_toktype(p): + '''toktype : TOKEN + | LEFT + | RIGHT + | NONASSOC''' + p[0] = p[1] + +def p_opttype(p): + '''opttype : '<' ID '>' + | empty''' + +def p_idlist(p): + '''idlist : idlist optcomma tokenid + | tokenid''' + if len(p) == 2: + p[0] = [p[1]] + else: + p[0] = p[1] + p[1].append(p[3]) + +def p_tokenid(p): + '''tokenid : ID + | ID NUMBER + | QLITERAL + | QLITERAL NUMBER''' + p[0] = p[1] + +def p_optsemi(p): + '''optsemi : ';' + | empty''' + +def p_optcomma(p): + '''optcomma : ',' + | empty''' + +def p_definition_type(p): + '''definition : TYPE '<' ID '>' namelist optsemi''' + # type declarations are ignored + +def p_namelist(p): + '''namelist : namelist optcomma ID + | ID''' + +def p_definition_union(p): + '''definition : UNION CODE optsemi''' + # Union declarations are ignored + +def p_rules(p): + '''rules : rules rule + | rule''' + if len(p) == 2: + rule = p[1] + else: + rule = p[2] + + # Print out a Python equivalent of this rule + + embedded = [ ] # Embedded actions (a mess) + embed_count = 0 + + rulename = rule[0] + rulecount = 1 + for r in rule[1]: + # r contains one of the rule possibilities + print "def p_%s_%d(p):" % (rulename,rulecount) + prod = [] + prodcode = "" + for i in range(len(r)): + item = r[i] + if item[0] == '{': # A code block + if i == len(r) - 1: + prodcode = item + break + else: + # an embedded action + embed_name = "_embed%d_%s" % (embed_count,rulename) + prod.append(embed_name) + embedded.append((embed_name,item)) + embed_count += 1 + else: + prod.append(item) + print " '''%s : %s'''" % (rulename, " ".join(prod)) + # Emit code + print_code(prodcode,4) + print + rulecount += 1 + + for e,code in embedded: + print "def p_%s(p):" % e + print " '''%s : '''" % e + print_code(code,4) + print + +def p_rule(p): + '''rule : ID ':' rulelist ';' ''' + p[0] = (p[1],[p[3]]) + +def p_rule2(p): + '''rule : ID ':' rulelist morerules ';' ''' + p[4].insert(0,p[3]) + p[0] = (p[1],p[4]) + +def p_rule_empty(p): + '''rule : ID ':' ';' ''' + p[0] = (p[1],[[]]) + +def p_rule_empty2(p): + '''rule : ID ':' morerules ';' ''' + + p[3].insert(0,[]) + p[0] = (p[1],p[3]) + +def p_morerules(p): + '''morerules : morerules '|' rulelist + | '|' rulelist + | '|' ''' + + if len(p) == 2: + p[0] = [[]] + elif len(p) == 3: + p[0] = [p[2]] + else: + p[0] = p[1] + p[0].append(p[3]) + +# print "morerules", len(p), p[0] + +def p_rulelist(p): + '''rulelist : rulelist ruleitem + | ruleitem''' + + if len(p) == 2: + p[0] = [p[1]] + else: + p[0] = p[1] + p[1].append(p[2]) + +def p_ruleitem(p): + '''ruleitem : ID + | QLITERAL + | CODE + | PREC''' + p[0] = p[1] + +def p_empty(p): + '''empty : ''' + +def p_error(p): + pass + +yacc.yacc(debug=0) + +def print_code(code,indent): + if not emit_code: return + codelines = code.splitlines() + for c in codelines: + print "%s# %s" % (" "*indent,c) + diff --git a/ext/ply/example/yply/yply.py b/ext/ply/example/yply/yply.py new file mode 100644 index 000000000..a4398171e --- /dev/null +++ b/ext/ply/example/yply/yply.py @@ -0,0 +1,53 @@ +#!/usr/local/bin/python +# yply.py +# +# Author: David Beazley (dave@dabeaz.com) +# Date : October 2, 2006 +# +# Converts a UNIX-yacc specification file into a PLY-compatible +# specification. To use, simply do this: +# +# % python yply.py [-nocode] inputfile.y >myparser.py +# +# The output of this program is Python code. In the output, +# any C code in the original file is included, but is commented. +# If you use the -nocode option, then all of the C code in the +# original file is discarded. +# +# Disclaimer: This just an example I threw together in an afternoon. +# It might have some bugs. However, it worked when I tried it on +# a yacc-specified C++ parser containing 442 rules and 855 parsing +# states. +# + +import sys +sys.path.insert(0,"../..") + +import ylex +import yparse + +from ply import * + +if len(sys.argv) == 1: + print "usage : yply.py [-nocode] inputfile" + raise SystemExit + +if len(sys.argv) == 3: + if sys.argv[1] == '-nocode': + yparse.emit_code = 0 + else: + print "Unknown option '%s'" % sys.argv[1] + raise SystemExit + filename = sys.argv[2] +else: + filename = sys.argv[1] + +yacc.parse(open(filename).read()) + +print """ +if __name__ == '__main__': + from ply import * + yacc.yacc() +""" + + diff --git a/ext/ply/lex.py b/ext/ply/lex.py deleted file mode 100644 index 7ad7a394b..000000000 --- a/ext/ply/lex.py +++ /dev/null @@ -1,681 +0,0 @@ -#----------------------------------------------------------------------------- -# ply: lex.py -# -# Author: David M. Beazley (beazley@cs.uchicago.edu) -# Department of Computer Science -# University of Chicago -# Chicago, IL 60637 -# -# Copyright (C) 2001, David M. Beazley -# -# $Header: /home/stever/bk/newmem2/ext/ply/lex.py 1.1 03/06/06 14:53:34-00:00 stever@ $ -# -# This library is free software; you can redistribute it and/or -# modify it under the terms of the GNU Lesser General Public -# License as published by the Free Software Foundation; either -# version 2.1 of the License, or (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# Lesser General Public License for more details. -# -# You should have received a copy of the GNU Lesser General Public -# License along with this library; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -# -# See the file COPYING for a complete copy of the LGPL. -# -# -# This module automatically constructs a lexical analysis module from regular -# expression rules defined in a user-defined module. The idea is essentially the same -# as that used in John Aycock's Spark framework, but the implementation works -# at the module level rather than requiring the use of classes. -# -# This module tries to provide an interface that is closely modeled after -# the traditional lex interface in Unix. It also differs from Spark -# in that: -# -# - It provides more extensive error checking and reporting if -# the user supplies a set of regular expressions that can't -# be compiled or if there is any other kind of a problem in -# the specification. -# -# - The interface is geared towards LALR(1) and LR(1) parser -# generators. That is tokens are generated one at a time -# rather than being generated in advanced all in one step. -# -# There are a few limitations of this module -# -# - The module interface makes it somewhat awkward to support more -# than one lexer at a time. Although somewhat inelegant from a -# design perspective, this is rarely a practical concern for -# most compiler projects. -# -# - The lexer requires that the entire input text be read into -# a string before scanning. I suppose that most machines have -# enough memory to make this a minor issues, but it makes -# the lexer somewhat difficult to use in interactive sessions -# or with streaming data. -# -#----------------------------------------------------------------------------- - -r""" -lex.py - -This module builds lex-like scanners based on regular expression rules. -To use the module, simply write a collection of regular expression rules -and actions like this: - -# lexer.py -import lex - -# Define a list of valid tokens -tokens = ( - 'IDENTIFIER', 'NUMBER', 'PLUS', 'MINUS' - ) - -# Define tokens as functions -def t_IDENTIFIER(t): - r' ([a-zA-Z_](\w|_)* ' - return t - -def t_NUMBER(t): - r' \d+ ' - return t - -# Some simple tokens with no actions -t_PLUS = r'\+' -t_MINUS = r'-' - -# Initialize the lexer -lex.lex() - -The tokens list is required and contains a complete list of all valid -token types that the lexer is allowed to produce. Token types are -restricted to be valid identifiers. This means that 'MINUS' is a valid -token type whereas '-' is not. - -Rules are defined by writing a function with a name of the form -t_rulename. Each rule must accept a single argument which is -a token object generated by the lexer. This token has the following -attributes: - - t.type = type string of the token. This is initially set to the - name of the rule without the leading t_ - t.value = The value of the lexeme. - t.lineno = The value of the line number where the token was encountered - -For example, the t_NUMBER() rule above might be called with the following: - - t.type = 'NUMBER' - t.value = '42' - t.lineno = 3 - -Each rule returns the token object it would like to supply to the -parser. In most cases, the token t is returned with few, if any -modifications. To discard a token for things like whitespace or -comments, simply return nothing. For instance: - -def t_whitespace(t): - r' \s+ ' - pass - -For faster lexing, you can also define this in terms of the ignore set like this: - -t_ignore = ' \t' - -The characters in this string are ignored by the lexer. Use of this feature can speed -up parsing significantly since scanning will immediately proceed to the next token. - -lex requires that the token returned by each rule has an attribute -t.type. Other than this, rules are free to return any kind of token -object that they wish and may construct a new type of token object -from the attributes of t (provided the new object has the required -type attribute). - -If illegal characters are encountered, the scanner executes the -function t_error(t) where t is a token representing the rest of the -string that hasn't been matched. If this function isn't defined, a -LexError exception is raised. The .text attribute of this exception -object contains the part of the string that wasn't matched. - -The t.skip(n) method can be used to skip ahead n characters in the -input stream. This is usually only used in the error handling rule. -For instance, the following rule would print an error message and -continue: - -def t_error(t): - print "Illegal character in input %s" % t.value[0] - t.skip(1) - -Of course, a nice scanner might wish to skip more than one character -if the input looks very corrupted. - -The lex module defines a t.lineno attribute on each token that can be used -to track the current line number in the input. The value of this -variable is not modified by lex so it is up to your lexer module -to correctly update its value depending on the lexical properties -of the input language. To do this, you might write rules such as -the following: - -def t_newline(t): - r' \n+ ' - t.lineno += t.value.count("\n") - -To initialize your lexer so that it can be used, simply call the lex.lex() -function in your rule file. If there are any errors in your -specification, warning messages or an exception will be generated to -alert you to the problem. - -(dave: this needs to be rewritten) -To use the newly constructed lexer from another module, simply do -this: - - import lex - import lexer - plex.input("position = initial + rate*60") - - while 1: - token = plex.token() # Get a token - if not token: break # No more tokens - ... do whatever ... - -Assuming that the module 'lexer' has initialized plex as shown -above, parsing modules can safely import 'plex' without having -to import the rule file or any additional imformation about the -scanner you have defined. -""" - -# ----------------------------------------------------------------------------- - - -__version__ = "1.3" - -import re, types, sys, copy - -# Exception thrown when invalid token encountered and no default -class LexError(Exception): - def __init__(self,message,s): - self.args = (message,) - self.text = s - -# Token class -class LexToken: - def __str__(self): - return "LexToken(%s,%r,%d)" % (self.type,self.value,self.lineno) - def __repr__(self): - return str(self) - def skip(self,n): - try: - self._skipn += n - except AttributeError: - self._skipn = n - -# ----------------------------------------------------------------------------- -# Lexer class -# -# input() - Store a new string in the lexer -# token() - Get the next token -# ----------------------------------------------------------------------------- - -class Lexer: - def __init__(self): - self.lexre = None # Master regular expression - self.lexdata = None # Actual input data (as a string) - self.lexpos = 0 # Current position in input text - self.lexlen = 0 # Length of the input text - self.lexindexfunc = [ ] # Reverse mapping of groups to functions and types - self.lexerrorf = None # Error rule (if any) - self.lextokens = None # List of valid tokens - self.lexignore = None # Ignored characters - self.lineno = 1 # Current line number - self.debug = 0 # Debugging mode - self.optimize = 0 # Optimized mode - self.token = self.errtoken - - def __copy__(self): - c = Lexer() - c.lexre = self.lexre - c.lexdata = self.lexdata - c.lexpos = self.lexpos - c.lexlen = self.lexlen - c.lenindexfunc = self.lexindexfunc - c.lexerrorf = self.lexerrorf - c.lextokens = self.lextokens - c.lexignore = self.lexignore - c.lineno = self.lineno - c.optimize = self.optimize - c.token = c.realtoken - - # ------------------------------------------------------------ - # input() - Push a new string into the lexer - # ------------------------------------------------------------ - def input(self,s): - if not isinstance(s,types.StringType): - raise ValueError, "Expected a string" - self.lexdata = s - self.lexpos = 0 - self.lexlen = len(s) - self.token = self.realtoken - - # Change the token routine to point to realtoken() - global token - if token == self.errtoken: - token = self.token - - # ------------------------------------------------------------ - # errtoken() - Return error if token is called with no data - # ------------------------------------------------------------ - def errtoken(self): - raise RuntimeError, "No input string given with input()" - - # ------------------------------------------------------------ - # token() - Return the next token from the Lexer - # - # Note: This function has been carefully implemented to be as fast - # as possible. Don't make changes unless you really know what - # you are doing - # ------------------------------------------------------------ - def realtoken(self): - # Make local copies of frequently referenced attributes - lexpos = self.lexpos - lexlen = self.lexlen - lexignore = self.lexignore - lexdata = self.lexdata - - while lexpos < lexlen: - # This code provides some short-circuit code for whitespace, tabs, and other ignored characters - if lexdata[lexpos] in lexignore: - lexpos += 1 - continue - - # Look for a regular expression match - m = self.lexre.match(lexdata,lexpos) - if m: - i = m.lastindex - lexpos = m.end() - tok = LexToken() - tok.value = m.group() - tok.lineno = self.lineno - tok.lexer = self - func,tok.type = self.lexindexfunc[i] - if not func: - self.lexpos = lexpos - return tok - - # If token is processed by a function, call it - self.lexpos = lexpos - newtok = func(tok) - self.lineno = tok.lineno # Update line number - - # Every function must return a token, if nothing, we just move to next token - if not newtok: continue - - # Verify type of the token. If not in the token map, raise an error - if not self.optimize: - if not self.lextokens.has_key(newtok.type): - raise LexError, ("%s:%d: Rule '%s' returned an unknown token type '%s'" % ( - func.func_code.co_filename, func.func_code.co_firstlineno, - func.__name__, newtok.type),lexdata[lexpos:]) - - return newtok - - # No match. Call t_error() if defined. - if self.lexerrorf: - tok = LexToken() - tok.value = self.lexdata[lexpos:] - tok.lineno = self.lineno - tok.type = "error" - tok.lexer = self - oldpos = lexpos - newtok = self.lexerrorf(tok) - lexpos += getattr(tok,"_skipn",0) - if oldpos == lexpos: - # Error method didn't change text position at all. This is an error. - self.lexpos = lexpos - raise LexError, ("Scanning error. Illegal character '%s'" % (lexdata[lexpos]), lexdata[lexpos:]) - if not newtok: continue - self.lexpos = lexpos - return newtok - - self.lexpos = lexpos - raise LexError, ("No match found", lexdata[lexpos:]) - - # No more input data - self.lexpos = lexpos + 1 - return None - - -# ----------------------------------------------------------------------------- -# validate_file() -# -# This checks to see if there are duplicated t_rulename() functions or strings -# in the parser input file. This is done using a simple regular expression -# match on each line in the filename. -# ----------------------------------------------------------------------------- - -def validate_file(filename): - import os.path - base,ext = os.path.splitext(filename) - if ext != '.py': return 1 # No idea what the file is. Return OK - - try: - f = open(filename) - lines = f.readlines() - f.close() - except IOError: - return 1 # Oh well - - fre = re.compile(r'\s*def\s+(t_[a-zA-Z_0-9]*)\(') - sre = re.compile(r'\s*(t_[a-zA-Z_0-9]*)\s*=') - counthash = { } - linen = 1 - noerror = 1 - for l in lines: - m = fre.match(l) - if not m: - m = sre.match(l) - if m: - name = m.group(1) - prev = counthash.get(name) - if not prev: - counthash[name] = linen - else: - print "%s:%d: Rule %s redefined. Previously defined on line %d" % (filename,linen,name,prev) - noerror = 0 - linen += 1 - return noerror - -# ----------------------------------------------------------------------------- -# _read_lextab(module) -# -# Reads lexer table from a lextab file instead of using introspection. -# ----------------------------------------------------------------------------- - -def _read_lextab(lexer, fdict, module): - exec "import %s as lextab" % module - lexer.lexre = re.compile(lextab._lexre, re.VERBOSE) - lexer.lexindexfunc = lextab._lextab - for i in range(len(lextab._lextab)): - t = lexer.lexindexfunc[i] - if t: - if t[0]: - lexer.lexindexfunc[i] = (fdict[t[0]],t[1]) - lexer.lextokens = lextab._lextokens - lexer.lexignore = lextab._lexignore - if lextab._lexerrorf: - lexer.lexerrorf = fdict[lextab._lexerrorf] - -# ----------------------------------------------------------------------------- -# lex(module) -# -# Build all of the regular expression rules from definitions in the supplied module -# ----------------------------------------------------------------------------- -def lex(module=None,debug=0,optimize=0,lextab="lextab"): - ldict = None - regex = "" - error = 0 - files = { } - lexer = Lexer() - lexer.debug = debug - lexer.optimize = optimize - global token,input - - if module: - if not isinstance(module, types.ModuleType): - raise ValueError,"Expected a module" - - ldict = module.__dict__ - - else: - # No module given. We might be able to get information from the caller. - try: - raise RuntimeError - except RuntimeError: - e,b,t = sys.exc_info() - f = t.tb_frame - f = f.f_back # Walk out to our calling function - ldict = f.f_globals # Grab its globals dictionary - - if optimize and lextab: - try: - _read_lextab(lexer,ldict, lextab) - if not lexer.lexignore: lexer.lexignore = "" - token = lexer.token - input = lexer.input - return lexer - - except ImportError: - pass - - # Get the tokens map - tokens = ldict.get("tokens",None) - if not tokens: - raise SyntaxError,"lex: module does not define 'tokens'" - if not (isinstance(tokens,types.ListType) or isinstance(tokens,types.TupleType)): - raise SyntaxError,"lex: tokens must be a list or tuple." - - # Build a dictionary of valid token names - lexer.lextokens = { } - if not optimize: - - # Utility function for verifying tokens - def is_identifier(s): - for c in s: - if not (c.isalnum() or c == '_'): return 0 - return 1 - - for n in tokens: - if not is_identifier(n): - print "lex: Bad token name '%s'" % n - error = 1 - if lexer.lextokens.has_key(n): - print "lex: Warning. Token '%s' multiply defined." % n - lexer.lextokens[n] = None - else: - for n in tokens: lexer.lextokens[n] = None - - - if debug: - print "lex: tokens = '%s'" % lexer.lextokens.keys() - - # Get a list of symbols with the t_ prefix - tsymbols = [f for f in ldict.keys() if f[:2] == 't_'] - - # Now build up a list of functions and a list of strings - fsymbols = [ ] - ssymbols = [ ] - for f in tsymbols: - if isinstance(ldict[f],types.FunctionType): - fsymbols.append(ldict[f]) - elif isinstance(ldict[f],types.StringType): - ssymbols.append((f,ldict[f])) - else: - print "lex: %s not defined as a function or string" % f - error = 1 - - # Sort the functions by line number - fsymbols.sort(lambda x,y: cmp(x.func_code.co_firstlineno,y.func_code.co_firstlineno)) - - # Sort the strings by regular expression length - ssymbols.sort(lambda x,y: (len(x[1]) < len(y[1])) - (len(x[1]) > len(y[1]))) - - # Check for non-empty symbols - if len(fsymbols) == 0 and len(ssymbols) == 0: - raise SyntaxError,"lex: no rules of the form t_rulename are defined." - - # Add all of the rules defined with actions first - for f in fsymbols: - - line = f.func_code.co_firstlineno - file = f.func_code.co_filename - files[file] = None - - if not optimize: - if f.func_code.co_argcount > 1: - print "%s:%d: Rule '%s' has too many arguments." % (file,line,f.__name__) - error = 1 - continue - - if f.func_code.co_argcount < 1: - print "%s:%d: Rule '%s' requires an argument." % (file,line,f.__name__) - error = 1 - continue - - if f.__name__ == 't_ignore': - print "%s:%d: Rule '%s' must be defined as a string." % (file,line,f.__name__) - error = 1 - continue - - if f.__name__ == 't_error': - lexer.lexerrorf = f - continue - - if f.__doc__: - if not optimize: - try: - c = re.compile(f.__doc__, re.VERBOSE) - except re.error,e: - print "%s:%d: Invalid regular expression for rule '%s'. %s" % (file,line,f.__name__,e) - error = 1 - continue - - if debug: - print "lex: Adding rule %s -> '%s'" % (f.__name__,f.__doc__) - - # Okay. The regular expression seemed okay. Let's append it to the master regular - # expression we're building - - if (regex): regex += "|" - regex += "(?P<%s>%s)" % (f.__name__,f.__doc__) - else: - print "%s:%d: No regular expression defined for rule '%s'" % (file,line,f.__name__) - - # Now add all of the simple rules - for name,r in ssymbols: - - if name == 't_ignore': - lexer.lexignore = r - continue - - if not optimize: - if name == 't_error': - raise SyntaxError,"lex: Rule 't_error' must be defined as a function" - error = 1 - continue - - if not lexer.lextokens.has_key(name[2:]): - print "lex: Rule '%s' defined for an unspecified token %s." % (name,name[2:]) - error = 1 - continue - try: - c = re.compile(r,re.VERBOSE) - except re.error,e: - print "lex: Invalid regular expression for rule '%s'. %s" % (name,e) - error = 1 - continue - if debug: - print "lex: Adding rule %s -> '%s'" % (name,r) - - if regex: regex += "|" - regex += "(?P<%s>%s)" % (name,r) - - if not optimize: - for f in files.keys(): - if not validate_file(f): - error = 1 - try: - if debug: - print "lex: regex = '%s'" % regex - lexer.lexre = re.compile(regex, re.VERBOSE) - - # Build the index to function map for the matching engine - lexer.lexindexfunc = [ None ] * (max(lexer.lexre.groupindex.values())+1) - for f,i in lexer.lexre.groupindex.items(): - handle = ldict[f] - if isinstance(handle,types.FunctionType): - lexer.lexindexfunc[i] = (handle,handle.__name__[2:]) - else: - # If rule was specified as a string, we build an anonymous - # callback function to carry out the action - lexer.lexindexfunc[i] = (None,f[2:]) - - # If a lextab was specified, we create a file containing the precomputed - # regular expression and index table - - if lextab and optimize: - lt = open(lextab+".py","w") - lt.write("# %s.py. This file automatically created by PLY. Don't edit.\n" % lextab) - lt.write("_lexre = %s\n" % repr(regex)) - lt.write("_lextab = [\n"); - for i in range(0,len(lexer.lexindexfunc)): - t = lexer.lexindexfunc[i] - if t: - if t[0]: - lt.write(" ('%s',%s),\n"% (t[0].__name__, repr(t[1]))) - else: - lt.write(" (None,%s),\n" % repr(t[1])) - else: - lt.write(" None,\n") - - lt.write("]\n"); - lt.write("_lextokens = %s\n" % repr(lexer.lextokens)) - lt.write("_lexignore = %s\n" % repr(lexer.lexignore)) - if (lexer.lexerrorf): - lt.write("_lexerrorf = %s\n" % repr(lexer.lexerrorf.__name__)) - else: - lt.write("_lexerrorf = None\n") - lt.close() - - except re.error,e: - print "lex: Fatal error. Unable to compile regular expression rules. %s" % e - error = 1 - if error: - raise SyntaxError,"lex: Unable to build lexer." - if not lexer.lexerrorf: - print "lex: Warning. no t_error rule is defined." - - if not lexer.lexignore: lexer.lexignore = "" - - # Create global versions of the token() and input() functions - token = lexer.token - input = lexer.input - - return lexer - -# ----------------------------------------------------------------------------- -# run() -# -# This runs the lexer as a main program -# ----------------------------------------------------------------------------- - -def runmain(lexer=None,data=None): - if not data: - try: - filename = sys.argv[1] - f = open(filename) - data = f.read() - f.close() - except IndexError: - print "Reading from standard input (type EOF to end):" - data = sys.stdin.read() - - if lexer: - _input = lexer.input - else: - _input = input - _input(data) - if lexer: - _token = lexer.token - else: - _token = token - - while 1: - tok = _token() - if not tok: break - print "(%s,'%s',%d)" % (tok.type, tok.value, tok.lineno) - - - - diff --git a/ext/ply/ply/__init__.py b/ext/ply/ply/__init__.py new file mode 100644 index 000000000..853a98554 --- /dev/null +++ b/ext/ply/ply/__init__.py @@ -0,0 +1,4 @@ +# PLY package +# Author: David Beazley (dave@dabeaz.com) + +__all__ = ['lex','yacc'] diff --git a/ext/ply/ply/lex.py b/ext/ply/ply/lex.py new file mode 100644 index 000000000..782b29286 --- /dev/null +++ b/ext/ply/ply/lex.py @@ -0,0 +1,867 @@ +#----------------------------------------------------------------------------- +# ply: lex.py +# +# Author: David M. Beazley (dave@dabeaz.com) +# +# Copyright (C) 2001-2007, David M. Beazley +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +# +# See the file COPYING for a complete copy of the LGPL. +#----------------------------------------------------------------------------- + +__version__ = "2.3" + +import re, sys, types + +# Regular expression used to match valid token names +_is_identifier = re.compile(r'^[a-zA-Z0-9_]+$') + +# Available instance types. This is used when lexers are defined by a class. +# It's a little funky because I want to preserve backwards compatibility +# with Python 2.0 where types.ObjectType is undefined. + +try: + _INSTANCETYPE = (types.InstanceType, types.ObjectType) +except AttributeError: + _INSTANCETYPE = types.InstanceType + class object: pass # Note: needed if no new-style classes present + +# Exception thrown when invalid token encountered and no default error +# handler is defined. +class LexError(Exception): + def __init__(self,message,s): + self.args = (message,) + self.text = s + +# Token class +class LexToken(object): + def __str__(self): + return "LexToken(%s,%r,%d,%d)" % (self.type,self.value,self.lineno,self.lexpos) + def __repr__(self): + return str(self) + def skip(self,n): + self.lexer.skip(n) + +# ----------------------------------------------------------------------------- +# Lexer class +# +# This class encapsulates all of the methods and data associated with a lexer. +# +# input() - Store a new string in the lexer +# token() - Get the next token +# ----------------------------------------------------------------------------- + +class Lexer: + def __init__(self): + self.lexre = None # Master regular expression. This is a list of + # tuples (re,findex) where re is a compiled + # regular expression and findex is a list + # mapping regex group numbers to rules + self.lexretext = None # Current regular expression strings + self.lexstatere = {} # Dictionary mapping lexer states to master regexs + self.lexstateretext = {} # Dictionary mapping lexer states to regex strings + self.lexstate = "INITIAL" # Current lexer state + self.lexstatestack = [] # Stack of lexer states + self.lexstateinfo = None # State information + self.lexstateignore = {} # Dictionary of ignored characters for each state + self.lexstateerrorf = {} # Dictionary of error functions for each state + self.lexreflags = 0 # Optional re compile flags + self.lexdata = None # Actual input data (as a string) + self.lexpos = 0 # Current position in input text + self.lexlen = 0 # Length of the input text + self.lexerrorf = None # Error rule (if any) + self.lextokens = None # List of valid tokens + self.lexignore = "" # Ignored characters + self.lexliterals = "" # Literal characters that can be passed through + self.lexmodule = None # Module + self.lineno = 1 # Current line number + self.lexdebug = 0 # Debugging mode + self.lexoptimize = 0 # Optimized mode + + def clone(self,object=None): + c = Lexer() + c.lexstatere = self.lexstatere + c.lexstateinfo = self.lexstateinfo + c.lexstateretext = self.lexstateretext + c.lexstate = self.lexstate + c.lexstatestack = self.lexstatestack + c.lexstateignore = self.lexstateignore + c.lexstateerrorf = self.lexstateerrorf + c.lexreflags = self.lexreflags + c.lexdata = self.lexdata + c.lexpos = self.lexpos + c.lexlen = self.lexlen + c.lextokens = self.lextokens + c.lexdebug = self.lexdebug + c.lineno = self.lineno + c.lexoptimize = self.lexoptimize + c.lexliterals = self.lexliterals + c.lexmodule = self.lexmodule + + # If the object parameter has been supplied, it means we are attaching the + # lexer to a new object. In this case, we have to rebind all methods in + # the lexstatere and lexstateerrorf tables. + + if object: + newtab = { } + for key, ritem in self.lexstatere.items(): + newre = [] + for cre, findex in ritem: + newfindex = [] + for f in findex: + if not f or not f[0]: + newfindex.append(f) + continue + newfindex.append((getattr(object,f[0].__name__),f[1])) + newre.append((cre,newfindex)) + newtab[key] = newre + c.lexstatere = newtab + c.lexstateerrorf = { } + for key, ef in self.lexstateerrorf.items(): + c.lexstateerrorf[key] = getattr(object,ef.__name__) + c.lexmodule = object + + # Set up other attributes + c.begin(c.lexstate) + return c + + # ------------------------------------------------------------ + # writetab() - Write lexer information to a table file + # ------------------------------------------------------------ + def writetab(self,tabfile): + tf = open(tabfile+".py","w") + tf.write("# %s.py. This file automatically created by PLY (version %s). Don't edit!\n" % (tabfile,__version__)) + tf.write("_lextokens = %s\n" % repr(self.lextokens)) + tf.write("_lexreflags = %s\n" % repr(self.lexreflags)) + tf.write("_lexliterals = %s\n" % repr(self.lexliterals)) + tf.write("_lexstateinfo = %s\n" % repr(self.lexstateinfo)) + + tabre = { } + for key, lre in self.lexstatere.items(): + titem = [] + for i in range(len(lre)): + titem.append((self.lexstateretext[key][i],_funcs_to_names(lre[i][1]))) + tabre[key] = titem + + tf.write("_lexstatere = %s\n" % repr(tabre)) + tf.write("_lexstateignore = %s\n" % repr(self.lexstateignore)) + + taberr = { } + for key, ef in self.lexstateerrorf.items(): + if ef: + taberr[key] = ef.__name__ + else: + taberr[key] = None + tf.write("_lexstateerrorf = %s\n" % repr(taberr)) + tf.close() + + # ------------------------------------------------------------ + # readtab() - Read lexer information from a tab file + # ------------------------------------------------------------ + def readtab(self,tabfile,fdict): + exec "import %s as lextab" % tabfile + self.lextokens = lextab._lextokens + self.lexreflags = lextab._lexreflags + self.lexliterals = lextab._lexliterals + self.lexstateinfo = lextab._lexstateinfo + self.lexstateignore = lextab._lexstateignore + self.lexstatere = { } + self.lexstateretext = { } + for key,lre in lextab._lexstatere.items(): + titem = [] + txtitem = [] + for i in range(len(lre)): + titem.append((re.compile(lre[i][0],lextab._lexreflags),_names_to_funcs(lre[i][1],fdict))) + txtitem.append(lre[i][0]) + self.lexstatere[key] = titem + self.lexstateretext[key] = txtitem + self.lexstateerrorf = { } + for key,ef in lextab._lexstateerrorf.items(): + self.lexstateerrorf[key] = fdict[ef] + self.begin('INITIAL') + + # ------------------------------------------------------------ + # input() - Push a new string into the lexer + # ------------------------------------------------------------ + def input(self,s): + if not (isinstance(s,types.StringType) or isinstance(s,types.UnicodeType)): + raise ValueError, "Expected a string" + self.lexdata = s + self.lexpos = 0 + self.lexlen = len(s) + + # ------------------------------------------------------------ + # begin() - Changes the lexing state + # ------------------------------------------------------------ + def begin(self,state): + if not self.lexstatere.has_key(state): + raise ValueError, "Undefined state" + self.lexre = self.lexstatere[state] + self.lexretext = self.lexstateretext[state] + self.lexignore = self.lexstateignore.get(state,"") + self.lexerrorf = self.lexstateerrorf.get(state,None) + self.lexstate = state + + # ------------------------------------------------------------ + # push_state() - Changes the lexing state and saves old on stack + # ------------------------------------------------------------ + def push_state(self,state): + self.lexstatestack.append(self.lexstate) + self.begin(state) + + # ------------------------------------------------------------ + # pop_state() - Restores the previous state + # ------------------------------------------------------------ + def pop_state(self): + self.begin(self.lexstatestack.pop()) + + # ------------------------------------------------------------ + # current_state() - Returns the current lexing state + # ------------------------------------------------------------ + def current_state(self): + return self.lexstate + + # ------------------------------------------------------------ + # skip() - Skip ahead n characters + # ------------------------------------------------------------ + def skip(self,n): + self.lexpos += n + + # ------------------------------------------------------------ + # token() - Return the next token from the Lexer + # + # Note: This function has been carefully implemented to be as fast + # as possible. Don't make changes unless you really know what + # you are doing + # ------------------------------------------------------------ + def token(self): + # Make local copies of frequently referenced attributes + lexpos = self.lexpos + lexlen = self.lexlen + lexignore = self.lexignore + lexdata = self.lexdata + + while lexpos < lexlen: + # This code provides some short-circuit code for whitespace, tabs, and other ignored characters + if lexdata[lexpos] in lexignore: + lexpos += 1 + continue + + # Look for a regular expression match + for lexre,lexindexfunc in self.lexre: + m = lexre.match(lexdata,lexpos) + if not m: continue + + # Set last match in lexer so that rules can access it if they want + self.lexmatch = m + + # Create a token for return + tok = LexToken() + tok.value = m.group() + tok.lineno = self.lineno + tok.lexpos = lexpos + tok.lexer = self + + lexpos = m.end() + i = m.lastindex + func,tok.type = lexindexfunc[i] + self.lexpos = lexpos + + if not func: + # If no token type was set, it's an ignored token + if tok.type: return tok + break + + # if func not callable, it means it's an ignored token + if not callable(func): + break + + # If token is processed by a function, call it + newtok = func(tok) + + # Every function must return a token, if nothing, we just move to next token + if not newtok: + lexpos = self.lexpos # This is here in case user has updated lexpos. + break + + # Verify type of the token. If not in the token map, raise an error + if not self.lexoptimize: + if not self.lextokens.has_key(newtok.type): + raise LexError, ("%s:%d: Rule '%s' returned an unknown token type '%s'" % ( + func.func_code.co_filename, func.func_code.co_firstlineno, + func.__name__, newtok.type),lexdata[lexpos:]) + + return newtok + else: + # No match, see if in literals + if lexdata[lexpos] in self.lexliterals: + tok = LexToken() + tok.value = lexdata[lexpos] + tok.lineno = self.lineno + tok.lexer = self + tok.type = tok.value + tok.lexpos = lexpos + self.lexpos = lexpos + 1 + return tok + + # No match. Call t_error() if defined. + if self.lexerrorf: + tok = LexToken() + tok.value = self.lexdata[lexpos:] + tok.lineno = self.lineno + tok.type = "error" + tok.lexer = self + tok.lexpos = lexpos + self.lexpos = lexpos + newtok = self.lexerrorf(tok) + if lexpos == self.lexpos: + # Error method didn't change text position at all. This is an error. + raise LexError, ("Scanning error. Illegal character '%s'" % (lexdata[lexpos]), lexdata[lexpos:]) + lexpos = self.lexpos + if not newtok: continue + return newtok + + self.lexpos = lexpos + raise LexError, ("Illegal character '%s' at index %d" % (lexdata[lexpos],lexpos), lexdata[lexpos:]) + + self.lexpos = lexpos + 1 + if self.lexdata is None: + raise RuntimeError, "No input string given with input()" + return None + +# ----------------------------------------------------------------------------- +# _validate_file() +# +# This checks to see if there are duplicated t_rulename() functions or strings +# in the parser input file. This is done using a simple regular expression +# match on each line in the filename. +# ----------------------------------------------------------------------------- + +def _validate_file(filename): + import os.path + base,ext = os.path.splitext(filename) + if ext != '.py': return 1 # No idea what the file is. Return OK + + try: + f = open(filename) + lines = f.readlines() + f.close() + except IOError: + return 1 # Oh well + + fre = re.compile(r'\s*def\s+(t_[a-zA-Z_0-9]*)\(') + sre = re.compile(r'\s*(t_[a-zA-Z_0-9]*)\s*=') + counthash = { } + linen = 1 + noerror = 1 + for l in lines: + m = fre.match(l) + if not m: + m = sre.match(l) + if m: + name = m.group(1) + prev = counthash.get(name) + if not prev: + counthash[name] = linen + else: + print >>sys.stderr, "%s:%d: Rule %s redefined. Previously defined on line %d" % (filename,linen,name,prev) + noerror = 0 + linen += 1 + return noerror + +# ----------------------------------------------------------------------------- +# _funcs_to_names() +# +# Given a list of regular expression functions, this converts it to a list +# suitable for output to a table file +# ----------------------------------------------------------------------------- + +def _funcs_to_names(funclist): + result = [] + for f in funclist: + if f and f[0]: + result.append((f[0].__name__,f[1])) + else: + result.append(f) + return result + +# ----------------------------------------------------------------------------- +# _names_to_funcs() +# +# Given a list of regular expression function names, this converts it back to +# functions. +# ----------------------------------------------------------------------------- + +def _names_to_funcs(namelist,fdict): + result = [] + for n in namelist: + if n and n[0]: + result.append((fdict[n[0]],n[1])) + else: + result.append(n) + return result + +# ----------------------------------------------------------------------------- +# _form_master_re() +# +# This function takes a list of all of the regex components and attempts to +# form the master regular expression. Given limitations in the Python re +# module, it may be necessary to break the master regex into separate expressions. +# ----------------------------------------------------------------------------- + +def _form_master_re(relist,reflags,ldict,toknames): + if not relist: return [] + regex = "|".join(relist) + try: + lexre = re.compile(regex,re.VERBOSE | reflags) + + # Build the index to function map for the matching engine + lexindexfunc = [ None ] * (max(lexre.groupindex.values())+1) + for f,i in lexre.groupindex.items(): + handle = ldict.get(f,None) + if type(handle) in (types.FunctionType, types.MethodType): + lexindexfunc[i] = (handle,toknames[handle.__name__]) + elif handle is not None: + # If rule was specified as a string, we build an anonymous + # callback function to carry out the action + if f.find("ignore_") > 0: + lexindexfunc[i] = (None,None) + else: + lexindexfunc[i] = (None, toknames[f]) + + return [(lexre,lexindexfunc)],[regex] + except Exception,e: + m = int(len(relist)/2) + if m == 0: m = 1 + llist, lre = _form_master_re(relist[:m],reflags,ldict,toknames) + rlist, rre = _form_master_re(relist[m:],reflags,ldict,toknames) + return llist+rlist, lre+rre + +# ----------------------------------------------------------------------------- +# def _statetoken(s,names) +# +# Given a declaration name s of the form "t_" and a dictionary whose keys are +# state names, this function returns a tuple (states,tokenname) where states +# is a tuple of state names and tokenname is the name of the token. For example, +# calling this with s = "t_foo_bar_SPAM" might return (('foo','bar'),'SPAM') +# ----------------------------------------------------------------------------- + +def _statetoken(s,names): + nonstate = 1 + parts = s.split("_") + for i in range(1,len(parts)): + if not names.has_key(parts[i]) and parts[i] != 'ANY': break + if i > 1: + states = tuple(parts[1:i]) + else: + states = ('INITIAL',) + + if 'ANY' in states: + states = tuple(names.keys()) + + tokenname = "_".join(parts[i:]) + return (states,tokenname) + +# ----------------------------------------------------------------------------- +# lex(module) +# +# Build all of the regular expression rules from definitions in the supplied module +# ----------------------------------------------------------------------------- +def lex(module=None,object=None,debug=0,optimize=0,lextab="lextab",reflags=0,nowarn=0): + global lexer + ldict = None + stateinfo = { 'INITIAL' : 'inclusive'} + error = 0 + files = { } + lexobj = Lexer() + lexobj.lexdebug = debug + lexobj.lexoptimize = optimize + global token,input + + if nowarn: warn = 0 + else: warn = 1 + + if object: module = object + + if module: + # User supplied a module object. + if isinstance(module, types.ModuleType): + ldict = module.__dict__ + elif isinstance(module, _INSTANCETYPE): + _items = [(k,getattr(module,k)) for k in dir(module)] + ldict = { } + for (i,v) in _items: + ldict[i] = v + else: + raise ValueError,"Expected a module or instance" + lexobj.lexmodule = module + + else: + # No module given. We might be able to get information from the caller. + try: + raise RuntimeError + except RuntimeError: + e,b,t = sys.exc_info() + f = t.tb_frame + f = f.f_back # Walk out to our calling function + ldict = f.f_globals # Grab its globals dictionary + + if optimize and lextab: + try: + lexobj.readtab(lextab,ldict) + token = lexobj.token + input = lexobj.input + lexer = lexobj + return lexobj + + except ImportError: + pass + + # Get the tokens, states, and literals variables (if any) + if (module and isinstance(module,_INSTANCETYPE)): + tokens = getattr(module,"tokens",None) + states = getattr(module,"states",None) + literals = getattr(module,"literals","") + else: + tokens = ldict.get("tokens",None) + states = ldict.get("states",None) + literals = ldict.get("literals","") + + if not tokens: + raise SyntaxError,"lex: module does not define 'tokens'" + if not (isinstance(tokens,types.ListType) or isinstance(tokens,types.TupleType)): + raise SyntaxError,"lex: tokens must be a list or tuple." + + # Build a dictionary of valid token names + lexobj.lextokens = { } + if not optimize: + for n in tokens: + if not _is_identifier.match(n): + print >>sys.stderr, "lex: Bad token name '%s'" % n + error = 1 + if warn and lexobj.lextokens.has_key(n): + print >>sys.stderr, "lex: Warning. Token '%s' multiply defined." % n + lexobj.lextokens[n] = None + else: + for n in tokens: lexobj.lextokens[n] = None + + if debug: + print "lex: tokens = '%s'" % lexobj.lextokens.keys() + + try: + for c in literals: + if not (isinstance(c,types.StringType) or isinstance(c,types.UnicodeType)) or len(c) > 1: + print >>sys.stderr, "lex: Invalid literal %s. Must be a single character" % repr(c) + error = 1 + continue + + except TypeError: + print >>sys.stderr, "lex: Invalid literals specification. literals must be a sequence of characters." + error = 1 + + lexobj.lexliterals = literals + + # Build statemap + if states: + if not (isinstance(states,types.TupleType) or isinstance(states,types.ListType)): + print >>sys.stderr, "lex: states must be defined as a tuple or list." + error = 1 + else: + for s in states: + if not isinstance(s,types.TupleType) or len(s) != 2: + print >>sys.stderr, "lex: invalid state specifier %s. Must be a tuple (statename,'exclusive|inclusive')" % repr(s) + error = 1 + continue + name, statetype = s + if not isinstance(name,types.StringType): + print >>sys.stderr, "lex: state name %s must be a string" % repr(name) + error = 1 + continue + if not (statetype == 'inclusive' or statetype == 'exclusive'): + print >>sys.stderr, "lex: state type for state %s must be 'inclusive' or 'exclusive'" % name + error = 1 + continue + if stateinfo.has_key(name): + print >>sys.stderr, "lex: state '%s' already defined." % name + error = 1 + continue + stateinfo[name] = statetype + + # Get a list of symbols with the t_ or s_ prefix + tsymbols = [f for f in ldict.keys() if f[:2] == 't_' ] + + # Now build up a list of functions and a list of strings + + funcsym = { } # Symbols defined as functions + strsym = { } # Symbols defined as strings + toknames = { } # Mapping of symbols to token names + + for s in stateinfo.keys(): + funcsym[s] = [] + strsym[s] = [] + + ignore = { } # Ignore strings by state + errorf = { } # Error functions by state + + if len(tsymbols) == 0: + raise SyntaxError,"lex: no rules of the form t_rulename are defined." + + for f in tsymbols: + t = ldict[f] + states, tokname = _statetoken(f,stateinfo) + toknames[f] = tokname + + if callable(t): + for s in states: funcsym[s].append((f,t)) + elif (isinstance(t, types.StringType) or isinstance(t,types.UnicodeType)): + for s in states: strsym[s].append((f,t)) + else: + print >>sys.stderr, "lex: %s not defined as a function or string" % f + error = 1 + + # Sort the functions by line number + for f in funcsym.values(): + f.sort(lambda x,y: cmp(x[1].func_code.co_firstlineno,y[1].func_code.co_firstlineno)) + + # Sort the strings by regular expression length + for s in strsym.values(): + s.sort(lambda x,y: (len(x[1]) < len(y[1])) - (len(x[1]) > len(y[1]))) + + regexs = { } + + # Build the master regular expressions + for state in stateinfo.keys(): + regex_list = [] + + # Add rules defined by functions first + for fname, f in funcsym[state]: + line = f.func_code.co_firstlineno + file = f.func_code.co_filename + files[file] = None + tokname = toknames[fname] + + ismethod = isinstance(f, types.MethodType) + + if not optimize: + nargs = f.func_code.co_argcount + if ismethod: + reqargs = 2 + else: + reqargs = 1 + if nargs > reqargs: + print >>sys.stderr, "%s:%d: Rule '%s' has too many arguments." % (file,line,f.__name__) + error = 1 + continue + + if nargs < reqargs: + print >>sys.stderr, "%s:%d: Rule '%s' requires an argument." % (file,line,f.__name__) + error = 1 + continue + + if tokname == 'ignore': + print >>sys.stderr, "%s:%d: Rule '%s' must be defined as a string." % (file,line,f.__name__) + error = 1 + continue + + if tokname == 'error': + errorf[state] = f + continue + + if f.__doc__: + if not optimize: + try: + c = re.compile("(?P<%s>%s)" % (f.__name__,f.__doc__), re.VERBOSE | reflags) + if c.match(""): + print >>sys.stderr, "%s:%d: Regular expression for rule '%s' matches empty string." % (file,line,f.__name__) + error = 1 + continue + except re.error,e: + print >>sys.stderr, "%s:%d: Invalid regular expression for rule '%s'. %s" % (file,line,f.__name__,e) + if '#' in f.__doc__: + print >>sys.stderr, "%s:%d. Make sure '#' in rule '%s' is escaped with '\\#'." % (file,line, f.__name__) + error = 1 + continue + + if debug: + print "lex: Adding rule %s -> '%s' (state '%s')" % (f.__name__,f.__doc__, state) + + # Okay. The regular expression seemed okay. Let's append it to the master regular + # expression we're building + + regex_list.append("(?P<%s>%s)" % (f.__name__,f.__doc__)) + else: + print >>sys.stderr, "%s:%d: No regular expression defined for rule '%s'" % (file,line,f.__name__) + + # Now add all of the simple rules + for name,r in strsym[state]: + tokname = toknames[name] + + if tokname == 'ignore': + if "\\" in r: + print >>sys.stderr, "lex: Warning. %s contains a literal backslash '\\'" % name + ignore[state] = r + continue + + if not optimize: + if tokname == 'error': + raise SyntaxError,"lex: Rule '%s' must be defined as a function" % name + error = 1 + continue + + if not lexobj.lextokens.has_key(tokname) and tokname.find("ignore_") < 0: + print >>sys.stderr, "lex: Rule '%s' defined for an unspecified token %s." % (name,tokname) + error = 1 + continue + try: + c = re.compile("(?P<%s>%s)" % (name,r),re.VERBOSE | reflags) + if (c.match("")): + print >>sys.stderr, "lex: Regular expression for rule '%s' matches empty string." % name + error = 1 + continue + except re.error,e: + print >>sys.stderr, "lex: Invalid regular expression for rule '%s'. %s" % (name,e) + if '#' in r: + print >>sys.stderr, "lex: Make sure '#' in rule '%s' is escaped with '\\#'." % name + + error = 1 + continue + if debug: + print "lex: Adding rule %s -> '%s' (state '%s')" % (name,r,state) + + regex_list.append("(?P<%s>%s)" % (name,r)) + + if not regex_list: + print >>sys.stderr, "lex: No rules defined for state '%s'" % state + error = 1 + + regexs[state] = regex_list + + + if not optimize: + for f in files.keys(): + if not _validate_file(f): + error = 1 + + if error: + raise SyntaxError,"lex: Unable to build lexer." + + # From this point forward, we're reasonably confident that we can build the lexer. + # No more errors will be generated, but there might be some warning messages. + + # Build the master regular expressions + + for state in regexs.keys(): + lexre, re_text = _form_master_re(regexs[state],reflags,ldict,toknames) + lexobj.lexstatere[state] = lexre + lexobj.lexstateretext[state] = re_text + if debug: + for i in range(len(re_text)): + print "lex: state '%s'. regex[%d] = '%s'" % (state, i, re_text[i]) + + # For inclusive states, we need to add the INITIAL state + for state,type in stateinfo.items(): + if state != "INITIAL" and type == 'inclusive': + lexobj.lexstatere[state].extend(lexobj.lexstatere['INITIAL']) + lexobj.lexstateretext[state].extend(lexobj.lexstateretext['INITIAL']) + + lexobj.lexstateinfo = stateinfo + lexobj.lexre = lexobj.lexstatere["INITIAL"] + lexobj.lexretext = lexobj.lexstateretext["INITIAL"] + + # Set up ignore variables + lexobj.lexstateignore = ignore + lexobj.lexignore = lexobj.lexstateignore.get("INITIAL","") + + # Set up error functions + lexobj.lexstateerrorf = errorf + lexobj.lexerrorf = errorf.get("INITIAL",None) + if warn and not lexobj.lexerrorf: + print >>sys.stderr, "lex: Warning. no t_error rule is defined." + + # Check state information for ignore and error rules + for s,stype in stateinfo.items(): + if stype == 'exclusive': + if warn and not errorf.has_key(s): + print >>sys.stderr, "lex: Warning. no error rule is defined for exclusive state '%s'" % s + if warn and not ignore.has_key(s) and lexobj.lexignore: + print >>sys.stderr, "lex: Warning. no ignore rule is defined for exclusive state '%s'" % s + elif stype == 'inclusive': + if not errorf.has_key(s): + errorf[s] = errorf.get("INITIAL",None) + if not ignore.has_key(s): + ignore[s] = ignore.get("INITIAL","") + + + # Create global versions of the token() and input() functions + token = lexobj.token + input = lexobj.input + lexer = lexobj + + # If in optimize mode, we write the lextab + if lextab and optimize: + lexobj.writetab(lextab) + + return lexobj + +# ----------------------------------------------------------------------------- +# runmain() +# +# This runs the lexer as a main program +# ----------------------------------------------------------------------------- + +def runmain(lexer=None,data=None): + if not data: + try: + filename = sys.argv[1] + f = open(filename) + data = f.read() + f.close() + except IndexError: + print "Reading from standard input (type EOF to end):" + data = sys.stdin.read() + + if lexer: + _input = lexer.input + else: + _input = input + _input(data) + if lexer: + _token = lexer.token + else: + _token = token + + while 1: + tok = _token() + if not tok: break + print "(%s,%r,%d,%d)" % (tok.type, tok.value, tok.lineno,tok.lexpos) + + +# ----------------------------------------------------------------------------- +# @TOKEN(regex) +# +# This decorator function can be used to set the regex expression on a function +# when its docstring might need to be set in an alternative way +# ----------------------------------------------------------------------------- + +def TOKEN(r): + def set_doc(f): + f.__doc__ = r + return f + return set_doc + +# Alternative spelling of the TOKEN decorator +Token = TOKEN + diff --git a/ext/ply/yacc.py b/ext/ply/ply/yacc.py index 1041745ed..39c17a9ed 100644 --- a/ext/ply/yacc.py +++ b/ext/ply/ply/yacc.py @@ -1,14 +1,9 @@ #----------------------------------------------------------------------------- # ply: yacc.py # -# Author: David M. Beazley (beazley@cs.uchicago.edu) -# Department of Computer Science -# University of Chicago -# Chicago, IL 60637 +# Author(s): David M. Beazley (dave@dabeaz.com) # -# Copyright (C) 2001, David M. Beazley -# -# $Header: /home/stever/bk/newmem2/ext/ply/yacc.py 1.3 03/06/06 14:59:28-00:00 stever@ $ +# Copyright (C) 2001-2007, David M. Beazley # # This library is free software; you can redistribute it and/or # modify it under the terms of the GNU Lesser General Public @@ -28,12 +23,10 @@ # # # This implements an LR parser that is constructed from grammar rules defined -# as Python functions. Roughly speaking, this module is a cross between -# John Aycock's Spark system and the GNU bison utility. -# -# Disclaimer: This is a work in progress. SLR parsing seems to work fairly -# well and there is extensive error checking. LALR(1) is in progress. The -# rest of this file is a bit of a mess. Please pardon the dust. +# as Python functions. The grammer is specified by supplying the BNF inside +# Python documentation strings. The inspiration for this technique was borrowed +# from John Aycock's Spark parsing system. PLY might be viewed as cross between +# Spark and the GNU bison utility. # # The current implementation is only somewhat object-oriented. The # LR parser itself is defined in terms of an object (which allows multiple @@ -41,9 +34,23 @@ # construction are defined in terms of global variables. Users shouldn't # notice unless they are trying to define multiple parsers at the same # time using threads (in which case they should have their head examined). -#----------------------------------------------------------------------------- +# +# This implementation supports both SLR and LALR(1) parsing. LALR(1) +# support was originally implemented by Elias Ioup (ezioup@alumni.uchicago.edu), +# using the algorithm found in Aho, Sethi, and Ullman "Compilers: Principles, +# Techniques, and Tools" (The Dragon Book). LALR(1) has since been replaced +# by the more efficient DeRemer and Pennello algorithm. +# +# :::::::: WARNING ::::::: +# +# Construction of LR parsing tables is fairly complicated and expensive. +# To make this module run fast, a *LOT* of work has been put into +# optimization---often at the expensive of readability and what might +# consider to be good Python "coding style." Modify the code at your +# own risk! +# ---------------------------------------------------------------------------- -__version__ = "1.3" +__version__ = "2.3" #----------------------------------------------------------------------------- # === User configurable parameters === @@ -56,7 +63,7 @@ yaccdebug = 1 # Debugging mode. If set, yacc generates a debug_file = 'parser.out' # Default name of the debugging file tab_module = 'parsetab' # Default name of the table module -default_lr = 'SLR' # Default LR table generation method +default_lr = 'LALR' # Default LR table generation method error_count = 3 # Number of symbols that must be shifted to leave recovery mode @@ -65,6 +72,16 @@ import re, types, sys, cStringIO, md5, os.path # Exception raised for yacc-related errors class YaccError(Exception): pass +# Available instance types. This is used when parsers are defined by a class. +# it's a little funky because I want to preserve backwards compatibility +# with Python 2.0 where types.ObjectType is undefined. + +try: + _INSTANCETYPE = (types.InstanceType, types.ObjectType) +except AttributeError: + _INSTANCETYPE = types.InstanceType + class object: pass # Note: needed if no new-style classes present + #----------------------------------------------------------------------------- # === LR Parsing Engine === # @@ -79,8 +96,10 @@ class YaccError(Exception): pass # .value = Symbol value # .lineno = Starting line number # .endlineno = Ending line number (optional, set automatically) +# .lexpos = Starting lex position +# .endlexpos = Ending lex position (optional, set automatically) -class YaccSymbol: +class YaccSymbol(object): def __str__(self): return self.type def __repr__(self): return str(self) @@ -90,19 +109,24 @@ class YaccSymbol: # The lineno() method returns the line number of a given # item (or 0 if not defined). The linespan() method returns # a tuple of (startline,endline) representing the range of lines -# for a symbol. +# for a symbol. The lexspan() method returns a tuple (lexpos,endlexpos) +# representing the range of positional information for a symbol. -class YaccSlice: - def __init__(self,s): +class YaccProduction: + def __init__(self,s,stack=None): self.slice = s self.pbstack = [] - + self.stack = stack def __getitem__(self,n): - return self.slice[n].value + if n >= 0: return self.slice[n].value + else: return self.stack[n].value def __setitem__(self,n,v): self.slice[n].value = v + def __getslice__(self,i,j): + return [s.value for s in self.slice[i:j]] + def __len__(self): return len(self.slice) @@ -114,6 +138,14 @@ class YaccSlice: endline = getattr(self.slice[n],"endlineno",startline) return startline,endline + def lexpos(self,n): + return getattr(self.slice[n],"lexpos",0) + + def lexspan(self,n): + startpos = getattr(self.slice[n],"lexpos",0) + endpos = getattr(self.slice[n],"endlexpos",startpos) + return startpos,endpos + def pushback(self,n): if n <= 0: raise ValueError, "Expected a positive value" @@ -145,31 +177,32 @@ class Parser: self.method = "Unknown LR" # Table construction method used def errok(self): - self.errorcount = 0 + self.errorok = 1 def restart(self): del self.statestack[:] del self.symstack[:] sym = YaccSymbol() - sym.type = '$' + sym.type = '$end' self.symstack.append(sym) self.statestack.append(0) - def parse(self,input=None,lexer=None,debug=0): + def parse(self,input=None,lexer=None,debug=0,tracking=0): lookahead = None # Current lookahead symbol lookaheadstack = [ ] # Stack of lookahead symbols actions = self.action # Local reference to action table goto = self.goto # Local reference to goto table prod = self.productions # Local reference to production list - pslice = YaccSlice(None) # Slice object passed to grammar rules - pslice.parser = self # Parser object - self.errorcount = 0 # Used during error recovery + pslice = YaccProduction(None) # Production object passed to grammar rules + errorcount = 0 # Used during error recovery # If no lexer was given, we will try to use the lex module if not lexer: - import lex as lexer + import lex + lexer = lex.lexer pslice.lexer = lexer + pslice.parser = self # If input was supplied, pass to lexer if input: @@ -183,18 +216,22 @@ class Parser: symstack = [ ] # Stack of grammar symbols self.symstack = symstack + pslice.stack = symstack # Put in the production errtoken = None # Err token - # The start state is assumed to be (0,$) + # The start state is assumed to be (0,$end) + statestack.append(0) sym = YaccSymbol() - sym.type = '$' + sym.type = '$end' symstack.append(sym) - + state = 0 while 1: # Get the next symbol on the input. If a lookahead symbol # is already set, we just use that. Otherwise, we'll pull # the next token off of the lookaheadstack or from the lexer + if debug > 1: + print 'state', state if not lookahead: if not lookaheadstack: lookahead = get_token() # Get the next token @@ -202,30 +239,32 @@ class Parser: lookahead = lookaheadstack.pop() if not lookahead: lookahead = YaccSymbol() - lookahead.type = '$' + lookahead.type = '$end' if debug: - print "%-20s : %s" % (lookahead, [xx.type for xx in symstack]) + errorlead = ("%s . %s" % (" ".join([xx.type for xx in symstack][1:]), str(lookahead))).lstrip() # Check the action table - s = statestack[-1] ltype = lookahead.type - t = actions.get((s,ltype),None) + t = actions[state].get(ltype) + if debug > 1: + print 'action', t if t is not None: if t > 0: # shift a symbol on the stack - if ltype == '$': + if ltype == '$end': # Error, end of input - print "yacc: Parse error. EOF" + sys.stderr.write("yacc: Parse error. EOF\n") return statestack.append(t) + state = t + if debug > 1: + sys.stderr.write("%-60s shift state %s\n" % (errorlead, t)) symstack.append(lookahead) lookahead = None # Decrease error count on successful shift - if self.errorcount > 0: - self.errorcount -= 1 - + if errorcount: errorcount -=1 continue if t < 0: @@ -238,57 +277,42 @@ class Parser: sym = YaccSymbol() sym.type = pname # Production name sym.value = None + if debug > 1: + sys.stderr.write("%-60s reduce %d\n" % (errorlead, -t)) if plen: targ = symstack[-plen-1:] targ[0] = sym - try: - sym.lineno = targ[1].lineno - sym.endlineno = getattr(targ[-1],"endlineno",targ[-1].lineno) - except AttributeError: - sym.lineno = 0 + if tracking: + t1 = targ[1] + sym.lineno = t1.lineno + sym.lexpos = t1.lexpos + t1 = targ[-1] + sym.endlineno = getattr(t1,"endlineno",t1.lineno) + sym.endlexpos = getattr(t1,"endlexpos",t1.lexpos) del symstack[-plen:] del statestack[-plen:] else: - sym.lineno = 0 + if tracking: + sym.lineno = lexer.lineno + sym.lexpos = lexer.lexpos targ = [ sym ] pslice.slice = targ - pslice.pbstack = [] + # Call the grammar rule with our special slice object p.func(pslice) - # Validate attributes of the resulting value attribute -# if require: -# try: -# t0 = targ[0] -# r = Requires.get(t0.type,None) -# t0d = t0.__dict__ -# if r: -# for field in r: -# tn = t0 -# for fname in field: -# try: -# tf = tn.__dict__ -# tn = tf.get(fname) -# except StandardError: -# tn = None -# if not tn: -# print "%s:%d: Rule %s doesn't set required attribute '%s'" % \ -# (p.file,p.line,p.name,".".join(field)) -# except TypeError,LookupError: -# print "Bad requires directive " % r -# pass - - # If there was a pushback, put that on the stack if pslice.pbstack: lookaheadstack.append(lookahead) for _t in pslice.pbstack: lookaheadstack.append(_t) lookahead = None + pslice.pbstack = [] symstack.append(sym) - statestack.append(goto[statestack[-1],pname]) + state = goto[statestack[-1]][pname] + statestack.append(state) continue if t == 0: @@ -296,19 +320,23 @@ class Parser: return getattr(n,"value",None) if t == None: - # We have some kind of parsing error here. To handle this, - # we are going to push the current token onto the tokenstack - # and replace it with an 'error' token. If there are any synchronization - # rules, they may catch it. + if debug: + sys.stderr.write(errorlead + "\n") + # We have some kind of parsing error here. To handle + # this, we are going to push the current token onto + # the tokenstack and replace it with an 'error' token. + # If there are any synchronization rules, they may + # catch it. # - # In addition to pushing the error token, we call call the user defined p_error() - # function if this is the first syntax error. This function is only called - # if errorcount == 0. - - if not self.errorcount: - self.errorcount = error_count + # In addition to pushing the error token, we call call + # the user defined p_error() function if this is the + # first syntax error. This function is only called if + # errorcount == 0. + if errorcount == 0 or self.errorok: + errorcount = error_count + self.errorok = 0 errtoken = lookahead - if errtoken.type == '$': + if errtoken.type == '$end': errtoken = None # End of file! if self.errorfunc: global errok,token,restart @@ -318,9 +346,10 @@ class Parser: tok = self.errorfunc(errtoken) del errok, token, restart # Delete special functions - if not self.errorcount: - # User must have done some kind of panic mode recovery on their own. The returned token - # is the next lookahead + if self.errorok: + # User must have done some kind of panic + # mode recovery on their own. The + # returned token is the next lookahead lookahead = tok errtoken = None continue @@ -329,21 +358,21 @@ class Parser: if hasattr(errtoken,"lineno"): lineno = lookahead.lineno else: lineno = 0 if lineno: - print "yacc: Syntax error at line %d, token=%s" % (lineno, errtoken.type) + sys.stderr.write("yacc: Syntax error at line %d, token=%s\n" % (lineno, errtoken.type)) else: - print "yacc: Syntax error, token=%s" % errtoken.type + sys.stderr.write("yacc: Syntax error, token=%s" % errtoken.type) else: - print "yacc: Parse error in input. EOF" + sys.stderr.write("yacc: Parse error in input. EOF\n") return else: - self.errorcount = error_count + errorcount = error_count # case 1: the statestack only has 1 entry on it. If we're in this state, the # entire parse has been rolled back and we're completely hosed. The token is # discarded and we just keep going. - if len(statestack) <= 1 and lookahead.type != '$': + if len(statestack) <= 1 and lookahead.type != '$end': lookahead = None errtoken = None # Nuke the pushback stack @@ -354,7 +383,7 @@ class Parser: # at the end of the file. nuke the top entry and generate an error token # Start nuking entries on the stack - if lookahead.type == '$': + if lookahead.type == '$end': # Whoa. We're really hosed here. Bail out return @@ -427,7 +456,7 @@ def validate_file(filename): if not prev: counthash[name] = linen else: - print "%s:%d: Function %s redefined. Previously defined on line %d" % (filename,linen,name,prev) + sys.stderr.write("%s:%d: Function %s redefined. Previously defined on line %d\n" % (filename,linen,name,prev)) noerror = 0 linen += 1 return noerror @@ -435,16 +464,16 @@ def validate_file(filename): # This function looks for functions that might be grammar rules, but which don't have the proper p_suffix. def validate_dict(d): for n,v in d.items(): - if n[0:2] == 'p_' and isinstance(v,types.FunctionType): continue + if n[0:2] == 'p_' and type(v) in (types.FunctionType, types.MethodType): continue if n[0:2] == 't_': continue if n[0:2] == 'p_': - print "yacc: Warning. '%s' not defined as a function" % n - if isinstance(v,types.FunctionType) and v.func_code.co_argcount == 1: + sys.stderr.write("yacc: Warning. '%s' not defined as a function\n" % n) + if 1 and isinstance(v,types.FunctionType) and v.func_code.co_argcount == 1: try: doc = v.__doc__.split(" ") if doc[1] == ':': - print "%s:%d: Warning. Possible grammar rule '%s' defined without p_ prefix." % (v.func_code.co_filename, v.func_code.co_firstlineno,n) + sys.stderr.write("%s:%d: Warning. Possible grammar rule '%s' defined without p_ prefix.\n" % (v.func_code.co_filename, v.func_code.co_firstlineno,n)) except StandardError: pass @@ -520,6 +549,7 @@ def initialize_vars(): # lr_next - Next LR item. Example, if we are ' E -> E . PLUS E' # then lr_next refers to 'E -> E PLUS . E' # lr_index - LR item index (location of the ".") in the prod list. +# lookaheads - LALR lookahead symbols for this item # len - Length of the production (number of symbols on right hand side) # ----------------------------------------------------------------------------- @@ -529,7 +559,11 @@ class Production: setattr(self,k,v) self.lr_index = -1 self.lr0_added = 0 # Flag indicating whether or not added to LR0 closure + self.lr1_added = 0 # Flag indicating whether or not added to LR1 self.usyms = [ ] + self.lookaheads = { } + self.lk_added = { } + self.setnumbers = [ ] def __str__(self): if self.prod: @@ -549,6 +583,8 @@ class Production: p.prod = list(self.prod) p.number = self.number p.lr_index = n + p.lookaheads = { } + p.setnumbers = self.setnumbers p.prod.insert(n,".") p.prod = tuple(p.prod) p.len = len(p.prod) @@ -569,11 +605,8 @@ class Production: class MiniProduction: pass -# Utility function -def is_identifier(s): - for c in s: - if not (c.isalnum() or c == '_'): return 0 - return 1 +# regex matching identifiers +_is_identifier = re.compile(r'^[a-zA-Z0-9_-]+$') # ----------------------------------------------------------------------------- # add_production() @@ -595,27 +628,40 @@ def is_identifier(s): def add_production(f,file,line,prodname,syms): if Terminals.has_key(prodname): - print "%s:%d: Illegal rule name '%s'. Already defined as a token." % (file,line,prodname) + sys.stderr.write("%s:%d: Illegal rule name '%s'. Already defined as a token.\n" % (file,line,prodname)) return -1 if prodname == 'error': - print "%s:%d: Illegal rule name '%s'. error is a reserved word." % (file,line,prodname) + sys.stderr.write("%s:%d: Illegal rule name '%s'. error is a reserved word.\n" % (file,line,prodname)) return -1 - if not is_identifier(prodname): - print "%s:%d: Illegal rule name '%s'" % (file,line,prodname) + if not _is_identifier.match(prodname): + sys.stderr.write("%s:%d: Illegal rule name '%s'\n" % (file,line,prodname)) return -1 - for s in syms: - if not is_identifier(s) and s != '%prec': - print "%s:%d: Illegal name '%s' in rule '%s'" % (file,line,s, prodname) + for x in range(len(syms)): + s = syms[x] + if s[0] in "'\"": + try: + c = eval(s) + if (len(c) > 1): + sys.stderr.write("%s:%d: Literal token %s in rule '%s' may only be a single character\n" % (file,line,s, prodname)) + return -1 + if not Terminals.has_key(c): + Terminals[c] = [] + syms[x] = c + continue + except SyntaxError: + pass + if not _is_identifier.match(s) and s != '%prec': + sys.stderr.write("%s:%d: Illegal name '%s' in rule '%s'\n" % (file,line,s, prodname)) return -1 # See if the rule is already in the rulemap map = "%s -> %s" % (prodname,syms) if Prodmap.has_key(map): m = Prodmap[map] - print "%s:%d: Duplicate rule %s." % (file,line, m) - print "%s:%d: Previous definition at %s:%d" % (file,line, m.file, m.line) + sys.stderr.write("%s:%d: Duplicate rule %s.\n" % (file,line, m)) + sys.stderr.write("%s:%d: Previous definition at %s:%d\n" % (file,line, m.file, m.line)) return -1 p = Production() @@ -640,12 +686,12 @@ def add_production(f,file,line,prodname,syms): try: precname = p.prod[i+1] except IndexError: - print "%s:%d: Syntax error. Nothing follows %%prec." % (p.file,p.line) + sys.stderr.write("%s:%d: Syntax error. Nothing follows %%prec.\n" % (p.file,p.line)) return -1 prec = Precedence.get(precname,None) if not prec: - print "%s:%d: Nothing known about the precedence of '%s'" % (p.file,p.line,precname) + sys.stderr.write("%s:%d: Nothing known about the precedence of '%s'\n" % (p.file,p.line,precname)) return -1 else: p.prec = prec @@ -692,12 +738,17 @@ def add_function(f): file = f.func_code.co_filename error = 0 - if f.func_code.co_argcount > 1: - print "%s:%d: Rule '%s' has too many arguments." % (file,line,f.__name__) + if isinstance(f,types.MethodType): + reqdargs = 2 + else: + reqdargs = 1 + + if f.func_code.co_argcount > reqdargs: + sys.stderr.write("%s:%d: Rule '%s' has too many arguments.\n" % (file,line,f.__name__)) return -1 - if f.func_code.co_argcount < 1: - print "%s:%d: Rule '%s' requires an argument." % (file,line,f.__name__) + if f.func_code.co_argcount < reqdargs: + sys.stderr.write("%s:%d: Rule '%s' requires an argument.\n" % (file,line,f.__name__)) return -1 if f.__doc__: @@ -713,7 +764,7 @@ def add_function(f): if p[0] == '|': # This is a continuation of a previous rule if not lastp: - print "%s:%d: Misplaced '|'." % (file,dline) + sys.stderr.write("%s:%d: Misplaced '|'.\n" % (file,dline)) return -1 prodname = lastp if len(p) > 1: @@ -729,15 +780,19 @@ def add_function(f): else: syms = [ ] if assign != ':' and assign != '::=': - print "%s:%d: Syntax error. Expected ':'" % (file,dline) + sys.stderr.write("%s:%d: Syntax error. Expected ':'\n" % (file,dline)) return -1 + + e = add_production(f,file,dline,prodname,syms) error += e + + except StandardError: - print "%s:%d: Syntax error in rule '%s'" % (file,dline,ps) + sys.stderr.write("%s:%d: Syntax error in rule '%s'\n" % (file,dline,ps)) error -= 1 else: - print "%s:%d: No documentation string specified in function '%s'" % (file,line,f.__name__) + sys.stderr.write("%s:%d: No documentation string specified in function '%s'\n" % (file,line,f.__name__)) return error @@ -757,7 +812,7 @@ def compute_reachable(): for s in Nonterminals.keys(): if not Reachable[s]: - print "yacc: Symbol '%s' is unreachable." % s + sys.stderr.write("yacc: Symbol '%s' is unreachable.\n" % s) def mark_reachable_from(s, Reachable): ''' @@ -788,7 +843,7 @@ def compute_terminates(): for t in Terminals.keys(): Terminates[t] = 1 - Terminates['$'] = 1 + Terminates['$end'] = 1 # Nonterminals: @@ -834,7 +889,7 @@ def compute_terminates(): # so it would be overkill to say that it's also non-terminating. pass else: - print "yacc: Infinite recursion detected for symbol '%s'." % s + sys.stderr.write("yacc: Infinite recursion detected for symbol '%s'.\n" % s) some_error = 1 return some_error @@ -851,7 +906,7 @@ def verify_productions(cycle_check=1): for s in p.prod: if not Prodnames.has_key(s) and not Terminals.has_key(s) and s != 'error': - print "%s:%d: Symbol '%s' used, but not defined as a token or a rule." % (p.file,p.line,s) + sys.stderr.write("%s:%d: Symbol '%s' used, but not defined as a token or a rule.\n" % (p.file,p.line,s)) error = 1 continue @@ -861,7 +916,7 @@ def verify_productions(cycle_check=1): _vf.write("Unused terminals:\n\n") for s,v in Terminals.items(): if s != 'error' and not v: - print "yacc: Warning. Token '%s' defined, but not used." % s + sys.stderr.write("yacc: Warning. Token '%s' defined, but not used.\n" % s) if yaccdebug: _vf.write(" %s\n"% s) unused_tok += 1 @@ -876,19 +931,19 @@ def verify_productions(cycle_check=1): for s,v in Nonterminals.items(): if not v: p = Prodnames[s][0] - print "%s:%d: Warning. Rule '%s' defined, but not used." % (p.file,p.line, s) + sys.stderr.write("%s:%d: Warning. Rule '%s' defined, but not used.\n" % (p.file,p.line, s)) unused_prod += 1 if unused_tok == 1: - print "yacc: Warning. There is 1 unused token." + sys.stderr.write("yacc: Warning. There is 1 unused token.\n") if unused_tok > 1: - print "yacc: Warning. There are %d unused tokens." % unused_tok + sys.stderr.write("yacc: Warning. There are %d unused tokens.\n" % unused_tok) if unused_prod == 1: - print "yacc: Warning. There is 1 unused rule." + sys.stderr.write("yacc: Warning. There is 1 unused rule.\n") if unused_prod > 1: - print "yacc: Warning. There are %d unused rules." % unused_prod + sys.stderr.write("yacc: Warning. There are %d unused rules.\n" % unused_prod) if yaccdebug: _vf.write("\nTerminals, with rules where they appear\n\n") @@ -957,16 +1012,16 @@ def add_precedence(plist): prec = p[0] terms = p[1:] if prec != 'left' and prec != 'right' and prec != 'nonassoc': - print "yacc: Invalid precedence '%s'" % prec + sys.stderr.write("yacc: Invalid precedence '%s'\n" % prec) return -1 for t in terms: if Precedence.has_key(t): - print "yacc: Precedence already specified for terminal '%s'" % t + sys.stderr.write("yacc: Precedence already specified for terminal '%s'\n" % t) error += 1 continue Precedence[t] = (prec,plevel) except: - print "yacc: Invalid precedence table." + sys.stderr.write("yacc: Invalid precedence table.\n") error += 1 return error @@ -1029,14 +1084,14 @@ def first(beta): # that might follow it. Dragon book, p. 189. def compute_follow(start=None): - # Add '$' to the follow list of the start symbol + # Add '$end' to the follow list of the start symbol for k in Nonterminals.keys(): Follow[k] = [ ] if not start: start = Productions[1].name - Follow[start] = [ '$' ] + Follow[start] = [ '$end' ] while 1: didadd = 0 @@ -1078,7 +1133,7 @@ def compute_first1(): for t in Terminals.keys(): First[t] = [t] - First['$'] = ['$'] + First['$end'] = ['$end'] First['#'] = ['#'] # what's this for? # Nonterminals: @@ -1115,12 +1170,14 @@ def compute_first1(): # Global variables for the LR parsing engine def lr_init_vars(): global _lr_action, _lr_goto, _lr_method - global _lr_goto_cache + global _lr_goto_cache, _lr0_cidhash _lr_action = { } # Action table _lr_goto = { } # Goto table _lr_method = "Unknown" # LR method used _lr_goto_cache = { } + _lr0_cidhash = { } + # Compute the LR(0) closure operation on I, where I is a set of LR(0) items. # prodlist is a list of productions. @@ -1178,25 +1235,16 @@ def lr0_goto(I,x): s[id(n)] = s1 gs.append(n) s = s1 - g = s.get('$',None) + g = s.get('$end',None) if not g: if gs: g = lr0_closure(gs) - s['$'] = g + s['$end'] = g else: - s['$'] = gs + s['$end'] = gs _lr_goto_cache[(id(I),x)] = g return g -# Compute the kernel of a set of LR(0) items -def lr0_kernel(I): - KI = [ ] - for p in I: - if p.name == "S'" or p.lr_index > 0 or p.len == 0: - KI.append(p) - - return KI - _lr0_cidhash = { } # Compute the LR(0) sets of item function @@ -1230,35 +1278,386 @@ def lr0_items(): return C # ----------------------------------------------------------------------------- -# slr_parse_table() +# ==== LALR(1) Parsing ==== +# +# LALR(1) parsing is almost exactly the same as SLR except that instead of +# relying upon Follow() sets when performing reductions, a more selective +# lookahead set that incorporates the state of the LR(0) machine is utilized. +# Thus, we mainly just have to focus on calculating the lookahead sets. +# +# The method used here is due to DeRemer and Pennelo (1982). +# +# DeRemer, F. L., and T. J. Pennelo: "Efficient Computation of LALR(1) +# Lookahead Sets", ACM Transactions on Programming Languages and Systems, +# Vol. 4, No. 4, Oct. 1982, pp. 615-649 +# +# Further details can also be found in: +# +# J. Tremblay and P. Sorenson, "The Theory and Practice of Compiler Writing", +# McGraw-Hill Book Company, (1985). +# +# Note: This implementation is a complete replacement of the LALR(1) +# implementation in PLY-1.x releases. That version was based on +# a less efficient algorithm and it had bugs in its implementation. +# ----------------------------------------------------------------------------- + +# ----------------------------------------------------------------------------- +# compute_nullable_nonterminals() +# +# Creates a dictionary containing all of the non-terminals that might produce +# an empty production. +# ----------------------------------------------------------------------------- + +def compute_nullable_nonterminals(): + nullable = {} + num_nullable = 0 + while 1: + for p in Productions[1:]: + if p.len == 0: + nullable[p.name] = 1 + continue + for t in p.prod: + if not nullable.has_key(t): break + else: + nullable[p.name] = 1 + if len(nullable) == num_nullable: break + num_nullable = len(nullable) + return nullable + +# ----------------------------------------------------------------------------- +# find_nonterminal_trans(C) +# +# Given a set of LR(0) items, this functions finds all of the non-terminal +# transitions. These are transitions in which a dot appears immediately before +# a non-terminal. Returns a list of tuples of the form (state,N) where state +# is the state number and N is the nonterminal symbol. +# +# The input C is the set of LR(0) items. +# ----------------------------------------------------------------------------- + +def find_nonterminal_transitions(C): + trans = [] + for state in range(len(C)): + for p in C[state]: + if p.lr_index < p.len - 1: + t = (state,p.prod[p.lr_index+1]) + if Nonterminals.has_key(t[1]): + if t not in trans: trans.append(t) + state = state + 1 + return trans + +# ----------------------------------------------------------------------------- +# dr_relation() +# +# Computes the DR(p,A) relationships for non-terminal transitions. The input +# is a tuple (state,N) where state is a number and N is a nonterminal symbol. +# +# Returns a list of terminals. +# ----------------------------------------------------------------------------- + +def dr_relation(C,trans,nullable): + dr_set = { } + state,N = trans + terms = [] + + g = lr0_goto(C[state],N) + for p in g: + if p.lr_index < p.len - 1: + a = p.prod[p.lr_index+1] + if Terminals.has_key(a): + if a not in terms: terms.append(a) + + # This extra bit is to handle the start state + if state == 0 and N == Productions[0].prod[0]: + terms.append('$end') + + return terms + +# ----------------------------------------------------------------------------- +# reads_relation() +# +# Computes the READS() relation (p,A) READS (t,C). +# ----------------------------------------------------------------------------- + +def reads_relation(C, trans, empty): + # Look for empty transitions + rel = [] + state, N = trans + + g = lr0_goto(C[state],N) + j = _lr0_cidhash.get(id(g),-1) + for p in g: + if p.lr_index < p.len - 1: + a = p.prod[p.lr_index + 1] + if empty.has_key(a): + rel.append((j,a)) + + return rel + +# ----------------------------------------------------------------------------- +# compute_lookback_includes() +# +# Determines the lookback and includes relations +# +# LOOKBACK: +# +# This relation is determined by running the LR(0) state machine forward. +# For example, starting with a production "N : . A B C", we run it forward +# to obtain "N : A B C ." We then build a relationship between this final +# state and the starting state. These relationships are stored in a dictionary +# lookdict. +# +# INCLUDES: +# +# Computes the INCLUDE() relation (p,A) INCLUDES (p',B). +# +# This relation is used to determine non-terminal transitions that occur +# inside of other non-terminal transition states. (p,A) INCLUDES (p', B) +# if the following holds: # -# This function constructs an SLR table. +# B -> LAT, where T -> epsilon and p' -L-> p +# +# L is essentially a prefix (which may be empty), T is a suffix that must be +# able to derive an empty string. State p' must lead to state p with the string L. +# +# ----------------------------------------------------------------------------- + +def compute_lookback_includes(C,trans,nullable): + + lookdict = {} # Dictionary of lookback relations + includedict = {} # Dictionary of include relations + + # Make a dictionary of non-terminal transitions + dtrans = {} + for t in trans: + dtrans[t] = 1 + + # Loop over all transitions and compute lookbacks and includes + for state,N in trans: + lookb = [] + includes = [] + for p in C[state]: + if p.name != N: continue + + # Okay, we have a name match. We now follow the production all the way + # through the state machine until we get the . on the right hand side + + lr_index = p.lr_index + j = state + while lr_index < p.len - 1: + lr_index = lr_index + 1 + t = p.prod[lr_index] + + # Check to see if this symbol and state are a non-terminal transition + if dtrans.has_key((j,t)): + # Yes. Okay, there is some chance that this is an includes relation + # the only way to know for certain is whether the rest of the + # production derives empty + + li = lr_index + 1 + while li < p.len: + if Terminals.has_key(p.prod[li]): break # No forget it + if not nullable.has_key(p.prod[li]): break + li = li + 1 + else: + # Appears to be a relation between (j,t) and (state,N) + includes.append((j,t)) + + g = lr0_goto(C[j],t) # Go to next set + j = _lr0_cidhash.get(id(g),-1) # Go to next state + + # When we get here, j is the final state, now we have to locate the production + for r in C[j]: + if r.name != p.name: continue + if r.len != p.len: continue + i = 0 + # This look is comparing a production ". A B C" with "A B C ." + while i < r.lr_index: + if r.prod[i] != p.prod[i+1]: break + i = i + 1 + else: + lookb.append((j,r)) + for i in includes: + if not includedict.has_key(i): includedict[i] = [] + includedict[i].append((state,N)) + lookdict[(state,N)] = lookb + + return lookdict,includedict + # ----------------------------------------------------------------------------- -def slr_parse_table(): +# digraph() +# traverse() +# +# The following two functions are used to compute set valued functions +# of the form: +# +# F(x) = F'(x) U U{F(y) | x R y} +# +# This is used to compute the values of Read() sets as well as FOLLOW sets +# in LALR(1) generation. +# +# Inputs: X - An input set +# R - A relation +# FP - Set-valued function +# ------------------------------------------------------------------------------ + +def digraph(X,R,FP): + N = { } + for x in X: + N[x] = 0 + stack = [] + F = { } + for x in X: + if N[x] == 0: traverse(x,N,stack,F,X,R,FP) + return F + +def traverse(x,N,stack,F,X,R,FP): + stack.append(x) + d = len(stack) + N[x] = d + F[x] = FP(x) # F(X) <- F'(x) + + rel = R(x) # Get y's related to x + for y in rel: + if N[y] == 0: + traverse(y,N,stack,F,X,R,FP) + N[x] = min(N[x],N[y]) + for a in F.get(y,[]): + if a not in F[x]: F[x].append(a) + if N[x] == d: + N[stack[-1]] = sys.maxint + F[stack[-1]] = F[x] + element = stack.pop() + while element != x: + N[stack[-1]] = sys.maxint + F[stack[-1]] = F[x] + element = stack.pop() + +# ----------------------------------------------------------------------------- +# compute_read_sets() +# +# Given a set of LR(0) items, this function computes the read sets. +# +# Inputs: C = Set of LR(0) items +# ntrans = Set of nonterminal transitions +# nullable = Set of empty transitions +# +# Returns a set containing the read sets +# ----------------------------------------------------------------------------- + +def compute_read_sets(C, ntrans, nullable): + FP = lambda x: dr_relation(C,x,nullable) + R = lambda x: reads_relation(C,x,nullable) + F = digraph(ntrans,R,FP) + return F + +# ----------------------------------------------------------------------------- +# compute_follow_sets() +# +# Given a set of LR(0) items, a set of non-terminal transitions, a readset, +# and an include set, this function computes the follow sets +# +# Follow(p,A) = Read(p,A) U U {Follow(p',B) | (p,A) INCLUDES (p',B)} +# +# Inputs: +# ntrans = Set of nonterminal transitions +# readsets = Readset (previously computed) +# inclsets = Include sets (previously computed) +# +# Returns a set containing the follow sets +# ----------------------------------------------------------------------------- + +def compute_follow_sets(ntrans,readsets,inclsets): + FP = lambda x: readsets[x] + R = lambda x: inclsets.get(x,[]) + F = digraph(ntrans,R,FP) + return F + +# ----------------------------------------------------------------------------- +# add_lookaheads() +# +# Attaches the lookahead symbols to grammar rules. +# +# Inputs: lookbacks - Set of lookback relations +# followset - Computed follow set +# +# This function directly attaches the lookaheads to productions contained +# in the lookbacks set +# ----------------------------------------------------------------------------- + +def add_lookaheads(lookbacks,followset): + for trans,lb in lookbacks.items(): + # Loop over productions in lookback + for state,p in lb: + if not p.lookaheads.has_key(state): + p.lookaheads[state] = [] + f = followset.get(trans,[]) + for a in f: + if a not in p.lookaheads[state]: p.lookaheads[state].append(a) + +# ----------------------------------------------------------------------------- +# add_lalr_lookaheads() +# +# This function does all of the work of adding lookahead information for use +# with LALR parsing +# ----------------------------------------------------------------------------- + +def add_lalr_lookaheads(C): + # Determine all of the nullable nonterminals + nullable = compute_nullable_nonterminals() + + # Find all non-terminal transitions + trans = find_nonterminal_transitions(C) + + # Compute read sets + readsets = compute_read_sets(C,trans,nullable) + + # Compute lookback/includes relations + lookd, included = compute_lookback_includes(C,trans,nullable) + + # Compute LALR FOLLOW sets + followsets = compute_follow_sets(trans,readsets,included) + + # Add all of the lookaheads + add_lookaheads(lookd,followsets) + +# ----------------------------------------------------------------------------- +# lr_parse_table() +# +# This function constructs the parse tables for SLR or LALR +# ----------------------------------------------------------------------------- +def lr_parse_table(method): global _lr_method goto = _lr_goto # Goto array action = _lr_action # Action array actionp = { } # Action production array (temporary) - _lr_method = "SLR" + _lr_method = method n_srconflict = 0 n_rrconflict = 0 if yaccdebug: - _vf.write("\n\nParsing method: SLR\n\n") + sys.stderr.write("yacc: Generating %s parsing table...\n" % method) + _vf.write("\n\nParsing method: %s\n\n" % method) # Step 1: Construct C = { I0, I1, ... IN}, collection of LR(0) items # This determines the number of states C = lr0_items() + if method == 'LALR': + add_lalr_lookaheads(C) + + # Build the parser table, state by state st = 0 for I in C: # Loop over each production in I actlist = [ ] # List of actions - + st_action = { } + st_actionp = { } + st_goto = { } if yaccdebug: _vf.write("\nstate %d\n\n" % st) for p in I: @@ -1267,37 +1666,41 @@ def slr_parse_table(): for p in I: try: - if p.prod[-1] == ".": + if p.len == p.lr_index + 1: if p.name == "S'": # Start symbol. Accept! - action[st,"$"] = 0 - actionp[st,"$"] = p + st_action["$end"] = 0 + st_actionp["$end"] = p else: # We are at the end of a production. Reduce! - for a in Follow[p.name]: + if method == 'LALR': + laheads = p.lookaheads[st] + else: + laheads = Follow[p.name] + for a in laheads: actlist.append((a,p,"reduce using rule %d (%s)" % (p.number,p))) - r = action.get((st,a),None) + r = st_action.get(a,None) if r is not None: # Whoa. Have a shift/reduce or reduce/reduce conflict if r > 0: # Need to decide on shift or reduce here # By default we favor shifting. Need to add # some precedence rules here. - sprec,slevel = Productions[actionp[st,a].number].prec + sprec,slevel = Productions[st_actionp[a].number].prec rprec,rlevel = Precedence.get(a,('right',0)) if (slevel < rlevel) or ((slevel == rlevel) and (rprec == 'left')): # We really need to reduce here. - action[st,a] = -p.number - actionp[st,a] = p + st_action[a] = -p.number + st_actionp[a] = p if not slevel and not rlevel: _vfc.write("shift/reduce conflict in state %d resolved as reduce.\n" % st) _vf.write(" ! shift/reduce conflict for %s resolved as reduce.\n" % a) n_srconflict += 1 elif (slevel == rlevel) and (rprec == 'nonassoc'): - action[st,a] = None + st_action[a] = None else: # Hmmm. Guess we'll keep the shift - if not slevel and not rlevel: + if not rlevel: _vfc.write("shift/reduce conflict in state %d resolved as shift.\n" % st) _vf.write(" ! shift/reduce conflict for %s resolved as shift.\n" % a) n_srconflict +=1 @@ -1307,17 +1710,17 @@ def slr_parse_table(): oldp = Productions[-r] pp = Productions[p.number] if oldp.line > pp.line: - action[st,a] = -p.number - actionp[st,a] = p - # print "Reduce/reduce conflict in state %d" % st + st_action[a] = -p.number + st_actionp[a] = p + # sys.stderr.write("Reduce/reduce conflict in state %d\n" % st) n_rrconflict += 1 - _vfc.write("reduce/reduce conflict in state %d resolved using rule %d (%s).\n" % (st, actionp[st,a].number, actionp[st,a])) - _vf.write(" ! reduce/reduce conflict for %s resolved using rule %d (%s).\n" % (a,actionp[st,a].number, actionp[st,a])) + _vfc.write("reduce/reduce conflict in state %d resolved using rule %d (%s).\n" % (st, st_actionp[a].number, st_actionp[a])) + _vf.write(" ! reduce/reduce conflict for %s resolved using rule %d (%s).\n" % (a,st_actionp[a].number, st_actionp[a])) else: - print "Unknown conflict in state %d" % st + sys.stderr.write("Unknown conflict in state %d\n" % st) else: - action[st,a] = -p.number - actionp[st,a] = p + st_action[a] = -p.number + st_actionp[a] = p else: i = p.lr_index a = p.prod[i+1] # Get symbol right after the "." @@ -1327,29 +1730,29 @@ def slr_parse_table(): if j >= 0: # We are in a shift state actlist.append((a,p,"shift and go to state %d" % j)) - r = action.get((st,a),None) + r = st_action.get(a,None) if r is not None: # Whoa have a shift/reduce or shift/shift conflict if r > 0: if r != j: - print "Shift/shift conflict in state %d" % st + sys.stderr.write("Shift/shift conflict in state %d\n" % st) elif r < 0: # Do a precedence check. # - if precedence of reduce rule is higher, we reduce. # - if precedence of reduce is same and left assoc, we reduce. # - otherwise we shift - rprec,rlevel = Productions[actionp[st,a].number].prec + rprec,rlevel = Productions[st_actionp[a].number].prec sprec,slevel = Precedence.get(a,('right',0)) if (slevel > rlevel) or ((slevel == rlevel) and (rprec != 'left')): # We decide to shift here... highest precedence to shift - action[st,a] = j - actionp[st,a] = p - if not slevel and not rlevel: + st_action[a] = j + st_actionp[a] = p + if not rlevel: n_srconflict += 1 _vfc.write("shift/reduce conflict in state %d resolved as shift.\n" % st) _vf.write(" ! shift/reduce conflict for %s resolved as shift.\n" % a) elif (slevel == rlevel) and (rprec == 'nonassoc'): - action[st,a] = None + st_action[a] = None else: # Hmmm. Guess we'll keep the reduce if not slevel and not rlevel: @@ -1358,25 +1761,30 @@ def slr_parse_table(): _vf.write(" ! shift/reduce conflict for %s resolved as reduce.\n" % a) else: - print "Unknown conflict in state %d" % st + sys.stderr.write("Unknown conflict in state %d\n" % st) else: - action[st,a] = j - actionp[st,a] = p + st_action[a] = j + st_actionp[a] = p except StandardError,e: - raise YaccError, "Hosed in slr_parse_table", e + print sys.exc_info() + raise YaccError, "Hosed in lr_parse_table" # Print the actions associated with each terminal if yaccdebug: + _actprint = { } for a,p,m in actlist: - if action.has_key((st,a)): - if p is actionp[st,a]: + if st_action.has_key(a): + if p is st_actionp[a]: _vf.write(" %-15s %s\n" % (a,m)) + _actprint[(a,m)] = 1 _vf.write("\n") for a,p,m in actlist: - if action.has_key((st,a)): - if p is not actionp[st,a]: - _vf.write(" ! %-15s [ %s ]\n" % (a,m)) + if st_action.has_key(a): + if p is not st_actionp[a]: + if not _actprint.has_key((a,m)): + _vf.write(" ! %-15s [ %s ]\n" % (a,m)) + _actprint[(a,m)] = 1 # Construct the goto table for this state if yaccdebug: @@ -1390,82 +1798,25 @@ def slr_parse_table(): g = lr0_goto(I,n) j = _lr0_cidhash.get(id(g),-1) if j >= 0: - goto[st,n] = j + st_goto[n] = j if yaccdebug: - _vf.write(" %-15s shift and go to state %d\n" % (n,j)) + _vf.write(" %-30s shift and go to state %d\n" % (n,j)) - st += 1 + action[st] = st_action + actionp[st] = st_actionp + goto[st] = st_goto - if n_srconflict == 1: - print "yacc: %d shift/reduce conflict" % n_srconflict - if n_srconflict > 1: - print "yacc: %d shift/reduce conflicts" % n_srconflict - if n_rrconflict == 1: - print "yacc: %d reduce/reduce conflict" % n_rrconflict - if n_rrconflict > 1: - print "yacc: %d reduce/reduce conflicts" % n_rrconflict - - -# ----------------------------------------------------------------------------- -# ==== LALR(1) Parsing ==== -# **** UNFINISHED! 6/16/01 -# ----------------------------------------------------------------------------- - - -# Compute the lr1_closure of a set I. I is a list of tuples (p,a) where -# p is a LR0 item and a is a terminal - -_lr1_add_count = 0 - -def lr1_closure(I): - global _lr1_add_count - - _lr1_add_count += 1 - - J = I[:] - - # Loop over items (p,a) in I. - ji = 0 - while ji < len(J): - p,a = J[ji] - # p = [ A -> alpha . B beta] - - # For each production B -> gamma - for B in p.lr1_after: - f = tuple(p.lr1_beta + (a,)) - - # For each terminal b in first(Beta a) - for b in first(f): - # Check if (B -> . gamma, b) is in J - # Only way this can happen is if the add count mismatches - pn = B.lr_next - if pn.lr_added.get(b,0) == _lr1_add_count: continue - pn.lr_added[b] = _lr1_add_count - J.append((pn,b)) - ji += 1 - - return J - -def lalr_parse_table(): - - # Compute some lr1 information about all of the productions - for p in LRitems: - try: - after = p.prod[p.lr_index + 1] - p.lr1_after = Prodnames[after] - p.lr1_beta = p.prod[p.lr_index + 2:] - except LookupError: - p.lr1_after = [ ] - p.lr1_beta = [ ] - p.lr_added = { } - - # Compute the LR(0) items - C = lr0_items() - CK = [] - for I in C: - CK.append(lr0_kernel(I)) + st += 1 - print CK + if yaccdebug: + if n_srconflict == 1: + sys.stderr.write("yacc: %d shift/reduce conflict\n" % n_srconflict) + if n_srconflict > 1: + sys.stderr.write("yacc: %d shift/reduce conflicts\n" % n_srconflict) + if n_rrconflict == 1: + sys.stderr.write("yacc: %d reduce/reduce conflict\n" % n_rrconflict) + if n_rrconflict > 1: + sys.stderr.write("yacc: %d reduce/reduce conflicts\n" % n_rrconflict) # ----------------------------------------------------------------------------- # ==== LR Utility functions ==== @@ -1477,8 +1828,8 @@ def lalr_parse_table(): # This function writes the LR parsing tables to a file # ----------------------------------------------------------------------------- -def lr_write_tables(modulename=tab_module): - filename = modulename + ".py" +def lr_write_tables(modulename=tab_module,outputdir=''): + filename = os.path.join(outputdir,modulename) + ".py" try: f = open(filename,"w") @@ -1498,13 +1849,14 @@ _lr_signature = %s if smaller: items = { } - for k,v in _lr_action.items(): - i = items.get(k[1]) - if not i: - i = ([],[]) - items[k[1]] = i - i[0].append(k[0]) - i[1].append(v) + for s,nd in _lr_action.items(): + for name,v in nd.items(): + i = items.get(name) + if not i: + i = ([],[]) + items[name] = i + i[0].append(s) + i[1].append(v) f.write("\n_lr_action_items = {") for k,v in items.items(): @@ -1522,7 +1874,8 @@ _lr_signature = %s _lr_action = { } for _k, _v in _lr_action_items.items(): for _x,_y in zip(_v[0],_v[1]): - _lr_action[(_x,_k)] = _y + if not _lr_action.has_key(_x): _lr_action[_x] = { } + _lr_action[_x][_k] = _y del _lr_action_items """) @@ -1536,13 +1889,14 @@ del _lr_action_items # Factor out names to try and make smaller items = { } - for k,v in _lr_goto.items(): - i = items.get(k[1]) - if not i: - i = ([],[]) - items[k[1]] = i - i[0].append(k[0]) - i[1].append(v) + for s,nd in _lr_goto.items(): + for name,v in nd.items(): + i = items.get(name) + if not i: + i = ([],[]) + items[name] = i + i[0].append(s) + i[1].append(v) f.write("\n_lr_goto_items = {") for k,v in items.items(): @@ -1560,7 +1914,8 @@ del _lr_action_items _lr_goto = { } for _k, _v in _lr_goto_items.items(): for _x,_y in zip(_v[0],_v[1]): - _lr_goto[(_x,_k)] = _y + if not _lr_goto.has_key(_x): _lr_goto[_x] = { } + _lr_goto[_x][_k] = _y del _lr_goto_items """) else: @@ -1580,11 +1935,12 @@ del _lr_goto_items else: f.write(" None,\n") f.write("]\n") + f.close() except IOError,e: - print "Unable to create '%s'" % filename - print e + print >>sys.stderr, "Unable to create '%s'" % filename + print >>sys.stderr, e return def lr_read_tables(module=tab_module,optimize=0): @@ -1604,13 +1960,14 @@ def lr_read_tables(module=tab_module,optimize=0): except (ImportError,AttributeError): return 0 + # ----------------------------------------------------------------------------- # yacc(module) # # Build the parser module # ----------------------------------------------------------------------------- -def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, start=None, check_recursion=1, optimize=0): +def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, start=None, check_recursion=1, optimize=0,write_tables=1,debugfile=debug_file,outputdir=''): global yaccdebug yaccdebug = debug @@ -1618,18 +1975,25 @@ def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, files = { } error = 0 - # Add starting symbol to signature - if start: - Signature.update(start) - # Try to figure out what module we are working with + # Add parsing method to signature + Signature.update(method) + + # If a "module" parameter was supplied, extract its dictionary. + # Note: a module may in fact be an instance as well. + if module: # User supplied a module object. - if not isinstance(module, types.ModuleType): + if isinstance(module, types.ModuleType): + ldict = module.__dict__ + elif isinstance(module, _INSTANCETYPE): + _items = [(k,getattr(module,k)) for k in dir(module)] + ldict = { } + for i in _items: + ldict[i[0]] = i[1] + else: raise ValueError,"Expected a module" - ldict = module.__dict__ - else: # No module given. We might be able to get information from the caller. # Throw an exception and unwind the traceback to get the globals @@ -1642,6 +2006,12 @@ def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, f = f.f_back # Walk out to our calling function ldict = f.f_globals # Grab its globals dictionary + # Add starting symbol to signature + if not start: + start = ldict.get("start",None) + if start: + Signature.update(start) + # If running in optimized mode. We're going to if (optimize and lr_read_tables(tabmodule,1)): @@ -1662,7 +2032,10 @@ def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, else: # Get the tokens map - tokens = ldict.get("tokens",None) + if (module and isinstance(module,_INSTANCETYPE)): + tokens = getattr(module,"tokens",None) + else: + tokens = ldict.get("tokens",None) if not tokens: raise YaccError,"module does not define a list 'tokens'" @@ -1682,7 +2055,7 @@ def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, v1 = [x.split(".") for x in v] Requires[r] = v1 except StandardError: - print "Invalid specification for rule '%s' in require. Expected a list of strings" % r + print >>sys.stderr, "Invalid specification for rule '%s' in require. Expected a list of strings" % r # Build the dictionary of terminals. We a record a 0 in the @@ -1690,12 +2063,12 @@ def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, # used in the grammar if 'error' in tokens: - print "yacc: Illegal token 'error'. Is a reserved word." + print >>sys.stderr, "yacc: Illegal token 'error'. Is a reserved word." raise YaccError,"Illegal token name" for n in tokens: if Terminals.has_key(n): - print "yacc: Warning. Token '%s' multiply defined." % n + print >>sys.stderr, "yacc: Warning. Token '%s' multiply defined." % n Terminals[n] = [ ] Terminals['error'] = [ ] @@ -1715,22 +2088,26 @@ def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, # Look for error handler ef = ldict.get('p_error',None) if ef: - if not isinstance(ef,types.FunctionType): - raise YaccError,"'p_error' defined, but is not a function." + if isinstance(ef,types.FunctionType): + ismethod = 0 + elif isinstance(ef, types.MethodType): + ismethod = 1 + else: + raise YaccError,"'p_error' defined, but is not a function or method." eline = ef.func_code.co_firstlineno efile = ef.func_code.co_filename files[efile] = None - if (ef.func_code.co_argcount != 1): + if (ef.func_code.co_argcount != 1+ismethod): raise YaccError,"%s:%d: p_error() requires 1 argument." % (efile,eline) global Errorfunc Errorfunc = ef else: - print "yacc: Warning. no p_error() function is defined." + print >>sys.stderr, "yacc: Warning. no p_error() function is defined." # Get the list of built-in functions with p_ prefix symbols = [ldict[f] for f in ldict.keys() - if (isinstance(ldict[f],types.FunctionType) and ldict[f].__name__[:2] == 'p_' + if (type(ldict[f]) in (types.FunctionType, types.MethodType) and ldict[f].__name__[:2] == 'p_' and ldict[f].__name__ != 'p_error')] # Check for non-empty symbols @@ -1773,7 +2150,7 @@ def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, augment_grammar(start) error = verify_productions(cycle_check=check_recursion) otherfunc = [ldict[f] for f in ldict.keys() - if (isinstance(ldict[f],types.FunctionType) and ldict[f].__name__[:2] != 'p_')] + if (type(f) in (types.FunctionType,types.MethodType) and ldict[f].__name__[:2] != 'p_')] if error: raise YaccError,"Unable to construct parser." @@ -1782,25 +2159,23 @@ def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, compute_first1() compute_follow(start) - if method == 'SLR': - slr_parse_table() - elif method == 'LALR1': - lalr_parse_table() - return + if method in ['SLR','LALR']: + lr_parse_table(method) else: raise YaccError, "Unknown parsing method '%s'" % method - lr_write_tables(tabmodule) + if write_tables: + lr_write_tables(tabmodule,outputdir) if yaccdebug: try: - f = open(debug_file,"w") + f = open(os.path.join(outputdir,debugfile),"w") f.write(_vfc.getvalue()) f.write("\n\n") f.write(_vf.getvalue()) f.close() except IOError,e: - print "yacc: can't create '%s'" % debug_file,e + print >>sys.stderr, "yacc: can't create '%s'" % debugfile,e # Made it here. Create a parser object and set up its internal state. # Set global parse() method to bound method of parser object. @@ -1816,6 +2191,9 @@ def yacc(method=default_lr, debug=yaccdebug, module=None, tabmodule=tab_module, global parse parse = p.parse + global parser + parser = p + # Clean up all of the globals we created if (not optimize): yacc_cleanup() diff --git a/ext/ply/setup.py b/ext/ply/setup.py new file mode 100644 index 000000000..f743ac78c --- /dev/null +++ b/ext/ply/setup.py @@ -0,0 +1,27 @@ +from distutils.core import setup + +setup(name = "ply", + description="Python Lex & Yacc", + long_description = """ +PLY is yet another implementation of lex and yacc for Python. Although several other +parsing tools are available for Python, there are several reasons why you might +want to take a look at PLY: + +It's implemented entirely in Python. + +It uses LR-parsing which is reasonably efficient and well suited for larger grammars. + +PLY provides most of the standard lex/yacc features including support for empty +productions, precedence rules, error recovery, and support for ambiguous grammars. + +PLY is extremely easy to use and provides very extensive error checking. +""", + license="""Lesser GPL (LGPL)""", + version = "2.3", + author = "David Beazley", + author_email = "dave@dabeaz.com", + maintainer = "David Beazley", + maintainer_email = "dave@dabeaz.com", + url = "http://www.dabeaz.com/ply/", + packages = ['ply'], + ) diff --git a/ext/ply/test/README b/ext/ply/test/README index bca748497..aac12b058 100644 --- a/ext/ply/test/README +++ b/ext/ply/test/README @@ -4,6 +4,8 @@ conditions. To run: $ python testlex.py . $ python testyacc.py . -(make sure lex.py and yacc.py exist in this directory before -running the tests). +The tests can also be run using the Python unittest module. + $ python rununit.py + +The script 'cleanup.sh' cleans up this directory to its original state. diff --git a/ext/ply/test/calclex.py b/ext/ply/test/calclex.py index f8eb91a09..d3e873266 100644 --- a/ext/ply/test/calclex.py +++ b/ext/ply/test/calclex.py @@ -1,6 +1,10 @@ # ----------------------------------------------------------------------------- # calclex.py # ----------------------------------------------------------------------------- +import sys + +sys.path.append("..") +import ply.lex as lex tokens = ( 'NAME','NUMBER', @@ -36,10 +40,9 @@ def t_newline(t): def t_error(t): print "Illegal character '%s'" % t.value[0] - t.skip(1) + t.lexer.skip(1) # Build the lexer -import lex lex.lex() diff --git a/ext/ply/test/cleanup.sh b/ext/ply/test/cleanup.sh new file mode 100644 index 000000000..d7d99b65f --- /dev/null +++ b/ext/ply/test/cleanup.sh @@ -0,0 +1,4 @@ +#!/bin/sh + +rm -f *~ *.pyc *.dif *.out + diff --git a/ext/ply/test/lex_doc1.exp b/ext/ply/test/lex_doc1.exp index 29381911d..5b63c1e91 100644 --- a/ext/ply/test/lex_doc1.exp +++ b/ext/ply/test/lex_doc1.exp @@ -1 +1 @@ -./lex_doc1.py:15: No regular expression defined for rule 't_NUMBER' +./lex_doc1.py:18: No regular expression defined for rule 't_NUMBER' diff --git a/ext/ply/test/lex_doc1.py b/ext/ply/test/lex_doc1.py index fb0fb885e..3951b5c5d 100644 --- a/ext/ply/test/lex_doc1.py +++ b/ext/ply/test/lex_doc1.py @@ -2,7 +2,10 @@ # # Missing documentation string -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", diff --git a/ext/ply/test/lex_dup1.exp b/ext/ply/test/lex_dup1.exp index 22bca3190..2098a40e5 100644 --- a/ext/ply/test/lex_dup1.exp +++ b/ext/ply/test/lex_dup1.exp @@ -1,2 +1,2 @@ -./lex_dup1.py:17: Rule t_NUMBER redefined. Previously defined on line 15 +./lex_dup1.py:20: Rule t_NUMBER redefined. Previously defined on line 18 SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_dup1.py b/ext/ply/test/lex_dup1.py index 88bbe00e9..68f80925b 100644 --- a/ext/ply/test/lex_dup1.py +++ b/ext/ply/test/lex_dup1.py @@ -2,7 +2,10 @@ # # Duplicated rule specifiers -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -19,7 +22,6 @@ t_NUMBER = r'\d+' def t_error(t): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_dup2.exp b/ext/ply/test/lex_dup2.exp index 883bdad46..d327cfe47 100644 --- a/ext/ply/test/lex_dup2.exp +++ b/ext/ply/test/lex_dup2.exp @@ -1,2 +1,2 @@ -./lex_dup2.py:19: Rule t_NUMBER redefined. Previously defined on line 15 +./lex_dup2.py:22: Rule t_NUMBER redefined. Previously defined on line 18 SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_dup2.py b/ext/ply/test/lex_dup2.py index 65e0b21a2..f4d346e75 100644 --- a/ext/ply/test/lex_dup2.py +++ b/ext/ply/test/lex_dup2.py @@ -2,7 +2,10 @@ # # Duplicated rule specifiers -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -23,7 +26,6 @@ def t_NUMBER(t): def t_error(t): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_dup3.exp b/ext/ply/test/lex_dup3.exp index 916612aa1..ec0680c6c 100644 --- a/ext/ply/test/lex_dup3.exp +++ b/ext/ply/test/lex_dup3.exp @@ -1,2 +1,2 @@ -./lex_dup3.py:17: Rule t_NUMBER redefined. Previously defined on line 15 +./lex_dup3.py:20: Rule t_NUMBER redefined. Previously defined on line 18 SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_dup3.py b/ext/ply/test/lex_dup3.py index 424101823..e17b52059 100644 --- a/ext/ply/test/lex_dup3.py +++ b/ext/ply/test/lex_dup3.py @@ -2,7 +2,10 @@ # # Duplicated rule specifiers -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -21,7 +24,6 @@ def t_NUMBER(t): def t_error(t): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_empty.py b/ext/ply/test/lex_empty.py index 6472832f1..96625f732 100644 --- a/ext/ply/test/lex_empty.py +++ b/ext/ply/test/lex_empty.py @@ -2,7 +2,10 @@ # # No rules defined -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -10,7 +13,6 @@ tokens = [ "NUMBER", ] -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_error1.py b/ext/ply/test/lex_error1.py index ed7980346..a99d9bedf 100644 --- a/ext/ply/test/lex_error1.py +++ b/ext/ply/test/lex_error1.py @@ -2,7 +2,10 @@ # # Missing t_error() rule -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -14,7 +17,6 @@ t_PLUS = r'\+' t_MINUS = r'-' t_NUMBER = r'\d+' -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_error2.py b/ext/ply/test/lex_error2.py index 80020f72b..a59c8d454 100644 --- a/ext/ply/test/lex_error2.py +++ b/ext/ply/test/lex_error2.py @@ -2,7 +2,10 @@ # # t_error defined, but not function -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -16,7 +19,6 @@ t_NUMBER = r'\d+' t_error = "foo" -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_error3.exp b/ext/ply/test/lex_error3.exp index 936828f93..1b482bf62 100644 --- a/ext/ply/test/lex_error3.exp +++ b/ext/ply/test/lex_error3.exp @@ -1,2 +1,2 @@ -./lex_error3.py:17: Rule 't_error' requires an argument. +./lex_error3.py:20: Rule 't_error' requires an argument. SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_error3.py b/ext/ply/test/lex_error3.py index 46facf589..584600f3b 100644 --- a/ext/ply/test/lex_error3.py +++ b/ext/ply/test/lex_error3.py @@ -2,7 +2,10 @@ # # t_error defined as function, but with wrong # args -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -17,7 +20,6 @@ t_NUMBER = r'\d+' def t_error(): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_error4.exp b/ext/ply/test/lex_error4.exp index 242516576..98505a232 100644 --- a/ext/ply/test/lex_error4.exp +++ b/ext/ply/test/lex_error4.exp @@ -1,2 +1,2 @@ -./lex_error4.py:17: Rule 't_error' has too many arguments. +./lex_error4.py:20: Rule 't_error' has too many arguments. SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_error4.py b/ext/ply/test/lex_error4.py index d777fee84..d05de7490 100644 --- a/ext/ply/test/lex_error4.py +++ b/ext/ply/test/lex_error4.py @@ -2,7 +2,10 @@ # # t_error defined as function, but too many args -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -17,7 +20,6 @@ t_NUMBER = r'\d+' def t_error(t,s): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_hedit.exp b/ext/ply/test/lex_hedit.exp index 0b09827c6..7b27dcb57 100644 --- a/ext/ply/test/lex_hedit.exp +++ b/ext/ply/test/lex_hedit.exp @@ -1,3 +1,3 @@ -(H_EDIT_DESCRIPTOR,'abc',1) -(H_EDIT_DESCRIPTOR,'abcdefghij',1) -(H_EDIT_DESCRIPTOR,'xy',1) +(H_EDIT_DESCRIPTOR,'abc',1,0) +(H_EDIT_DESCRIPTOR,'abcdefghij',1,6) +(H_EDIT_DESCRIPTOR,'xy',1,20) diff --git a/ext/ply/test/lex_hedit.py b/ext/ply/test/lex_hedit.py index 68f9fcbd1..9949549c4 100644 --- a/ext/ply/test/lex_hedit.py +++ b/ext/ply/test/lex_hedit.py @@ -13,6 +13,10 @@ # This example shows how to modify the state of the lexer to parse # such tokens # ----------------------------------------------------------------------------- +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = ( 'H_EDIT_DESCRIPTOR', @@ -33,10 +37,9 @@ def t_H_EDIT_DESCRIPTOR(t): def t_error(t): print "Illegal character '%s'" % t.value[0] - t.skip(1) + t.lexer.skip(1) # Build the lexer -import lex lex.lex() lex.runmain(data="3Habc 10Habcdefghij 2Hxy") diff --git a/ext/ply/test/lex_ignore.exp b/ext/ply/test/lex_ignore.exp index c3b04a154..6b6b67cdc 100644 --- a/ext/ply/test/lex_ignore.exp +++ b/ext/ply/test/lex_ignore.exp @@ -1,2 +1,7 @@ -./lex_ignore.py:17: Rule 't_ignore' must be defined as a string. +./lex_ignore.py:20: Rule 't_ignore' must be defined as a string. +Traceback (most recent call last): + File "./lex_ignore.py", line 29, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_ignore.py b/ext/ply/test/lex_ignore.py index 49c303f81..94b026693 100644 --- a/ext/ply/test/lex_ignore.py +++ b/ext/ply/test/lex_ignore.py @@ -2,7 +2,10 @@ # # Improperly specific ignore declaration -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -22,7 +25,6 @@ def t_error(t): pass import sys -sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_ignore2.exp b/ext/ply/test/lex_ignore2.exp new file mode 100644 index 000000000..0eb6bf266 --- /dev/null +++ b/ext/ply/test/lex_ignore2.exp @@ -0,0 +1 @@ +lex: Warning. t_ignore contains a literal backslash '\' diff --git a/ext/ply/test/lex_ignore2.py b/ext/ply/test/lex_ignore2.py new file mode 100644 index 000000000..fc95bd1e5 --- /dev/null +++ b/ext/ply/test/lex_ignore2.py @@ -0,0 +1,29 @@ +# lex_token.py +# +# ignore declaration as a raw string + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +t_ignore = r' \t' + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_nowarn.py b/ext/ply/test/lex_nowarn.py new file mode 100644 index 000000000..d60d31c53 --- /dev/null +++ b/ext/ply/test/lex_nowarn.py @@ -0,0 +1,30 @@ +# lex_token.py +# +# Missing t_error() rule + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + "NUMBER", + ] + +states = (('foo','exclusive'),) + +t_ignore = ' \t' +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +t_foo_NUMBER = r'\d+' + +sys.tracebacklimit = 0 + +lex.lex(nowarn=1) + + diff --git a/ext/ply/test/lex_re1.exp b/ext/ply/test/lex_re1.exp index 634eefefe..4d54f4b89 100644 --- a/ext/ply/test/lex_re1.exp +++ b/ext/ply/test/lex_re1.exp @@ -1,2 +1,7 @@ lex: Invalid regular expression for rule 't_NUMBER'. unbalanced parenthesis +Traceback (most recent call last): + File "./lex_re1.py", line 25, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_re1.py b/ext/ply/test/lex_re1.py index 4a055ad72..9e544fe0d 100644 --- a/ext/ply/test/lex_re1.py +++ b/ext/ply/test/lex_re1.py @@ -2,7 +2,10 @@ # # Bad regular expression in a string -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -18,7 +21,6 @@ def t_error(t): pass import sys -sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_re2.exp b/ext/ply/test/lex_re2.exp new file mode 100644 index 000000000..a4e2e8920 --- /dev/null +++ b/ext/ply/test/lex_re2.exp @@ -0,0 +1,7 @@ +lex: Regular expression for rule 't_PLUS' matches empty string. +Traceback (most recent call last): + File "./lex_re2.py", line 25, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." +SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_re2.py b/ext/ply/test/lex_re2.py new file mode 100644 index 000000000..522b41592 --- /dev/null +++ b/ext/ply/test/lex_re2.py @@ -0,0 +1,27 @@ +# lex_token.py +# +# Regular expression rule matches empty string + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +t_PLUS = r'\+?' +t_MINUS = r'-' +t_NUMBER = r'(\d+)' + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_re3.exp b/ext/ply/test/lex_re3.exp new file mode 100644 index 000000000..b9ada216d --- /dev/null +++ b/ext/ply/test/lex_re3.exp @@ -0,0 +1,8 @@ +lex: Invalid regular expression for rule 't_POUND'. unbalanced parenthesis +lex: Make sure '#' in rule 't_POUND' is escaped with '\#'. +Traceback (most recent call last): + File "./lex_re3.py", line 27, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." +SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_re3.py b/ext/ply/test/lex_re3.py new file mode 100644 index 000000000..099e1568c --- /dev/null +++ b/ext/ply/test/lex_re3.py @@ -0,0 +1,29 @@ +# lex_token.py +# +# Regular expression rule matches empty string + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + "POUND", + ] + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'(\d+)' +t_POUND = r'#' + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_rule1.py b/ext/ply/test/lex_rule1.py index ff3764ea1..e49a15bba 100644 --- a/ext/ply/test/lex_rule1.py +++ b/ext/ply/test/lex_rule1.py @@ -2,7 +2,10 @@ # # Rule defined as some other type -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -17,7 +20,6 @@ t_NUMBER = 1 def t_error(t): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_state1.exp b/ext/ply/test/lex_state1.exp new file mode 100644 index 000000000..facad03cc --- /dev/null +++ b/ext/ply/test/lex_state1.exp @@ -0,0 +1,7 @@ +lex: states must be defined as a tuple or list. +Traceback (most recent call last): + File "./lex_state1.py", line 38, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." +SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_state1.py b/ext/ply/test/lex_state1.py new file mode 100644 index 000000000..887bc2345 --- /dev/null +++ b/ext/ply/test/lex_state1.py @@ -0,0 +1,40 @@ +# lex_state1.py +# +# Bad state declaration + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +states = 'comment' + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +# Comments +def t_comment(t): + r'/\*' + t.lexer.begin('comment') + print "Entering comment state" + +def t_comment_body_part(t): + r'(.|\n)*\*/' + print "comment body", t + t.lexer.begin('INITIAL') + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_state2.exp b/ext/ply/test/lex_state2.exp new file mode 100644 index 000000000..8b042515a --- /dev/null +++ b/ext/ply/test/lex_state2.exp @@ -0,0 +1,8 @@ +lex: invalid state specifier 'comment'. Must be a tuple (statename,'exclusive|inclusive') +lex: invalid state specifier 'example'. Must be a tuple (statename,'exclusive|inclusive') +Traceback (most recent call last): + File "./lex_state2.py", line 38, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." +SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_state2.py b/ext/ply/test/lex_state2.py new file mode 100644 index 000000000..3053c7110 --- /dev/null +++ b/ext/ply/test/lex_state2.py @@ -0,0 +1,40 @@ +# lex_state2.py +# +# Bad state declaration + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +states = ('comment','example') + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +# Comments +def t_comment(t): + r'/\*' + t.lexer.begin('comment') + print "Entering comment state" + +def t_comment_body_part(t): + r'(.|\n)*\*/' + print "comment body", t + t.lexer.begin('INITIAL') + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_state3.exp b/ext/ply/test/lex_state3.exp new file mode 100644 index 000000000..53ab57ff1 --- /dev/null +++ b/ext/ply/test/lex_state3.exp @@ -0,0 +1,8 @@ +lex: state name 1 must be a string +lex: No rules defined for state 'example' +Traceback (most recent call last): + File "./lex_state3.py", line 40, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." +SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_state3.py b/ext/ply/test/lex_state3.py new file mode 100644 index 000000000..bb22d241e --- /dev/null +++ b/ext/ply/test/lex_state3.py @@ -0,0 +1,42 @@ +# lex_state2.py +# +# Bad state declaration + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +comment = 1 +states = ((comment, 'inclusive'), + ('example', 'exclusive')) + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +# Comments +def t_comment(t): + r'/\*' + t.lexer.begin('comment') + print "Entering comment state" + +def t_comment_body_part(t): + r'(.|\n)*\*/' + print "comment body", t + t.lexer.begin('INITIAL') + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_state4.exp b/ext/ply/test/lex_state4.exp new file mode 100644 index 000000000..412ae8f8a --- /dev/null +++ b/ext/ply/test/lex_state4.exp @@ -0,0 +1,7 @@ +lex: state type for state comment must be 'inclusive' or 'exclusive' +Traceback (most recent call last): + File "./lex_state4.py", line 39, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." +SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_state4.py b/ext/ply/test/lex_state4.py new file mode 100644 index 000000000..3815135b4 --- /dev/null +++ b/ext/ply/test/lex_state4.py @@ -0,0 +1,41 @@ +# lex_state2.py +# +# Bad state declaration + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +comment = 1 +states = (('comment', 'exclsive'),) + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +# Comments +def t_comment(t): + r'/\*' + t.lexer.begin('comment') + print "Entering comment state" + +def t_comment_body_part(t): + r'(.|\n)*\*/' + print "comment body", t + t.lexer.begin('INITIAL') + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_state5.exp b/ext/ply/test/lex_state5.exp new file mode 100644 index 000000000..8eeae5641 --- /dev/null +++ b/ext/ply/test/lex_state5.exp @@ -0,0 +1,7 @@ +lex: state 'comment' already defined. +Traceback (most recent call last): + File "./lex_state5.py", line 40, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." +SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_state5.py b/ext/ply/test/lex_state5.py new file mode 100644 index 000000000..58718538c --- /dev/null +++ b/ext/ply/test/lex_state5.py @@ -0,0 +1,42 @@ +# lex_state2.py +# +# Bad state declaration + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +comment = 1 +states = (('comment', 'exclusive'), + ('comment', 'exclusive')) + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +# Comments +def t_comment(t): + r'/\*' + t.lexer.begin('comment') + print "Entering comment state" + +def t_comment_body_part(t): + r'(.|\n)*\*/' + print "comment body", t + t.lexer.begin('INITIAL') + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_state_noerror.exp b/ext/ply/test/lex_state_noerror.exp new file mode 100644 index 000000000..e14149f18 --- /dev/null +++ b/ext/ply/test/lex_state_noerror.exp @@ -0,0 +1 @@ +lex: Warning. no error rule is defined for exclusive state 'comment' diff --git a/ext/ply/test/lex_state_noerror.py b/ext/ply/test/lex_state_noerror.py new file mode 100644 index 000000000..3fda7da49 --- /dev/null +++ b/ext/ply/test/lex_state_noerror.py @@ -0,0 +1,41 @@ +# lex_state2.py +# +# Declaration of a state for which no rules are defined + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +comment = 1 +states = (('comment', 'exclusive'),) + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +# Comments +def t_comment(t): + r'/\*' + t.lexer.begin('comment') + print "Entering comment state" + +def t_comment_body_part(t): + r'(.|\n)*\*/' + print "comment body", t + t.lexer.begin('INITIAL') + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_state_norule.exp b/ext/ply/test/lex_state_norule.exp new file mode 100644 index 000000000..7097d2a3a --- /dev/null +++ b/ext/ply/test/lex_state_norule.exp @@ -0,0 +1,7 @@ +lex: No rules defined for state 'example' +Traceback (most recent call last): + File "./lex_state_norule.py", line 40, in <module> + lex.lex() + File "../ply/lex.py", line 759, in lex + raise SyntaxError,"lex: Unable to build lexer." +SyntaxError: lex: Unable to build lexer. diff --git a/ext/ply/test/lex_state_norule.py b/ext/ply/test/lex_state_norule.py new file mode 100644 index 000000000..2f6cabc51 --- /dev/null +++ b/ext/ply/test/lex_state_norule.py @@ -0,0 +1,42 @@ +# lex_state2.py +# +# Declaration of a state for which no rules are defined + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +comment = 1 +states = (('comment', 'exclusive'), + ('example', 'exclusive')) + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +# Comments +def t_comment(t): + r'/\*' + t.lexer.begin('comment') + print "Entering comment state" + +def t_comment_body_part(t): + r'(.|\n)*\*/' + print "comment body", t + t.lexer.begin('INITIAL') + +def t_error(t): + pass + +import sys + +lex.lex() + + diff --git a/ext/ply/test/lex_state_try.exp b/ext/ply/test/lex_state_try.exp new file mode 100644 index 000000000..11768b893 --- /dev/null +++ b/ext/ply/test/lex_state_try.exp @@ -0,0 +1,7 @@ +(NUMBER,'3',1,0) +(PLUS,'+',1,2) +(NUMBER,'4',1,4) +Entering comment state +comment body LexToken(body_part,'This is a comment */',1,9) +(PLUS,'+',1,30) +(NUMBER,'10',1,32) diff --git a/ext/ply/test/lex_state_try.py b/ext/ply/test/lex_state_try.py new file mode 100644 index 000000000..a2206cbc3 --- /dev/null +++ b/ext/ply/test/lex_state_try.py @@ -0,0 +1,48 @@ +# lex_state2.py +# +# Declaration of a state for which no rules are defined + +import sys +sys.path.insert(0,"..") + +import ply.lex as lex + +tokens = [ + "PLUS", + "MINUS", + "NUMBER", + ] + +comment = 1 +states = (('comment', 'exclusive'),) + +t_PLUS = r'\+' +t_MINUS = r'-' +t_NUMBER = r'\d+' + +t_ignore = " \t" + +# Comments +def t_comment(t): + r'/\*' + t.lexer.begin('comment') + print "Entering comment state" + +def t_comment_body_part(t): + r'(.|\n)*\*/' + print "comment body", t + t.lexer.begin('INITIAL') + +def t_error(t): + pass + +t_comment_error = t_error +t_comment_ignore = t_ignore + +import sys + +lex.lex() + +data = "3 + 4 /* This is a comment */ + 10" + +lex.runmain(data=data) diff --git a/ext/ply/test/lex_token1.py b/ext/ply/test/lex_token1.py index e8eca2b63..380c31ce1 100644 --- a/ext/ply/test/lex_token1.py +++ b/ext/ply/test/lex_token1.py @@ -2,7 +2,10 @@ # # Tests for absence of tokens variable -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex t_PLUS = r'\+' t_MINUS = r'-' @@ -11,7 +14,6 @@ t_NUMBER = r'\d+' def t_error(t): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_token2.py b/ext/ply/test/lex_token2.py index 38b34dabe..87db8a0ab 100644 --- a/ext/ply/test/lex_token2.py +++ b/ext/ply/test/lex_token2.py @@ -2,7 +2,10 @@ # # Tests for tokens of wrong type -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = "PLUS MINUS NUMBER" @@ -13,7 +16,6 @@ t_NUMBER = r'\d+' def t_error(t): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_token3.py b/ext/ply/test/lex_token3.py index 909f9180d..27ce9476d 100644 --- a/ext/ply/test/lex_token3.py +++ b/ext/ply/test/lex_token3.py @@ -2,7 +2,10 @@ # # tokens is right type, but is missing a token for one rule -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -16,7 +19,7 @@ t_NUMBER = r'\d+' def t_error(t): pass -import sys + sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_token4.py b/ext/ply/test/lex_token4.py index d77d1662c..612ff13c2 100644 --- a/ext/ply/test/lex_token4.py +++ b/ext/ply/test/lex_token4.py @@ -2,7 +2,10 @@ # # Bad token name -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -18,7 +21,6 @@ t_NUMBER = r'\d+' def t_error(t): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/lex_token5.exp b/ext/ply/test/lex_token5.exp index d7bcb2e7c..2f038890a 100644 --- a/ext/ply/test/lex_token5.exp +++ b/ext/ply/test/lex_token5.exp @@ -1 +1 @@ -lex.LexError: ./lex_token5.py:16: Rule 't_NUMBER' returned an unknown token type 'NUM' +ply.lex.LexError: ./lex_token5.py:19: Rule 't_NUMBER' returned an unknown token type 'NUM' diff --git a/ext/ply/test/lex_token5.py b/ext/ply/test/lex_token5.py index d9b0c96aa..77fabdee9 100644 --- a/ext/ply/test/lex_token5.py +++ b/ext/ply/test/lex_token5.py @@ -2,7 +2,10 @@ # # Return a bad token name -import lex +import sys +sys.path.insert(0,"..") + +import ply.lex as lex tokens = [ "PLUS", @@ -21,7 +24,6 @@ def t_NUMBER(t): def t_error(t): pass -import sys sys.tracebacklimit = 0 lex.lex() diff --git a/ext/ply/test/rununit.py b/ext/ply/test/rununit.py new file mode 100644 index 000000000..cb7a2298b --- /dev/null +++ b/ext/ply/test/rununit.py @@ -0,0 +1,62 @@ +#!/usr/bin/env python +'''Script to run all tests using python "unittest" module''' + +__author__ = "Miki Tebeka <miki.tebeka@zoran.com>" + +from unittest import TestCase, main, makeSuite, TestSuite +from os import popen, environ, remove +from glob import glob +from sys import executable, argv +from os.path import isfile, basename, splitext + +# Add path to lex.py and yacc.py +environ["PYTHONPATH"] = ".." + +class PLYTest(TestCase): + '''General test case for PLY test''' + def _runtest(self, filename): + '''Run a single test file an compare result''' + exp_file = filename.replace(".py", ".exp") + self.failUnless(isfile(exp_file), "can't find %s" % exp_file) + pipe = popen("%s %s 2>&1" % (executable, filename)) + out = pipe.read().strip() + self.failUnlessEqual(out, open(exp_file).read().strip()) + + +class LexText(PLYTest): + '''Testing Lex''' + pass + +class YaccTest(PLYTest): + '''Testing Yacc''' + + def tearDown(self): + '''Cleanup parsetab.py[c] file''' + for ext in (".py", ".pyc"): + fname = "parsetab%s" % ext + if isfile(fname): + remove(fname) + +def add_test(klass, filename): + '''Add a test to TestCase class''' + def t(self): + self._runtest(filename) + # Test name is test_FILENAME without the ./ and without the .py + setattr(klass, "test_%s" % (splitext(basename(filename))[0]), t) + +# Add lex tests +for file in glob("./lex_*.py"): + add_test(LexText, file) +lex_suite = makeSuite(LexText, "test_") + +# Add yacc tests +for file in glob("./yacc_*.py"): + add_test(YaccTest, file) +yacc_suite = makeSuite(YaccTest, "test_") + +# All tests suite +test_suite = TestSuite((lex_suite, yacc_suite)) + +if __name__ == "__main__": + main() + diff --git a/ext/ply/test/yacc_badargs.exp b/ext/ply/test/yacc_badargs.exp index b145c51f2..e99467659 100644 --- a/ext/ply/test/yacc_badargs.exp +++ b/ext/ply/test/yacc_badargs.exp @@ -1,3 +1,3 @@ -./yacc_badargs.py:21: Rule 'p_statement_assign' has too many arguments. -./yacc_badargs.py:25: Rule 'p_statement_expr' requires an argument. -yacc.YaccError: Unable to construct parser. +./yacc_badargs.py:23: Rule 'p_statement_assign' has too many arguments. +./yacc_badargs.py:27: Rule 'p_statement_expr' requires an argument. +ply.yacc.YaccError: Unable to construct parser. diff --git a/ext/ply/test/yacc_badargs.py b/ext/ply/test/yacc_badargs.py index 12075efcc..810e5298a 100644 --- a/ext/ply/test/yacc_badargs.py +++ b/ext/ply/test/yacc_badargs.py @@ -5,6 +5,8 @@ # ----------------------------------------------------------------------------- import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc from calclex import tokens @@ -59,7 +61,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_badprec.exp b/ext/ply/test/yacc_badprec.exp index 7764b0246..f4f574b99 100644 --- a/ext/ply/test/yacc_badprec.exp +++ b/ext/ply/test/yacc_badprec.exp @@ -1 +1 @@ -yacc.YaccError: precedence must be a list or tuple. +ply.yacc.YaccError: precedence must be a list or tuple. diff --git a/ext/ply/test/yacc_badprec.py b/ext/ply/test/yacc_badprec.py index 55bf7720d..8f64652e6 100644 --- a/ext/ply/test/yacc_badprec.py +++ b/ext/ply/test/yacc_badprec.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -55,7 +58,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_badprec2.exp b/ext/ply/test/yacc_badprec2.exp index 1df1427b2..8fac075ce 100644 --- a/ext/ply/test/yacc_badprec2.exp +++ b/ext/ply/test/yacc_badprec2.exp @@ -1,3 +1,3 @@ yacc: Invalid precedence table. -yacc: Generating SLR parsing table... -yacc: 4 shift/reduce conflicts +yacc: Generating LALR parsing table... +yacc: 8 shift/reduce conflicts diff --git a/ext/ply/test/yacc_badprec2.py b/ext/ply/test/yacc_badprec2.py index 9cbc99827..206bda768 100644 --- a/ext/ply/test/yacc_badprec2.py +++ b/ext/ply/test/yacc_badprec2.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -59,7 +62,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_badrule.exp b/ext/ply/test/yacc_badrule.exp index 553779778..a87bf7d68 100644 --- a/ext/ply/test/yacc_badrule.exp +++ b/ext/ply/test/yacc_badrule.exp @@ -1,5 +1,5 @@ -./yacc_badrule.py:22: Syntax error. Expected ':' -./yacc_badrule.py:26: Syntax error in rule 'statement' -./yacc_badrule.py:31: Syntax error. Expected ':' -./yacc_badrule.py:40: Syntax error. Expected ':' -yacc.YaccError: Unable to construct parser. +./yacc_badrule.py:25: Syntax error. Expected ':' +./yacc_badrule.py:29: Syntax error in rule 'statement' +./yacc_badrule.py:34: Syntax error. Expected ':' +./yacc_badrule.py:43: Syntax error. Expected ':' +ply.yacc.YaccError: Unable to construct parser. diff --git a/ext/ply/test/yacc_badrule.py b/ext/ply/test/yacc_badrule.py index cad3a967e..f5fef8ad6 100644 --- a/ext/ply/test/yacc_badrule.py +++ b/ext/ply/test/yacc_badrule.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -59,7 +62,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_badtok.exp b/ext/ply/test/yacc_badtok.exp index f6e64726c..ccdc0e7a1 100644 --- a/ext/ply/test/yacc_badtok.exp +++ b/ext/ply/test/yacc_badtok.exp @@ -1 +1 @@ -yacc.YaccError: tokens must be a list or tuple. +ply.yacc.YaccError: tokens must be a list or tuple. diff --git a/ext/ply/test/yacc_badtok.py b/ext/ply/test/yacc_badtok.py index a17d26aaa..4f2af5162 100644 --- a/ext/ply/test/yacc_badtok.py +++ b/ext/ply/test/yacc_badtok.py @@ -7,6 +7,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + tokens = "Hello" # Parsing rules @@ -60,7 +63,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_dup.exp b/ext/ply/test/yacc_dup.exp index 99f3fe22c..fdfb2103d 100644 --- a/ext/ply/test/yacc_dup.exp +++ b/ext/ply/test/yacc_dup.exp @@ -1,4 +1,4 @@ -./yacc_dup.py:25: Function p_statement redefined. Previously defined on line 21 +./yacc_dup.py:28: Function p_statement redefined. Previously defined on line 24 yacc: Warning. Token 'EQUALS' defined, but not used. yacc: Warning. There is 1 unused token. -yacc: Generating SLR parsing table... +yacc: Generating LALR parsing table... diff --git a/ext/ply/test/yacc_dup.py b/ext/ply/test/yacc_dup.py index 557cd0ae1..e0b683d8f 100644 --- a/ext/ply/test/yacc_dup.py +++ b/ext/ply/test/yacc_dup.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -59,7 +62,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_error1.exp b/ext/ply/test/yacc_error1.exp index 980fc905c..13bed0461 100644 --- a/ext/ply/test/yacc_error1.exp +++ b/ext/ply/test/yacc_error1.exp @@ -1 +1 @@ -yacc.YaccError: ./yacc_error1.py:59: p_error() requires 1 argument. +ply.yacc.YaccError: ./yacc_error1.py:62: p_error() requires 1 argument. diff --git a/ext/ply/test/yacc_error1.py b/ext/ply/test/yacc_error1.py index 413004520..2768fc14a 100644 --- a/ext/ply/test/yacc_error1.py +++ b/ext/ply/test/yacc_error1.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -59,7 +62,6 @@ def p_expression_name(t): def p_error(t,s): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_error2.exp b/ext/ply/test/yacc_error2.exp index d0573b4dd..4a7628d78 100644 --- a/ext/ply/test/yacc_error2.exp +++ b/ext/ply/test/yacc_error2.exp @@ -1 +1 @@ -yacc.YaccError: ./yacc_error2.py:59: p_error() requires 1 argument. +ply.yacc.YaccError: ./yacc_error2.py:62: p_error() requires 1 argument. diff --git a/ext/ply/test/yacc_error2.py b/ext/ply/test/yacc_error2.py index d4fd1d219..8f3a05290 100644 --- a/ext/ply/test/yacc_error2.py +++ b/ext/ply/test/yacc_error2.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -59,7 +62,6 @@ def p_expression_name(t): def p_error(): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_error3.exp b/ext/ply/test/yacc_error3.exp index 31eaee754..7fca2fe95 100644 --- a/ext/ply/test/yacc_error3.exp +++ b/ext/ply/test/yacc_error3.exp @@ -1 +1 @@ -yacc.YaccError: 'p_error' defined, but is not a function. +ply.yacc.YaccError: 'p_error' defined, but is not a function or method. diff --git a/ext/ply/test/yacc_error3.py b/ext/ply/test/yacc_error3.py index 7093fab48..b387de5d1 100644 --- a/ext/ply/test/yacc_error3.py +++ b/ext/ply/test/yacc_error3.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -58,7 +61,6 @@ def p_expression_name(t): p_error = "blah" -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_inf.exp b/ext/ply/test/yacc_inf.exp index a7f47dada..88cfa4a2e 100644 --- a/ext/ply/test/yacc_inf.exp +++ b/ext/ply/test/yacc_inf.exp @@ -2,4 +2,4 @@ yacc: Warning. Token 'NUMBER' defined, but not used. yacc: Warning. There is 1 unused token. yacc: Infinite recursion detected for symbol 'statement'. yacc: Infinite recursion detected for symbol 'expression'. -yacc.YaccError: Unable to construct parser. +ply.yacc.YaccError: Unable to construct parser. diff --git a/ext/ply/test/yacc_inf.py b/ext/ply/test/yacc_inf.py index 885e2c4df..9b9aef75d 100644 --- a/ext/ply/test/yacc_inf.py +++ b/ext/ply/test/yacc_inf.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -47,7 +50,6 @@ def p_expression_group(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_missing1.exp b/ext/ply/test/yacc_missing1.exp index 065d6a54a..de63d4f48 100644 --- a/ext/ply/test/yacc_missing1.exp +++ b/ext/ply/test/yacc_missing1.exp @@ -1,2 +1,2 @@ -./yacc_missing1.py:22: Symbol 'location' used, but not defined as a token or a rule. -yacc.YaccError: Unable to construct parser. +./yacc_missing1.py:25: Symbol 'location' used, but not defined as a token or a rule. +ply.yacc.YaccError: Unable to construct parser. diff --git a/ext/ply/test/yacc_missing1.py b/ext/ply/test/yacc_missing1.py index e63904d0e..fbc54d8c5 100644 --- a/ext/ply/test/yacc_missing1.py +++ b/ext/ply/test/yacc_missing1.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -59,7 +62,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_nodoc.exp b/ext/ply/test/yacc_nodoc.exp index 3f52a3287..889ccfce7 100644 --- a/ext/ply/test/yacc_nodoc.exp +++ b/ext/ply/test/yacc_nodoc.exp @@ -1,2 +1,2 @@ -./yacc_nodoc.py:25: No documentation string specified in function 'p_statement_expr' -yacc: Generating SLR parsing table... +./yacc_nodoc.py:28: No documentation string specified in function 'p_statement_expr' +yacc: Generating LALR parsing table... diff --git a/ext/ply/test/yacc_nodoc.py b/ext/ply/test/yacc_nodoc.py index e3941bdaa..4c5ab20a9 100644 --- a/ext/ply/test/yacc_nodoc.py +++ b/ext/ply/test/yacc_nodoc.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -58,7 +61,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_noerror.exp b/ext/ply/test/yacc_noerror.exp index 986fa31fa..3ae771225 100644 --- a/ext/ply/test/yacc_noerror.exp +++ b/ext/ply/test/yacc_noerror.exp @@ -1,2 +1,2 @@ yacc: Warning. no p_error() function is defined. -yacc: Generating SLR parsing table... +yacc: Generating LALR parsing table... diff --git a/ext/ply/test/yacc_noerror.py b/ext/ply/test/yacc_noerror.py index d92f48ea6..9c11838eb 100644 --- a/ext/ply/test/yacc_noerror.py +++ b/ext/ply/test/yacc_noerror.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -56,7 +59,7 @@ def p_expression_name(t): print "Undefined name '%s'" % t[1] t[0] = 0 -import yacc + yacc.yacc() diff --git a/ext/ply/test/yacc_nop.exp b/ext/ply/test/yacc_nop.exp index 062878b9e..515fff7dc 100644 --- a/ext/ply/test/yacc_nop.exp +++ b/ext/ply/test/yacc_nop.exp @@ -1,2 +1,2 @@ -./yacc_nop.py:25: Warning. Possible grammar rule 'statement_expr' defined without p_ prefix. -yacc: Generating SLR parsing table... +./yacc_nop.py:28: Warning. Possible grammar rule 'statement_expr' defined without p_ prefix. +yacc: Generating LALR parsing table... diff --git a/ext/ply/test/yacc_nop.py b/ext/ply/test/yacc_nop.py index c599ffd5d..c0b431d4b 100644 --- a/ext/ply/test/yacc_nop.py +++ b/ext/ply/test/yacc_nop.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -59,7 +62,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_notfunc.exp b/ext/ply/test/yacc_notfunc.exp index 271167341..f73bc93a5 100644 --- a/ext/ply/test/yacc_notfunc.exp +++ b/ext/ply/test/yacc_notfunc.exp @@ -1,4 +1,4 @@ yacc: Warning. 'p_statement_assign' not defined as a function yacc: Warning. Token 'EQUALS' defined, but not used. yacc: Warning. There is 1 unused token. -yacc: Generating SLR parsing table... +yacc: Generating LALR parsing table... diff --git a/ext/ply/test/yacc_notfunc.py b/ext/ply/test/yacc_notfunc.py index f61663d60..838935509 100644 --- a/ext/ply/test/yacc_notfunc.py +++ b/ext/ply/test/yacc_notfunc.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -57,7 +60,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_notok.exp b/ext/ply/test/yacc_notok.exp index 708f6f597..d2399fe17 100644 --- a/ext/ply/test/yacc_notok.exp +++ b/ext/ply/test/yacc_notok.exp @@ -1 +1 @@ -yacc.YaccError: module does not define a list 'tokens' +ply.yacc.YaccError: module does not define a list 'tokens' diff --git a/ext/ply/test/yacc_notok.py b/ext/ply/test/yacc_notok.py index dfa0059be..e566a1bf4 100644 --- a/ext/ply/test/yacc_notok.py +++ b/ext/ply/test/yacc_notok.py @@ -7,6 +7,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + # Parsing rules precedence = ( ('left','PLUS','MINUS'), @@ -58,7 +61,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_rr.exp b/ext/ply/test/yacc_rr.exp index 0ec556d16..f73cefdec 100644 --- a/ext/ply/test/yacc_rr.exp +++ b/ext/ply/test/yacc_rr.exp @@ -1,2 +1,2 @@ -yacc: Generating SLR parsing table... +yacc: Generating LALR parsing table... yacc: 1 reduce/reduce conflict diff --git a/ext/ply/test/yacc_rr.py b/ext/ply/test/yacc_rr.py index c061c2c17..bb8cba235 100644 --- a/ext/ply/test/yacc_rr.py +++ b/ext/ply/test/yacc_rr.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -63,7 +66,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_simple.exp b/ext/ply/test/yacc_simple.exp index de7964b6f..38360315f 100644 --- a/ext/ply/test/yacc_simple.exp +++ b/ext/ply/test/yacc_simple.exp @@ -1 +1 @@ -yacc: Generating SLR parsing table... +yacc: Generating LALR parsing table... diff --git a/ext/ply/test/yacc_simple.py b/ext/ply/test/yacc_simple.py index 7b4b40b17..b5dc9f39c 100644 --- a/ext/ply/test/yacc_simple.py +++ b/ext/ply/test/yacc_simple.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -59,7 +62,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_sr.exp b/ext/ply/test/yacc_sr.exp index 7225ad94b..1b764502c 100644 --- a/ext/ply/test/yacc_sr.exp +++ b/ext/ply/test/yacc_sr.exp @@ -1,2 +1,2 @@ -yacc: Generating SLR parsing table... +yacc: Generating LALR parsing table... yacc: 20 shift/reduce conflicts diff --git a/ext/ply/test/yacc_sr.py b/ext/ply/test/yacc_sr.py index 4341f6997..e2f03ec74 100644 --- a/ext/ply/test/yacc_sr.py +++ b/ext/ply/test/yacc_sr.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -54,7 +57,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_term1.exp b/ext/ply/test/yacc_term1.exp index 422d2bacd..40f9bdf64 100644 --- a/ext/ply/test/yacc_term1.exp +++ b/ext/ply/test/yacc_term1.exp @@ -1,2 +1,2 @@ -./yacc_term1.py:22: Illegal rule name 'NUMBER'. Already defined as a token. -yacc.YaccError: Unable to construct parser. +./yacc_term1.py:25: Illegal rule name 'NUMBER'. Already defined as a token. +ply.yacc.YaccError: Unable to construct parser. diff --git a/ext/ply/test/yacc_term1.py b/ext/ply/test/yacc_term1.py index 97a2e7a60..bbc52da86 100644 --- a/ext/ply/test/yacc_term1.py +++ b/ext/ply/test/yacc_term1.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -59,7 +62,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_unused.exp b/ext/ply/test/yacc_unused.exp index 390754de3..6caafd266 100644 --- a/ext/ply/test/yacc_unused.exp +++ b/ext/ply/test/yacc_unused.exp @@ -1,4 +1,4 @@ -./yacc_unused.py:60: Symbol 'COMMA' used, but not defined as a token or a rule. +./yacc_unused.py:63: Symbol 'COMMA' used, but not defined as a token or a rule. yacc: Symbol 'COMMA' is unreachable. yacc: Symbol 'exprlist' is unreachable. -yacc.YaccError: Unable to construct parser. +ply.yacc.YaccError: Unable to construct parser. diff --git a/ext/ply/test/yacc_unused.py b/ext/ply/test/yacc_unused.py index 4cbd63327..3a61f99cd 100644 --- a/ext/ply/test/yacc_unused.py +++ b/ext/ply/test/yacc_unused.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -68,7 +71,6 @@ def p_expr_list_2(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/ext/ply/test/yacc_uprec.exp b/ext/ply/test/yacc_uprec.exp index b1a71a250..eb9a39886 100644 --- a/ext/ply/test/yacc_uprec.exp +++ b/ext/ply/test/yacc_uprec.exp @@ -1,2 +1,2 @@ -./yacc_uprec.py:35: Nothing known about the precedence of 'UMINUS' -yacc.YaccError: Unable to construct parser. +./yacc_uprec.py:38: Nothing known about the precedence of 'UMINUS' +ply.yacc.YaccError: Unable to construct parser. diff --git a/ext/ply/test/yacc_uprec.py b/ext/ply/test/yacc_uprec.py index 139ce6318..0e8711e88 100644 --- a/ext/ply/test/yacc_uprec.py +++ b/ext/ply/test/yacc_uprec.py @@ -6,6 +6,9 @@ import sys sys.tracebacklimit = 0 +sys.path.insert(0,"..") +import ply.yacc as yacc + from calclex import tokens # Parsing rules @@ -54,7 +57,6 @@ def p_expression_name(t): def p_error(t): print "Syntax error at '%s'" % t.value -import yacc yacc.yacc() diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py new file mode 100644 index 000000000..a19aeb763 --- /dev/null +++ b/src/arch/alpha/AlphaSystem.py @@ -0,0 +1,52 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from System import System + +class AlphaSystem(System): + type = 'AlphaSystem' + console = Param.String("file that contains the console code") + pal = Param.String("file that contains palcode") + system_type = Param.UInt64("Type of system we are emulating") + system_rev = Param.UInt64("Revision of system we are emulating") + +class LinuxAlphaSystem(AlphaSystem): + type = 'LinuxAlphaSystem' + system_type = 34 + system_rev = 1 << 10 + +class FreebsdAlphaSystem(AlphaSystem): + type = 'FreebsdAlphaSystem' + system_type = 34 + system_rev = 1 << 10 + +class Tru64AlphaSystem(AlphaSystem): + type = 'Tru64AlphaSystem' + system_type = 12 + system_rev = 2<<1 diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py new file mode 100644 index 000000000..559516725 --- /dev/null +++ b/src/arch/alpha/AlphaTLB.py @@ -0,0 +1,42 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +class AlphaTLB(SimObject): + type = 'AlphaTLB' + abstract = True + size = Param.Int("TLB size") + +class AlphaDTB(AlphaTLB): + type = 'AlphaDTB' + size = 64 + +class AlphaITB(AlphaTLB): + type = 'AlphaITB' + size = 48 diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 61611e9f6..2d59180c4 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -40,6 +40,9 @@ if env['TARGET_ISA'] == 'alpha': Source('remote_gdb.cc') if env['FULL_SYSTEM']: + SimObject('AlphaSystem.py') + SimObject('AlphaTLB.py') + Source('arguments.cc') Source('ev5.cc') Source('idle_event.cc') diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh index 650f2bfa2..0407ce99b 100644 --- a/src/arch/alpha/predecoder.hh +++ b/src/arch/alpha/predecoder.hh @@ -69,9 +69,9 @@ namespace AlphaISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst) { - fetchPC = pc; + fetchPC = _fetchPC; assert(off == 0); ext_inst = inst; #if FULL_SYSTEM @@ -80,13 +80,6 @@ namespace AlphaISA #endif } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(fetchPC + sizeof(machInst), 0, machInst); - } - bool needMoreBytes() { return true; diff --git a/src/arch/alpha/remote_gdb.cc b/src/arch/alpha/remote_gdb.cc index a68e5218e..ea5db36f4 100644 --- a/src/arch/alpha/remote_gdb.cc +++ b/src/arch/alpha/remote_gdb.cc @@ -284,7 +284,7 @@ RemoteGDB::setSingleStep() // User was stopped at pc, e.g. the instruction at pc was not // executed. MachInst inst = read<MachInst>(pc); - StaticInstPtr si(inst); + StaticInstPtr si(inst, pc); if (si->hasBranchTarget(pc, context, bpc)) { // Don't bother setting a breakpoint on the taken branch if it // is the same as the next pc diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 2dfff8c5f..714bca22a 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -292,6 +292,10 @@ ITB::regStats() Fault ITB::translate(RequestPtr &req, ThreadContext *tc) const { + //If this is a pal pc, then set PHYSICAL + if(FULL_SYSTEM && PcPAL(req->getPC())) + req->setFlags(req->getFlags() | PHYSICAL); + if (PcPAL(req->getPC())) { // strip off PAL PC marker (lsb is 1) req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 4c8d0706d..7edb9f3d7 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -40,8 +40,8 @@ from types import * # of 'build' in the current tree. sys.path[0:0] = [os.environ['M5_PLY']] -import lex -import yacc +from ply import lex +from ply import yacc ##################################################################### # @@ -194,7 +194,7 @@ def t_error(t): t.skip(1) # Build the lexer -lex.lex() +lexer = lex.lex() ##################################################################### # @@ -729,7 +729,7 @@ def p_error(t): # END OF GRAMMAR RULES # # Now build the parser. -yacc.yacc() +parser = yacc.yacc() ##################################################################### @@ -1881,7 +1881,8 @@ def parse_isa_desc(isa_desc_file, output_dir): fileNameStack.push((isa_desc_file, 0)) # Parse it. - (isa_name, namespace, global_code, namespace_code) = yacc.parse(isa_desc) + (isa_name, namespace, global_code, namespace_code) = \ + parser.parse(isa_desc, lexer=lexer) # grab the last three path components of isa_desc_file to put in # the output diff --git a/src/arch/micro_asm.py b/src/arch/micro_asm.py new file mode 100644 index 000000000..a8a63e1f8 --- /dev/null +++ b/src/arch/micro_asm.py @@ -0,0 +1,491 @@ +# Copyright (c) 2003-2005 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +import os +import sys +import re +import string +import traceback +# get type names +from types import * + +# Prepend the directory where the PLY lex & yacc modules are found +# to the search path. +sys.path[0:0] = [os.environ['M5_PLY']] + +from ply import lex +from ply import yacc + +########################################################################## +# +# Base classes for use outside of the assembler +# +########################################################################## + +class Micro_Container(object): + def __init__(self, name): + self.microops = [] + self.name = name + self.directives = {} + self.micro_classes = {} + self.labels = {} + + def add_microop(self, microop): + self.microops.append(microop) + + def __str__(self): + string = "%s:\n" % self.name + for microop in self.microops: + string += " %s\n" % microop + return string + +class Combinational_Macroop(Micro_Container): + pass + +class Rom_Macroop(object): + def __init__(self, name, target): + self.name = name + self.target = target + + def __str__(self): + return "%s: %s\n" % (self.name, self.target) + +class Rom(Micro_Container): + def __init__(self, name): + super(Rom, self).__init__(name) + self.externs = {} + +########################################################################## +# +# Support classes +# +########################################################################## + +class Label(object): + def __init__(self): + self.extern = False + self.name = "" + +class Block(object): + def __init__(self): + self.statements = [] + +class Statement(object): + def __init__(self): + self.is_microop = False + self.is_directive = False + self.params = "" + +class Microop(Statement): + def __init__(self): + super(Microop, self).__init__() + self.mnemonic = "" + self.labels = [] + self.is_microop = True + +class Directive(Statement): + def __init__(self): + super(Directive, self).__init__() + self.name = "" + self.is_directive = True + +########################################################################## +# +# Functions that handle common tasks +# +########################################################################## + +def print_error(message): + print + print "*** %s" % message + print + +def handle_statement(parser, container, statement): + if statement.is_microop: + try: + microop = eval('parser.microops[statement.mnemonic](%s)' % + statement.params) + except: + print_error("Error creating microop object.") + raise + try: + for label in statement.labels: + container.labels[label.name] = microop + if label.extern: + container.externs[label.name] = microop + container.add_microop(microop) + except: + print_error("Error adding microop.") + raise + elif statement.is_directive: + try: + eval('container.directives[statement.name](%s)' % statement.params) + except: + print_error("Error executing directive.") + print container.directives + raise + else: + raise Exception, "Didn't recognize the type of statement", statement + +########################################################################## +# +# Lexer specification +# +########################################################################## + +# Error handler. Just call exit. Output formatted to work under +# Emacs compile-mode. Optional 'print_traceback' arg, if set to True, +# prints a Python stack backtrace too (can be handy when trying to +# debug the parser itself). +def error(lineno, string, print_traceback = False): + # Print a Python stack backtrace if requested. + if (print_traceback): + traceback.print_exc() + if lineno != 0: + line_str = "%d:" % lineno + else: + line_str = "" + sys.exit("%s %s" % (line_str, string)) + +reserved = ('DEF', 'MACROOP', 'ROM', 'EXTERN') + +tokens = reserved + ( + # identifier + 'ID', + # arguments for microops and directives + 'PARAMS', + + 'LPAREN', 'RPAREN', + 'LBRACE', 'RBRACE', + 'COLON', 'SEMI', 'DOT', + 'NEWLINE' + ) + +# New lines are ignored at the top level, but they end statements in the +# assembler +states = ( + ('asm', 'exclusive'), + ('params', 'exclusive'), +) + +reserved_map = { } +for r in reserved: + reserved_map[r.lower()] = r + +# Ignore comments +def t_ANY_COMMENT(t): + r'\#[^\n]*(?=\n)' + +def t_ANY_MULTILINECOMMENT(t): + r'/\*([^/]|((?<!\*)/))*\*/' + +# A colon marks the end of a label. It should follow an ID which will +# put the lexer in the "params" state. Seeing the colon will put it back +# in the "asm" state since it knows it saw a label and not a mnemonic. +def t_params_COLON(t): + r':' + t.lexer.begin('asm') + return t + +# An "ID" in the micro assembler is either a label, directive, or mnemonic +# If it's either a directive or a mnemonic, it will be optionally followed by +# parameters. If it's a label, the following colon will make the lexer stop +# looking for parameters. +def t_asm_ID(t): + r'[A-Za-z_]\w*' + t.type = reserved_map.get(t.value, 'ID') + t.lexer.begin('params') + return t + +# If there is a label and you're -not- in the assember (which would be caught +# above), don't start looking for parameters. +def t_ANY_ID(t): + r'[A-Za-z_]\w*' + t.type = reserved_map.get(t.value, 'ID') + return t + +# Parameters are a string of text which don't contain an unescaped statement +# statement terminator, ie a newline or semi colon. +def t_params_PARAMS(t): + r'([^\n;\\]|(\\[\n;\\]))+' + t.lineno += t.value.count('\n') + unescapeParamsRE = re.compile(r'(\\[\n;\\])') + def unescapeParams(mo): + val = mo.group(0) + print "About to sub %s for %s" % (val[1], val) + return val[1] + print "Looking for matches in %s" % t.value + t.value = unescapeParamsRE.sub(unescapeParams, t.value) + t.lexer.begin('asm') + return t + +# Braces enter and exit micro assembly +def t_INITIAL_LBRACE(t): + r'\{' + t.lexer.begin('asm') + return t + +def t_asm_RBRACE(t): + r'\}' + t.lexer.begin('INITIAL') + return t + +# At the top level, keep track of newlines only for line counting. +def t_INITIAL_NEWLINE(t): + r'\n+' + t.lineno += t.value.count('\n') + +# In the micro assembler, do line counting but also return a token. The +# token is needed by the parser to detect the end of a statement. +def t_asm_NEWLINE(t): + r'\n+' + t.lineno += t.value.count('\n') + return t + +# A newline or semi colon when looking for params signals that the statement +# is over and the lexer should go back to looking for regular assembly. +def t_params_NEWLINE(t): + r'\n+' + t.lineno += t.value.count('\n') + t.lexer.begin('asm') + return t + +def t_params_SEMI(t): + r';' + t.lexer.begin('asm') + return t + +# Basic regular expressions to pick out simple tokens +t_ANY_LPAREN = r'\(' +t_ANY_RPAREN = r'\)' +t_ANY_SEMI = r';' +t_ANY_DOT = r'\.' + +t_ANY_ignore = ' \t\x0c' + +def t_ANY_error(t): + error(t.lineno, "illegal character '%s'" % t.value[0]) + t.skip(1) + +########################################################################## +# +# Parser specification +# +########################################################################## + +# Start symbol for a file which may have more than one macroop or rom +# specification. +def p_file(t): + 'file : opt_rom_or_macros' + +def p_opt_rom_or_macros_0(t): + 'opt_rom_or_macros : ' + +def p_opt_rom_or_macros_1(t): + 'opt_rom_or_macros : rom_or_macros' + +def p_rom_or_macros_0(t): + 'rom_or_macros : rom_or_macro' + +def p_rom_or_macros_1(t): + 'rom_or_macros : rom_or_macros rom_or_macro' + +def p_rom_or_macro_0(t): + '''rom_or_macro : rom_block + | macroop_def''' + +# Defines a section of microcode that should go in the current ROM +def p_rom_block(t): + 'rom_block : DEF ROM block SEMI' + if not t.parser.rom: + print_error("Rom block found, but no Rom object specified.") + raise TypeError, "Rom block found, but no Rom object was specified." + for statement in t[3].statements: + handle_statement(t.parser, t.parser.rom, statement) + t[0] = t.parser.rom + +# Defines a macroop that jumps to an external label in the ROM +def p_macroop_def_0(t): + 'macroop_def : DEF MACROOP ID LPAREN ID RPAREN SEMI' + if not t.parser.rom_macroop_type: + print_error("ROM based macroop found, but no ROM macroop class was specified.") + raise TypeError, "ROM based macroop found, but no ROM macroop class was specified." + macroop = t.parser.rom_macroop_type(t[3], t[5]) + t.parser.macroops[t[3]] = macroop + + +# Defines a macroop that is combinationally generated +def p_macroop_def_1(t): + 'macroop_def : DEF MACROOP ID block SEMI' + try: + curop = t.parser.macro_type(t[3]) + except TypeError: + print_error("Error creating macroop object.") + raise + for statement in t[4].statements: + handle_statement(t.parser, curop, statement) + t.parser.macroops[t[3]] = curop + +# A block of statements +def p_block(t): + 'block : LBRACE statements RBRACE' + block = Block() + block.statements = t[2] + t[0] = block + +def p_statements_0(t): + 'statements : statement' + if t[1]: + t[0] = [t[1]] + else: + t[0] = [] + +def p_statements_1(t): + 'statements : statements statement' + if t[2]: + t[1].append(t[2]) + t[0] = t[1] + +def p_statement(t): + 'statement : content_of_statement end_of_statement' + t[0] = t[1] + +# A statement can be a microop or an assembler directive +def p_content_of_statement_0(t): + '''content_of_statement : microop + | directive''' + t[0] = t[1] + +# Ignore empty statements +def p_content_of_statement_1(t): + 'content_of_statement : ' + pass + +# Statements are ended by newlines or a semi colon +def p_end_of_statement(t): + '''end_of_statement : NEWLINE + | SEMI''' + pass + +# Different flavors of microop to avoid shift/reduce errors +def p_microop_0(t): + 'microop : labels ID' + microop = Microop() + microop.labels = t[1] + microop.mnemonic = t[2] + t[0] = microop + +def p_microop_1(t): + 'microop : ID' + microop = Microop() + microop.mnemonic = t[1] + t[0] = microop + +def p_microop_2(t): + 'microop : labels ID PARAMS' + microop = Microop() + microop.labels = t[1] + microop.mnemonic = t[2] + microop.params = t[3] + t[0] = microop + +def p_microop_3(t): + 'microop : ID PARAMS' + microop = Microop() + microop.mnemonic = t[1] + microop.params = t[2] + t[0] = microop + +# Labels in the microcode +def p_labels_0(t): + 'labels : label' + t[0] = [t[1]] + +def p_labels_1(t): + 'labels : labels label' + t[1].append(t[2]) + t[0] = t[1] + +def p_label_0(t): + 'label : ID COLON' + label = Label() + label.is_extern = False + label.text = t[1] + t[0] = label + +def p_label_1(t): + 'label : EXTERN ID COLON' + label = Label() + label.is_extern = True + label.text = t[2] + t[0] = label + +# Directives for the macroop +def p_directive_0(t): + 'directive : DOT ID' + directive = Directive() + directive.name = t[2] + t[0] = directive + +def p_directive_1(t): + 'directive : DOT ID PARAMS' + directive = Directive() + directive.name = t[2] + directive.params = t[3] + t[0] = directive + +# Parse error handler. Note that the argument here is the offending +# *token*, not a grammar symbol (hence the need to use t.value) +def p_error(t): + if t: + error(t.lineno, "syntax error at '%s'" % t.value) + else: + error(0, "unknown syntax error", True) + +class MicroAssembler(object): + + def __init__(self, macro_type, microops, + rom = None, rom_macroop_type = None): + self.lexer = lex.lex() + self.parser = yacc.yacc() + self.parser.macro_type = macro_type + self.parser.macroops = {} + self.parser.microops = microops + self.parser.rom = rom + self.parser.rom_macroop_type = rom_macroop_type + + def assemble(self, asm): + self.parser.parse(asm, lexer=self.lexer) + # Begin debug printing + for macroop in self.parser.macroops.values(): + print macroop + print self.parser.rom + # End debug printing + macroops = self.parser.macroops + self.parser.macroops = {} + return macroops diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py new file mode 100755 index 000000000..b074ecb58 --- /dev/null +++ b/src/arch/micro_asm_test.py @@ -0,0 +1,107 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from micro_asm import MicroAssembler, Combinational_Macroop, Rom_Macroop, Rom + +class Bah(object): + def __init__(self): + self.mnemonic = "bah" + +class Bah_Tweaked(object): + def __init__(self): + self.mnemonic = "bah_tweaked" + +class Hoop(object): + def __init__(self, first_param, second_param): + self.mnemonic = "hoop_%s_%s" % (first_param, second_param) + def __str__(self): + return "%s" % self.mnemonic + +class Dah(object): + def __init__(self): + self.mnemonic = "dah" + +microops = { + "bah": Bah, + "hoop": Hoop, + "dah": Dah +} + +class TestMacroop(Combinational_Macroop): + def tweak(self): + microops["bah"] = Bah_Tweaked + def untweak(self): + microops["bah"] = Bah + def print_debug(self, message): + print message + + def __init__(self, name): + super(TestMacroop, self).__init__(name) + self.directives = { + "tweak": self.tweak, + "untweak": self.untweak, + "print": self.print_debug + } + +assembler = MicroAssembler(TestMacroop, microops, Rom('main ROM'), Rom_Macroop) + +testAssembly = ''' +# Single line comment + +def rom { + goo: bah + extern la: hoop 4*8, "a" +}; /* multiline comment on one line */ + +/* multi line comment across lines + to make sure they work */ + +def macroop squishy { + .tweak + bah + .untweak + .print "In the midst" + bah + dah # single line comment after something + .tweak +}; + +#Extending the rom... +def rom +{ + #Here's more stuff for the rom + bah +}; + +def macroop squashy { + bah +}; + +def macroop jumper (bar); +''' +assembler.assemble(testAssembly) diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh index a25cce8a7..90f768d73 100644 --- a/src/arch/mips/predecoder.hh +++ b/src/arch/mips/predecoder.hh @@ -66,19 +66,12 @@ namespace MipsISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr currPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) { assert(off == 0); emi = inst; } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(0, 0, machInst); - } - bool needMoreBytes() { return true; diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index e342c79cf..c9dbb8cf2 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -41,6 +41,9 @@ if env['TARGET_ISA'] == 'sparc': Source('remote_gdb.cc') if env['FULL_SYSTEM']: + SimObject('SparcSystem.py') + SimObject('SparcTLB.py') + Source('arguments.cc') Source('pagetable.cc') Source('stacktrace.cc') diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py new file mode 100644 index 000000000..2e65f640d --- /dev/null +++ b/src/arch/sparc/SparcSystem.py @@ -0,0 +1,74 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * + +from PhysicalMemory import * +from System import System + +class SparcSystem(System): + type = 'SparcSystem' + _rom_base = 0xfff0000000 + _nvram_base = 0x1f11000000 + _hypervisor_desc_base = 0x1f12080000 + _partition_desc_base = 0x1f12000000 + # ROM for OBP/Reset/Hypervisor + rom = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_rom_base, size='8MB')), + "Memory to hold the ROM data") + # nvram + nvram = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_nvram_base, size='8kB')), + "Memory to hold the nvram data") + # hypervisor description + hypervisor_desc = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_hypervisor_desc_base, size='8kB')), + "Memory to hold the hypervisor description") + # partition description + partition_desc = Param.PhysicalMemory( + PhysicalMemory(range=AddrRange(_partition_desc_base, size='8kB')), + "Memory to hold the partition description") + + reset_addr = Param.Addr(_rom_base, "Address to load ROM at") + hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base, + "Address to load hypervisor at") + openboot_addr = Param.Addr(Addr('512kB') + _rom_base, + "Address to load openboot at") + nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram") + hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base, + "Address for the hypervisor description") + partition_desc_addr = Param.Addr(_partition_desc_base, + "Address for the partition description") + + reset_bin = Param.String("file that contains the reset code") + hypervisor_bin = Param.String("file that contains the hypervisor code") + openboot_bin = Param.String("file that contains the openboot code") + nvram_bin = Param.String("file that contains the contents of nvram") + hypervisor_desc_bin = Param.String("file that contains the hypervisor description") + partition_desc_bin = Param.String("file that contains the partition description") + diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py new file mode 100644 index 000000000..30e5ebb08 --- /dev/null +++ b/src/arch/sparc/SparcTLB.py @@ -0,0 +1,42 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +from m5.SimObject import SimObject +from m5.params import * +class SparcTLB(SimObject): + type = 'SparcTLB' + abstract = True + size = Param.Int("TLB size") + +class SparcDTB(SparcTLB): + type = 'SparcDTB' + size = 64 + +class SparcITB(SparcTLB): + type = 'SparcITB' + size = 64 diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index ea74ef179..5d36e5e41 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -248,14 +248,14 @@ def template BlockMemConstructor {{ : %(base_class)s("%(mnemonic)s", machInst) { %(constructor)s; - microOps[0] = new %(class_name)s_0(machInst); - microOps[1] = new %(class_name)s_1(machInst); - microOps[2] = new %(class_name)s_2(machInst); - microOps[3] = new %(class_name)s_3(machInst); - microOps[4] = new %(class_name)s_4(machInst); - microOps[5] = new %(class_name)s_5(machInst); - microOps[6] = new %(class_name)s_6(machInst); - microOps[7] = new %(class_name)s_7(machInst); + microops[0] = new %(class_name)s_0(machInst); + microops[1] = new %(class_name)s_1(machInst); + microops[2] = new %(class_name)s_2(machInst); + microops[3] = new %(class_name)s_3(machInst); + microops[4] = new %(class_name)s_4(machInst); + microops[5] = new %(class_name)s_5(machInst); + microops[6] = new %(class_name)s_6(machInst); + microops[7] = new %(class_name)s_7(machInst); } }}; @@ -289,9 +289,9 @@ let {{ for microPc in range(8): flag_code = '' if (microPc == 7): - flag_code = "flags[IsLastMicroOp] = true;" + flag_code = "flags[IsLastMicroop] = true;" elif (microPc == 0): - flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" + flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroop] = true;" else: flag_code = "flags[IsDelayedCommit] = true;" pcedCode = matcher.sub("Frd_%d" % microPc, code) diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa index da0f97d1b..c1d0c4f36 100644 --- a/src/arch/sparc/isa/formats/micro.isa +++ b/src/arch/sparc/isa/formats/micro.isa @@ -58,33 +58,33 @@ output header {{ class SparcMacroInst : public SparcStaticInst { protected: - const uint32_t numMicroOps; + const uint32_t numMicroops; //Constructor. SparcMacroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, uint32_t _numMicroOps) + OpClass __opClass, uint32_t _numMicroops) : SparcStaticInst(mnem, _machInst, __opClass), - numMicroOps(_numMicroOps) + numMicroops(_numMicroops) { - assert(numMicroOps); - microOps = new StaticInstPtr[numMicroOps]; - flags[IsMacroOp] = true; + assert(numMicroops); + microops = new StaticInstPtr[numMicroops]; + flags[IsMacroop] = true; } ~SparcMacroInst() { - delete [] microOps; + delete [] microops; } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - StaticInstPtr * microOps; + StaticInstPtr * microops; - StaticInstPtr fetchMicroOp(MicroPC microPC) + StaticInstPtr fetchMicroop(MicroPC microPC) { - assert(microPC < numMicroOps); - return microOps[microPC]; + assert(microPC < numMicroops); + return microops[microPC]; } %(MacroExecute)s @@ -100,7 +100,7 @@ output header {{ ExtMachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass) { - flags[IsMicroOp] = true; + flags[IsMicroop] = true; } }; diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index f511ef454..0300694cc 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -142,27 +142,38 @@ void MiscRegFile::clear() MiscReg MiscRegFile::readRegNoEffect(int miscReg) { - switch (miscReg) { - case MISCREG_TLB_DATA: - /* Package up all the data for the tlb: - * 6666555555555544444444443333333333222222222211111111110000000000 - * 3210987654321098765432109876543210987654321098765432109876543210 - * secContext | priContext | |tl|partid| |||||^hpriv - * ||||^red - * |||^priv - * ||^am - * |^lsuim - * ^lsudm - */ - return bits((uint64_t)hpstate,2,2) | - bits((uint64_t)hpstate,5,5) << 1 | - bits((uint64_t)pstate,3,2) << 2 | - bits((uint64_t)lsuCtrlReg,3,2) << 4 | - bits((uint64_t)partId,7,0) << 8 | - bits((uint64_t)tl,2,0) << 16 | - (uint64_t)priContext << 32 | - (uint64_t)secContext << 48; + // The three miscRegs are moved up from the switch statement + // due to more frequent calls. + + if (miscReg == MISCREG_GL) + return gl; + if (miscReg == MISCREG_CWP) + return cwp; + if (miscReg == MISCREG_TLB_DATA) { + /* Package up all the data for the tlb: + * 6666555555555544444444443333333333222222222211111111110000000000 + * 3210987654321098765432109876543210987654321098765432109876543210 + * secContext | priContext | |tl|partid| |||||^hpriv + * ||||^red + * |||^priv + * ||^am + * |^lsuim + * ^lsudm + */ + return bits((uint64_t)hpstate,2,2) | + bits((uint64_t)hpstate,5,5) << 1 | + bits((uint64_t)pstate,3,2) << 2 | + bits((uint64_t)lsuCtrlReg,3,2) << 4 | + bits((uint64_t)partId,7,0) << 8 | + bits((uint64_t)tl,2,0) << 16 | + (uint64_t)priContext << 32 | + (uint64_t)secContext << 48; + } + + switch (miscReg) { + //case MISCREG_TLB_DATA: + // [original contents see above] //case MISCREG_Y: // return y; //case MISCREG_CCR: @@ -207,8 +218,9 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) return tl; case MISCREG_PIL: return pil; - case MISCREG_CWP: - return cwp; + //CWP, GL moved + //case MISCREG_CWP: + // return cwp; //case MISCREG_CANSAVE: // return cansave; //case MISCREG_CANRESTORE: @@ -219,8 +231,8 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg) // return otherwin; //case MISCREG_WSTATE: // return wstate; - case MISCREG_GL: - return gl; + //case MISCREG_GL: + // return gl; /** Hyper privileged registers */ case MISCREG_HPSTATE: diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 4a8c9dc4a..38d8fd1a2 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -67,7 +67,7 @@ namespace SparcISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr currPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) { assert(off == 0); @@ -85,13 +85,6 @@ namespace SparcISA << (sizeof(MachInst) * 8)); } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(0, 0, machInst); - } - bool needMoreBytes() { return true; diff --git a/src/arch/x86/intregfile.cc b/src/arch/x86/intregfile.cc index 15e86d88b..9c9ea134e 100644 --- a/src/arch/x86/intregfile.cc +++ b/src/arch/x86/intregfile.cc @@ -87,6 +87,7 @@ #include "arch/x86/intregfile.hh" #include "base/misc.hh" +#include "base/trace.hh" #include "sim/serialize.hh" #include <string.h> @@ -119,11 +120,13 @@ void IntRegFile::clear() IntReg IntRegFile::readReg(int intReg) { + DPRINTF(X86, "Read int reg %d and got value %#x\n", intReg, regs[intReg]); return regs[intReg]; } void IntRegFile::setReg(int intReg, const IntReg &val) { + DPRINTF(X86, "Setting int reg %d to value %#x\n", intReg, val); regs[intReg] = val; } diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh index 562539de9..fc2098716 100644 --- a/src/arch/x86/intregs.hh +++ b/src/arch/x86/intregs.hh @@ -66,45 +66,45 @@ namespace X86ISA INTREG_EAX = INTREG_RAX, INTREG_AX = INTREG_RAX, INTREG_AL = INTREG_RAX, - INTREG_AH = INTREG_RAX, INTREG_RCX, INTREG_ECX = INTREG_RCX, INTREG_CX = INTREG_RCX, INTREG_CL = INTREG_RCX, - INTREG_CH = INTREG_RCX, INTREG_RDX, INTREG_EDX = INTREG_RDX, INTREG_DX = INTREG_RDX, INTREG_DL = INTREG_RDX, - INTREG_DH = INTREG_RDX, INTREG_RBX, INTREG_EBX = INTREG_RBX, INTREG_BX = INTREG_RBX, INTREG_BL = INTREG_RBX, - INTREG_BH = INTREG_RBX, INTREG_RSP, INTREG_ESP = INTREG_RSP, INTREG_SP = INTREG_RSP, INTREG_SPL = INTREG_RSP, + INTREG_AH = INTREG_RSP, INTREG_RBP, INTREG_EBP = INTREG_RBP, INTREG_BP = INTREG_RBP, INTREG_BPL = INTREG_RBP, + INTREG_CH = INTREG_RBP, INTREG_RSI, INTREG_ESI = INTREG_RSI, INTREG_SI = INTREG_RSI, INTREG_SIL = INTREG_RSI, + INTREG_DH = INTREG_RSI, INTREG_RDI, INTREG_EDI = INTREG_RDI, INTREG_DI = INTREG_RDI, INTREG_DIL = INTREG_RDI, + INTREG_BH = INTREG_RDI, INTREG_R8, INTREG_R8D = INTREG_R8, diff --git a/src/arch/x86/isa/base.isa b/src/arch/x86/isa/base.isa index eba24f709..eed969b47 100644 --- a/src/arch/x86/isa/base.isa +++ b/src/arch/x86/isa/base.isa @@ -95,6 +95,14 @@ output header {{ /** * Base class for all X86 static instructions. */ + BitUnion64(X86IntReg) + Bitfield<63,0> R; + Bitfield<31,0> E; + Bitfield<15,0> X; + Bitfield<15,8> H; + Bitfield<7, 0> L; + EndBitUnion(X86IntReg) + class X86StaticInst : public StaticInst { protected: @@ -114,10 +122,50 @@ output header {{ inline uint64_t merge(uint64_t into, uint64_t val, int size) const { - //FIXME This needs to be significantly more sophisticated + X86IntReg reg; + reg = into; + //FIXME This needs to be handle high bytes as well + switch(size) + { + case 1: + reg.L = val; + break; + case 2: + reg.X = val; + break; + case 4: + //XXX Check if this should be zeroed or sign extended + reg = 0; + reg.E = val; + break; + case 8: + reg.R = val; + break; + default: + panic("Tried to merge with unrecognized size %d.\n", size); + } return val; } + inline uint64_t pick(uint64_t from, int size) + { + X86IntReg reg; + reg = from; + switch(size) + { + case 1: + return reg.L; + case 2: + return reg.E; + case 4: + return reg.X; + case 8: + return reg.R; + default: + panic("Tried to pick with unrecognized size %d.\n", size); + } + } + }; }}; @@ -128,6 +176,39 @@ output decoder {{ ccprintf(os, "\t%s ", mnemonic); } + inline void printMnemonic(std::ostream &os, + const char * instMnemonic, const char * mnemonic) + { + ccprintf(os, "\t%s : %s ", instMnemonic, mnemonic); + } + + void printSegment(std::ostream &os, int segment) + { + switch (segment) + { + case 0: + ccprintf(os, "ES"); + break; + case 1: + ccprintf(os, "CS"); + break; + case 2: + ccprintf(os, "SS"); + break; + case 3: + ccprintf(os, "DS"); + break; + case 4: + ccprintf(os, "FS"); + break; + case 5: + ccprintf(os, "GS"); + break; + default: + panic("Unrecognized segment %d\n", segment); + } + } + void X86StaticInst::printSrcReg(std::ostream &os, int reg) const { @@ -197,6 +278,8 @@ output decoder {{ case INTREG_R15W: ccprintf(os, "r15"); break; + default: + ccprintf(os, "t%d", reg - NUM_INTREGS); } } else if (reg < Ctrl_Base_DepTag) { ccprintf(os, "%%f%d", reg - FP_Base_DepTag); diff --git a/src/arch/x86/isa/bitfields.isa b/src/arch/x86/isa/bitfields.isa index fff324caa..8707bbb4c 100644 --- a/src/arch/x86/isa/bitfields.isa +++ b/src/arch/x86/isa/bitfields.isa @@ -58,9 +58,21 @@ // Bitfield definitions. // -//Prefixes +//REX prefix def bitfield REX rex; +def bitfield REX_W rex.w; +def bitfield REX_R rex.r; +def bitfield REX_X rex.x; +def bitfield REX_B rex.b; + +//Legacy prefixes def bitfield LEGACY legacy; +def bitfield LEGACY_REPNE legacy.repne; +def bitfield LEGACY_REP legacy.rep; +def bitfield LEGACY_LOCK legacy.lock; +def bitfield LEGACY_ADDR legacy.addr; +def bitfield LEGACY_OP legacy.op; +def bitfield LEGACY_SEG legacy.seg; // Pieces of the opcode def bitfield OPCODE_NUM opcode.num; @@ -85,3 +97,11 @@ def bitfield SIB sib; def bitfield SIB_SCALE sib.scale; def bitfield SIB_INDEX sib.index; def bitfield SIB_BASE sib.base; + +def bitfield OPSIZE opSize; +def bitfield ADDRSIZE addrSize; +def bitfield STACKSIZE stackSize; + +def bitfield MODE mode; +def bitfield MODE_MODE mode.mode; +def bitfield MODE_SUBMODE mode.submode; diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index 4e044363b..b72b2b16a 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -61,12 +61,11 @@ 0x1: decode OPCODE_OP_TOP5 { format WarnUnimpl { 0x00: decode OPCODE_OP_BOTTOM3 { - 0x4: Inst::ADD(rAl,Ib); - 0x5: Inst::ADD(rAx,Iz); + 0x4: ADD(); + 0x5: ADD(); 0x6: push_ES(); 0x7: pop_ES(); - default: MultiInst::ADD(OPCODE_OP_BOTTOM3, - [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); + default: ADD(); } 0x01: decode OPCODE_OP_BOTTOM3 { 0x0: or_Eb_Gb(); @@ -129,7 +128,8 @@ {{"Tried to execute the SS segment override prefix!"}}); 0x7: aaa(); default: MultiInst::XOR(OPCODE_OP_BOTTOM3, - [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); + [Eb,Gb], [Ev,Gv], + [Gb,Eb], [Gv,Ev]); } 0x07: decode OPCODE_OP_BOTTOM3 { 0x0: cmp_Eb_Gb(); @@ -163,11 +163,11 @@ 0x7: dec_eDI(); } 0x0A: decode OPCODE_OP_BOTTOM3 { - 0x0: push_rAX(); + 0x0: Inst::PUSH(rAx); 0x1: push_rCX(); 0x2: push_rDX(); 0x3: push_rBX(); - 0x4: push_rSP(); + 0x4: Inst::PUSH(rSP); 0x5: push_rBP(); 0x6: push_rSI(); 0x7: push_rDI(); @@ -179,7 +179,7 @@ 0x3: pop_rBX(); 0x4: pop_rSP(); 0x5: pop_rBP(); - 0x6: pop_rSI(); + 0x6: Inst::POP(rSI); 0x7: pop_rDI(); } 0x0C: decode OPCODE_OP_BOTTOM3 { @@ -230,18 +230,28 @@ 0x0: group1_Eb_Ib(); 0x1: group1_Ev_Iz(); 0x2: group1_Eb_Ib(); - 0x3: group1_Ev_Ib(); + //0x3: group1_Ev_Ib(); + 0x3: decode MODRM_REG { + 0x0: add_Eb_Ib(); + 0x1: or_Eb_Ib(); + 0x2: adc_Eb_Ib(); + 0x3: sbb_Eb_Ib(); + 0x4: Inst::AND(Eb,Ib); + 0x5: sub_Eb_Ib(); + 0x6: xor_Eb_Ib(); + 0x7: cmp_Eb_Ib(); + } 0x4: test_Eb_Gb(); 0x5: test_Ev_Gv(); 0x6: xchg_Eb_Gb(); 0x7: xchg_Ev_Gv(); } 0x11: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::MOV(); //mov_Eb_Gb(); - 0x1: Inst::MOV(); //mov_Ev_Gv(); - 0x2: Inst::MOV(); //mov_Gb_Eb(); - 0x3: Inst::MOV(); //mov_Gv_Ev(); - 0x4: Inst::MOV(); //mov_MwRv_Sw(); + 0x0: Inst::MOV(Eb,Gb); + 0x1: Inst::MOV(Ev,Gv); + 0x2: Inst::MOV(Gb,Eb); + 0x3: Inst::MOV(Gv,Eb); + 0x4: mov_MwRv_Sw(); //What to do with this one? 0x5: lea_Gv_M(); 0x6: mov_Sw_MwRv(); 0x7: group10_Ev(); //Make sure this is Ev @@ -313,8 +323,14 @@ 0x3: ret_near(); 0x4: les_Gz_Mp(); 0x5: lds_Gz_Mp(); - 0x6: group12_Eb_Ib(); - 0x7: group12_Ev_Iz(); + //0x6: group12_Eb_Ib(); + 0x6: decode MODRM_REG { + 0x0: Inst::MOV(Eb,Ib); + } + //0x7: group12_Ev_Iz(); + 0x7: decode MODRM_REG { + 0x0: Inst::MOV(Ev,Iz); + } } 0x19: decode OPCODE_OP_BOTTOM3 { 0x0: enter_Iw_Ib(); diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa index 8f91c249c..37b28fe64 100644 --- a/src/arch/x86/isa/formats/multi.isa +++ b/src/arch/x86/isa/formats/multi.isa @@ -55,32 +55,23 @@ // // Authors: Gabe Black -//////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////// // -// Instructions that do the same thing to multiple sets of arguments. +// Instructions operate on one or multiple types of sets of arguments. // - -let {{ - def doInst(name, Name, opTypeSet): - if not instDict.has_key(Name): - raise Exception, "Unrecognized instruction: %s" % Name - inst = instDict[Name]() - return inst.emit(opTypeSet) -}}; +////////////////////////////////////////////////////////////////////////// def format Inst(*opTypeSet) {{ - (header_output, - decoder_output, - decode_block, - exce_output) = doInst(name, Name, list(opTypeSet)).makeList() + blocks = specializeInst(Name, list(opTypeSet), EmulEnv()) + (header_output, decoder_output, + decode_block, exec_output) = blocks.makeList() }}; def format MultiInst(switchVal, *opTypeSets) {{ switcher = {} for (count, opTypeSet) in zip(xrange(len(opTypeSets)), opTypeSets): - switcher[count] = (opTypeSet,) - (header_output, - decoder_output, - decode_block, - exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher).makeList() + switcher[count] = (Name, opTypeSet, EmulEnv()) + blocks = doSplitDecode(specializeInst, switchVal, switcher) + (header_output, decoder_output, + decode_block, exec_output) = blocks.makeList() }}; diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 3440ec5da..8bb282150 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -99,6 +99,7 @@ output header {{ #include "arch/x86/faults.hh" #include "arch/x86/isa_traits.hh" #include "arch/x86/regfile.hh" +#include "arch/x86/types.hh" #include "base/misc.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" @@ -106,6 +107,7 @@ output header {{ }}; output decoder {{ + #include "base/cprintf.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" // for Jump::branchTarget() diff --git a/src/arch/x86/isa/insts/__init__.py b/src/arch/x86/isa/insts/__init__.py new file mode 100644 index 000000000..717690926 --- /dev/null +++ b/src/arch/x86/isa/insts/__init__.py @@ -0,0 +1,79 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["arithmetic", + "cache_and_memory_management", + "compare_and_test", + "control_transfer", + "data_conversion", + "data_transfer", + "flags", + "input_output", + "load_effective_address", + "load_segment_registers", + "logical", + "no_operation", + "processor_information", + "rotate_and_shift", + "semaphores", + "string", + "system_calls"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/arithmetic/__init__.py b/src/arch/x86/isa/insts/arithmetic/__init__.py new file mode 100644 index 000000000..c7e6b8c5f --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["add_and_subtract", + "increment_and_decrement", + "multiply_and_divide"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode + diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py new file mode 100644 index 000000000..283152f30 --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class ADC(Inst): +# "Adc ^0 ^0 ^1" +# class ADD(Inst): +# "Add ^0 ^0 ^1" +# class SBB(Inst): +# "Sbb ^0 ^0 ^1" +# class SUB(Inst): +# "Sub ^0 ^0 ^1" +# class NEG(Inst): +# "Sub ^0 $0 ^0" +#}}; diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py new file mode 100644 index 000000000..c504d47ce --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class DEC(Inst): +# "GenFault ${new UnimpInstFault}" +# class INC(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py new file mode 100644 index 000000000..662022e6a --- /dev/null +++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class MUL(Inst): +# "GenFault ${new UnimpInstFault}" +# class IMUL(Inst): +# "GenFault ${new UnimpInstFault}" +# class DIV(Inst): +# "GenFault ${new UnimpInstFault}" +# class IDIV(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/cache_and_memory_management.py b/src/arch/x86/isa/insts/cache_and_memory_management.py new file mode 100644 index 000000000..b5fc43fcd --- /dev/null +++ b/src/arch/x86/isa/insts/cache_and_memory_management.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LFENCE(Inst): +# "GenFault ${new UnimpInstFault}" +# class SFENCE(Inst): +# "GenFault ${new UnimpInstFault}" +# class MFENCE(Inst): +# "GenFault ${new UnimpInstFault}" +# class PREFETCHlevel(Inst): +# "GenFault ${new UnimpInstFault}" +# class PREFETCH(Inst): +# "GenFault ${new UnimpInstFault}" +# class PREFETCHW(Inst): +# "GenFault ${new UnimpInstFault}" +# class CLFLUSH(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/__init__.py b/src/arch/x86/isa/insts/compare_and_test/__init__.py new file mode 100644 index 000000000..56f33585a --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["bit_scan", + "bit_test", + "bounds", + "compare", + "set_byte_on_condition", + "test"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/compare_and_test/bit_scan.py b/src/arch/x86/isa/insts/compare_and_test/bit_scan.py new file mode 100644 index 000000000..f04520296 --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/bit_scan.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BSF(Inst): +# "GenFault ${new UnimpInstFault}" +# class BSR(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/compare_and_test/bit_test.py new file mode 100644 index 000000000..e950f008a --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/bit_test.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BT(Inst): +# "GenFault ${new UnimpInstFault}" +# class BTC(Inst): +# "GenFault ${new UnimpInstFault}" +# class BTR(Inst): +# "GenFault ${new UnimpInstFault}" +# class BTS(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/bounds.py b/src/arch/x86/isa/insts/compare_and_test/bounds.py new file mode 100644 index 000000000..4b6cc8f71 --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/bounds.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BOUND(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/compare.py b/src/arch/x86/isa/insts/compare_and_test/compare.py new file mode 100644 index 000000000..12b5b859f --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/compare.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py new file mode 100644 index 000000000..3d9250c2d --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SETcc(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py new file mode 100644 index 000000000..b4d1cf9b8 --- /dev/null +++ b/src/arch/x86/isa/insts/compare_and_test/test.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class TEST(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/__init__.py b/src/arch/x86/isa/insts/control_transfer/__init__.py new file mode 100644 index 000000000..6694b857c --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["call", + "conditional_jump", + "interrupts_and_exceptions", + "jump", + "loop", + "xreturn"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py new file mode 100644 index 000000000..231db6e40 --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/call.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CALL(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/conditional_jump.py b/src/arch/x86/isa/insts/control_transfer/conditional_jump.py new file mode 100644 index 000000000..7ca426be6 --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/conditional_jump.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class JCC(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py new file mode 100644 index 000000000..7039b4b5c --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class INT(Inst): +# "GenFault ${new UnimpInstFault}" +# class INTO(Inst): +# "GenFault ${new UnimpInstFault}" +# class IRET(Inst): +# "GenFault ${new UnimpInstFault}" +# class IRETD(Inst): +# "GenFault ${new UnimpInstFault}" +# class IRETQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/jump.py b/src/arch/x86/isa/insts/control_transfer/jump.py new file mode 100644 index 000000000..e90e5b12b --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/jump.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class JMP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/loop.py b/src/arch/x86/isa/insts/control_transfer/loop.py new file mode 100644 index 000000000..d742f217f --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/loop.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LOOPcc(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/control_transfer/xreturn.py b/src/arch/x86/isa/insts/control_transfer/xreturn.py new file mode 100644 index 000000000..aaffa2b92 --- /dev/null +++ b/src/arch/x86/isa/insts/control_transfer/xreturn.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class RET(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/__init__.py b/src/arch/x86/isa/insts/data_conversion/__init__.py new file mode 100644 index 000000000..b3a40b8a0 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["ascii_adjust", + "bcd_adjust", + "endian_conversion", + "extract_sign_mask", + "sign_extension", + "translate"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py b/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py new file mode 100644 index 000000000..a1e322e56 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class AAA(Inst): +# "GenFault ${new UnimpInstFault}" +# class AAD(Inst): +# "GenFault ${new UnimpInstFault}" +# class AAM(Inst): +# "GenFault ${new UnimpInstFault}" +# class AAS(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py b/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py new file mode 100644 index 000000000..213724768 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class DAA(Inst): +# "GenFault ${new UnimpInstFault}" +# class DAS(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/endian_conversion.py b/src/arch/x86/isa/insts/data_conversion/endian_conversion.py new file mode 100644 index 000000000..b98d09816 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/endian_conversion.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class BSWAP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py b/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py new file mode 100644 index 000000000..1e0810594 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class MOVMSKPS(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVMSKPD(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/data_conversion/sign_extension.py new file mode 100644 index 000000000..e96eee694 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/sign_extension.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CBW(Inst): +# "GenFault ${new UnimpInstFault}" +# class CWDE(Inst): +# "GenFault ${new UnimpInstFault}" +# class CDQE(Inst): +# "GenFault ${new UnimpInstFault}" +# class CWD(Inst): +# "GenFault ${new UnimpInstFault}" +# class CDQ(Inst): +# "GenFault ${new UnimpInstFault}" +# class CQO(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_conversion/translate.py b/src/arch/x86/isa/insts/data_conversion/translate.py new file mode 100644 index 000000000..bb286b976 --- /dev/null +++ b/src/arch/x86/isa/insts/data_conversion/translate.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class XLAT(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/__init__.py b/src/arch/x86/isa/insts/data_transfer/__init__.py new file mode 100644 index 000000000..eda173b34 --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/__init__.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["conditional_move", + "move", + "stack_operations"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/data_transfer/conditional_move.py new file mode 100644 index 000000000..513e90c4e --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/conditional_move.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMOVcc(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py new file mode 100644 index 000000000..ff4af0af4 --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/move.py @@ -0,0 +1,89 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop MOV_R_R { + mov "env.reg", "env.reg", "env.regm" +}; + +def macroop MOV_M_R { + #Do a store to put the register operand into memory +}; + +def macroop MOV_R_M { + #Do a load to fill the register operand from memory +}; + +def macroop MOV_R_I { + limm "env.reg", "IMMEDIATE" +}; + +def macroop MOV_M_I { + limm "env.reg", "IMMEDIATE" + #Do a store to put the register operand into memory +}; +''' +#let {{ +# class MOV(Inst): +# "Mov ^0 ^0 ^1" +# class MOVSX(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVZX(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVD(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVNTI(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py new file mode 100644 index 000000000..50b690354 --- /dev/null +++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py @@ -0,0 +1,94 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop POP_R { + + # Make the default data size of pops 64 bits in 64 bit mode + .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + + ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] + addi "INTREG_RSP", "INTREG_RSP", "env.dataSize" +}; + +def macroop PUSH_R { + + # Make the default data size of pops 64 bits in 64 bit mode + .adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;" + + subi "INTREG_RSP", "INTREG_RSP", "env.dataSize" + st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"] +}; +''' +#let {{ +# class POP(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPA(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPA(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPAD(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSH(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHA(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHAD(Inst): +# "GenFault ${new UnimpInstFault}" +# class ENTER(Inst): +# "GenFault ${new UnimpInstFault}" +# class LEAVE(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/flags/__init__.py b/src/arch/x86/isa/insts/flags/__init__.py new file mode 100644 index 000000000..92a8e6a2d --- /dev/null +++ b/src/arch/x86/isa/insts/flags/__init__.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["load_and_store", + "push_and_pop", + "set_and_clear"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/flags/load_and_store.py b/src/arch/x86/isa/insts/flags/load_and_store.py new file mode 100644 index 000000000..c6f279a25 --- /dev/null +++ b/src/arch/x86/isa/insts/flags/load_and_store.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LAHF(Inst): +# "GenFault ${new UnimpInstFault}" +# class SAHF(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/flags/push_and_pop.py b/src/arch/x86/isa/insts/flags/push_and_pop.py new file mode 100644 index 000000000..dbb6c34c4 --- /dev/null +++ b/src/arch/x86/isa/insts/flags/push_and_pop.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class POPF(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPFD(Inst): +# "GenFault ${new UnimpInstFault}" +# class POPFQ(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHF(Inst): +# "GenFault ${new UnimpInstFault}" +# class PUSHFD(Inst): +# "GenFault ${new UnimpInstFault}" +# class pushfq(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/flags/set_and_clear.py b/src/arch/x86/isa/insts/flags/set_and_clear.py new file mode 100644 index 000000000..d70b95382 --- /dev/null +++ b/src/arch/x86/isa/insts/flags/set_and_clear.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CLC(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMC(Inst): +# "GenFault ${new UnimpInstFault}" +# class STC(Inst): +# "GenFault ${new UnimpInstFault}" +# class CLD(Inst): +# "GenFault ${new UnimpInstFault}" +# class STD(Inst): +# "GenFault ${new UnimpInstFault}" +# class CLI(Inst): +# "GenFault ${new UnimpInstFault}" +# class STI(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/input_output/__init__.py b/src/arch/x86/isa/insts/input_output/__init__.py new file mode 100644 index 000000000..54fb3d9b0 --- /dev/null +++ b/src/arch/x86/isa/insts/input_output/__init__.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["general_io", + "string_io"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/input_output/general_io.py b/src/arch/x86/isa/insts/input_output/general_io.py new file mode 100644 index 000000000..f9aa9d6e4 --- /dev/null +++ b/src/arch/x86/isa/insts/input_output/general_io.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class IN(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUT(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/input_output/string_io.py b/src/arch/x86/isa/insts/input_output/string_io.py new file mode 100644 index 000000000..a35ba772f --- /dev/null +++ b/src/arch/x86/isa/insts/input_output/string_io.py @@ -0,0 +1,78 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class INS(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class INSQ(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTS(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class OUTSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py new file mode 100644 index 000000000..dab6960b1 --- /dev/null +++ b/src/arch/x86/isa/insts/load_effective_address.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LEA(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/load_segment_registers.py b/src/arch/x86/isa/insts/load_segment_registers.py new file mode 100644 index 000000000..8aec4b99e --- /dev/null +++ b/src/arch/x86/isa/insts/load_segment_registers.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LDS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LES(Inst): +# "GenFault ${new UnimpInstFault}" +# class LFS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LGS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LSS(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOV_SEG(Inst): +# "GenFault ${new UnimpInstFault}" +# class POP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py new file mode 100644 index 000000000..824c75053 --- /dev/null +++ b/src/arch/x86/isa/insts/logical.py @@ -0,0 +1,114 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop XOR_R_R +{ + xor "env.reg", "env.reg", "env.regm" +}; + +def macroop XOR_R_I +{ + limm "NUM_INTREGS+1", "IMMEDIATE" + xor "env.reg", "env.reg", "NUM_INTREGS+1" +}; + +def macroop XOR_M_R +{ + #Do a load to get one of the sources + xor "NUM_INTREGS+1", "NUM_INTREGS+1", "env.reg" + #Do a store to write the destination +}; + +def macroop XOR_R_M +{ + #Do a load to get one of the sources + xor "env.reg", "env.reg", "NUM_INTREGS+1" +}; + +def macroop AND_R_I +{ + limm "NUM_INTREGS+1", "IMMEDIATE" + and "env.reg", "env.reg", "NUM_INTREGS+1" +}; + +def macroop AND_M_I +{ + #Do a load to get one of the sources + limm "NUM_INTREGS+1", "IMMEDIATE" + and "NUM_INTREGS+1", "NUM_INTREGS+1", "NUM_INTREGS+2" + #Do a store to write the destination +}; +''' +#let {{ +#microcodeString = ''' +# def macroop AND +# { +# And reg reg regm +# }; +# def macroop OR +# { +# Or reg reg regm +# }; +# def macroop XOR +# { +# Xor reg reg regm +# }; +# def macroop NOT +# { +# Xor reg reg "0xFFFFFFFFFFFFFFFFULL" +# }; +#''' +#}}; diff --git a/src/arch/x86/isa/insts/no_operation.py b/src/arch/x86/isa/insts/no_operation.py new file mode 100644 index 000000000..1a287aea7 --- /dev/null +++ b/src/arch/x86/isa/insts/no_operation.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class NOP(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/processor_information.py b/src/arch/x86/isa/insts/processor_information.py new file mode 100644 index 000000000..b9c8a407e --- /dev/null +++ b/src/arch/x86/isa/insts/processor_information.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CPUID(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/rotate_and_shift/__init__.py b/src/arch/x86/isa/insts/rotate_and_shift/__init__.py new file mode 100644 index 000000000..c6c019f0d --- /dev/null +++ b/src/arch/x86/isa/insts/rotate_and_shift/__init__.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["rotate", + "shift"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py new file mode 100644 index 000000000..e3aaf0043 --- /dev/null +++ b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class RCL(Inst): +# "GenFault ${new UnimpInstFault}" +# class RCR(Inst): +# "GenFault ${new UnimpInstFault}" +# class ROL(Inst): +# "GenFault ${new UnimpInstFault}" +# class ROR(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py new file mode 100644 index 000000000..f72794657 --- /dev/null +++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SAL(Inst): +# "GenFault ${new UnimpInstFault}" +# class SAR(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHL(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHR(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHLD(Inst): +# "GenFault ${new UnimpInstFault}" +# class SHRD(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/semaphores.py b/src/arch/x86/isa/insts/semaphores.py new file mode 100644 index 000000000..32f28cf82 --- /dev/null +++ b/src/arch/x86/isa/insts/semaphores.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMPXCHG(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPXCHG8B(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPXCHG16B(Inst): +# "GenFault ${new UnimpInstFault}" +# class XADD(Inst): +# "GenFault ${new UnimpInstFault}" +# class XCHG(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/__init__.py b/src/arch/x86/isa/insts/string/__init__.py new file mode 100644 index 000000000..f43a8d3e5 --- /dev/null +++ b/src/arch/x86/isa/insts/string/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["compare_strings", + "load_string", + "move_string", + "scan_string", + "store_string"] + +microcode = "" +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/string/compare_strings.py b/src/arch/x86/isa/insts/string/compare_strings.py new file mode 100644 index 000000000..1484c4706 --- /dev/null +++ b/src/arch/x86/isa/insts/string/compare_strings.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class CMPS(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class CMPSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/load_string.py b/src/arch/x86/isa/insts/string/load_string.py new file mode 100644 index 000000000..0f749a273 --- /dev/null +++ b/src/arch/x86/isa/insts/string/load_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class LODS(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class LODSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/move_string.py b/src/arch/x86/isa/insts/string/move_string.py new file mode 100644 index 000000000..0a855b384 --- /dev/null +++ b/src/arch/x86/isa/insts/string/move_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class MOVS(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSB(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSW(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSD(Inst): +# "GenFault ${new UnimpInstFault}" +# class MOVSQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/scan_string.py b/src/arch/x86/isa/insts/string/scan_string.py new file mode 100644 index 000000000..cd3d5b549 --- /dev/null +++ b/src/arch/x86/isa/insts/string/scan_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SCAS(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASB(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASW(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASD(Inst): +# "GenFault ${new UnimpInstFault}" +# class SCASQ(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/insts/string/store_string.py b/src/arch/x86/isa/insts/string/store_string.py new file mode 100644 index 000000000..08a126c1f --- /dev/null +++ b/src/arch/x86/isa/insts/string/store_string.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class STOS(Inst): +# "Add 0 0 0" +# class STOSB(Inst): +# "Add 0 0 0" +# class STOSW(Inst): +# "Add 0 0 0" +# class STOSD(Inst): +# "Add 0 0 0" +# class STOSQ(Inst): +# "Add 0 0 0" +#}}; diff --git a/src/arch/x86/isa/insts/system_calls.py b/src/arch/x86/isa/insts/system_calls.py new file mode 100644 index 000000000..e056bea84 --- /dev/null +++ b/src/arch/x86/isa/insts/system_calls.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = "" +#let {{ +# class SYSENTER(Inst): +# "GenFault ${new UnimpInstFault}" +# class SYSEXIT(Inst): +# "GenFault ${new UnimpInstFault}" +# class SYSCALL(Inst): +# "GenFault ${new UnimpInstFault}" +# class SYSRET(Inst): +# "GenFault ${new UnimpInstFault}" +#}}; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 663ec7aee..0cc818409 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -71,34 +71,34 @@ def template MacroExecPanic {{ output header {{ - // Base class for macroops - class MacroOp : public StaticInst + // Base class for combinationally generated macroops + class Macroop : public StaticInst { protected: - const uint32_t numMicroOps; + const uint32_t numMicroops; //Constructor. - MacroOp(const char *mnem, ExtMachInst _machInst, - uint32_t _numMicroOps) + Macroop(const char *mnem, ExtMachInst _machInst, + uint32_t _numMicroops) : StaticInst(mnem, _machInst, No_OpClass), - numMicroOps(_numMicroOps) + numMicroops(_numMicroops) { - assert(numMicroOps); - microOps = new StaticInstPtr[numMicroOps]; - flags[IsMacroOp] = true; + assert(numMicroops); + microops = new StaticInstPtr[numMicroops]; + flags[IsMacroop] = true; } - ~MacroOp() + ~Macroop() { - delete [] microOps; + delete [] microops; } - StaticInstPtr * microOps; + StaticInstPtr * microops; - StaticInstPtr fetchMicroOp(MicroPC microPC) + StaticInstPtr fetchMicroop(MicroPC microPC) { - assert(microPC < numMicroOps); - return microOps[microPC]; + assert(microPC < numMicroops); + return microops[microPC]; } std::string generateDisassembly(Addr pc, @@ -113,26 +113,30 @@ output header {{ // Basic instruction class declaration template. def template MacroDeclare {{ - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s + namespace X86Macroop { - public: - // Constructor. - %(class_name)s(ExtMachInst machInst); + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + // Constructor. + %(class_name)s(ExtMachInst machInst, EmulEnv env); + }; }; }}; // Basic instruction class constructor template. def template MacroConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst, %(num_micro_ops)s) + inline X86Macroop::%(class_name)s::%(class_name)s(ExtMachInst machInst, EmulEnv env) + : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s) { - %(constructor)s; - //alloc_micro_ops is the code that sets up the microOps - //array in the parent class. - %(alloc_micro_ops)s; + %(adjust_env)s; + %(constructor)s; + //alloc_microops is the code that sets up the microops + //array in the parent class. + %(alloc_microops)s; } }}; @@ -142,23 +146,103 @@ def template MacroConstructor {{ // let {{ - def genMacroOp(name, Name, opSeq): - numMicroOps = len(opSeq) - allocMicroOps = '' - micropc = 0 - for op in opSeq: - allocMicroOps += \ - "microOps[%d] = %s;\n" % \ - (micropc, op.getAllocator('"' + name + '"', True, False, #op.delayed, - micropc == 0, - micropc == numMicroOps - 1)) - micropc += 1 - iop = InstObjParams(name, Name, 'MacroOp', - {'code' : '', 'num_micro_ops' : numMicroOps, - 'alloc_micro_ops' : allocMicroOps}) - header_output = MacroDeclare.subst(iop) - decoder_output = MacroConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = '' - return (header_output, decoder_output, decode_block, exec_output) + from micro_asm import Combinational_Macroop, Rom_Macroop + class X86Macroop(Combinational_Macroop): + def setAdjustEnv(self, val): + self.adjust_env = val + def __init__(self, name): + super(X86Macroop, self).__init__(name) + self.directives = { + "adjust_env" : self.setAdjustEnv + } + self.declared = False + self.adjust_env = "" + def getAllocator(self, env): + return "new X86Macroop::%s(machInst, %s)" % (self.name, env.getAllocator()) + def getDeclaration(self): + #FIXME This first parameter should be the mnemonic. I need to + #write some code which pulls that out + iop = InstObjParams(self.name, self.name, "Macroop", {"code" : ""}) + return MacroDeclare.subst(iop); + def getDefinition(self): + #FIXME This first parameter should be the mnemonic. I need to + #write some code which pulls that out + numMicroops = len(self.microops) + allocMicroops = '' + micropc = 0 + for op in self.microops: + allocMicroops += \ + "microops[%d] = %s;\n" % \ + (micropc, op.getAllocator(True, False, + micropc == 0, + micropc == numMicroops - 1)) + micropc += 1 + iop = InstObjParams(self.name, self.name, "Macroop", + {"code" : "", "num_microops" : numMicroops, + "alloc_microops" : allocMicroops, + "adjust_env" : self.adjust_env}) + return MacroConstructor.subst(iop); +}}; + +output header {{ + struct EmulEnv + { + X86ISA::RegIndex reg; + X86ISA::RegIndex regm; + uint8_t scale; + X86ISA::RegIndex index; + X86ISA::RegIndex base; + int dataSize; + int addressSize; + int stackSize; + + EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm, + int _dataSize, int _addressSize, int _stackSize) : + reg(_reg), regm(_regm), + dataSize(_dataSize), addressSize(_addressSize), + stackSize(_stackSize) + {;} + }; +}}; + +let {{ + class EmulEnv(object): + def __init__(self): + self.reg = "0" + self.regUsed = False + self.regm = "0" + self.regmUsed = False + self.addressSize = "ADDRSIZE" + self.dataSize = "OPSIZE" + self.stackSize = "STACKSIZE" + def getAllocator(self): + return '''EmulEnv(%(reg)s, + %(regm)s, + %(dataSize)s, + %(addressSize)s, + %(stackSize)s)''' % \ + self.__dict__ + def addReg(self, reg): + if not self.regUsed: + self.reg = reg + self.regUsed = True + elif not self.regmUsed: + self.regm = reg + self.regmUsed = True + else: + raise Exception, "EmulEnv is out of register specialization spots." +}}; + +let {{ + def genMacroop(Name, env): + blocks = OutputBlocks() + if not macroopDict.has_key(Name): + raise Exception, "Unrecognized instruction: %s" % Name + macroop = macroopDict[Name] + if not macroop.declared: + blocks.header_output = macroop.getDeclaration() + blocks.decoder_output = macroop.getDefinition() + macroop.declared = True + blocks.decode_block = "return %s;\n" % macroop.getAllocator(env) + return blocks }}; diff --git a/src/arch/x86/isa/main.isa b/src/arch/x86/isa/main.isa index 063d7125d..fed8903c0 100644 --- a/src/arch/x86/isa/main.isa +++ b/src/arch/x86/isa/main.isa @@ -67,60 +67,32 @@ //////////////////////////////////////////////////////////////////// // // Namespace statement. Everything below this line will be in the -// SparcISAInst namespace. +// X86ISAInst namespace. // namespace X86ISA; -//////////////////////////////////////////////////////////////////// -// -// General infrastructure code. These files provide infrastructure -// which was developed to support x86 but isn't specific to it. -// - -//Include code to build macroops. -##include "macroop.isa" - -//Include the simple microcode assembler. This will hopefully stay -//unspecialized for x86 and can later be made available to other ISAs. -##include "microasm.isa" +//Include the operand_types and operand definitions. These are needed by +//the microop definitions. +##include "operands.isa" -//////////////////////////////////////////////////////////////////// -// -// X86 only infrastructure code. -// +//Include the bitfield definitions +##include "bitfields.isa" //Include the base class for x86 instructions, and some support code. ##include "base.isa" -//Include code to specialize an instruction template to operate on -//a particular set of operands. This is specific to x86 and the x86 -//microcode ISA. -##include "specialize.isa" - -//////////////////////////////////////////////////////////////////// -// -// Code which directly specifies isa components like instructions -// microops, and the decoder. -// - //Include the definitions for the instruction formats ##include "formats/formats.isa" -//Include the operand_types and operand definitions. These are needed by -//the microop definitions. -##include "operands.isa" - -//Include the definitions of the micro ops. -//These are StaticInst classes which stand on their own and make up an -//internal instruction set. -##include "microops/microops.isa" - -//Include the instruction definitions which are microop assembler programs. -##include "insts/insts.isa" +//This file brings in the microcode, microop classes, macroop classes, +//and supporting components and assembles everything into macroops. +##include "microasm.isa" -//Include the bitfield definitions -##include "bitfields.isa" +//Include code to specialize an instruction template to operate on +//a particular set of operands. This is specific to x86 and the x86 +//microcode ISA. +##include "specialize.isa" //Include the decoder definition ##include "decoder/decoder.isa" diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 9d21b6bcc..fde430691 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -55,177 +55,22 @@ // // Authors: Gabe Black -//////////////////////////////////////////////////////////////////// -// -// The microcode assembler -// +//Include the definitions of the micro ops. +//These are StaticInst classes which stand on their own and make up an +//internal instruction set, and also python representations which are passed +//into the microcode assembler. +##include "microops/microops.isa" -let {{ - # These are used when setting up microops so that they can specialize their - # base class template properly. - RegOpType = "RegisterOperand" - ImmOpType = "ImmediateOperand" -}}; +//Include code to build macroops in both C++ and python. +##include "macroop.isa" let {{ - class MicroOpStatement(object): - def __init__(self): - self.className = '' - self.label = '' - self.args = [] - - # This converts a list of python bools into - # a comma seperated list of C++ bools. - def microFlagsText(self, vals): - text = "" - for val in vals: - if val: - text += ", true" - else: - text += ", false" - return text - - def getAllocator(self, mnemonic, *microFlags): - args = '' - signature = "<" - emptySig = True - for arg in self.args: - if not emptySig: - signature += ", " - emptySig = False - if arg.has_key("operandImm"): - args += ", %s" % arg["operandImm"] - signature += ImmOpType - elif arg.has_key("operandReg"): - args += ", %s" % arg["operandReg"] - signature += RegOpType - elif arg.has_key("operandLabel"): - raise Exception, "Found a label while creating allocator string." - else: - raise Exception, "Unrecognized operand type." - signature += ">" - return 'new %s%s(machInst, %s%s%s)' % (self.className, signature, mnemonic, self.microFlagsText(microFlags), args) -}}; - -let{{ - def assembleMicro(name, Name, code): - - # This function takes in a block of microcode assembly and returns - # a python list of objects which describe it. - - # Keep this around in case we need it later - orig_code = code - # A list of the statements we've found thus far - statements = [] - - # Regular expressions to pull each piece of the statement out at a - # time. Each expression expects the thing it's looking for to be at - # the beginning of the line, so the previous component is stripped - # before continuing. - labelRe = re.compile(r'^[ \t]*(?P<label>\w\w*)[ \t]:') - lineRe = re.compile(r'^(?P<line>..*)(\n|$)') - classRe = re.compile(r'^[ \t]*(?P<className>[a-zA-Z_]\w*)') - # This recognizes three different flavors of operands: - # 1. Raw decimal numbers composed of digits between 0 and 9 - # 2. Code beginning with "{" and continuing until the first "}" - # ^ This one might need revising - # 3. A label, which starts with a capital or small letter, or - # underscore, which is optionally followed by a sequence of - # capital or small letters, underscores, or digts between 0 and 9 - opRe = re.compile( \ - r'^[ \t]*((\@(?P<operandLabel0>\w\w*))|' + - r'(\@\{(?P<operandLabel1>[^}]*)\})|' + - r'(\%(?P<operandReg0>\w\w*))|' + - r'(\%\{(?P<operandReg1>[^}]*)\})|' + - r'(\$(?P<operandImm0>\w\w*))|' + - r'(\$\{(?P<operandImm1>[^}]*)\}))') - lineMatch = lineRe.search(code) - while lineMatch != None: - statement = MicroOpStatement() - # Get a line and seperate it from the rest of the code - line = lineMatch.group("line") - orig_line = line - #print "Parsing line %s" % line - code = lineRe.sub('', code, 1) - - # Find the label, if any - labelMatch = labelRe.search(line) - if labelMatch != None: - statement.label = labelMatch.group("label") - #print "Found label %s." % statement.label - # Clear the label from the statement - line = labelRe.sub('', line, 1) - - # Find the class name which is roughly equivalent to the op name - classMatch = classRe.search(line) - if classMatch == None: - raise Exception, "Couldn't find class name in statement: %s" \ - % orig_line - else: - statement.className = classMatch.group("className") - #print "Found class name %s." % statement.className - - # Clear the class name from the statement - line = classRe.sub('', line, 1) - - #Find as many arguments as you can - statement.args = [] - opMatch = opRe.search(line) - while opMatch is not None: - statement.args.append({}) - # args is a list of dicts which collect different - # representations of operand values. Different forms might be - # needed in different places, for instance to replace a label - # with an offset. - for opType in ("operandLabel0", "operandReg0", "operandImm0", - "operandLabel1", "operandReg1", "operandImm1"): - if opMatch.group(opType): - statement.args[-1][opType[:-1]] = opMatch.group(opType) - if len(statement.args[-1]) == 0: - print "Problem parsing operand in statement: %s" \ - % orig_line - line = opRe.sub('', line, 1) - #print "Found operand %s." % statement.args[-1] - opMatch = opRe.search(line) - #print "Found operands", statement.args - - # Add this statement to our collection - statements.append(statement) - - # Get the next line - lineMatch = lineRe.search(code) - - # Decode the labels into displacements - - labels = {} - micropc = 0 - for statement in statements: - if statement.label: - labels[statement.label] = count - micropc += 1 - micropc = 0 - for statement in statements: - for arg in statement.args: - if arg.has_key("operandLabel"): - if not labels.has_key(arg["operandLabel"]): - raise Exception, "Unrecognized label: %s." % arg["operandLabel"] - # This is assuming that intra microcode branches go to - # the next micropc + displacement, or - # micropc + 1 + displacement. - arg["operandImm"] = labels[arg["operandLabel"]] - micropc - 1 - micropc += 1 - - if len(statements) == 0: - raise Exception, "Didn't find any microops in microcode: \n%s" % orig_code - - # If we can implement this instruction with exactly one microop, just - # use that directly. - if len(statements) == 1: - decode_block = "return %s;" % \ - statements[0].getAllocator('"' + name + '"') - return ('', '', decode_block, '') - else: - # Build a macroop to contain the sequence of microops we've - # been given. - return genMacroOp(name, Name, statements) + import sys + sys.path[0:0] = ["src/arch/x86/isa/"] + from insts import microcode + print microcode + from micro_asm import MicroAssembler, Rom_Macroop, Rom + mainRom = Rom('main ROM') + assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop) + macroopDict = assembler.assemble(microcode) }}; diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index f0aab7872..79ac4493a 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -55,25 +55,23 @@ // // Authors: Gabe Black -//The operand types a microop template can be specialized with -output header {{ - enum OperandType { - RegisterOperand, - ImmediateOperand - }; +let {{ + # This will be populated with mappings between microop mnemonics and + # the classes that represent them. + microopClasses = {} }}; //A class which is the base of all x86 micro ops. It provides a function to //set necessary flags appropriately. output header {{ - class X86MicroOpBase : public X86StaticInst + class X86MicroopBase : public X86StaticInst { protected: const char * instMnem; uint8_t opSize; uint8_t addrSize; - X86MicroOpBase(ExtMachInst _machInst, + X86MicroopBase(ExtMachInst _machInst, const char *mnem, const char *_instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, @@ -81,10 +79,10 @@ output header {{ X86StaticInst(mnem, _machInst, __opClass), instMnem(_instMnem) { - flags[IsMicroOp] = isMicro; + flags[IsMicroop] = isMicro; flags[IsDelayedCommit] = isDelayed; - flags[IsFirstMicroOp] = isFirst; - flags[IsLastMicroOp] = isLast; + flags[IsFirstMicroop] = isFirst; + flags[IsLastMicroop] = isLast; } std::string generateDisassembly(Addr pc, @@ -99,96 +97,40 @@ output header {{ }; }}; -// This sets up a class which is templated on the type of -// arguments a particular flavor of a microcode instruction -// can accept. It's parameters are specialized to create polymorphic -// behavior in microops. -def template BaseMicroOpTemplateDeclare {{ - template%(signature)s - class %(class_name)s; -}}; - -let {{ - def buildBaseMicroOpTemplate(Name, numParams): - assert(numParams > 0) - signature = "<" - signature += "int SignatureOperandTypeSpecifier0" - for count in xrange(1,numParams): - signature += \ - ", int SingatureOperandTypeSpecifier%d" % count - signature += ">" - subs = {"signature" : signature, "class_name" : Name} - return BaseMicroOpTemplateDeclare.subst(subs) -}}; +////////////////////////////////////////////////////////////////////////// +// +// Base class for the python representation of x86 microops +// +////////////////////////////////////////////////////////////////////////// let {{ - def buildMicroOpTemplateDict(*params): - signature = "<" - if len(params): - signature += params[0] - if len(params) > 1: - for param in params[1:]: - signature += ", %s" % param - signature += ">" - subs = {"param_dec" : "", "param_arg_dec" : "", - "param_init" : "", "signature" : signature} - for count in xrange(len(params)): - subs["param_dec"] += "uint64_t param%d;\n" % count - subs["param_arg_dec"] += ", uint64_t _param%d" % count - subs["param_init"] += ", param%d(_param%d)" % (count, count) - return subs -}}; - -// A tmeplate for building a specialized version of the microcode -// instruction which specifies which arguments it wants -def template MicroOpDeclare {{ - template<> - class %(class_name)s%(signature)s : public X86MicroOpBase - { - protected: - %(param_dec)s - void buildMe(); - - public: - %(class_name)s(ExtMachInst _machInst, - const char * instMnem, - bool isMicro, bool isDelayed, - bool isFirst, bool isLast - %(param_arg_dec)s); - - %(class_name)s(ExtMachInst _machInst, - const char * instMnem - %(param_arg_dec)s); - - %(BasicExecDeclare)s - }; + class X86Microop(object): + def __init__(self, name): + self.name = name + + # This converts a python bool into a C++ bool + def cppBool(self, val): + if val: + return "true" + else: + return "false" + + # This converts a list of python bools into + # a comma seperated list of C++ bools. + def microFlagsText(self, vals): + text = "" + for val in vals: + text += ", %s" % self.cppBool(val) + return text + + def getAllocator(self, mnemonic, *microFlags): + return 'new %s(machInst, %s)' % (self.className, mnemonic, self.microFlagsText(microFlags)) }}; -def template MicroOpConstructor {{ - - inline void %(class_name)s%(signature)s::buildMe() - { - %(constructor)s; - } - - inline %(class_name)s%(signature)s::%(class_name)s( - ExtMachInst machInst, const char * instMnem - %(param_arg_dec)s) : - %(base_class)s(machInst, "%(mnemonic)s", instMnem, - false, false, false, false, %(op_class)s) - %(param_init)s - { - buildMe(); - } +////////////////////////////////////////////////////////////////////////// +// +// FpOp Microop templates +// +////////////////////////////////////////////////////////////////////////// - inline %(class_name)s%(signature)s::%(class_name)s( - ExtMachInst machInst, const char * instMnem, - bool isMicro, bool isDelayed, bool isFirst, bool isLast - %(param_arg_dec)s) - : %(base_class)s(machInst, "%(mnemonic)s", instMnem, - isMicro, isDelayed, isFirst, isLast, %(op_class)s) - %(param_init)s - { - buildMe(); - } -}}; +//TODO Actually write an fp microop base class. diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa new file mode 100644 index 000000000..38b690e6a --- /dev/null +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -0,0 +1,423 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// LdStOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + + +// Load templates + +output header {{ + /** + * Base class for load and store ops + */ + class LdStOp : public X86MicroopBase + { + protected: + const uint8_t scale; + const RegIndex index; + const RegIndex base; + const uint64_t disp; + const uint8_t segment; + const RegIndex data; + const uint8_t dataSize; + const uint8_t addressSize; + + //Constructor + LdStOp(ExtMachInst _machInst, + const char * mnem, const char * _instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize, + OpClass __opClass) : + X86MicroopBase(machInst, mnem, _instMnem, + isMicro, isDelayed, isFirst, isLast, __opClass), + scale(_scale), index(_index), base(_base), + disp(_disp), segment(_segment), + data(_data), + dataSize(_dataSize), addressSize(_addressSize) + {} + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string LdStOp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + printReg(response, data); + response << ", "; + printSegment(response, segment); + ccprintf(response, ":[%d*", scale); + printReg(response, index); + response << " + "; + printReg(response, base); + ccprintf(response, " + %#x]", disp); + return response.str(); + } +}}; + +def template MicroLoadExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + Addr EA; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, 0); + if(fault == NoFault) + { + %(code)s; + } + if(fault == NoFault) + { + %(op_wb)s; + } + + return fault; + } +}}; + +def template MicroLoadInitiateAcc {{ + Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, + Trace::InstRecord * traceData) const + { + Fault fault = NoFault; + Addr EA; + + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, 0); + + return fault; + } +}}; + +def template MicroLoadCompleteAcc {{ + Fault %(class_name)s::completeAcc(PacketPtr pkt, + %(CPU_exec_context)s * xc, + Trace::InstRecord * traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + + Mem = pkt->get<typeof(Mem)>(); + %(code)s; + + if(fault == NoFault) + { + %(op_wb)s; + } + + return fault; + } +}}; + +// Store templates + +def template MicroStoreExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s * xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + Addr EA; + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + %(code)s; + + if(fault == NoFault) + { + fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, + EA, 0, 0); + } + if(fault == NoFault) + { + %(op_wb)s; + } + + return fault; + } +}}; + +def template MicroStoreInitiateAcc {{ + Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, + Trace::InstRecord * traceData) const + { + Fault fault = NoFault; + + Addr EA; + %(op_decl)s; + %(op_rd)s; + %(ea_code)s; + DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); + + %(code)s; + + if(fault == NoFault) + { + fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, + EA, 0, 0); + } + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +def template MicroStoreCompleteAcc {{ + Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc, + Trace::InstRecord * traceData) const + { + return NoFault; + } +}}; + +// Common templates + +//This delcares the initiateAcc function in memory operations +def template InitiateAccDeclare {{ + Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; +}}; + +//This declares the completeAcc function in memory operations +def template CompleteAccDeclare {{ + Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; +}}; + +def template MicroLdStOpDeclare {{ + class %(class_name)s : public %(base_class)s + { + protected: + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize); + + %(BasicExecDeclare)s + + %(InitiateAccDeclare)s + + %(CompleteAccDeclare)s + }; +}}; + +def template MicroLdStOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, + _scale, _index, _base, + _disp, _segment, _data, + _dataSize, _addressSize, %(op_class)s) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + uint8_t _scale, RegIndex _index, RegIndex _base, + uint64_t _disp, uint8_t _segment, + RegIndex _data, + uint8_t _dataSize, uint8_t _addressSize) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, + _scale, _index, _base, + _disp, _segment, _data, + _dataSize, _addressSize, %(op_class)s) + { + buildMe(); + } +}}; + +let {{ + class LdStOp(X86Microop): + def __init__(self, data, segment, addr, disp): + self.data = data + [self.scale, self.index, self.base] = addr + self.disp = disp + self.segment = segment + self.dataSize = "env.dataSize" + self.addressSize = "env.addressSize" + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(scale)s, %(index)s, %(base)s, + %(disp)s, %(segment)s, %(data)s, + %(dataSize)s, %(addressSize)s)''' % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "scale" : self.scale, "index" : self.index, + "base" : self.base, + "disp" : self.disp, + "segment" : self.segment, "data" : self.data, + "dataSize" : self.dataSize, "addressSize" : self.addressSize} + return allocator +}}; + +let {{ + + # Make these empty strings so that concatenating onto + # them will always work. + header_output = "" + decoder_output = "" + exec_output = "" + + calculateEA = "EA = scale * Index + Base + disp;" + + def defineMicroLoadOp(mnemonic, code): + global header_output + global decoder_output + global exec_output + global microopClasses + Name = mnemonic + name = mnemonic.lower() + + # Build up the all register version of this micro op + iop = InstObjParams(name, Name, 'LdStOp', + {"code": code, "ea_code": calculateEA}) + header_output += MicroLdStOpDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroLoadExecute.subst(iop) + exec_output += MicroLoadInitiateAcc.subst(iop) + exec_output += MicroLoadCompleteAcc.subst(iop) + + class LoadOp(LdStOp): + def __init__(self, data, segment, addr, disp = 0): + super(LoadOp, self).__init__(data, segment, addr, disp) + self.className = Name + self.mnemonic = name + + microopClasses[name] = LoadOp + + defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') + + def defineMicroStoreOp(mnemonic, code): + global header_output + global decoder_output + global exec_output + global microopClasses + Name = mnemonic + name = mnemonic.lower() + + # Build up the all register version of this micro op + iop = InstObjParams(name, Name, 'LdStOp', + {"code": code, "ea_code": calculateEA}) + header_output += MicroLdStOpDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroStoreExecute.subst(iop) + exec_output += MicroStoreInitiateAcc.subst(iop) + exec_output += MicroStoreCompleteAcc.subst(iop) + + class StoreOp(LdStOp): + def __init__(self, data, addr, segment): + super(LoadOp, self).__init__(data, addr, segment) + self.className = Name + self.mnemonic = name + + microopClasses[name] = StoreOp + + defineMicroLoadOp('St', 'Mem = Data;') +}}; + diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa new file mode 100644 index 000000000..141d7523f --- /dev/null +++ b/src/arch/x86/isa/microops/limmop.isa @@ -0,0 +1,170 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// LIMMOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + +def template MicroLimmOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + %(op_decl)s; + %(op_rd)s; + %(code)s; + %(op_wb)s; + return NoFault; + } +}}; + +def template MicroLimmOpDeclare {{ + class %(class_name)s : public X86MicroopBase + { + protected: + const RegIndex dest; + const uint64_t imm; + void buildMe(); + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _dest, uint64_t _imm); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + RegIndex _dest, uint64_t _imm); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroLimmOpDisassembly {{ + std::string %(class_name)s::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + printReg(response, dest); + response << ", "; + ccprintf(response, "%#x", imm); + return response.str(); + } +}}; + +def template MicroLimmOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + RegIndex _dest, uint64_t _imm) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s), + dest(_dest), imm(_imm) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _dest, uint64_t _imm) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s), + dest(_dest), imm(_imm) + { + buildMe(); + } +}}; + +let {{ + class LimmOp(X86Microop): + def __init__(self, dest, imm): + self.className = "Limm" + self.mnemonic = "limm" + self.dest = dest + self.imm = imm + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(dest)s, %(imm)s)''' % { + "class_name" : self.className, + "mnemonic" : self.mnemonic, + "flags" : self.microFlagsText(microFlags), + "dest" : self.dest, "imm" : self.imm } + return allocator + + microopClasses["limm"] = LimmOp +}}; + +let {{ + # Build up the all register version of this micro op + iop = InstObjParams("limm", "Limm", 'X86MicroopBase', + {"code" : "DestReg = imm;"}) + header_output += MicroLimmOpDeclare.subst(iop) + decoder_output += MicroLimmOpConstructor.subst(iop) + decoder_output += MicroLimmOpDisassembly.subst(iop) + exec_output += MicroLimmOpExecute.subst(iop) +}}; diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa index d877152eb..50c9ac498 100644 --- a/src/arch/x86/isa/microops/microops.isa +++ b/src/arch/x86/isa/microops/microops.isa @@ -56,8 +56,14 @@ //Common microop stuff ##include "base.isa" -//A microop that generates a specified fault -##include "fault.isa" +//Register microop definitions +##include "regop.isa" -//Integer microop definitions -##include "int.isa" +//Load immediate microop definition +##include "limmop.isa" + +//Load/store microop definitions +##include "ldstop.isa" + +//Miscellaneous microop definitions +##include "specop.isa" diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa new file mode 100644 index 000000000..d5fb25cb5 --- /dev/null +++ b/src/arch/x86/isa/microops/regop.isa @@ -0,0 +1,413 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// RegOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + +output header {{ + /** + * Base classes for RegOps which provides a generateDisassembly method. + */ + class RegOp : public X86MicroopBase + { + protected: + const RegIndex src1; + const RegIndex src2; + const RegIndex dest; + const bool setStatus; + const uint8_t dataSize; + const uint8_t ext; + + // Constructor + RegOp(ExtMachInst _machInst, + const char *mnem, const char *_instMnem, + bool isMicro, bool isDelayed, + bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext, + OpClass __opClass) : + X86MicroopBase(_machInst, mnem, _instMnem, + isMicro, isDelayed, isFirst, isLast, + __opClass), + src1(_src1), src2(_src2), dest(_dest), + setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + }; + + class RegOpImm : public X86MicroopBase + { + protected: + const RegIndex src1; + const uint8_t imm8; + const RegIndex dest; + const bool setStatus; + const uint8_t dataSize; + const uint8_t ext; + + // Constructor + RegOpImm(ExtMachInst _machInst, + const char * mnem, const char *_instMnem, + bool isMicro, bool isDelayed, + bool isFirst, bool isLast, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext, + OpClass __opClass) : + X86MicroopBase(_machInst, mnem, _instMnem, + isMicro, isDelayed, isFirst, isLast, + __opClass), + src1(_src1), imm8(_imm8), dest(_dest), + setStatus(_setStatus), dataSize(_dataSize), ext(_ext) + { + } + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + }; +}}; + +output decoder {{ + std::string RegOp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + printReg(response, dest); + response << ", "; + printReg(response, src1); + response << ", "; + printReg(response, src2); + return response.str(); + } + + std::string RegOpImm::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + printReg(response, dest); + response << ", "; + printReg(response, src1); + ccprintf(response, ", %#x", imm8); + return response.str(); + } +}}; + +def template MicroRegOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + + //Write the resulting state to the execution context + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +def template MicroRegOpImmExecute {{ + Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + %(code)s; + + //Write the resulting state to the execution context + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +def template MicroRegOpDeclare {{ + class %(class_name)s : public %(base_class)s + { + protected: + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroRegOpImmDeclare {{ + + class %(class_name)sImm : public %(base_class)s + { + protected: + void buildMe(); + + public: + %(class_name)sImm(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(class_name)sImm(ExtMachInst _machInst, + const char * instMnem, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroRegOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, + _src1, _src2, _dest, _setStatus, _dataSize, _ext, + %(op_class)s) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, + _src1, _src2, _dest, _setStatus, _dataSize, _ext, + %(op_class)s) + { + buildMe(); + } +}}; + +def template MicroRegOpImmConstructor {{ + + inline void %(class_name)sImm::buildMe() + { + %(constructor)s; + } + + inline %(class_name)sImm::%(class_name)sImm( + ExtMachInst machInst, const char * instMnem, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, + _src1, _imm8, _dest, _setStatus, _dataSize, _ext, + %(op_class)s) + { + buildMe(); + } + + inline %(class_name)sImm::%(class_name)sImm( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, uint8_t _imm8, RegIndex _dest, + bool _setStatus, uint8_t _dataSize, uint8_t _ext) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, + _src1, _imm8, _dest, _setStatus, _dataSize, _ext, + %(op_class)s) + { + buildMe(); + } +}}; + +let {{ + class RegOp(X86Microop): + def __init__(self, dest, src1, src2): + self.dest = dest + self.src1 = src1 + self.src2 = src2 + self.setStatus = False + self.dataSize = "env.dataSize" + self.ext = 0 + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(src1)s, %(src2)s, %(dest)s, + %(setStatus)s, %(dataSize)s, %(ext)s)''' % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "src2" : self.src2, + "dest" : self.dest, + "setStatus" : self.cppBool(self.setStatus), + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator + + class RegOpImm(X86Microop): + def __init__(self, dest, src1, imm8): + self.dest = dest + self.src1 = src1 + self.imm8 = imm8 + self.setStatus = False + self.dataSize = "env.dataSize" + self.ext = 0 + + def getAllocator(self, *microFlags): + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(src1)s, %(imm8)s, %(dest)s, + %(setStatus)s, %(dataSize)s, %(ext)s)''' % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "imm8" : self.imm8, + "dest" : self.dest, + "setStatus" : self.cppBool(self.setStatus), + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator +}}; + +let {{ + + # Make these empty strings so that concatenating onto + # them will always work. + header_output = "" + decoder_output = "" + exec_output = "" + + def defineMicroRegOp(mnemonic, code): + global header_output + global decoder_output + global exec_output + global microopClasses + Name = mnemonic + name = mnemonic.lower() + + # Find op2 in each of the instruction definitions. Create two versions + # of the code, one with an integer operand, and one with an immediate + # operand. + matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") + regCode = matcher.sub("SrcReg2", code) + immCode = matcher.sub("imm8", code) + + # Build up the all register version of this micro op + iop = InstObjParams(name, Name, 'RegOp', {"code" : regCode}) + header_output += MicroRegOpDeclare.subst(iop) + decoder_output += MicroRegOpConstructor.subst(iop) + exec_output += MicroRegOpExecute.subst(iop) + + class RegOpChild(RegOp): + def __init__(self, dest, src1, src2): + super(RegOpChild, self).__init__(dest, src1, src2) + self.className = Name + self.mnemonic = name + + microopClasses[name] = RegOpChild + + # Build up the immediate version of this micro op + iop = InstObjParams(name + "i", Name, + 'RegOpImm', {"code" : immCode}) + header_output += MicroRegOpImmDeclare.subst(iop) + decoder_output += MicroRegOpImmConstructor.subst(iop) + exec_output += MicroRegOpImmExecute.subst(iop) + + class RegOpImmChild(RegOpImm): + def __init__(self, dest, src1, imm): + super(RegOpImmChild, self).__init__(dest, src1, imm) + self.className = Name + "Imm" + self.mnemonic = name + "i" + + microopClasses[name + "i"] = RegOpImmChild + + defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF + defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') + defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF + defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF + defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') + defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF + defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') + defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg + defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') + +}}; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa new file mode 100644 index 000000000..96fdf1c5e --- /dev/null +++ b/src/arch/x86/isa/microops/specop.isa @@ -0,0 +1,125 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// Fault Microop +// +////////////////////////////////////////////////////////////////////////// + +def template MicroFaultExecute {{ + Fault %(class_name)s ::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + //Return the fault we were constructed with + return fault; + } +}}; + +def template MicroFaultDeclare {{ + class %(class_name)s : public X86MicroopBase + { + protected: + Fault fault; + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + Fault _fault); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + Fault _fault); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroFaultConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, Fault _fault) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, %(op_class)s), fault(_fault) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + Fault _fault) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, %(op_class)s), + fault(_fault) + { + buildMe(); + } +}}; + +let {{ + # This microop takes in a single parameter, a fault to return. + iop = InstObjParams("fault", "GenFault", 'X86MicroopBase', {"code" : ""}) + header_output += MicroFaultDeclare.subst(iop) + decoder_output += MicroFaultConstructor.subst(iop) + exec_output += MicroFaultExecute.subst(iop) +}}; diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index af469ab3d..b2ac17d66 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -96,7 +96,12 @@ def operand_types {{ }}; def operands {{ - 'IntRegOp0': ('IntReg', 'udw', 'param0', 'IsInteger', 1), - 'IntRegOp1': ('IntReg', 'udw', 'param1', 'IsInteger', 2), - 'IntRegOp2': ('IntReg', 'udw', 'param2', 'IsInteger', 2), + 'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1), + 'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2), + 'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3), + 'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4), + 'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5), + 'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6), + 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10), + 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index ff92c3551..bb2be47d9 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -66,24 +66,26 @@ let {{ # vals is a dict which matches case values with what should be decoded to. # builder is called on the exploded contents of "vals" values to generate # whatever code should be used. - def doSplitDecode(name, Name, builder, switchVal, vals, default = None): + def doSplitDecode(builder, switchVal, vals, default = None): blocks = OutputBlocks() - blocks.decode_block += 'switch(%s) {\n' % switchVal + blocks.decode_block = 'switch(%s) {\n' % switchVal for (val, todo) in vals.items(): - built = builder(name, Name, *todo) - built.decode_block = '\tcase %s: %s\n' % (val, built.decode_block) - blocks.append(built) + new_blocks = builder(*todo) + new_blocks.decode_block = \ + '\tcase %s: %s\n' % (val, new_blocks.decode_block) + blocks.append(new_blocks) if default: - built = builder(name, Name, *default) - built.decode_block = '\tdefault: %s\n' % built.decode_block - blocks.append(built) + new_blocks = builder(*default) + new_blocks.decode_block = \ + '\tdefault: %s\n' % new_blocks.decode_block + blocks.append(new_blocks) blocks.decode_block += '}\n' return blocks }}; let {{ class OpType(object): - parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Za-z0-9][A-Za-z0-9]*))") + parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Z0-9]*)(?P<rsize>[a-z]*))") def __init__(self, opTypeString): match = OpType.parser.search(opTypeString) if match == None: @@ -91,74 +93,78 @@ let {{ self.reg = match.group("reg") self.tag = match.group("tag") self.size = match.group("size") + self.rsize = match.group("rsize") + + ModRMRegIndex = "(MODRM_REG | (REX_R << 3))" + ModRMRMIndex = "(MODRM_RM | (REX_B << 3))" # This function specializes the given piece of code to use a particular - # set of argument types described by "opTypes". These are "implemented" - # in reverse order. - def specializeInst(name, Name, code, opTypes): - opNum = len(opTypes) - 1 + # set of argument types described by "opTypes". + def specializeInst(Name, opTypes, env): + # print "Specializing %s with opTypes %s" % (Name, opTypes) while len(opTypes): - # print "Building a composite op with tags", opTypes - # print "And code", code - opNum = len(opTypes) - 1 - # A regular expression to find the operand placeholders we're - # interested in. - opRe = re.compile("\\^(?P<operandNum>%d)(?=[^0-9]|$)" % opNum) - - # Parse the operand type strign we're working with - opType = OpType(opTypes[opNum]) + # Parse the operand type string we're working with + opType = OpType(opTypes[0]) if opType.reg: #Figure out what to do with fixed register operands - if opType.reg in ("Ax", "Bx", "Cx", "Dx"): - code = opRe.sub("%%{INTREG_R%s}" % opType.reg.upper(), code) - elif opType.reg == "Al": - # We need a way to specify register width - code = opRe.sub("%{INTREG_RAX}", code) + #This is the index to use, so we should stick it some place. + if opType.reg in ("A", "B", "C", "D"): + env.addReg("INTREG_R%sX" % opType.reg) else: - print "Didn't know how to encode fixed register %s!" % opType.reg + env.addReg("INTREG_R%s" % opType.reg) + if opType.size: + if opType.rsize in ("l", "h", "b"): + print "byte" + elif opType.rsize == "x": + print "word" + else: + print "Didn't recognize fixed register size %s!" % opType.rsize + Name += "_R" elif opType.tag == None or opType.size == None: raise Exception, "Problem parsing operand tag: %s" % opType.tag elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"): # Use the "reg" field of the ModRM byte to select the register - code = opRe.sub("%{(uint8_t)MODRM_REG}", code) + env.addReg(ModRMRegIndex) + Name += "_R" elif opType.tag in ("E", "Q", "W"): # This might refer to memory or to a register. We need to # divide it up farther. - regCode = opRe.sub("%{(uint8_t)MODRM_RM}", code) regTypes = copy.copy(opTypes) - regTypes.pop(-1) + regTypes.pop(0) + regEnv = copy.copy(env) + regEnv.addReg(ModRMRMIndex) + regName = Name + "_R" # This needs to refer to memory, but we'll fill in the details # later. It needs to take into account unaligned memory # addresses. - code = "GenFault ${new UnimpInstFault}\n" + code - memCode = opRe.sub("%0", code) memTypes = copy.copy(opTypes) - memTypes.pop(-1) - return doSplitDecode(name, Name, specializeInst, "MODRM_MOD", - {"3" : (regCode, regTypes)}, (memCode, memTypes)) + memTypes.pop(0) + memEnv = copy.copy(env) + memName = Name + "_M" + print "%0" + return doSplitDecode(specializeInst, "MODRM_MOD", + {"3" : (regName, regTypes, regEnv)}, + (memName, memTypes, memEnv)) elif opType.tag in ("I", "J"): - # Immediates are already in the instruction, so don't leave in - # those parameters - code = opRe.sub("${IMMEDIATE}", code) + # Immediates + Name += "_I" elif opType.tag == "M": # This needs to refer to memory, but we'll fill in the details # later. It needs to take into account unaligned memory # addresses. - code = "GenFault ${new UnimpInstFault}\n" + code - code = opRe.sub("%0", code) + print "%0" + Name += "_M" elif opType.tag in ("PR", "R", "VR"): # There should probably be a check here to verify that mod # is equal to 11b - code = opRe.sub("%{(uint8_t)MODRM_RM}", code) + env.addReg(ModRMRMIndex) + Name += "_R" else: raise Exception, "Unrecognized tag %s." % opType.tag - opTypes.pop(-1) + opTypes.pop(0) - # At this point, we've built up "code" to have all the necessary extra - # instructions needed to implement whatever types of operands were - # specified. Now we'll assemble it it into a StaticInst. - blocks = OutputBlocks() - blocks.append(assembleMicro(name, Name, code)) - return blocks + # Generate code to return a macroop of the given name which will + # operate in the "emulation environment" env + return genMacroop(Name, env) }}; diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 5a625f741..4c02ee35e 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -81,8 +81,8 @@ namespace X86ISA // These enumerate all the registers for dependence tracking. enum DependenceTags { - //The number of microcode registers needs to be added to this - FP_Base_DepTag = 16, + //There are 16 microcode registers at the moment + FP_Base_DepTag = 32, Ctrl_Base_DepTag = FP_Base_DepTag + //mmx/x87 registers @@ -93,7 +93,7 @@ namespace X86ISA // semantically meaningful register indices //There is no such register in X86 - const int ZeroReg = 0; + const int ZeroReg = NUM_INTREGS; const int StackPointerReg = INTREG_RSP; //X86 doesn't seem to have a link register const int ReturnAddressReg = 0; diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc index 573012ee6..3ed18aeb2 100644 --- a/src/arch/x86/predecoder.cc +++ b/src/arch/x86/predecoder.cc @@ -62,6 +62,24 @@ namespace X86ISA { + void Predecoder::reset() + { + origPC = basePC + offset; + DPRINTF(Predecoder, "Setting origPC to %#x\n", origPC); + emi.rex = 0; + emi.legacy = 0; + emi.opcode.num = 0; + + immediateCollected = 0; + emi.immediate = 0; + displacementCollected = 0; + emi.displacement = 0; + + emi.modRM = 0; + emi.sib = 0; + emi.mode = 0; + } + void Predecoder::process() { //This function drives the predecoder state machine. @@ -78,6 +96,9 @@ namespace X86ISA uint8_t nextByte = getNextByte(); switch(state) { + case ResetState: + reset(); + state = PrefixState; case PrefixState: state = doPrefixState(nextByte); break; @@ -150,7 +171,6 @@ namespace X86ISA emi.rex = nextByte; break; case 0: - emi.opcode.num = 0; nextState = OpcodeState; break; default: @@ -188,55 +208,50 @@ namespace X86ISA DPRINTF(Predecoder, "Found opcode %#x.\n", nextByte); emi.opcode.op = nextByte; - //Prepare for any immediate/displacement we might need - immediateCollected = 0; - emi.immediate = 0; - displacementCollected = 0; - emi.displacement = 0; - //Figure out the effective operand size. This can be overriden to //a fixed value at the decoder level. + int logOpSize; if(/*FIXME long mode*/1) { - if(emi.rex && emi.rex.w) - emi.opSize = 3; // 64 bit operand size + if(emi.rex.w) + logOpSize = 3; // 64 bit operand size else if(emi.legacy.op) - emi.opSize = 1; // 16 bit operand size + logOpSize = 1; // 16 bit operand size else - emi.opSize = 2; // 32 bit operand size + logOpSize = 2; // 32 bit operand size } else if(/*FIXME default 32*/1) { if(emi.legacy.op) - emi.opSize = 1; // 16 bit operand size + logOpSize = 1; // 16 bit operand size else - emi.opSize = 2; // 32 bit operand size + logOpSize = 2; // 32 bit operand size } else // 16 bit default operand size { if(emi.legacy.op) - emi.opSize = 2; // 32 bit operand size + logOpSize = 2; // 32 bit operand size else - emi.opSize = 1; // 16 bit operand size + logOpSize = 1; // 16 bit operand size } //Figure out how big of an immediate we'll retreive based //on the opcode. int immType = ImmediateType[emi.opcode.num - 1][nextByte]; - immediateSize = SizeTypeToSize[emi.opSize - 1][immType]; + immediateSize = SizeTypeToSize[logOpSize - 1][immType]; + + //Set the actual op size + emi.opSize = 1 << logOpSize; //Determine what to expect next if (UsesModRM[emi.opcode.num - 1][nextByte]) { nextState = ModRMState; } else { - //If there's no modRM byte, set it to 0 so we can detect - //that later. - emi.modRM = 0; if(immediateSize) { nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } } } @@ -282,7 +297,7 @@ namespace X86ISA nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } //The ModRM byte is consumed no matter what consumeByte(); @@ -304,7 +319,7 @@ namespace X86ISA nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } return nextState; } @@ -344,7 +359,7 @@ namespace X86ISA nextState = ImmediateState; } else { emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } } else @@ -375,12 +390,19 @@ namespace X86ISA //Instructions which use true 64 bit immediates won't be //affected, and instructions that use true 32 bit immediates //won't notice. - if(immediateSize == 4) + switch(immediateSize) + { + case 4: emi.immediate = sext<32>(emi.immediate); + break; + case 1: + emi.immediate = sext<8>(emi.immediate); + } + DPRINTF(Predecoder, "Collected immediate %#x.\n", emi.immediate); emiIsReady = true; - nextState = PrefixState; + nextState = ResetState; } else nextState = ImmediateState; diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index 6562ab9f5..3c858f061 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -60,6 +60,8 @@ #include "arch/x86/types.hh" #include "base/bitfield.hh" +#include "base/misc.hh" +#include "base/trace.hh" #include "sim/host.hh" class ThreadContext; @@ -81,6 +83,8 @@ namespace X86ISA MachInst fetchChunk; //The pc of the start of fetchChunk Addr basePC; + //The pc the current instruction started at + Addr origPC; //The offset into fetchChunk of current processing int offset; //The extended machine instruction being generated @@ -130,6 +134,8 @@ namespace X86ISA outOfBytes = true; } + void reset(); + //State machine state protected: //Whether or not we're out of bytes @@ -144,6 +150,7 @@ namespace X86ISA int immediateCollected; enum State { + ResetState, PrefixState, OpcodeState, ModRMState, @@ -166,10 +173,13 @@ namespace X86ISA public: Predecoder(ThreadContext * _tc) : - tc(_tc), basePC(0), offset(0), + tc(_tc), basePC(0), origPC(0), offset(0), outOfBytes(true), emiIsReady(false), - state(PrefixState) - {} + state(ResetState) + { + emi.mode.mode = LongMode; + emi.mode.submode = SixtyFourBitMode; + } ThreadContext * getTC() { @@ -185,9 +195,9 @@ namespace X86ISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr currPC, Addr off, MachInst data) + void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data) { - basePC = currPC; + basePC = fetchPC; offset = off; fetchChunk = data; assert(off < sizeof(MachInst)); @@ -195,13 +205,6 @@ namespace X86ISA process(); } - //Use this to give data to the predecoder. This should be used - //when instructions are executed in order. - void moreBytes(MachInst machInst) - { - moreBytes(basePC + sizeof(machInst), 0, machInst); - } - bool needMoreBytes() { return outOfBytes; @@ -219,6 +222,15 @@ namespace X86ISA emiIsReady = false; return emi; } + + int getInstSize() + { + DPRINTF(Predecoder, + "Calculating the instruction size: " + "basePC: %#x offset: %#x origPC: %#x\n", + basePC, offset, origPC); + return basePC + offset - origPC; + } }; }; diff --git a/src/arch/x86/predecoder_tables.cc b/src/arch/x86/predecoder_tables.cc index 38b9c57a3..6fe54b719 100644 --- a/src/arch/x86/predecoder_tables.cc +++ b/src/arch/x86/predecoder_tables.cc @@ -170,7 +170,7 @@ namespace X86ISA // noimm byte word dword qword oword vword zword enter pointer {0, 1, 2, 4, 8, 16, 2, 2, 3, 4 }, //16 bit {0, 1, 2, 4, 8, 16, 4, 4, 3, 6 }, //32 bit - {0, 1, 2, 4, 8, 16, 4, 8, 3, 0 } //64 bit + {0, 1, 2, 4, 8, 16, 8, 4, 3, 0 } //64 bit }; //This table determines the immediate type. The first index is the diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc index 568eb1d94..f54f531e2 100644 --- a/src/arch/x86/regfile.cc +++ b/src/arch/x86/regfile.cc @@ -117,7 +117,8 @@ void RegFile::setNextPC(Addr val) Addr RegFile::readNextNPC() { - return nextRip + sizeof(MachInst); + //There's no way to know how big the -next- instruction will be. + return nextRip + 1; } void RegFile::setNextNPC(Addr val) diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 022f20ee5..298dff80b 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -120,6 +120,24 @@ namespace X86ISA Bitfield<2,0> bottom3; EndBitUnion(Opcode) + BitUnion8(OperatingMode) + Bitfield<3> mode; + Bitfield<2,0> submode; + EndBitUnion(OperatingMode) + + enum X86Mode { + LongMode, + LegacyMode + }; + + enum X86SubMode { + SixtyFourBitMode, + CompatabilityMode, + ProtectedMode, + Virtual8086Mode, + RealMode + }; + //The intermediate structure the x86 predecoder returns. struct ExtMachInst { @@ -149,7 +167,13 @@ namespace X86ISA //The effective operand size. uint8_t opSize; - //The + //The effective address size. + uint8_t addrSize; + //The effective stack size. + uint8_t stackSize; + + //Mode information + OperatingMode mode; }; inline static std::ostream & @@ -191,6 +215,14 @@ namespace X86ISA return false; if(emi1.displacement != emi2.displacement) return false; + if(emi1.mode != emi2.mode) + return false; + if(emi1.opSize != emi2.opSize) + return false; + if(emi1.addrSize != emi2.addrSize) + return false; + if(emi1.stackSize != emi2.stackSize) + return false; return true; } diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 1c98e7fbc..3f3f1cca3 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -79,7 +79,8 @@ namespace __hash_namespace { ((uint64_t)emi.opcode.prefixB << 8) | ((uint64_t)emi.opcode.op)) ^ emi.immediate ^ emi.displacement ^ - emi.opSize; + emi.mode ^ + emi.opSize ^ emi.addrSize ^ emi.stackSize; }; }; } diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index fa54c24e9..e45d62f8f 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -60,8 +60,7 @@ namespace X86ISA { - //XXX This will definitely need to be something larger in the future. - const int NumMicroIntRegs = 0; + const int NumMicroIntRegs = 16; const int NumMMXRegs = 8; const int NumXMMRegs = 16; diff --git a/src/base/SConscript b/src/base/SConscript index cc9d06a0e..ca68bfb60 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -57,7 +57,8 @@ Source('circlebuf.cc') Source('cprintf.cc') Source('crc.cc') Source('fast_alloc.cc') -Source('fenv.c') +if env['USE_FENV']: + Source('fenv.c') Source('fifo_buffer.cc') Source('hostinfo.cc') Source('hybrid_pred.cc') diff --git a/src/base/fenv.c b/src/base/fenv.c index 269913a60..2ec2f796f 100644 --- a/src/base/fenv.c +++ b/src/base/fenv.c @@ -39,7 +39,7 @@ static const int m5_round_ops[] = {FE_DOWNWARD, FE_TONEAREST, FE_TOWARDZERO, FE void m5_fesetround(int rm) { - assert(rm > 0 && rm < 4); + assert(rm >= 0 && rm < 4); fesetround(m5_round_ops[rm]); } diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index 8f157da28..f76ea593b 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -31,23 +31,14 @@ #include <string> -// Because of the -Wundef flag we have to do this -#define __LIBELF_INTERNAL__ 0 -#define __LIBELF_NEED_LINK_H 0 -#define __LIBELF_SYMBOL_VERSIONS 0 - #include "gelf.h" #include "base/loader/elf_object.hh" -#include "base/misc.hh" - #include "base/loader/symtab.hh" - +#include "base/misc.hh" #include "base/trace.hh" // for DPRINTF - #include "sim/byteswap.hh" - using namespace std; ObjectFile * diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 761b30c2b..8d3f53d4c 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -2094,9 +2094,13 @@ class UnaryNode : public Node return vresult; } - Result total() const { - Op op; - return op(l->total()); + Result total() const + { + const VResult &vec = this->result(); + Result total = 0; + for (int i = 0; i < size(); i++) + total += vec[i]; + return total; } virtual size_t size() const { return l->size(); } @@ -2149,9 +2153,13 @@ class BinaryNode : public Node return vresult; } - Result total() const { - Op op; - return op(l->total(), r->total()); + Result total() const + { + const VResult &vec = this->result(); + Result total = 0; + for (int i = 0; i < size(); i++) + total += vec[i]; + return total; } virtual size_t size() const { diff --git a/src/python/m5/objects/BaseCPU.py b/src/cpu/BaseCPU.py index 986220c3f..6c2aace51 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -1,12 +1,45 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.SimObject import SimObject from m5.params import * from m5.proxy import * from m5 import build_env -from AlphaTLB import AlphaDTB, AlphaITB -from SparcTLB import SparcDTB, SparcITB from Bus import Bus import sys +if build_env['FULL_SYSTEM']: + if build_env['TARGET_ISA'] == 'alpha': + from AlphaTLB import AlphaDTB, AlphaITB + + if build_env['TARGET_ISA'] == 'sparc': + from SparcTLB import SparcDTB, SparcITB + class BaseCPU(SimObject): type = 'BaseCPU' abstract = True diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py new file mode 100644 index 000000000..ad2d1b87b --- /dev/null +++ b/src/cpu/FuncUnit.py @@ -0,0 +1,46 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.SimObject import SimObject +from m5.params import * + +class OpClass(Enum): + vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', + 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', + 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] + +class OpDesc(SimObject): + type = 'OpDesc' + issueLat = Param.Int(1, "cycles until another can be issued") + opClass = Param.OpClass("type of operation") + opLat = Param.Int(1, "cycles until result is available") + +class FUDesc(SimObject): + type = 'FUDesc' + count = Param.Int("number of these FU's available") + opList = VectorParam.OpDesc("operation classes for this FU type") diff --git a/src/cpu/IntrControl.py b/src/cpu/IntrControl.py new file mode 100644 index 000000000..eb4b1696b --- /dev/null +++ b/src/cpu/IntrControl.py @@ -0,0 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +class IntrControl(SimObject): + type = 'IntrControl' + sys = Param.System(Parent.any, "the system we are part of") diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 1c2278f6f..cce13a072 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -103,6 +103,9 @@ env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS'])) # and one of these are not being used. CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU'] +SimObject('BaseCPU.py') +SimObject('FuncUnit.py') + Source('activity.cc') Source('base.cc') Source('cpuevent.cc') @@ -116,6 +119,8 @@ Source('simple_thread.cc') Source('thread_state.cc') if env['FULL_SYSTEM']: + SimObject('IntrControl.py') + Source('intr_control.cc') Source('profile.cc') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 4dccee0d3..078ae1283 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -179,10 +179,9 @@ BaseCPU::BaseCPU(Params *p) if (p->functionTraceStart == 0) { functionTracingEnabled = true; } else { - Event *e = - new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, - true); - e->schedule(p->functionTraceStart); + new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this, + p->functionTraceStart, + true); } } #if FULL_SYSTEM diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 3e2b0f03e..9b87f2e8a 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -162,7 +162,7 @@ Trace::InstRecord::dump() static int fd = 0; //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { if(!cosim_listener) { @@ -245,7 +245,7 @@ Trace::InstRecord::dump() #if 0 //THE_ISA == SPARC_ISA //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { static uint64_t regs[32] = { 0, 0, 0, 0, 0, 0, 0, 0, @@ -432,7 +432,7 @@ Trace::InstRecord::dump() setupSharedData(); // We took a trap on a micro-op... - if (wasMicro && !staticInst->isMicroOp()) + if (wasMicro && !staticInst->isMicroop()) { // let's skip comparing this tick while (!compared) @@ -444,13 +444,13 @@ Trace::InstRecord::dump() wasMicro = false; } - if (staticInst->isLastMicroOp()) + if (staticInst->isLastMicroop()) wasMicro = false; - else if (staticInst->isMicroOp()) + else if (staticInst->isMicroop()) wasMicro = true; - if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { + if(!staticInst->isMicroop() || staticInst->isLastMicroop()) { while (!compared) { if (shared_data->flags == OWN_M5) { m5Pc = PC & TheISA::PAddrImplMask; @@ -650,12 +650,13 @@ Trace::InstRecord::dump() << endl; predecoder.setTC(thread); - predecoder.moreBytes(m5Pc, 0, shared_data->instruction); + predecoder.moreBytes(m5Pc, m5Pc, 0, + shared_data->instruction); assert(predecoder.extMachInstReady()); StaticInstPtr legionInst = - StaticInst::decode(predecoder.getExtMachInst()); + StaticInst::decode(predecoder.getExtMachInst(), lgnPc); outs << setfill(' ') << setw(15) << " Legion Inst: " << "0x" << setw(8) << setfill('0') << hex diff --git a/src/cpu/memtest/MemTest.py b/src/cpu/memtest/MemTest.py new file mode 100644 index 000000000..381519972 --- /dev/null +++ b/src/cpu/memtest/MemTest.py @@ -0,0 +1,52 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +from m5 import build_env + +class MemTest(SimObject): + type = 'MemTest' + max_loads = Param.Counter("number of loads to execute") + atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n") + memory_size = Param.Int(65536, "memory size") + percent_dest_unaligned = Param.Percent(50, + "percent of copy dest address that are unaligned") + percent_reads = Param.Percent(65, "target read percentage") + percent_source_unaligned = Param.Percent(50, + "percent of copy source address that are unaligned") + percent_functional = Param.Percent(50, "percent of access that are functional") + percent_uncacheable = Param.Percent(10, + "target uncacheable percentage") + progress_interval = Param.Counter(1000000, + "progress report interval (in accesses)") + trace_addr = Param.Addr(0, "address to trace") + + test = Port("Port to the memory system to test") + functional = Port("Port to the functional memory used for verification") diff --git a/src/cpu/memtest/SConscript b/src/cpu/memtest/SConscript index 7b4d6d2c5..1f6621a4c 100644 --- a/src/cpu/memtest/SConscript +++ b/src/cpu/memtest/SConscript @@ -31,4 +31,6 @@ Import('*') if 'O3CPU' in env['CPU_MODELS']: + SimObject('MemTest.py') + Source('memtest.cc') diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index 607cf1066..15774904a 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -190,14 +190,8 @@ MemTest::init() blockAddrMask = blockSize - 1; traceBlockAddr = blockAddr(traceBlockAddr); - // set up intial memory contents here - - cachePort.memsetBlob(baseAddr1, 1, size); - funcPort.memsetBlob(baseAddr1, 1, size); - cachePort.memsetBlob(baseAddr2, 2, size); - funcPort.memsetBlob(baseAddr2, 2, size); - cachePort.memsetBlob(uncacheAddr, 3, size); - funcPort.memsetBlob(uncacheAddr, 3, size); + // initial memory contents for both physical memory and functional + // memory should be 0; no need to initialize them. } static void @@ -267,7 +261,7 @@ MemTest::completeRequest(PacketPtr pkt) break; */ default: - panic("invalid command"); + panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt()); } if (blockAddr(req->getPaddr()) == traceBlockAddr) { diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh index 264309fd7..123ee2a6c 100644 --- a/src/cpu/memtest/memtest.hh +++ b/src/cpu/memtest/memtest.hh @@ -115,8 +115,8 @@ class MemTest : public MemObject virtual void recvRetry(); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } }; CpuPort cachePort; diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py new file mode 100644 index 000000000..4f07f9867 --- /dev/null +++ b/src/cpu/o3/FUPool.py @@ -0,0 +1,40 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.SimObject import SimObject +from m5.params import * +from FuncUnit import * +from FuncUnitConfig import * + +class FUPool(SimObject): + type = 'FUPool' + FUList = VectorParam.FUDesc("list of FU's for this pool") + +class DefaultFUPool(FUPool): + FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), + WritePort(), RdWrPort(), IprPort() ] diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py new file mode 100644 index 000000000..954381f86 --- /dev/null +++ b/src/cpu/o3/FuncUnitConfig.py @@ -0,0 +1,69 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +from m5.SimObject import SimObject +from m5.params import * +from FuncUnit import * + +class IntALU(FUDesc): + opList = [ OpDesc(opClass='IntAlu') ] + count = 6 + +class IntMultDiv(FUDesc): + opList = [ OpDesc(opClass='IntMult', opLat=3), + OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ] + count=2 + +class FP_ALU(FUDesc): + opList = [ OpDesc(opClass='FloatAdd', opLat=2), + OpDesc(opClass='FloatCmp', opLat=2), + OpDesc(opClass='FloatCvt', opLat=2) ] + count = 4 + +class FP_MultDiv(FUDesc): + opList = [ OpDesc(opClass='FloatMult', opLat=4), + OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), + OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] + count = 2 + +class ReadPort(FUDesc): + opList = [ OpDesc(opClass='MemRead') ] + count = 0 + +class WritePort(FUDesc): + opList = [ OpDesc(opClass='MemWrite') ] + count = 0 + +class RdWrPort(FUDesc): + opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] + count = 4 + +class IprPort(FUDesc): + opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ] + count = 1 + diff --git a/src/python/m5/objects/O3CPU.py b/src/cpu/o3/O3CPU.py index 5fba4e96f..e031faefa 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -1,10 +1,40 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + from m5.params import * from m5.proxy import * from m5 import build_env from BaseCPU import BaseCPU -from Checker import O3Checker from FUPool import * +if build_env['USE_CHECKER']: + from O3Checker import O3Checker + class DerivO3CPU(BaseCPU): type = 'DerivO3CPU' activity = Param.Unsigned(0, "Initial count") diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py new file mode 100644 index 000000000..43a71d67b --- /dev/null +++ b/src/cpu/o3/O3Checker.py @@ -0,0 +1,43 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class O3Checker(BaseCPU): + type = 'O3Checker' + exitOnError = Param.Bool(False, "Exit on an error") + updateOnError = Param.Bool(False, + "Update the checker with the main CPU's state on an error") + warnOnlyOnLoadError = Param.Bool(False, + "If a load result is incorrect, only print a warning and do not exit") + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index bb1dfb613..ad61ad228 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -33,6 +33,10 @@ import sys Import('*') if 'O3CPU' in env['CPU_MODELS']: + SimObject('FUPool.py') + SimObject('FuncUnitConfig.py') + SimObject('O3CPU.py') + Source('base_dyn_inst.cc') Source('bpred_unit.cc') Source('commit.cc') @@ -71,6 +75,7 @@ if 'O3CPU' in env['CPU_MODELS']: sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) if env['USE_CHECKER']: + SimObject('O3Checker.py') Source('checker_builder.cc') if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 7645a226c..d954bd1e7 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -100,8 +100,8 @@ class DefaultFetch /** Returns the address ranges of this device. */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } /** Timing version of receive. Handles setting fetch to the * proper status to start fetching. */ diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 3ae7bc402..0fd1e7bac 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -29,6 +29,9 @@ * Korey Sewell */ +#include <algorithm> +#include <cstring> + #include "config/use_checker.hh" #include "arch/isa_traits.hh" @@ -48,8 +51,6 @@ #include "sim/system.hh" #endif // FULL_SYSTEM -#include <algorithm> - template<class Impl> void DefaultFetch<Impl>::IcachePort::setPeer(Port *port) @@ -374,7 +375,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt) return; } - memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize); + memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize); cacheDataValid[tid] = true; if (!drainPending) { @@ -1116,7 +1117,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) (&cacheData[tid][offset])); predecoder.setTC(cpu->thread[tid]->getTC()); - predecoder.moreBytes(fetch_PC, 0, inst); + predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst); ext_inst = predecoder.getExtMachInst(); staticInst = StaticInstPtr(ext_inst); @@ -1153,10 +1154,14 @@ DefaultFetch<Impl>::fetch(bool &status_change) DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, instruction->staticInst->disassemble(fetch_PC)); +#if TRACING_ON instruction->traceData = Trace::getInstRecord(curTick, cpu->tcBase(tid), instruction->staticInst, instruction->readPC()); +#else + instruction->traceData = NULL; +#endif ///FIXME This needs to be more robust in dealing with delay slots predicted_branch |= diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index fd8f878a7..06de608e0 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -316,8 +316,8 @@ class LSQ { /** Returns the address ranges of this device. */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } /** Timing version of receive. Handles writing back and * completing the load or store that has returned from diff --git a/src/cpu/op_class.cc b/src/cpu/op_class.cc index f7ef49c0f..02cb4a08a 100644 --- a/src/cpu/op_class.cc +++ b/src/cpu/op_class.cc @@ -34,7 +34,7 @@ const char * opClassStrings[Num_OpClasses] = { - "(null)", + "No_OpClass", "IntAlu", "IntMult", "IntDiv", diff --git a/src/python/m5/objects/OzoneCPU.py b/src/cpu/ozone/OzoneCPU.py index 0913e044c..b9cfb448f 100644 --- a/src/python/m5/objects/OzoneCPU.py +++ b/src/cpu/ozone/OzoneCPU.py @@ -1,13 +1,45 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + from m5.params import * from m5 import build_env from BaseCPU import BaseCPU +if build_env['USE_CHECKER']: + from OzoneChecker import OzoneChecker + class DerivOzoneCPU(BaseCPU): type = 'DerivOzoneCPU' numThreads = Param.Unsigned("number of HW thread contexts") - checker = Param.BaseCPU("Checker CPU") + if build_env['USE_CHECKER']: + checker = Param.BaseCPU("Checker CPU") if build_env['FULL_SYSTEM']: profile = Param.Latency('0ns', "trace the kernel stack") diff --git a/src/cpu/ozone/OzoneChecker.py b/src/cpu/ozone/OzoneChecker.py new file mode 100644 index 000000000..f20b8770e --- /dev/null +++ b/src/cpu/ozone/OzoneChecker.py @@ -0,0 +1,43 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class OzoneChecker(BaseCPU): + type = 'OzoneChecker' + exitOnError = Param.Bool(False, "Exit on an error") + updateOnError = Param.Bool(False, + "Update the checker with the main CPU's state on an error") + warnOnlyOnLoadError = Param.Bool(False, + "If a load result is incorrect, only print a warning and do not exit") + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript index 4a040684a..cb2006456 100644 --- a/src/cpu/ozone/SConscript +++ b/src/cpu/ozone/SConscript @@ -31,6 +31,9 @@ Import('*') if 'OzoneCPU' in env['CPU_MODELS']: + SimObject('OzoneCPU.py') + SimObject('SimpleOzoneCPU.py') + need_bp_unit = True Source('base_dyn_inst.cc') Source('bpred_unit.cc') @@ -42,4 +45,5 @@ if 'OzoneCPU' in env['CPU_MODELS']: Source('lw_lsq.cc') Source('rename_table.cc') if env['USE_CHECKER']: + SimObject('OzoneChecker.py') Source('checker_builder.cc') diff --git a/src/python/m5/objects/SimpleOzoneCPU.py b/src/cpu/ozone/SimpleOzoneCPU.py index 193f31b0f..93603092b 100644 --- a/src/python/m5/objects/SimpleOzoneCPU.py +++ b/src/cpu/ozone/SimpleOzoneCPU.py @@ -1,3 +1,31 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + from m5.params import * from m5 import build_env from BaseCPU import BaseCPU diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index d78162243..d1214223b 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -53,7 +53,6 @@ #include "arch/vtophys.hh" #include "base/callback.hh" #include "cpu/profile.hh" -#include "mem/physical.hh" #include "sim/faults.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh index 0acf99ead..667392c06 100644 --- a/src/cpu/ozone/front_end.hh +++ b/src/cpu/ozone/front_end.hh @@ -91,8 +91,8 @@ class FrontEnd /** Returns the address ranges of this device. */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } /** Timing version of receive. Handles setting fetch to the * proper status to start fetching. */ diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index c981b8e63..2048ad6bb 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -257,8 +257,8 @@ class OzoneLWLSQ { virtual void recvStatusChange(Status status); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } virtual bool recvTiming(PacketPtr pkt); diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py new file mode 100644 index 000000000..e97f059c1 --- /dev/null +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -0,0 +1,43 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class AtomicSimpleCPU(BaseCPU): + type = 'AtomicSimpleCPU' + width = Param.Int(1, "CPU width") + simulate_stalls = Param.Bool(False, "Simulate cache stall cycles") + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + _mem_ports = ['icache_port', 'dcache_port'] diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript index 9a6a80473..ccccab2b5 100644 --- a/src/cpu/simple/SConscript +++ b/src/cpu/simple/SConscript @@ -33,10 +33,12 @@ Import('*') need_simple_base = False if 'AtomicSimpleCPU' in env['CPU_MODELS']: need_simple_base = True + SimObject('AtomicSimpleCPU.py') Source('atomic.cc') if 'TimingSimpleCPU' in env['CPU_MODELS']: need_simple_base = True + SimObject('TimingSimpleCPU.py') Source('timing.cc') if need_simple_base: diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py new file mode 100644 index 000000000..2fcde175c --- /dev/null +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -0,0 +1,41 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5 import build_env +from BaseCPU import BaseCPU + +class TimingSimpleCPU(BaseCPU): + type = 'TimingSimpleCPU' + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") + icache_port = Port("Instruction Port") + dcache_port = Port("Data Port") + _mem_ports = ['icache_port', 'dcache_port'] diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index b0a01c3a3..ea1c7d87f 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -540,8 +540,8 @@ AtomicSimpleCPU::tick() } // @todo remove me after debugging with legion done - if (curStaticInst && (!curStaticInst->isMicroOp() || - curStaticInst->isFirstMicroOp())) + if (curStaticInst && (!curStaticInst->isMicroop() || + curStaticInst->isFirstMicroop())) instCnt++; if (simulate_stalls) { @@ -557,7 +557,7 @@ AtomicSimpleCPU::tick() } } - if(predecoder.needMoreBytes() || fault != NoFault) + if(fault != NoFault || !stayAtPC) advancePC(fault); } diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index ad4aa4708..b127e3791 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -104,8 +104,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU virtual void recvRetry(); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = true; } }; CpuPort icachePort; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 4fed2059b..b7f60522f 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -70,7 +70,7 @@ using namespace std; using namespace TheISA; BaseSimpleCPU::BaseSimpleCPU(Params *p) - : BaseCPU(p), thread(NULL), predecoder(NULL) + : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL) { #if FULL_SYSTEM thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); @@ -91,6 +91,9 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p) lastDcacheStall = 0; threadContexts.push_back(tc); + + fetchOffset = 0; + stayAtPC = false; } BaseSimpleCPU::~BaseSimpleCPU() @@ -326,18 +329,19 @@ BaseSimpleCPU::checkForInterrupts() Fault BaseSimpleCPU::setupFetchRequest(Request *req) { + Addr threadPC = thread->readPC(); + // set up memory request for instruction fetch #if ISA_HAS_DELAY_SLOT - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(), + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC, thread->readNextPC(),thread->readNextNPC()); #else - DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(), + DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC, thread->readNextPC()); #endif - req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst), - (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0, - thread->readPC()); + Addr fetchPC = (threadPC & PCMask) + fetchOffset; + req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC); Fault fault = thread->translateInstReq(req); @@ -365,8 +369,10 @@ BaseSimpleCPU::preExecute() // decode the instruction inst = gtoh(inst); + //If we're not in the middle of a macro instruction if (!curMacroStaticInst) { + StaticInstPtr instPtr = NULL; //Predecode, ie bundle up an ExtMachInst @@ -374,36 +380,50 @@ BaseSimpleCPU::preExecute() predecoder.setTC(thread->getTC()); //If more fetch data is needed, pass it in. if(predecoder.needMoreBytes()) - predecoder.moreBytes(thread->readPC(), 0, inst); + predecoder.moreBytes(thread->readPC(), + (thread->readPC() & PCMask) + fetchOffset, 0, inst); else predecoder.process(); - //If an instruction is ready, decode it - if (predecoder.extMachInstReady()) - instPtr = StaticInst::decode(predecoder.getExtMachInst()); + + //If an instruction is ready, decode it. Otherwise, we'll have to + //fetch beyond the MachInst at the current pc. + if (predecoder.extMachInstReady()) { +#if THE_ISA == X86_ISA + thread->setNextPC(thread->readPC() + predecoder.getInstSize()); +#endif // X86_ISA + stayAtPC = false; + instPtr = StaticInst::decode(predecoder.getExtMachInst(), + thread->readPC()); + } else { + stayAtPC = true; + fetchOffset += sizeof(MachInst); + } //If we decoded an instruction and it's microcoded, start pulling //out micro ops - if (instPtr && instPtr->isMacroOp()) { + if (instPtr && instPtr->isMacroop()) { curMacroStaticInst = instPtr; curStaticInst = curMacroStaticInst-> - fetchMicroOp(thread->readMicroPC()); + fetchMicroop(thread->readMicroPC()); } else { curStaticInst = instPtr; } } else { //Read the next micro op from the macro op curStaticInst = curMacroStaticInst-> - fetchMicroOp(thread->readMicroPC()); + fetchMicroop(thread->readMicroPC()); } //If we decoded an instruction this "tick", record information about it. if(curStaticInst) { +#if TRACING_ON traceData = Trace::getInstRecord(curTick, tc, curStaticInst, thread->readPC()); DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n", curStaticInst->getName(), curStaticInst->machInst); +#endif // TRACING_ON #if FULL_SYSTEM thread->setInst(inst); @@ -418,7 +438,7 @@ BaseSimpleCPU::postExecute() if (thread->profile) { bool usermode = TheISA::inUserMode(tc); thread->profilePC = usermode ? 1 : thread->readPC(); - StaticInstPtr si(inst); + StaticInstPtr si(inst, thread->readPC()); ProfileNode *node = thread->profile->consume(tc, si); if (node) thread->profileNode = node; @@ -447,14 +467,16 @@ BaseSimpleCPU::postExecute() void BaseSimpleCPU::advancePC(Fault fault) { + //Since we're moving to a new pc, zero out the offset + fetchOffset = 0; if (fault != NoFault) { curMacroStaticInst = StaticInst::nullStaticInstPtr; fault->invoke(tc); thread->setMicroPC(0); thread->setNextMicroPC(1); - } else if (predecoder.needMoreBytes()) { + } else { //If we're at the last micro op for this instruction - if (curStaticInst && curStaticInst->isLastMicroOp()) { + if (curStaticInst && curStaticInst->isLastMicroop()) { //We should be working with a macro op assert(curMacroStaticInst); //Close out this macro op, and clean up the diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 787259c96..d221baca8 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -137,6 +137,12 @@ class BaseSimpleCPU : public BaseCPU StaticInstPtr curStaticInst; StaticInstPtr curMacroStaticInst; + //This is the offset from the current pc that fetch should be performed at + Addr fetchOffset; + //This flag says to stay at the current pc. This is useful for + //instructions which go beyond MachInst boundaries. + bool stayAtPC; + void checkForInterrupts(); Fault setupFetchRequest(Request *req); void preExecute(); @@ -160,6 +166,9 @@ class BaseSimpleCPU : public BaseCPU return numInst - startNumInst; } + // Mask to align PCs to MachInst sized boundaries + static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); + // number of simulated memory references Stats::Scalar<> numMemRefs; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index fa7bb4f86..7698a588d 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -168,9 +168,7 @@ TimingSimpleCPU::resume() delete fetchEvent; } - fetchEvent = - new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); - fetchEvent->schedule(nextCycle()); + fetchEvent = new FetchEvent(this, nextCycle()); } changeState(SimObject::Running); @@ -224,9 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay) _status = Running; // kick things off by initiating the fetch of the next instruction - fetchEvent = - new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); - fetchEvent->schedule(nextCycle(curTick + cycles(delay))); + fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay))); } @@ -564,8 +560,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) { if (pkt->isResponse()) { // delay processing of returned data until next CPU clock edge - Tick mem_time = pkt->req->getTime(); - Tick next_tick = cpu->nextCycle(mem_time); + Tick next_tick = cpu->nextCycle(curTick); if (next_tick == curTick) cpu->completeIfetch(pkt); @@ -659,8 +654,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) { if (pkt->isResponse()) { // delay processing of returned data until next CPU clock edge - Tick mem_time = pkt->req->getTime(); - Tick next_tick = cpu->nextCycle(mem_time); + Tick next_tick = cpu->nextCycle(curTick); if (next_tick == curTick) cpu->completeDataAccess(pkt); diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index ef062d24a..39958bfb6 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -66,8 +66,6 @@ class TimingSimpleCPU : public BaseSimpleCPU Event *drainEvent; - Event *fetchEvent; - private: class CpuPort : public Port @@ -93,8 +91,8 @@ class TimingSimpleCPU : public BaseSimpleCPU virtual void recvStatusChange(Status status); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); } + bool &snoop) + { resp.clear(); snoop = false; } struct TickEvent : public Event { @@ -199,7 +197,12 @@ class TimingSimpleCPU : public BaseSimpleCPU void completeIfetch(PacketPtr ); void completeDataAccess(PacketPtr ); void advanceInst(Fault fault); + private: + + typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; + FetchEvent *fetchEvent; + void completeDrain(); }; diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 824914ad0..95848ee2c 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -38,7 +38,6 @@ #include "config/full_system.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" -#include "mem/physical.hh" #include "mem/request.hh" #include "sim/byteswap.hh" #include "sim/eventq.hh" diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc index 64fcc0580..52a7ede03 100644 --- a/src/cpu/static_inst.cc +++ b/src/cpu/static_inst.cc @@ -37,6 +37,8 @@ StaticInstPtr StaticInst::nullStaticInstPtr; // Define the decode cache hash map. StaticInst::DecodeCache StaticInst::decodeCache; +StaticInst::AddrDecodeCache StaticInst::addrDecodeCache; +StaticInst::cacheElement StaticInst::recentDecodes[2]; void StaticInst::dumpDecodeCacheStats() @@ -76,9 +78,9 @@ StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const } StaticInstPtr -StaticInst::fetchMicroOp(MicroPC micropc) +StaticInst::fetchMicroop(MicroPC micropc) { - panic("StaticInst::fetchMicroOp() called on instruction " + panic("StaticInst::fetchMicroop() called on instruction " "that is not microcoded."); } diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index a58ac85d6..b0a19c151 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -63,6 +63,7 @@ class AtomicSimpleCPU; class TimingSimpleCPU; class InorderCPU; class SymbolTable; +class AddrDecodePage; namespace Trace { class InstRecord; @@ -143,11 +144,11 @@ class StaticInstBase : public RefCounted IsUnverifiable, ///< Can't be verified by a checker //Flags for microcode - IsMacroOp, ///< Is a macroop containing microops - IsMicroOp, ///< Is a microop + IsMacroop, ///< Is a macroop containing microops + IsMicroop, ///< Is a microop IsDelayedCommit, ///< This microop doesn't commit right away - IsLastMicroOp, ///< This microop ends a microop sequence - IsFirstMicroOp, ///< This microop begins a microop sequence + IsLastMicroop, ///< This microop ends a microop sequence + IsFirstMicroop, ///< This microop begins a microop sequence //This flag doesn't do anything yet IsMicroBranch, ///< This microop branches within the microcode for a macroop @@ -242,11 +243,11 @@ class StaticInstBase : public RefCounted bool isQuiesce() const { return flags[IsQuiesce]; } bool isIprAccess() const { return flags[IsIprAccess]; } bool isUnverifiable() const { return flags[IsUnverifiable]; } - bool isMacroOp() const { return flags[IsMacroOp]; } - bool isMicroOp() const { return flags[IsMicroOp]; } + bool isMacroop() const { return flags[IsMacroop]; } + bool isMicroop() const { return flags[IsMicroop]; } bool isDelayedCommit() const { return flags[IsDelayedCommit]; } - bool isLastMicroOp() const { return flags[IsLastMicroOp]; } - bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; } + bool isLastMicroop() const { return flags[IsLastMicroop]; } + bool isFirstMicroop() const { return flags[IsFirstMicroop]; } //This flag doesn't do anything yet bool isMicroBranch() const { return flags[IsMicroBranch]; } //@} @@ -349,6 +350,7 @@ class StaticInst : public StaticInstBase : StaticInstBase(__opClass), machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) { + memset(&recentDecodes, 0, 2 * sizeof(cacheElement)); } public: @@ -369,7 +371,7 @@ class StaticInst : public StaticInstBase * Return the microop that goes with a particular micropc. This should * only be defined/used in macroops which will contain microops */ - virtual StaticInstPtr fetchMicroOp(MicroPC micropc); + virtual StaticInstPtr fetchMicroop(MicroPC micropc); /** * Return the target address for a PC-relative branch. @@ -437,11 +439,52 @@ class StaticInst : public StaticInstBase /// Decode a machine instruction. /// @param mach_inst The binary instruction to decode. /// @retval A pointer to the corresponding StaticInst object. - //This is defined as inline below. - static StaticInstPtr decode(ExtMachInst mach_inst); + //This is defined as inlined below. + static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); /// Return name of machine instruction std::string getName() { return mnemonic; } + + /// Decoded instruction cache type, for address decoding. + /// A generic hash_map is used. + typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; + + /// A cache of decoded instruction objects from addresses. + static AddrDecodeCache addrDecodeCache; + + struct cacheElement { + Addr page_addr; + AddrDecodePage *decodePage; + } ; + + /// An array of recently decoded instructions. + // might not use an array if there is only two elements + static struct cacheElement recentDecodes[2]; + + /// Updates the recently decoded instructions entries + /// @param page_addr The page address recently used. + /// @param decodePage Pointer to decoding page containing the decoded + /// instruction. + static inline void + updateCache(Addr page_addr, AddrDecodePage *decodePage) + { + recentDecodes[1].page_addr = recentDecodes[0].page_addr; + recentDecodes[1].decodePage = recentDecodes[0].decodePage; + recentDecodes[0].page_addr = page_addr; + recentDecodes[0].decodePage = decodePage; + } + + /// Searches the decoded instruction cache for instruction decoding. + /// If it is not found, then we decode the instruction. + /// Otherwise, we get the instruction from the cache and move it into + /// the address-to-instruction decoding page. + /// @param mach_inst The binary instruction to decode. + /// @param addr The address that contained the binary instruction. + /// @param decodePage Pointer to decoding page containing the instruction. + /// @retval A pointer to the corresponding StaticInst object. + //This is defined as inlined below. + static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, + AddrDecodePage * decodePage); }; typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; @@ -472,8 +515,8 @@ class StaticInstPtr : public RefCountingPtr<StaticInst> /// Construct directly from machine instruction. /// Calls StaticInst::decode(). - explicit StaticInstPtr(TheISA::ExtMachInst mach_inst) - : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst)) + explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) + : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) { } @@ -484,8 +527,55 @@ class StaticInstPtr : public RefCountingPtr<StaticInst> } }; +/// A page of a list of decoded instructions from an address. +class AddrDecodePage +{ + typedef TheISA::ExtMachInst ExtMachInst; + protected: + StaticInstPtr instructions[TheISA::PageBytes]; + bool valid[TheISA::PageBytes]; + Addr lowerMask; + + public: + /// Constructor + AddrDecodePage() { + lowerMask = TheISA::PageBytes - 1; + memset(valid, 0, TheISA::PageBytes); + } + + /// Checks if the instruction is already decoded and the machine + /// instruction in the cache matches the current machine instruction + /// related to the address + /// @param mach_inst The binary instruction to check + /// @param addr The address containing the instruction + inline bool decoded(ExtMachInst mach_inst, Addr addr) + { + return (valid[addr & lowerMask] && + (instructions[addr & lowerMask]->machInst == mach_inst)); + } + + /// Returns the instruction object. decoded should be called first + /// to check if the instruction is valid. + /// @param addr The address of the instruction. + /// @retval A pointer to the corresponding StaticInst object. + inline StaticInstPtr getInst(Addr addr) + { return instructions[addr & lowerMask]; } + + /// Inserts a pointer to a StaticInst object into the list of decoded + /// instructions on the page. + /// @param addr The address of the instruction. + /// @param si A pointer to the corresponding StaticInst object. + inline void insert(Addr addr, StaticInstPtr &si) + { + instructions[addr & lowerMask] = si; + valid[addr & lowerMask] = true; + } + +}; + + inline StaticInstPtr -StaticInst::decode(StaticInst::ExtMachInst mach_inst) +StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) { #ifdef DECODE_CACHE_HASH_STATS // Simple stats on decode hash_map. Turns out the default @@ -499,12 +589,54 @@ StaticInst::decode(StaticInst::ExtMachInst mach_inst) } #endif + Addr page_addr = addr & ~(TheISA::PageBytes - 1); + + // checks recently decoded addresses + if (recentDecodes[0].decodePage && + page_addr == recentDecodes[0].page_addr) { + if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) + return recentDecodes[0].decodePage->getInst(addr); + + return searchCache(mach_inst, addr, recentDecodes[0].decodePage); + } + + if (recentDecodes[1].decodePage && + page_addr == recentDecodes[1].page_addr) { + if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) + return recentDecodes[1].decodePage->getInst(addr); + + return searchCache(mach_inst, addr, recentDecodes[1].decodePage); + } + + // searches the page containing the address to decode + AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); + if (iter != addrDecodeCache.end()) { + updateCache(page_addr, iter->second); + if (iter->second->decoded(mach_inst, addr)) + return iter->second->getInst(addr); + + return searchCache(mach_inst, addr, iter->second); + } + + // creates a new object for a page of decoded instructions + AddrDecodePage * decodePage = new AddrDecodePage; + addrDecodeCache[page_addr] = decodePage; + updateCache(page_addr, decodePage); + return searchCache(mach_inst, addr, decodePage); +} + +inline StaticInstPtr +StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, + AddrDecodePage * decodePage) +{ DecodeCache::iterator iter = decodeCache.find(mach_inst); if (iter != decodeCache.end()) { + decodePage->insert(addr, iter->second); return iter->second; } StaticInstPtr si = TheISA::decodeInst(mach_inst); + decodePage->insert(addr, si); decodeCache[mach_inst] = si; return si; } diff --git a/src/dev/BadDevice.py b/src/dev/BadDevice.py new file mode 100644 index 000000000..4fc592184 --- /dev/null +++ b/src/dev/BadDevice.py @@ -0,0 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from Device import BasicPioDevice + +class BadDevice(BasicPioDevice): + type = 'BadDevice' + devicename = Param.String("Name of device to error on") diff --git a/src/python/m5/objects/Device.py b/src/dev/Device.py index 90fbfb552..adf262f26 100644 --- a/src/python/m5/objects/Device.py +++ b/src/dev/Device.py @@ -1,3 +1,31 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.params import * from m5.proxy import * from MemObject import MemObject diff --git a/src/dev/DiskImage.py b/src/dev/DiskImage.py new file mode 100644 index 000000000..af2407458 --- /dev/null +++ b/src/dev/DiskImage.py @@ -0,0 +1,44 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +class DiskImage(SimObject): + type = 'DiskImage' + abstract = True + image_file = Param.String("disk image file") + read_only = Param.Bool(False, "read only image") + +class RawDiskImage(DiskImage): + type = 'RawDiskImage' + +class CowDiskImage(DiskImage): + type = 'CowDiskImage' + child = Param.DiskImage(RawDiskImage(read_only=True), + "child image") + table_size = Param.Int(65536, "initial table size") diff --git a/src/python/m5/objects/Ethernet.py b/src/dev/Ethernet.py index bfe30950c..e81862a96 100644 --- a/src/python/m5/objects/Ethernet.py +++ b/src/dev/Ethernet.py @@ -1,8 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.SimObject import SimObject from m5.params import * from m5.proxy import * -from m5 import build_env -from Device import DmaDevice from Pci import PciDevice, PciConfigData class EtherInt(SimObject): @@ -36,46 +62,19 @@ class EtherDump(SimObject): file = Param.String("dump file") maxlen = Param.Int(96, "max portion of packet data to dump") -if build_env['ALPHA_TLASER']: - - class EtherDev(DmaDevice): - type = 'EtherDev' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - - intr_delay = Param.Latency('0us', "Interrupt Delay") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") - tlaser = Param.Turbolaser(Parent.any, "Turbolaser") - - class EtherDevInt(EtherInt): - type = 'EtherDevInt' - device = Param.EtherDev("Ethernet device of this interface") - - class IGbE(PciDevice): type = 'IGbE' hardware_address = Param.String("Ethernet Hardware Address") - use_flow_control = Param.Bool(False, "Should we use xon/xoff flow contorl (UNIMPLMENTD)") + use_flow_control = Param.Bool(False, + "Should we use xon/xoff flow contorl (UNIMPLEMENTD)") rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") - rx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") - tx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") + rx_desc_cache_size = Param.Int(64, + "Number of enteries in the rx descriptor cache") + tx_desc_cache_size = Param.Int(64, + "Number of enteries in the rx descriptor cache") clock = Param.Clock('500MHz', "Clock speed of the device") - class IGbEPciData(PciConfigData): VendorID = 0x8086 DeviceID = 0x1075 diff --git a/src/dev/Ide.py b/src/dev/Ide.py new file mode 100644 index 000000000..6bbaad00e --- /dev/null +++ b/src/dev/Ide.py @@ -0,0 +1,68 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from Pci import PciDevice, PciConfigData + +class IdeID(Enum): vals = ['master', 'slave'] + +class IdeControllerPciData(PciConfigData): + VendorID = 0x8086 + DeviceID = 0x7111 + Command = 0x0 + Status = 0x280 + Revision = 0x0 + ClassCode = 0x01 + SubClassCode = 0x01 + ProgIF = 0x85 + BAR0 = 0x00000001 + BAR1 = 0x00000001 + BAR2 = 0x00000001 + BAR3 = 0x00000001 + BAR4 = 0x00000001 + BAR5 = 0x00000001 + InterruptLine = 0x1f + InterruptPin = 0x01 + BAR0Size = '8B' + BAR1Size = '4B' + BAR2Size = '8B' + BAR3Size = '4B' + BAR4Size = '16B' + +class IdeDisk(SimObject): + type = 'IdeDisk' + delay = Param.Latency('1us', "Fixed disk delay in microseconds") + driveID = Param.IdeID('master', "Drive ID") + image = Param.DiskImage("Disk image") + +class IdeController(PciDevice): + type = 'IdeController' + disks = VectorParam.IdeDisk("IDE disks attached to this controller") + + configdata =IdeControllerPciData() diff --git a/src/python/m5/objects/Pci.py b/src/dev/Pci.py index 9d40adbfe..b2c013f41 100644 --- a/src/python/m5/objects/Pci.py +++ b/src/dev/Pci.py @@ -1,3 +1,31 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.SimObject import SimObject from m5.params import * from m5.proxy import * diff --git a/src/dev/Platform.py b/src/dev/Platform.py new file mode 100644 index 000000000..cb414121b --- /dev/null +++ b/src/dev/Platform.py @@ -0,0 +1,35 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +class Platform(SimObject): + type = 'Platform' + abstract = True + intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/src/dev/SConscript b/src/dev/SConscript index ea529b536..2e0d75650 100644 --- a/src/dev/SConscript +++ b/src/dev/SConscript @@ -32,6 +32,17 @@ Import('*') if env['FULL_SYSTEM']: + SimObject('BadDevice.py') + SimObject('Device.py') + SimObject('DiskImage.py') + SimObject('Ethernet.py') + SimObject('Ide.py') + SimObject('Pci.py') + SimObject('Platform.py') + SimObject('SimConsole.py') + SimObject('SimpleDisk.py') + SimObject('Uart.py') + Source('baddev.cc') Source('disk_image.cc') Source('etherbus.cc') diff --git a/src/dev/SimConsole.py b/src/dev/SimConsole.py new file mode 100644 index 000000000..bb8420527 --- /dev/null +++ b/src/dev/SimConsole.py @@ -0,0 +1,39 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * + +class SimConsole(SimObject): + type = 'SimConsole' + append_name = Param.Bool(True, "append name() to filename") + intr_control = Param.IntrControl(Parent.any, "interrupt controller") + port = Param.TcpPort(3456, "listen port") + number = Param.Int(0, "console number") + output = Param.String('console', "file to dump output to") diff --git a/src/dev/SimpleDisk.py b/src/dev/SimpleDisk.py new file mode 100644 index 000000000..1c9193035 --- /dev/null +++ b/src/dev/SimpleDisk.py @@ -0,0 +1,35 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +class SimpleDisk(SimObject): + type = 'SimpleDisk' + disk = Param.DiskImage("Disk Image") + system = Param.System(Parent.any, "Sysetm Pointer") diff --git a/src/dev/Uart.py b/src/dev/Uart.py new file mode 100644 index 000000000..e32517a4c --- /dev/null +++ b/src/dev/Uart.py @@ -0,0 +1,45 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from m5 import build_env +from Device import BasicPioDevice + +class Uart(BasicPioDevice): + type = 'Uart' + abstract = True + sim_console = Param.SimConsole(Parent.any, "The console") + +class Uart8250(Uart): + type = 'Uart8250' + +if build_env['ALPHA_TLASER']: + class Uart8530(Uart): + type = 'Uart8530' + diff --git a/src/dev/alpha/AlphaConsole.py b/src/dev/alpha/AlphaConsole.py new file mode 100644 index 000000000..43c7ef954 --- /dev/null +++ b/src/dev/alpha/AlphaConsole.py @@ -0,0 +1,38 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from Device import BasicPioDevice + +class AlphaConsole(BasicPioDevice): + type = 'AlphaConsole' + cpu = Param.BaseCPU(Parent.cpu[0], "Processor") + disk = Param.SimpleDisk("Simple Disk") + sim_console = Param.SimConsole(Parent.any, "The Simulator Console") + system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript index c985fdd9f..8d7f5493b 100644 --- a/src/dev/alpha/SConscript +++ b/src/dev/alpha/SConscript @@ -32,6 +32,9 @@ Import('*') if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha': + SimObject('AlphaConsole.py') + SimObject('Tsunami.py') + Source('console.cc') Source('tsunami.cc') Source('tsunami_cchip.cc') diff --git a/src/python/m5/objects/Tsunami.py b/src/dev/alpha/Tsunami.py index 85105ff20..484976c09 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/dev/alpha/Tsunami.py @@ -1,3 +1,31 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.params import * from m5.proxy import * from Device import BasicPioDevice, IsaFake, BadAddr diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index e0272c655..baf13c49a 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -656,7 +656,7 @@ IGbE::RxDescCache::writePacket(EthPacketPtr packet) return false; pktPtr = packet; - + pktDone = false; igbe->dmaWrite(igbe->platform->pciToDma(unusedCache.front()->buf), packet->length, &pktEvent, packet->data); return true; @@ -683,8 +683,12 @@ IGbE::RxDescCache::pktComplete() uint8_t status = RXDS_DD | RXDS_EOP; uint8_t err = 0; + IpPtr ip(pktPtr); + if (ip) { + DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", ip->id()); + if (igbe->regs.rxcsum.ipofld()) { DPRINTF(EthernetDesc, "Checking IP checksum\n"); status |= RXDS_IPCS; @@ -715,7 +719,10 @@ IGbE::RxDescCache::pktComplete() err |= RXDE_TCPE; } } - } // if ip + } else { // if ip + DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); + } + desc->status = htole(status); desc->errors = htole(err); @@ -912,10 +919,20 @@ IGbE::TxDescCache::pktComplete() DPRINTF(EthernetDesc, "TxDescriptor data d1: %#llx d2: %#llx\n", desc->d1, desc->d2); + if (DTRACE(EthernetDesc)) { + IpPtr ip(pktPtr); + if (ip) + DPRINTF(EthernetDesc, "Proccesing Ip packet with Id=%d\n", + ip->id()); + else + DPRINTF(EthernetSM, "Proccesing Non-Ip packet\n"); + } + // Checksums are only ofloaded for new descriptor types if (TxdOp::isData(desc) && ( TxdOp::ixsm(desc) || TxdOp::txsm(desc)) ) { DPRINTF(EthernetDesc, "Calculating checksums for packet\n"); IpPtr ip(pktPtr); + if (TxdOp::ixsm(desc)) { ip->sum(0); ip->sum(cksum(ip)); @@ -1192,6 +1209,7 @@ IGbE::rxStateMachine() // If the packet is done check for interrupts/descriptors/etc if (rxDescCache.packetDone()) { + rxDmaPacket = false; DPRINTF(EthernetSM, "RXS: Packet completed DMA to memory\n"); int descLeft = rxDescCache.descLeft(); switch (regs.rctl.rdmts()) { @@ -1236,6 +1254,12 @@ IGbE::rxStateMachine() return; } + if (rxDmaPacket) { + DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); + rxTick = false; + return; + } + if (!rxDescCache.descUnused()) { DPRINTF(EthernetSM, "RXS: No descriptors available in cache, stopping ticking\n"); rxTick = false; @@ -1262,6 +1286,7 @@ IGbE::rxStateMachine() rxFifo.pop(); DPRINTF(EthernetSM, "RXS: stopping ticking until packet DMA completes\n"); rxTick = false; + rxDmaPacket = true; } void diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index 2dec3b08c..b6da53b09 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -80,6 +80,8 @@ class IGbE : public PciDev bool txTick; bool txFifoTick; + bool rxDmaPacket; + // Event and function to deal with RDTR timer expiring void rdtrProcess() { rxDescCache.writeback(0); diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index d430ace72..ecbb391ef 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -48,9 +48,9 @@ PioPort::recvAtomic(PacketPtr pkt) } void -PioPort::getDeviceAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) +PioPort::getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) { - snoop.clear(); + snoop = false; device->addressRanges(resp); } @@ -218,6 +218,9 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, DmaReqState *reqState = new DmaReqState(event, this, size); + + DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size, + event->scheduled()); for (ChunkGenerator gen(addr, size, peerBlockSize()); !gen.done(); gen.next()) { Request *req = new Request(gen.addr(), gen.size(), 0); @@ -231,6 +234,8 @@ DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, assert(pendingCount >= 0); pendingCount++; + DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(), + gen.size()); queueDma(pkt); } @@ -281,19 +286,28 @@ DmaPort::sendDma() if (transmitList.size() && backoffTime && !inRetry && !backoffEvent.scheduled()) { + DPRINTF(DMA, "-- Scheduling backoff timer for %d\n", + backoffTime+curTick); backoffEvent.schedule(backoffTime+curTick); } } else if (state == System::Atomic) { transmitList.pop_front(); Tick lat; + DPRINTF(DMA, "--Sending DMA for addr: %#x size: %d\n", + pkt->req->getPaddr(), pkt->req->getSize()); lat = sendAtomic(pkt); assert(pkt->senderState); DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState); assert(state); - state->numBytes += pkt->req->getSize(); + + DPRINTF(DMA, "--Received response for DMA for addr: %#x size: %d nb: %d, tot: %d sched %d\n", + pkt->req->getPaddr(), pkt->req->getSize(), state->numBytes, + state->totBytes, state->completionEvent->scheduled()); + if (state->totBytes == state->numBytes) { + assert(!state->completionEvent->scheduled()); state->completionEvent->schedule(curTick + lat); delete state; delete pkt->req; diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index bd150bfe4..25bd2de8d 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -59,7 +59,7 @@ class PioPort : public SimpleTimingPort virtual Tick recvAtomic(PacketPtr pkt); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); public: @@ -127,8 +127,8 @@ class DmaPort : public Port virtual void recvRetry() ; virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) - { resp.clear(); snoop.clear(); } + bool &snoop) + { resp.clear(); snoop = false; } void queueDma(PacketPtr pkt, bool front = false); void sendDma(); diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index d9985f808..e9d9c419d 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -1270,8 +1270,7 @@ NSGigE::cpuIntrPost(Tick when) if (intrEvent) intrEvent->squash(); - intrEvent = new IntrEvent(this, true); - intrEvent->schedule(intrTick); + intrEvent = new IntrEvent(this, intrTick, true); } void @@ -2770,8 +2769,7 @@ NSGigE::unserialize(Checkpoint *cp, const std::string §ion) Tick intrEventTick; UNSERIALIZE_SCALAR(intrEventTick); if (intrEventTick) { - intrEvent = new IntrEvent(this, true); - intrEvent->schedule(intrEventTick); + intrEvent = new IntrEvent(this, intrEventTick, true); } } diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc index f906e69cf..c2a2bc02d 100644 --- a/src/dev/pcidev.cc +++ b/src/dev/pcidev.cc @@ -76,9 +76,9 @@ PciDev::PciConfigPort::recvAtomic(PacketPtr pkt) void PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { - snoop.clear(); + snoop = false;; resp.push_back(RangeSize(configAddr, PCI_CONFIG_SIZE+1)); } diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh index 5044e2932..5ddbe84a0 100644 --- a/src/dev/pcidev.hh +++ b/src/dev/pcidev.hh @@ -89,7 +89,7 @@ class PciDev : public DmaDevice virtual Tick recvAtomic(PacketPtr pkt); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); Platform *platform; diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 420761620..e13fdb0bc 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -630,8 +630,7 @@ Base::cpuIntrPost(Tick when) if (intrEvent) intrEvent->squash(); - intrEvent = new IntrEvent(this, true); - intrEvent->schedule(intrTick); + intrEvent = new IntrEvent(this, intrTick, true); } void @@ -1339,8 +1338,7 @@ Base::unserialize(Checkpoint *cp, const std::string §ion) Tick intrEventTick; UNSERIALIZE_SCALAR(intrEventTick); if (intrEventTick) { - intrEvent = new IntrEvent(this, true); - intrEvent->schedule(intrEventTick); + intrEvent = new IntrEvent(this, intrEventTick, true); } } diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript index 8511b16fb..2ebf9fe05 100644 --- a/src/dev/sparc/SConscript +++ b/src/dev/sparc/SConscript @@ -32,6 +32,8 @@ Import('*') if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc': + SimObject('T1000.py') + Source('dtod.cc') Source('iob.cc') Source('t1000.cc') diff --git a/src/python/m5/objects/T1000.py b/src/dev/sparc/T1000.py index 0acfa0920..a033e27e2 100644 --- a/src/python/m5/objects/T1000.py +++ b/src/dev/sparc/T1000.py @@ -1,3 +1,31 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + from m5.params import * from m5.proxy import * from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr diff --git a/src/kern/tru64/tru64_events.cc b/src/kern/tru64/tru64_events.cc index 0ad89f8bd..4db5df067 100644 --- a/src/kern/tru64/tru64_events.cc +++ b/src/kern/tru64/tru64_events.cc @@ -54,7 +54,7 @@ BadAddrEvent::process(ThreadContext *tc) uint64_t a0 = tc->readIntReg(ArgumentReg0); AddrRangeList resp; - AddrRangeList snoop; + bool snoop; AddrRangeIter iter; bool found = false; diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py new file mode 100644 index 000000000..8377221cd --- /dev/null +++ b/src/mem/Bridge.py @@ -0,0 +1,44 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ali Saidi + +from m5.params import * +from MemObject import MemObject + +class Bridge(MemObject): + type = 'Bridge' + side_a = Port('Side A port') + side_b = Port('Side B port') + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") + delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") + write_ack = Param.Bool(False, "Should this bridge ack writes") + fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") + fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/mem/Bus.py b/src/mem/Bus.py new file mode 100644 index 000000000..247a1fe31 --- /dev/null +++ b/src/mem/Bus.py @@ -0,0 +1,49 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5 import build_env +from m5.params import * +from m5.proxy import * +from MemObject import MemObject + +if build_env['FULL_SYSTEM']: + from Device import BadAddr + +class Bus(MemObject): + type = 'Bus' + port = VectorPort("vector port for connecting devices") + bus_id = Param.Int(0, "blah") + clock = Param.Clock("1GHz", "bus clock speed") + width = Param.Int(64, "bus width (bytes)") + responder_set = Param.Bool(False, "Did the user specify a default responder.") + block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") + if build_env['FULL_SYSTEM']: + responder = BadAddr(pio_addr=0x0, pio_latency="1ps") + default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") + else: + default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py new file mode 100644 index 000000000..269cf4403 --- /dev/null +++ b/src/mem/MemObject.py @@ -0,0 +1,34 @@ +# Copyright (c) 2006-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +from m5.SimObject import SimObject +from m5.SimObject import SimObject + +class MemObject(SimObject): + type = 'MemObject' + abstract = True diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py new file mode 100644 index 000000000..2ef3df7c1 --- /dev/null +++ b/src/mem/PhysicalMemory.py @@ -0,0 +1,57 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.params import * +from m5.proxy import * +from MemObject import * + +class PhysicalMemory(MemObject): + type = 'PhysicalMemory' + port = VectorPort("the access port") + range = Param.AddrRange(AddrRange('128MB'), "Device Address") + file = Param.String('', "memory mapped file") + latency = Param.Latency('1t', "latency of an access") + zero = Param.Bool(False, "zero initialize memory") + +class DRAMMemory(PhysicalMemory): + type = 'DRAMMemory' + # Many of these should be observed from the configuration + cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") + mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") + mem_actpolicy = Param.String("open", "Open/Close policy") + memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") + bus_width = Param.Int(16, "") + act_lat = Param.Int(2, "RAS to CAS delay") + cas_lat = Param.Int(1, "CAS delay") + war_lat = Param.Int(2, "write after read delay") + pre_lat = Param.Int(2, "precharge delay") + dpl_lat = Param.Int(2, "data in to precharge delay") + trc_lat = Param.Int(6, "row cycle delay") + num_banks = Param.Int(4, "Number of Banks") + num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") + diff --git a/src/mem/SConscript b/src/mem/SConscript index 61fb766d6..bbb1e96fe 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -30,6 +30,11 @@ Import('*') +SimObject('Bridge.py') +SimObject('Bus.py') +SimObject('PhysicalMemory.py') +SimObject('MemObject.py') + Source('bridge.cc') Source('bus.cc') Source('dram.cc') diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index e89473be3..04b0308e1 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -119,7 +119,14 @@ Bridge::BridgePort::recvTiming(PacketPtr pkt) DPRINTF(BusBridge, "recvTiming: src %d dest %d addr 0x%x\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr()); - if (pkt->isRequest() && otherPort->reqQueueFull()) { + DPRINTF(BusBridge, "Local queue size: %d outreq: %d outresp: %d\n", + sendQueue.size(), queuedRequests, outstandingResponses); + DPRINTF(BusBridge, "Remove queue size: %d outreq: %d outresp: %d\n", + otherPort->sendQueue.size(), otherPort->queuedRequests, + otherPort->outstandingResponses); + + if (pkt->isRequest() && otherPort->reqQueueFull() && pkt->result != + Packet::Nacked) { DPRINTF(BusBridge, "Remote queue full, nacking\n"); nackRequest(pkt); return true; @@ -191,7 +198,7 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt) void Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) { - if (pkt->isResponse() || pkt->result == Packet::Nacked) { + if (pkt->isResponse() || pkt->result == Packet::Nacked) { // This is a response for a request we forwarded earlier. The // corresponding PacketBuffer should be stored in the packet's // senderState field. @@ -201,9 +208,9 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) // from original request buf->fixResponse(pkt); - // Check if this packet was expecting a response (this is either it or - // its a nacked packet and we won't be seeing that response) - if (buf->expectResponse) + // Check if this packet was expecting a response and it's a nacked + // packet, in which case we will never being seeing it + if (buf->expectResponse && pkt->result == Packet::Nacked) --outstandingResponses; @@ -213,6 +220,13 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) delete buf; } + + if (pkt->isRequest() && pkt->result != Packet::Nacked) { + ++queuedRequests; + } + + + Tick readyTime = curTick + delay; PacketBuffer *buf = new PacketBuffer(pkt, readyTime); DPRINTF(BusBridge, "old sender state: %#X, new sender state: %#X\n", @@ -225,7 +239,6 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt) if (sendQueue.empty()) { sendEvent.schedule(readyTime); } - ++queuedRequests; sendQueue.push_back(buf); } @@ -234,8 +247,6 @@ Bridge::BridgePort::trySend() { assert(!sendQueue.empty()); - int pbs = peerBlockSize(); - PacketBuffer *buf = sendQueue.front(); assert(buf->ready <= curTick); @@ -244,16 +255,22 @@ Bridge::BridgePort::trySend() pkt->flags &= ~SNOOP_COMMIT; //CLear it if it was set + // Ugly! @todo When multilevel coherence works this will be removed if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite && - pkt->result != Packet::Nacked && pkt->getOffset(pbs) && - pkt->getSize() != pbs) { - buf->partialWriteFix(this); - pkt = buf->pkt; + pkt->result != Packet::Nacked) { + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq, + Packet::Broadcast); + funcPkt->dataStatic(pkt->getPtr<uint8_t>()); + sendFunctional(funcPkt); + pkt->cmd = MemCmd::WriteReq; + delete funcPkt; } DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n", buf->origSrc, pkt->getDest(), pkt->getAddr()); + bool wasReq = pkt->isRequest(); + bool wasNacked = pkt->result == Packet::Nacked; if (sendTiming(pkt)) { // send successful @@ -270,8 +287,12 @@ Bridge::BridgePort::trySend() delete buf; } - if (!buf->nacked) + if (!wasNacked) { + if (wasReq) --queuedRequests; + else + --outstandingResponses; + } // If there are more packets to send, schedule event to try again. if (!sendQueue.empty()) { @@ -281,7 +302,6 @@ Bridge::BridgePort::trySend() } } else { DPRINTF(BusBridge, " unsuccessful\n"); - buf->undoPartialWriteFix(); inRetry = true; } DPRINTF(BusBridge, "trySend: queue size: %d outreq: %d outstanding resp: %d\n", @@ -305,7 +325,18 @@ Bridge::BridgePort::recvRetry() Tick Bridge::BridgePort::recvAtomic(PacketPtr pkt) { - return otherPort->sendAtomic(pkt) + delay; + // fix partial atomic writes... similar to the timing code that does the + // same... will be removed once our code gets this right + if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite) { + + PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq, + Packet::Broadcast); + funcPkt->dataStatic(pkt->getPtr<uint8_t>()); + otherPort->sendFunctional(funcPkt); + delete funcPkt; + pkt->cmd = MemCmd::WriteReq; + } + return delay + otherPort->sendAtomic(pkt); } /** Function called by the port when the bus is receiving a Functional @@ -336,7 +367,7 @@ Bridge::BridgePort::recvStatusChange(Port::Status status) void Bridge::BridgePort::getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { otherPort->getPeerAddressRanges(resp, snoop); } @@ -387,3 +418,4 @@ CREATE_SIM_OBJECT(Bridge) REGISTER_SIM_OBJECT("Bridge", Bridge) + diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index cb5a6baed..89d626611 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -80,18 +80,13 @@ class Bridge : public MemObject short origSrc; bool expectResponse; - bool partialWriteFixed; - PacketPtr oldPkt; - bool nacked; - PacketBuffer(PacketPtr _pkt, Tick t, bool nack = false) : ready(t), pkt(_pkt), origSenderState(_pkt->senderState), origSrc(_pkt->getSrc()), - expectResponse(_pkt->needsResponse() && !nack), - partialWriteFixed(false), nacked(nack) + expectResponse(_pkt->needsResponse() && !nack) { - if (!pkt->isResponse() && !nack) + if (!pkt->isResponse() && !nack && pkt->result != Packet::Nacked) pkt->senderState = this; } @@ -100,46 +95,7 @@ class Bridge : public MemObject assert(pkt->senderState == this); pkt->setDest(origSrc); pkt->senderState = origSenderState; - if (partialWriteFixed) - delete oldPkt; - } - - void partialWriteFix(Port *port) - { - assert(!partialWriteFixed); - assert(expectResponse); - - int pbs = port->peerBlockSize(); - partialWriteFixed = true; - PacketDataPtr data; - - data = new uint8_t[pbs]; - PacketPtr funcPkt = new Packet(pkt->req, MemCmd::ReadReq, - Packet::Broadcast, pbs); - - funcPkt->dataStatic(data); - port->sendFunctional(funcPkt); - assert(funcPkt->result == Packet::Success); - delete funcPkt; - - oldPkt = pkt; - memcpy(data + oldPkt->getOffset(pbs), pkt->getPtr<uint8_t>(), - pkt->getSize()); - pkt = new Packet(oldPkt->req, MemCmd::WriteInvalidateReq, - Packet::Broadcast, pbs); - pkt->dataDynamicArray(data); - pkt->senderState = oldPkt->senderState; } - - void undoPartialWriteFix() - { - if (!partialWriteFixed) - return; - delete pkt; - pkt = oldPkt; - partialWriteFixed = false; - } - }; /** @@ -226,7 +182,7 @@ class Bridge : public MemObject /** When receiving a address range request the peer port, pass it to the bridge. */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); }; BridgePort portA, portB; diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 95d4e2873..13e545064 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -296,16 +296,15 @@ Bus::findPort(Addr addr, int id) { /* An interval tree would be a better way to do this. --ali. */ int dest_id = -1; - AddrRangeIter iter; - range_map<Addr,int>::iterator i; - i = portMap.find(RangeSize(addr,1)); + PortIter i = portMap.find(RangeSize(addr,1)); if (i != portMap.end()) dest_id = i->second; // Check if this matches the default range if (dest_id == -1) { - for (iter = defaultRange.begin(); iter != defaultRange.end(); iter++) { + for (AddrRangeIter iter = defaultRange.begin(); + iter != defaultRange.end(); iter++) { if (*iter == addr) { DPRINTF(Bus, " found addr %#llx on default\n", addr); return defaultPort; @@ -333,88 +332,63 @@ Bus::findPort(Addr addr, int id) return interfaces[dest_id]; } -std::vector<int> -Bus::findSnoopPorts(Addr addr, int id) -{ - int i = 0; - AddrRangeIter iter; - std::vector<int> ports; - - while (i < portSnoopList.size()) - { - if (portSnoopList[i].range == addr && portSnoopList[i].portId != id) { - //Careful to not overlap ranges - //or snoop will be called more than once on the port - - //@todo Fix this hack because ranges are overlapping - //need to make sure we dont't create overlapping ranges - bool hack_overlap = false; - int size = ports.size(); - for (int j=0; j < size; j++) { - if (ports[j] == portSnoopList[i].portId) - hack_overlap = true; - } - - if (!hack_overlap) - ports.push_back(portSnoopList[i].portId); -// DPRINTF(Bus, " found snoop addr %#llx on device%d\n", addr, -// portSnoopList[i].portId); - } - i++; - } - return ports; -} - Tick Bus::atomicSnoop(PacketPtr pkt, Port *responder) { - std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc()); Tick response_time = 0; - while (!ports.empty()) - { - if (interfaces[ports.back()] != responder) { - Tick response = interfaces[ports.back()]->sendAtomic(pkt); + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); + s_iter++) { + BusPort *p = *s_iter; + if (p != responder && p->getId() != pkt->getSrc()) { + Tick response = p->sendAtomic(pkt); if (response) { assert(!response_time); //Multiple responders response_time = response; } } - ports.pop_back(); } + return response_time; } void Bus::functionalSnoop(PacketPtr pkt, Port *responder) { - std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc()); - - //The packet may be changed by another bus on snoops, restore the id after each - int id = pkt->getSrc(); - while (!ports.empty() && pkt->result != Packet::Success) - { - if (interfaces[ports.back()] != responder) - interfaces[ports.back()]->sendFunctional(pkt); - ports.pop_back(); - pkt->setSrc(id); + // The packet may be changed by another bus on snoops, restore the + // id after each + int src_id = pkt->getSrc(); + + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); + s_iter++) { + BusPort *p = *s_iter; + if (p != responder && p->getId() != src_id) { + p->sendFunctional(pkt); + } + if (pkt->result == Packet::Success) { + break; + } + pkt->setSrc(src_id); } } bool Bus::timingSnoop(PacketPtr pkt, Port* responder) { - std::vector<int> ports = findSnoopPorts(pkt->getAddr(), pkt->getSrc()); - bool success = true; - - while (!ports.empty() && success) - { - if (interfaces[ports.back()] != responder) //Don't call if responder also, once will do - success = interfaces[ports.back()]->sendTiming(pkt); - ports.pop_back(); + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); + s_iter++) { + BusPort *p = *s_iter; + if (p != responder && p->getId() != pkt->getSrc()) { + bool success = p->sendTiming(pkt); + if (!success) + return false; + } } - return success; + return true; } @@ -467,7 +441,7 @@ void Bus::recvStatusChange(Port::Status status, int id) { AddrRangeList ranges; - AddrRangeList snoops; + bool snoops; AddrRangeIter iter; assert(status == Port::RangeChange && @@ -480,7 +454,7 @@ Bus::recvStatusChange(Port::Status status, int id) // Only try to update these ranges if the user set a default responder. if (responderSet) { defaultPort->getPeerAddressRanges(ranges, snoops); - assert(snoops.size() == 0); + assert(snoops == false); for(iter = ranges.begin(); iter != ranges.end(); iter++) { defaultRange.push_back(*iter); DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for default range\n", @@ -490,39 +464,33 @@ Bus::recvStatusChange(Port::Status status, int id) } else { assert((id < maxId && id >= 0) || id == defaultId); - Port *port = interfaces[id]; - range_map<Addr,int>::iterator portIter; - std::vector<DevMap>::iterator snoopIter; + BusPort *port = interfaces[id]; // Clean out any previously existent ids - for (portIter = portMap.begin(); portIter != portMap.end(); ) { + for (PortIter portIter = portMap.begin(); + portIter != portMap.end(); ) { if (portIter->second == id) portMap.erase(portIter++); else portIter++; } - for (snoopIter = portSnoopList.begin(); snoopIter != portSnoopList.end(); ) { - if (snoopIter->portId == id) - snoopIter = portSnoopList.erase(snoopIter); + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); ) { + if ((*s_iter)->getId() == id) + s_iter = snoopPorts.erase(s_iter); else - snoopIter++; + s_iter++; } port->getPeerAddressRanges(ranges, snoops); - for(iter = snoops.begin(); iter != snoops.end(); iter++) { - DevMap dm; - dm.portId = id; - dm.range = *iter; - - //@todo, make sure we don't overlap ranges - DPRINTF(BusAddrRanges, "Adding snoop range %#llx - %#llx for id %d\n", - dm.range.start, dm.range.end, id); - portSnoopList.push_back(dm); + if (snoops) { + DPRINTF(BusAddrRanges, "Adding id %d to snoop list\n", id); + snoopPorts.push_back(port); } - for(iter = ranges.begin(); iter != ranges.end(); iter++) { + for (iter = ranges.begin(); iter != ranges.end(); iter++) { DPRINTF(BusAddrRanges, "Adding range %#llx - %#llx for id %d\n", iter->start, iter->end, id); if (portMap.insert(*iter, id) == portMap.end()) @@ -545,28 +513,24 @@ Bus::recvStatusChange(Port::Status status, int id) } void -Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id) +Bus::addressRanges(AddrRangeList &resp, bool &snoop, int id) { - std::vector<DevMap>::iterator snoopIter; - range_map<Addr,int>::iterator portIter; - AddrRangeIter dflt_iter; - bool subset; - resp.clear(); - snoop.clear(); + snoop = false; DPRINTF(BusAddrRanges, "received address range request, returning:\n"); - for (dflt_iter = defaultRange.begin(); dflt_iter != defaultRange.end(); - dflt_iter++) { + for (AddrRangeIter dflt_iter = defaultRange.begin(); + dflt_iter != defaultRange.end(); dflt_iter++) { resp.push_back(*dflt_iter); DPRINTF(BusAddrRanges, " -- Dflt: %#llx : %#llx\n",dflt_iter->start, dflt_iter->end); } - for (portIter = portMap.begin(); portIter != portMap.end(); portIter++) { - subset = false; - for (dflt_iter = defaultRange.begin(); dflt_iter != defaultRange.end(); - dflt_iter++) { + for (PortIter portIter = portMap.begin(); + portIter != portMap.end(); portIter++) { + bool subset = false; + for (AddrRangeIter dflt_iter = defaultRange.begin(); + dflt_iter != defaultRange.end(); dflt_iter++) { if ((portIter->first.start < dflt_iter->start && portIter->first.end >= dflt_iter->start) || (portIter->first.start < dflt_iter->end && @@ -587,15 +551,11 @@ Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id) } } - for (snoopIter = portSnoopList.begin(); - snoopIter != portSnoopList.end(); snoopIter++) - { - if (snoopIter->portId != id) { - snoop.push_back(snoopIter->range); - DPRINTF(BusAddrRanges, " -- Snoop: %#llx : %#llx\n", - snoopIter->range.start, snoopIter->range.end); - //@todo We need to properly insert snoop ranges - //not overlapping the ranges (multiple) + for (SnoopIter s_iter = snoopPorts.begin(); s_iter != snoopPorts.end(); + s_iter++) { + if ((*s_iter)->getId() != id) { + snoop = true; + break; } } } @@ -606,17 +566,17 @@ Bus::findBlockSize(int id) if (cachedBlockSizeValid) return cachedBlockSize; - int max_bs = -1, tmp_bs; - range_map<Addr,int>::iterator portIter; - std::vector<DevMap>::iterator snoopIter; - for (portIter = portMap.begin(); portIter != portMap.end(); portIter++) { - tmp_bs = interfaces[portIter->second]->peerBlockSize(); + int max_bs = -1; + + for (PortIter portIter = portMap.begin(); + portIter != portMap.end(); portIter++) { + int tmp_bs = interfaces[portIter->second]->peerBlockSize(); if (tmp_bs > max_bs) max_bs = tmp_bs; } - for (snoopIter = portSnoopList.begin(); - snoopIter != portSnoopList.end(); snoopIter++) { - tmp_bs = interfaces[snoopIter->portId]->peerBlockSize(); + for (SnoopIter s_iter = snoopPorts.begin(); + s_iter != snoopPorts.end(); s_iter++) { + int tmp_bs = (*s_iter)->peerBlockSize(); if (tmp_bs > max_bs) max_bs = tmp_bs; } @@ -645,6 +605,13 @@ Bus::drain(Event * de) } } +void +Bus::startup() +{ + if (tickNextIdle < curTick) + tickNextIdle = (curTick / clock) * clock + clock; +} + BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus) Param<int> bus_id; diff --git a/src/mem/bus.hh b/src/mem/bus.hh index f0dc67b12..ee647e20a 100644 --- a/src/mem/bus.hh +++ b/src/mem/bus.hh @@ -52,93 +52,6 @@ class Bus : public MemObject { - /** a globally unique id for this bus. */ - int busId; - /** the clock speed for the bus */ - int clock; - /** the width of the bus in bytes */ - int width; - /** the next tick at which the bus will be idle */ - Tick tickNextIdle; - - Event * drainEvent; - - - static const int defaultId = -3; //Make it unique from Broadcast - - struct DevMap { - int portId; - Range<Addr> range; - }; - range_map<Addr, int> portMap; - AddrRangeList defaultRange; - std::vector<DevMap> portSnoopList; - - /** Function called by the port when the bus is recieving a Timing - transaction.*/ - bool recvTiming(PacketPtr pkt); - - /** Function called by the port when the bus is recieving a Atomic - transaction.*/ - Tick recvAtomic(PacketPtr pkt); - - /** Function called by the port when the bus is recieving a Functional - transaction.*/ - void recvFunctional(PacketPtr pkt); - - /** Timing function called by port when it is once again able to process - * requests. */ - void recvRetry(int id); - - /** Function called by the port when the bus is recieving a status change.*/ - void recvStatusChange(Port::Status status, int id); - - /** Find which port connected to this bus (if any) should be given a packet - * with this address. - * @param addr Address to find port for. - * @param id Id of the port this packet was received from (to prevent - * loops) - * @return pointer to port that the packet should be sent out of. - */ - Port *findPort(Addr addr, int id); - - /** Find all ports with a matching snoop range, except src port. Keep in mind - * that the ranges shouldn't overlap or you will get a double snoop to the same - * interface.and the cache will assert out. - * @param addr Address to find snoop prts for. - * @param id Id of the src port of the request to avoid calling snoop on src - * @return vector of IDs to snoop on - */ - std::vector<int> findSnoopPorts(Addr addr, int id); - - /** Snoop all relevant ports atomicly. */ - Tick atomicSnoop(PacketPtr pkt, Port* responder); - - /** Snoop all relevant ports functionally. */ - void functionalSnoop(PacketPtr pkt, Port *responder); - - /** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want - * the snoop to happen - * @return True if succeds. - */ - bool timingSnoop(PacketPtr pkt, Port *responder); - - /** Process address range request. - * @param resp addresses that we can respond to - * @param snoop addresses that we would like to snoop - * @param id ide of the busport that made the request. - */ - void addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id); - - /** Occupy the bus with transmitting the packet pkt */ - void occupyBus(PacketPtr pkt); - - /** Ask everyone on the bus what their size is - * @param id id of the busport that made the request - * @return the max of all the sizes - */ - int findBlockSize(int id); - /** Declaration of the buses port type, one will be instantiated for each of the interfaces connecting to the bus. */ class BusPort : public Port @@ -198,7 +111,7 @@ class Bus : public MemObject // the 'owned' address ranges of all the other interfaces on // this bus... virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { bus->addressRanges(resp, snoop, id); } // Ask the bus to ask everyone on the bus what their block size is and @@ -219,6 +132,84 @@ class Bus : public MemObject const char *description(); }; + /** a globally unique id for this bus. */ + int busId; + /** the clock speed for the bus */ + int clock; + /** the width of the bus in bytes */ + int width; + /** the next tick at which the bus will be idle */ + Tick tickNextIdle; + + Event * drainEvent; + + + static const int defaultId = -3; //Make it unique from Broadcast + + typedef range_map<Addr,int>::iterator PortIter; + range_map<Addr, int> portMap; + + AddrRangeList defaultRange; + + typedef std::vector<BusPort*>::iterator SnoopIter; + std::vector<BusPort*> snoopPorts; + + /** Function called by the port when the bus is recieving a Timing + transaction.*/ + bool recvTiming(PacketPtr pkt); + + /** Function called by the port when the bus is recieving a Atomic + transaction.*/ + Tick recvAtomic(PacketPtr pkt); + + /** Function called by the port when the bus is recieving a Functional + transaction.*/ + void recvFunctional(PacketPtr pkt); + + /** Timing function called by port when it is once again able to process + * requests. */ + void recvRetry(int id); + + /** Function called by the port when the bus is recieving a status change.*/ + void recvStatusChange(Port::Status status, int id); + + /** Find which port connected to this bus (if any) should be given a packet + * with this address. + * @param addr Address to find port for. + * @param id Id of the port this packet was received from (to prevent + * loops) + * @return pointer to port that the packet should be sent out of. + */ + Port *findPort(Addr addr, int id); + + /** Snoop all relevant ports atomicly. */ + Tick atomicSnoop(PacketPtr pkt, Port* responder); + + /** Snoop all relevant ports functionally. */ + void functionalSnoop(PacketPtr pkt, Port *responder); + + /** Call snoop on caches, be sure to set SNOOP_COMMIT bit if you want + * the snoop to happen + * @return True if succeds. + */ + bool timingSnoop(PacketPtr pkt, Port *responder); + + /** Process address range request. + * @param resp addresses that we can respond to + * @param snoop addresses that we would like to snoop + * @param id ide of the busport that made the request. + */ + void addressRanges(AddrRangeList &resp, bool &snoop, int id); + + /** Occupy the bus with transmitting the packet pkt */ + void occupyBus(PacketPtr pkt); + + /** Ask everyone on the bus what their size is + * @param id id of the busport that made the request + * @return the max of all the sizes + */ + int findBlockSize(int id); + BusFreeEvent busIdle; bool inRetry; @@ -276,6 +267,7 @@ class Bus : public MemObject virtual void deletePortRefs(Port *p); virtual void init(); + virtual void startup(); unsigned int drain(Event *de); diff --git a/src/python/m5/objects/BaseCache.py b/src/mem/cache/BaseCache.py index 773a11bea..32f3f0174 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -1,4 +1,33 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + from m5.params import * +from m5.proxy import Self from MemObject import MemObject class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] @@ -9,7 +38,7 @@ class BaseCache(MemObject): "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - latency = Param.Int("Latency") + latency = Param.Latency("Latency") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', @@ -49,7 +78,7 @@ class BaseCache(MemObject): "Squash prefetches with a later time on a subsequent miss") prefetch_degree = Param.Int(1, "Degree of the prefetch depth") - prefetch_latency = Param.Tick(10, + prefetch_latency = Param.Latency(10 * Self.latency, "Latency of the prefetcher") prefetch_policy = Param.Prefetch('none', "Type of prefetcher to use") @@ -59,6 +88,5 @@ class BaseCache(MemObject): "Use the CPU ID to seperate calculations of prefetches") prefetch_data_accesses_only = Param.Bool(False, "Only prefetch on data not on instruction accesses") - hit_latency = Param.Int(1,"Hit Latency of the cache") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index 7150719ad..546e037bd 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -30,6 +30,8 @@ Import('*') +SimObject('BaseCache.py') + Source('base_cache.cc') Source('cache.cc') Source('cache_builder.cc') diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index ed665dafb..8aac02460 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -59,8 +59,7 @@ BaseCache::CachePort::recvStatusChange(Port::Status status) } void -BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) +BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp, bool &snoop) { cache->getAddressRanges(resp, snoop, isCpuSide); } @@ -134,8 +133,7 @@ BaseCache::CachePort::recvRetry() isCpuSide && cache->doSlaveRequest()) { DPRINTF(CachePort, "%s has more responses/requests\n", name()); - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); - reqCpu->schedule(curTick + 1); + new BaseCache::RequestEvent(this, curTick + 1); } waitingOnRetry = false; } @@ -178,8 +176,7 @@ BaseCache::CachePort::recvRetry() { DPRINTF(CachePort, "%s has more requests\n", name()); //Still more to issue, rerequest in 1 cycle - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); - reqCpu->schedule(curTick + 1); + new BaseCache::RequestEvent(this, curTick + 1); } } else @@ -196,8 +193,7 @@ BaseCache::CachePort::recvRetry() { DPRINTF(CachePort, "%s has more requests\n", name()); //Still more to issue, rerequest in 1 cycle - BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(this, false); - reqCpu->schedule(curTick + 1); + new BaseCache::RequestEvent(this, curTick + 1); } } if (waitingOnRetry) DPRINTF(CachePort, "%s STILL Waiting on retry\n", name()); @@ -228,102 +224,109 @@ BaseCache::CachePort::clearBlocked() } } -BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, bool _newResponse) - : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), - newResponse(_newResponse) +BaseCache::RequestEvent::RequestEvent(CachePort *_cachePort, Tick when) + : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) { - if (!newResponse) - this->setFlags(AutoDelete); - pkt = NULL; + this->setFlags(AutoDelete); + schedule(when); } void -BaseCache::CacheEvent::process() +BaseCache::RequestEvent::process() { - if (!newResponse) - { - if (cachePort->waitingOnRetry) return; - //We have some responses to drain first - if (!cachePort->drainList.empty()) { - DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name()); - if (cachePort->sendTiming(cachePort->drainList.front())) { - DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name()); - cachePort->drainList.pop_front(); - if (!cachePort->drainList.empty() || - !cachePort->isCpuSide && cachePort->cache->doMasterRequest() || - cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) { - - DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name()); - this->schedule(curTick + 1); - } - } - else { - cachePort->waitingOnRetry = true; - DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + if (cachePort->waitingOnRetry) return; + //We have some responses to drain first + if (!cachePort->drainList.empty()) { + DPRINTF(CachePort, "%s trying to drain a response\n", cachePort->name()); + if (cachePort->sendTiming(cachePort->drainList.front())) { + DPRINTF(CachePort, "%s drains a response succesfully\n", cachePort->name()); + cachePort->drainList.pop_front(); + if (!cachePort->drainList.empty() || + !cachePort->isCpuSide && cachePort->cache->doMasterRequest() || + cachePort->isCpuSide && cachePort->cache->doSlaveRequest()) { + + DPRINTF(CachePort, "%s still has outstanding bus reqs\n", cachePort->name()); + this->schedule(curTick + 1); } } - else if (!cachePort->isCpuSide) - { //MSHR - DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name()); - if (!cachePort->cache->doMasterRequest()) { - //This can happen if I am the owner of a block and see an upgrade - //while the block was in my WB Buffers. I just remove the - //wb and de-assert the masterRequest - return; - } + else { + cachePort->waitingOnRetry = true; + DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + } + } + else if (!cachePort->isCpuSide) + { //MSHR + DPRINTF(CachePort, "%s trying to send a MSHR request\n", cachePort->name()); + if (!cachePort->cache->doMasterRequest()) { + //This can happen if I am the owner of a block and see an upgrade + //while the block was in my WB Buffers. I just remove the + //wb and de-assert the masterRequest + return; + } - pkt = cachePort->cache->getPacket(); - MSHR* mshr = (MSHR*) pkt->senderState; - //Copy the packet, it may be modified/destroyed elsewhere - PacketPtr copyPkt = new Packet(*pkt); - copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>()); - mshr->pkt = copyPkt; + PacketPtr pkt = cachePort->cache->getPacket(); + MSHR* mshr = (MSHR*) pkt->senderState; + //Copy the packet, it may be modified/destroyed elsewhere + PacketPtr copyPkt = new Packet(*pkt); + copyPkt->dataStatic<uint8_t>(pkt->getPtr<uint8_t>()); + mshr->pkt = copyPkt; - bool success = cachePort->sendTiming(pkt); - DPRINTF(Cache, "Address %x was %s in sending the timing request\n", - pkt->getAddr(), success ? "succesful" : "unsuccesful"); + bool success = cachePort->sendTiming(pkt); + DPRINTF(Cache, "Address %x was %s in sending the timing request\n", + pkt->getAddr(), success ? "succesful" : "unsuccesful"); - cachePort->waitingOnRetry = !success; - if (cachePort->waitingOnRetry) { - DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); - } + cachePort->waitingOnRetry = !success; + if (cachePort->waitingOnRetry) { + DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + } - cachePort->cache->sendResult(pkt, mshr, success); - if (success && cachePort->cache->doMasterRequest()) - { - DPRINTF(CachePort, "%s still more MSHR requests to send\n", - cachePort->name()); - //Still more to issue, rerequest in 1 cycle - pkt = NULL; - this->schedule(curTick+1); - } + cachePort->cache->sendResult(pkt, mshr, success); + if (success && cachePort->cache->doMasterRequest()) + { + DPRINTF(CachePort, "%s still more MSHR requests to send\n", + cachePort->name()); + //Still more to issue, rerequest in 1 cycle + this->schedule(curTick+1); } - else + } + else + { + //CSHR + assert(cachePort->cache->doSlaveRequest()); + PacketPtr pkt = cachePort->cache->getCoherencePacket(); + MSHR* cshr = (MSHR*) pkt->senderState; + bool success = cachePort->sendTiming(pkt); + cachePort->cache->sendCoherenceResult(pkt, cshr, success); + cachePort->waitingOnRetry = !success; + if (cachePort->waitingOnRetry) + DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); + if (success && cachePort->cache->doSlaveRequest()) { - //CSHR - assert(cachePort->cache->doSlaveRequest()); - pkt = cachePort->cache->getCoherencePacket(); - MSHR* cshr = (MSHR*) pkt->senderState; - bool success = cachePort->sendTiming(pkt); - cachePort->cache->sendCoherenceResult(pkt, cshr, success); - cachePort->waitingOnRetry = !success; - if (cachePort->waitingOnRetry) - DPRINTF(CachePort, "%s now waiting on a retry\n", cachePort->name()); - if (success && cachePort->cache->doSlaveRequest()) - { - DPRINTF(CachePort, "%s still more CSHR requests to send\n", - cachePort->name()); - //Still more to issue, rerequest in 1 cycle - pkt = NULL; - this->schedule(curTick+1); - } + DPRINTF(CachePort, "%s still more CSHR requests to send\n", + cachePort->name()); + //Still more to issue, rerequest in 1 cycle + this->schedule(curTick+1); } - return; } - //Else it's a response +} + +const char * +BaseCache::RequestEvent::description() +{ + return "Cache request event"; +} + +BaseCache::ResponseEvent::ResponseEvent(CachePort *_cachePort) + : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) +{ +} + +void +BaseCache::ResponseEvent::process() +{ assert(cachePort->transmitList.size()); assert(cachePort->transmitList.front().first <= curTick); - pkt = cachePort->transmitList.front().second; + PacketPtr pkt = cachePort->transmitList.front().second; cachePort->transmitList.pop_front(); if (!cachePort->transmitList.empty()) { Tick time = cachePort->transmitList.front().first; @@ -354,9 +357,9 @@ BaseCache::CacheEvent::process() } const char * -BaseCache::CacheEvent::description() +BaseCache::ResponseEvent::description() { - return "BaseCache timing event"; + return "Cache response event"; } void diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index ee871c1c4..f06a79dc0 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -87,7 +87,7 @@ class BaseCache : public MemObject virtual void recvStatusChange(Status status); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); virtual int deviceBlockSize(); @@ -117,13 +117,20 @@ class BaseCache : public MemObject std::list<std::pair<Tick,PacketPtr> > transmitList; }; - struct CacheEvent : public Event + struct RequestEvent : public Event { CachePort *cachePort; - PacketPtr pkt; - bool newResponse; - CacheEvent(CachePort *_cachePort, bool response); + RequestEvent(CachePort *_cachePort, Tick when); + void process(); + const char *description(); + }; + + struct ResponseEvent : public Event + { + CachePort *cachePort; + + ResponseEvent(CachePort *_cachePort); void process(); const char *description(); }; @@ -132,8 +139,8 @@ class BaseCache : public MemObject CachePort *cpuSidePort; CachePort *memSidePort; - CacheEvent *sendEvent; - CacheEvent *memSendEvent; + ResponseEvent *sendEvent; + ResponseEvent *memSendEvent; private: void recvStatusChange(Port::Status status, bool isCpuSide) @@ -432,9 +439,7 @@ class BaseCache : public MemObject { if (!doMasterRequest() && !memSidePort->waitingOnRetry) { - BaseCache::CacheEvent * reqCpu = - new BaseCache::CacheEvent(memSidePort, false); - reqCpu->schedule(time); + new RequestEvent(memSidePort, time); } uint8_t flag = 1<<cause; masterRequests |= flag; @@ -469,9 +474,7 @@ class BaseCache : public MemObject { if (!doSlaveRequest() && !cpuSidePort->waitingOnRetry) { - BaseCache::CacheEvent * reqCpu = - new BaseCache::CacheEvent(cpuSidePort, false); - reqCpu->schedule(time); + new RequestEvent(cpuSidePort, time); } uint8_t flag = 1<<cause; slaveRequests |= flag; @@ -653,19 +656,18 @@ class BaseCache : public MemObject */ void rangeChange() {} - void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide) + void getAddressRanges(AddrRangeList &resp, bool &snoop, bool isCpuSide) { if (isCpuSide) { - AddrRangeList dummy; + bool dummy; memSidePort->getPeerAddressRanges(resp, dummy); } else { //This is where snoops get updated AddrRangeList dummy; - cpuSidePort->getPeerAddressRanges(dummy, snoop); - return; + snoop = true; } } diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc index 318b57d50..e887f711e 100644 --- a/src/mem/cache/cache_builder.cc +++ b/src/mem/cache/cache_builder.cc @@ -134,7 +134,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache) Param<bool> prefetch_cache_check_push; Param<bool> prefetch_use_cpu_id; Param<bool> prefetch_data_accesses_only; - Param<int> hit_latency; END_DECLARE_SIM_OBJECT_PARAMS(BaseCache) @@ -190,8 +189,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache) INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"), INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true), INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true), - INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false), - INIT_PARAM_DFLT(hit_latency, "Hit Latecny for a succesful access", 1) + INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false) END_INIT_SIM_OBJECT_PARAMS(BaseCache) @@ -211,7 +209,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache) BUILD_NULL_PREFETCHER(TAGS); \ } \ Cache<TAGS, c>::Params params(tags, mq, coh, base_params, \ - pf, prefetch_access, hit_latency, \ + pf, prefetch_access, latency, \ true, \ store_compressed, \ adaptive_compression, \ diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index c70f10151..9b094c1e3 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -1146,11 +1146,11 @@ template<class TagStore, class Coherence> Port * Cache<TagStore,Coherence>::getPort(const std::string &if_name, int idx) { - if (if_name == "") + if (if_name == "" || if_name == "cpu_side") { if (cpuSidePort == NULL) { cpuSidePort = new CpuSidePort(name() + "-cpu_side_port", this); - sendEvent = new CacheEvent(cpuSidePort, true); + sendEvent = new ResponseEvent(cpuSidePort); } return cpuSidePort; } @@ -1158,20 +1158,12 @@ Cache<TagStore,Coherence>::getPort(const std::string &if_name, int idx) { return new CpuSidePort(name() + "-cpu_side_funcport", this); } - else if (if_name == "cpu_side") - { - if (cpuSidePort == NULL) { - cpuSidePort = new CpuSidePort(name() + "-cpu_side_port", this); - sendEvent = new CacheEvent(cpuSidePort, true); - } - return cpuSidePort; - } else if (if_name == "mem_side") { if (memSidePort != NULL) panic("Already have a mem side for this cache\n"); memSidePort = new MemSidePort(name() + "-mem_side_port", this); - memSendEvent = new CacheEvent(memSidePort, true); + memSendEvent = new ResponseEvent(memSidePort); return memSidePort; } else panic("Port name %s unrecognized\n", if_name); @@ -1290,9 +1282,9 @@ template<class TagStore, class Coherence> void Cache<TagStore,Coherence>::MemSidePort::recvFunctional(PacketPtr pkt) { - if (checkFunctional(pkt)) { - myCache()->probe(pkt, false, cache->cpuSidePort); - } + myCache()->probe(pkt, false, cache->cpuSidePort); + if (pkt->result != Packet::Success) + checkFunctional(pkt); } diff --git a/src/python/m5/objects/CoherenceProtocol.py b/src/mem/cache/coherence/CoherenceProtocol.py index 82adb6862..82adb6862 100644 --- a/src/python/m5/objects/CoherenceProtocol.py +++ b/src/mem/cache/coherence/CoherenceProtocol.py diff --git a/src/mem/cache/coherence/SConscript b/src/mem/cache/coherence/SConscript index 03a2d85d7..4f5966140 100644 --- a/src/mem/cache/coherence/SConscript +++ b/src/mem/cache/coherence/SConscript @@ -30,6 +30,8 @@ Import('*') +SimObject('CoherenceProtocol.py') + Source('coherence_protocol.cc') Source('uni_coherence.cc') diff --git a/src/python/m5/objects/Repl.py b/src/mem/cache/tags/Repl.py index b76aa1d6e..b76aa1d6e 100644 --- a/src/python/m5/objects/Repl.py +++ b/src/mem/cache/tags/Repl.py diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript index baf71f687..3fcaec4fa 100644 --- a/src/mem/cache/tags/SConscript +++ b/src/mem/cache/tags/SConscript @@ -38,5 +38,6 @@ Source('split.cc') Source('split_lifo.cc') Source('split_lru.cc') +SimObject('Repl.py') Source('repl/gen.cc') Source('repl/repl.cc') diff --git a/src/mem/packet.cc b/src/mem/packet.cc index 2463a19ba..f70c0cec3 100644 --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -192,11 +192,12 @@ fixPacket(PacketPtr func, PacketPtr timing) func->flags |= SATISFIED; return false; } else { - // In this case the timing packet only partially satisfies the - // requset, so we would need more information to make this work. - // Like bytes valid in the packet or something, so the request could - // continue and get this bit of possibly newer data along with the - // older data not written to yet. + // In this case the timing packet only partially satisfies + // the request, so we would need more information to make + // this work. Like bytes valid in the packet or + // something, so the request could continue and get this + // bit of possibly newer data along with the older data + // not written to yet. panic("Timing packet only partially satisfies the functional" "request. Now what?"); } diff --git a/src/mem/packet.hh b/src/mem/packet.hh index dc23e9f6d..c1e6a1e7f 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -506,16 +506,18 @@ class Packet bool intersect(PacketPtr p); }; -/** This function given a functional packet and a timing packet either satisfies - * the timing packet, or updates the timing packet to reflect the updated state - * in the timing packet. It returns if the functional packet should continue to - * traverse the memory hierarchy or not. +/** This function given a functional packet and a timing packet either + * satisfies the timing packet, or updates the timing packet to + * reflect the updated state in the timing packet. It returns if the + * functional packet should continue to traverse the memory hierarchy + * or not. */ bool fixPacket(PacketPtr func, PacketPtr timing); -/** This function is a wrapper for the fixPacket field that toggles the hasData bit - * it is used when a response is waiting in the caches, but hasn't been marked as a - * response yet (so the fixPacket needs to get the correct value for the hasData) +/** This function is a wrapper for the fixPacket field that toggles + * the hasData bit it is used when a response is waiting in the + * caches, but hasn't been marked as a response yet (so the fixPacket + * needs to get the correct value for the hasData) */ bool fixDelayedResponsePacket(PacketPtr func, PacketPtr timing); diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index 96bc23793..b29a07078 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -90,8 +90,6 @@ PageTable::page_check(Addr addr, int64_t size) const } - - void PageTable::allocate(Addr vaddr, int64_t size) { @@ -109,12 +107,7 @@ PageTable::allocate(Addr vaddr, int64_t size) } pTable[vaddr] = system->new_page(); - pTableCache[2].paddr = pTableCache[1].paddr; - pTableCache[2].vaddr = pTableCache[1].vaddr; - pTableCache[1].paddr = pTableCache[0].paddr; - pTableCache[1].vaddr = pTableCache[0].vaddr; - pTableCache[0].paddr = pTable[vaddr]; - pTableCache[0].vaddr = vaddr; + updateCache(vaddr, pTable[vaddr]); } } @@ -126,16 +119,16 @@ PageTable::translate(Addr vaddr, Addr &paddr) Addr page_addr = pageAlign(vaddr); paddr = 0; - if (pTableCache[0].vaddr == vaddr) { - paddr = pTableCache[0].paddr; + if (pTableCache[0].vaddr == page_addr) { + paddr = pTableCache[0].paddr + pageOffset(vaddr); return true; } - if (pTableCache[1].vaddr == vaddr) { - paddr = pTableCache[1].paddr; + if (pTableCache[1].vaddr == page_addr) { + paddr = pTableCache[1].paddr + pageOffset(vaddr); return true; } - if (pTableCache[2].vaddr == vaddr) { - paddr = pTableCache[2].paddr; + if (pTableCache[2].vaddr == page_addr) { + paddr = pTableCache[2].paddr + pageOffset(vaddr); return true; } @@ -145,6 +138,7 @@ PageTable::translate(Addr vaddr, Addr &paddr) return false; } + updateCache(page_addr, iter->second); paddr = iter->second + pageOffset(vaddr); return true; } diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index 0e2b1f58c..64c824238 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -95,6 +95,22 @@ class PageTable */ Fault translate(RequestPtr &req); + /** + * Update the page table cache. + * @param vaddr virtual address (page aligned) to check + * @param paddr physical address (page aligned) to return + */ + inline void updateCache(Addr vaddr, Addr paddr) + { + pTableCache[2].paddr = pTableCache[1].paddr; + pTableCache[2].vaddr = pTableCache[1].vaddr; + pTableCache[1].paddr = pTableCache[0].paddr; + pTableCache[1].vaddr = pTableCache[0].vaddr; + pTableCache[0].paddr = paddr; + pTableCache[0].vaddr = vaddr; + } + + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); }; diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 5d7d7382a..9d840fe69 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -52,7 +52,7 @@ using namespace std; using namespace TheISA; PhysicalMemory::PhysicalMemory(Params *p) - : MemObject(p->name), pmemAddr(NULL), port(NULL), lat(p->latency), _params(p) + : MemObject(p->name), pmemAddr(NULL), lat(p->latency), _params(p) { if (params()->addrRange.size() % TheISA::PageBytes != 0) panic("Memory Size not divisible by page size\n"); @@ -76,9 +76,14 @@ PhysicalMemory::PhysicalMemory(Params *p) void PhysicalMemory::init() { - if (!port) - panic("PhysicalMemory not connected to anything!"); - port->sendStatusChange(Port::RangeChange); + if (ports.size() == 0) { + fatal("PhysicalMemory object %s is unconnected!", name()); + } + + for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) { + if (*pi) + (*pi)->sendStatusChange(Port::RangeChange); + } } PhysicalMemory::~PhysicalMemory() @@ -335,19 +340,33 @@ PhysicalMemory::doFunctionalAccess(PacketPtr pkt) Port * PhysicalMemory::getPort(const std::string &if_name, int idx) { - if (if_name == "port" && idx == -1) { - if (port != NULL) - panic("PhysicalMemory::getPort: additional port requested to memory!"); - port = new MemoryPort(name() + "-port", this); - return port; - } else if (if_name == "functional") { - /* special port for functional writes at startup. And for memtester */ - return new MemoryPort(name() + "-funcport", this); - } else { + // Accept request for "functional" port for backwards compatibility + // with places where this function is called from C++. I'd prefer + // to move all these into Python someday. + if (if_name == "functional") { + return new MemoryPort(csprintf("%s-functional", name()), this); + } + + if (if_name != "port") { panic("PhysicalMemory::getPort: unknown port %s requested", if_name); } + + if (idx >= ports.size()) { + ports.resize(idx+1); + } + + if (ports[idx] != NULL) { + panic("PhysicalMemory::getPort: port %d already assigned", idx); + } + + MemoryPort *port = + new MemoryPort(csprintf("%s-port%d", name(), idx), this); + + ports[idx] = port; + return port; } + void PhysicalMemory::recvStatusChange(Port::Status status) { @@ -366,18 +385,17 @@ PhysicalMemory::MemoryPort::recvStatusChange(Port::Status status) void PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { memory->getAddressRanges(resp, snoop); } void -PhysicalMemory::getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) +PhysicalMemory::getAddressRanges(AddrRangeList &resp, bool &snoop) { - snoop.clear(); + snoop = false; resp.clear(); - resp.push_back(RangeSize(start(), - params()->addrRange.size())); + resp.push_back(RangeSize(start(), params()->addrRange.size())); } int @@ -396,20 +414,7 @@ PhysicalMemory::MemoryPort::recvAtomic(PacketPtr pkt) void PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt) { - //Since we are overriding the function, make sure to have the impl of the - //check or functional accesses here. - std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin(); - std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end(); - bool notDone = true; - - while (i != end && notDone) { - PacketPtr target = i->second; - // If the target contains data, and it overlaps the - // probed request, need to update data - if (target->intersect(pkt)) - notDone = fixPacket(pkt, target); - i++; - } + checkFunctional(pkt); // Default implementation of SimpleTimingPort::recvFunctional() // calls recvAtomic() and throws away the latency; we can save a @@ -420,7 +425,11 @@ PhysicalMemory::MemoryPort::recvFunctional(PacketPtr pkt) unsigned int PhysicalMemory::drain(Event *de) { - int count = port->drain(de); + int count = 0; + for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) { + count += (*pi)->drain(de); + } + if (count) changeState(Draining); else diff --git a/src/mem/physical.hh b/src/mem/physical.hh index f7200b502..b9af5d334 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -64,7 +64,7 @@ class PhysicalMemory : public MemObject virtual void recvStatusChange(Status status); virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop); + bool &snoop); virtual int deviceBlockSize(); }; @@ -141,9 +141,10 @@ class PhysicalMemory : public MemObject } uint8_t *pmemAddr; - MemoryPort *port; int pagePtr; Tick lat; + std::vector<MemoryPort*> ports; + typedef std::vector<MemoryPort*>::iterator PortIterator; public: Addr new_page(); @@ -168,7 +169,7 @@ class PhysicalMemory : public MemObject public: int deviceBlockSize(); - void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop); + void getAddressRanges(AddrRangeList &resp, bool &snoop); virtual Port *getPort(const std::string &if_name, int idx = -1); void virtual init(); unsigned int drain(Event *de); diff --git a/src/mem/port.hh b/src/mem/port.hh index 877e00293..b23de6050 100644 --- a/src/mem/port.hh +++ b/src/mem/port.hh @@ -172,7 +172,7 @@ class Port @param snoop is a list of ranges snooped */ virtual void getDeviceAddressRanges(AddrRangeList &resp, - AddrRangeList &snoop) + bool &snoop) { panic("??"); } public: @@ -222,7 +222,7 @@ class Port /** Called by the associated device if it wishes to find out the address ranges connected to the peer ports devices. */ - void getPeerAddressRanges(AddrRangeList &resp, AddrRangeList &snoop) + void getPeerAddressRanges(AddrRangeList &resp, bool &snoop) { peer->getDeviceAddressRanges(resp, snoop); } /** This function is a wrapper around sendFunctional() diff --git a/src/mem/tport.cc b/src/mem/tport.cc index 9a4bd7967..ed4c0c172 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -31,23 +31,30 @@ #include "mem/tport.hh" void -SimpleTimingPort::recvFunctional(PacketPtr pkt) +SimpleTimingPort::checkFunctional(PacketPtr pkt) { - std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin(); - std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end(); - bool notDone = true; + DeferredPacketIterator i = transmitList.begin(); + DeferredPacketIterator end = transmitList.end(); - while (i != end && notDone) { - PacketPtr target = i->second; + for (; i != end; ++i) { + PacketPtr target = i->pkt; // If the target contains data, and it overlaps the // probed request, need to update data - if (target->intersect(pkt)) - notDone = fixPacket(pkt, target); - - i++; + if (target->intersect(pkt)) { + if (!fixPacket(pkt, target)) { + // fixPacket returns true for continue, false for done + return; + } + } } +} - //Then just do an atomic access and throw away the returned latency +void +SimpleTimingPort::recvFunctional(PacketPtr pkt) +{ + checkFunctional(pkt); + + // Just do an atomic access and throw away the returned latency if (pkt->result != Packet::Success) recvAtomic(pkt); } @@ -65,93 +72,94 @@ SimpleTimingPort::recvTiming(PacketPtr pkt) // turn packet around to go back to requester if response expected if (pkt->needsResponse()) { pkt->makeTimingResponse(); - sendTiming(pkt, latency); + schedSendTiming(pkt, curTick + latency); } - else { - if (pkt->cmd != MemCmd::UpgradeReq) - { - delete pkt->req; - delete pkt; - } + else if (pkt->cmd != MemCmd::UpgradeReq) { + delete pkt->req; + delete pkt; } return true; } -void -SimpleTimingPort::recvRetry() -{ - assert(!transmitList.empty()); - if (Port::sendTiming(transmitList.front().second)) { - transmitList.pop_front(); - DPRINTF(Bus, "No Longer waiting on retry\n"); - if (!transmitList.empty()) { - Tick time = transmitList.front().first; - sendEvent.schedule(time <= curTick ? curTick+1 : time); - } - } - - if (transmitList.empty() && drainEvent) { - drainEvent->process(); - drainEvent = NULL; - } -} void -SimpleTimingPort::sendTiming(PacketPtr pkt, Tick time) +SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when) { + assert(when > curTick); + // Nothing is on the list: add it and schedule an event if (transmitList.empty()) { - assert(!sendEvent.scheduled()); - sendEvent.schedule(curTick+time); - transmitList.push_back(std::pair<Tick,PacketPtr>(time+curTick,pkt)); + assert(!sendEvent->scheduled()); + sendEvent->schedule(when); + transmitList.push_back(DeferredPacket(when, pkt)); return; } // something is on the list and this belongs at the end - if (time+curTick >= transmitList.back().first) { - transmitList.push_back(std::pair<Tick,PacketPtr>(time+curTick,pkt)); + if (when >= transmitList.back().tick) { + transmitList.push_back(DeferredPacket(when, pkt)); return; } // Something is on the list and this belongs somewhere else - std::list<std::pair<Tick,PacketPtr> >::iterator i = transmitList.begin(); - std::list<std::pair<Tick,PacketPtr> >::iterator end = transmitList.end(); - bool done = false; + DeferredPacketIterator i = transmitList.begin(); + DeferredPacketIterator end = transmitList.end(); - while (i != end && !done) { - if (time+curTick < i->first) { + for (; i != end; ++i) { + if (when < i->tick) { if (i == transmitList.begin()) { //Inserting at begining, reschedule - sendEvent.reschedule(time+curTick); + sendEvent->reschedule(when); } - transmitList.insert(i,std::pair<Tick,PacketPtr>(time+curTick,pkt)); - done = true; + transmitList.insert(i, DeferredPacket(when, pkt)); + return; } - i++; } - assert(done); + assert(false); // should never get here } + void -SimpleTimingPort::SendEvent::process() +SimpleTimingPort::sendDeferredPacket() { - assert(port->transmitList.size()); - assert(port->transmitList.front().first <= curTick); - if (port->Port::sendTiming(port->transmitList.front().second)) { + assert(deferredPacketReady()); + bool success = sendTiming(transmitList.front().pkt); + + if (success) { //send successful, remove packet - port->transmitList.pop_front(); - if (!port->transmitList.empty()) { - Tick time = port->transmitList.front().first; - schedule(time <= curTick ? curTick+1 : time); + transmitList.pop_front(); + if (!transmitList.empty()) { + Tick time = transmitList.front().tick; + sendEvent->schedule(time <= curTick ? curTick+1 : time); } - if (port->transmitList.empty() && port->drainEvent) { - port->drainEvent->process(); - port->drainEvent = NULL; + + if (transmitList.empty() && drainEvent) { + drainEvent->process(); + drainEvent = NULL; } - return; } - // send unsuccessful (due to flow control). Will get retry - // callback later; save for then if not already - DPRINTF(Bus, "Waiting on retry\n"); + + waitingOnRetry = !success; + + if (waitingOnRetry) { + DPRINTF(Bus, "Send failed, waiting on retry\n"); + } +} + + +void +SimpleTimingPort::recvRetry() +{ + DPRINTF(Bus, "Received retry\n"); + assert(waitingOnRetry); + sendDeferredPacket(); +} + + +void +SimpleTimingPort::processSendEvent() +{ + assert(!waitingOnRetry); + sendDeferredPacket(); } diff --git a/src/mem/tport.hh b/src/mem/tport.hh index 3d28ea3e5..ea0f05ed1 100644 --- a/src/mem/tport.hh +++ b/src/mem/tport.hh @@ -58,9 +58,26 @@ class SimpleTimingPort : public Port { protected: + /** A deferred packet, buffered to transmit later. */ + class DeferredPacket { + public: + Tick tick; ///< The tick when the packet is ready to transmit + PacketPtr pkt; ///< Pointer to the packet to transmit + DeferredPacket(Tick t, PacketPtr p) + : tick(t), pkt(p) + {} + }; + + typedef std::list<DeferredPacket> DeferredPacketList; + typedef std::list<DeferredPacket>::iterator DeferredPacketIterator; + /** A list of outgoing timing response packets that haven't been * serviced yet. */ - std::list<std::pair<Tick,PacketPtr> > transmitList; + DeferredPacketList transmitList; + + /** This function attempts to send deferred packets. Scheduled to + * be called in the future via SendEvent. */ + void processSendEvent(); /** * This class is used to implemented sendTiming() with a delay. When @@ -68,32 +85,38 @@ class SimpleTimingPort : public Port * When the event time expires it attempts to send the packet. * If it cannot, the packet sent when recvRetry() is called. **/ - class SendEvent : public Event - { - SimpleTimingPort *port; - - public: - SendEvent(SimpleTimingPort *p) - : Event(&mainEventQueue), port(p) - { } - - virtual void process(); + typedef EventWrapper<SimpleTimingPort, &SimpleTimingPort::processSendEvent> + SendEvent; - virtual const char *description() - { return "Future scheduled sendTiming event"; } - }; - - SendEvent sendEvent; + Event *sendEvent; /** If we need to drain, keep the drain event around until we're done * here.*/ Event *drainEvent; + /** Remember whether we're awaiting a retry from the bus. */ + bool waitingOnRetry; + + /** Check the list of buffered packets against the supplied + * functional request. */ + void checkFunctional(PacketPtr funcPkt); + + /** Check whether we have a packet ready to go on the transmit list. */ + bool deferredPacketReady() + { return !transmitList.empty() && transmitList.front().tick <= curTick; } + /** Schedule a sendTiming() event to be called in the future. * @param pkt packet to send - * @param time increment from now (in ticks) to send packet + * @param absolute time (in ticks) to send packet + */ + void schedSendTiming(PacketPtr pkt, Tick when); + + /** Attempt to send the packet at the head of the deferred packet + * list. Caller must guarantee that the deferred packet list is + * non-empty and that the head packet is scheduled for curTick (or + * earlier). */ - void sendTiming(PacketPtr pkt, Tick time); + void sendDeferredPacket(); /** This function is notification that the device should attempt to send a * packet again. */ @@ -115,9 +138,14 @@ class SimpleTimingPort : public Port public: SimpleTimingPort(std::string pname, MemObject *_owner = NULL) - : Port(pname, _owner), sendEvent(this), drainEvent(NULL) + : Port(pname, _owner), + sendEvent(new SendEvent(this)), + drainEvent(NULL), + waitingOnRetry(false) {} + ~SimpleTimingPort() { delete sendEvent; } + /** Hook for draining timing accesses from the system. The * associated SimObject's drain() functions should be implemented * something like this when this class is used: diff --git a/src/python/SConscript b/src/python/SConscript index 3c5ab4da1..66b852d25 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -60,56 +60,3 @@ SwigSource('m5.internal', 'swig/sim_object.i') SwigSource('m5.internal', 'swig/stats.i') SwigSource('m5.internal', 'swig/trace.i') PySource('m5.internal', 'm5/internal/__init__.py') - -SimObject('m5/objects/AlphaConsole.py') -SimObject('m5/objects/AlphaTLB.py') -SimObject('m5/objects/BadDevice.py') -SimObject('m5/objects/BaseCPU.py') -SimObject('m5/objects/BaseCache.py') -SimObject('m5/objects/BaseHier.py') -SimObject('m5/objects/BaseMem.py') -SimObject('m5/objects/BaseMemory.py') -SimObject('m5/objects/BranchPred.py') -SimObject('m5/objects/Bridge.py') -SimObject('m5/objects/Bus.py') -SimObject('m5/objects/Checker.py') -SimObject('m5/objects/CoherenceProtocol.py') -SimObject('m5/objects/DRAMMemory.py') -SimObject('m5/objects/Device.py') -SimObject('m5/objects/DiskImage.py') -SimObject('m5/objects/Ethernet.py') -SimObject('m5/objects/FUPool.py') -SimObject('m5/objects/FastCPU.py') -#SimObject('m5/objects/FreebsdSystem.py') -SimObject('m5/objects/FullCPU.py') -SimObject('m5/objects/FuncUnit.py') -SimObject('m5/objects/FuncUnitConfig.py') -SimObject('m5/objects/FunctionalMemory.py') -SimObject('m5/objects/HierParams.py') -SimObject('m5/objects/Ide.py') -SimObject('m5/objects/IntrControl.py') -SimObject('m5/objects/LinuxSystem.py') -SimObject('m5/objects/MainMemory.py') -SimObject('m5/objects/MemObject.py') -SimObject('m5/objects/MemTest.py') -SimObject('m5/objects/MemoryController.py') -SimObject('m5/objects/O3CPU.py') -SimObject('m5/objects/OzoneCPU.py') -SimObject('m5/objects/Pci.py') -SimObject('m5/objects/PhysicalMemory.py') -SimObject('m5/objects/PipeTrace.py') -SimObject('m5/objects/Platform.py') -SimObject('m5/objects/Process.py') -SimObject('m5/objects/Repl.py') -SimObject('m5/objects/Root.py') -SimObject('m5/objects/Sampler.py') -SimObject('m5/objects/SimConsole.py') -SimObject('m5/objects/SimpleCPU.py') -SimObject('m5/objects/SimpleDisk.py') -#SimObject('m5/objects/SimpleOzoneCPU.py') -SimObject('m5/objects/SparcTLB.py') -SimObject('m5/objects/System.py') -SimObject('m5/objects/T1000.py') -#SimObject('m5/objects/Tru64System.py') -SimObject('m5/objects/Tsunami.py') -SimObject('m5/objects/Uart.py') diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 42266a80e..f87e13732 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -722,6 +722,13 @@ class SimObject(object): for child in self._children.itervalues(): child.resume() + def getMemoryMode(self): + if not isinstance(self, m5.objects.System): + return None + + system_ptr = internal.sim_object.convertToSystemPtr(self._ccObject) + return system_ptr.getMemoryMode() + def changeTiming(self, mode): if isinstance(self, m5.objects.System): # i don't know if there's a better way to do this - calling diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 06dc92bc6..a9206a474 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -190,17 +190,20 @@ def changeToAtomic(system): if not isinstance(system, (objects.Root, objects.System)): raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ (type(system), objects.Root, objects.System) - doDrain(system) - print "Changing memory mode to atomic" - system.changeTiming(internal.sim_object.SimObject.Atomic) + if system.getMemoryMode() != internal.sim_object.SimObject.Atomic: + doDrain(system) + print "Changing memory mode to atomic" + system.changeTiming(internal.sim_object.SimObject.Atomic) def changeToTiming(system): if not isinstance(system, (objects.Root, objects.System)): raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \ (type(system), objects.Root, objects.System) - doDrain(system) - print "Changing memory mode to timing" - system.changeTiming(internal.sim_object.SimObject.Timing) + + if system.getMemoryMode() != internal.sim_object.SimObject.Timing: + doDrain(system) + print "Changing memory mode to timing" + system.changeTiming(internal.sim_object.SimObject.Timing) def switchCpus(cpuList): print "switching cpus" diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py deleted file mode 100644 index f968aaa40..000000000 --- a/src/python/m5/objects/AlphaConsole.py +++ /dev/null @@ -1,10 +0,0 @@ -from m5.params import * -from m5.proxy import * -from Device import BasicPioDevice - -class AlphaConsole(BasicPioDevice): - type = 'AlphaConsole' - cpu = Param.BaseCPU(Parent.cpu[0], "Processor") - disk = Param.SimpleDisk("Simple Disk") - sim_console = Param.SimConsole(Parent.any, "The Simulator Console") - system = Param.AlphaSystem(Parent.any, "system object") diff --git a/src/python/m5/objects/AlphaTLB.py b/src/python/m5/objects/AlphaTLB.py deleted file mode 100644 index af7c04a84..000000000 --- a/src/python/m5/objects/AlphaTLB.py +++ /dev/null @@ -1,14 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class AlphaTLB(SimObject): - type = 'AlphaTLB' - abstract = True - size = Param.Int("TLB size") - -class AlphaDTB(AlphaTLB): - type = 'AlphaDTB' - size = 64 - -class AlphaITB(AlphaTLB): - type = 'AlphaITB' - size = 48 diff --git a/src/python/m5/objects/BadDevice.py b/src/python/m5/objects/BadDevice.py deleted file mode 100644 index 919623887..000000000 --- a/src/python/m5/objects/BadDevice.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.params import * -from Device import BasicPioDevice - -class BadDevice(BasicPioDevice): - type = 'BadDevice' - devicename = Param.String("Name of device to error on") diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py deleted file mode 100644 index 33b24ad3c..000000000 --- a/src/python/m5/objects/Bridge.py +++ /dev/null @@ -1,16 +0,0 @@ -from m5.params import * -from MemObject import MemObject - -class Bridge(MemObject): - type = 'Bridge' - side_a = Port('Side A port') - side_b = Port('Side B port') - req_size_a = Param.Int(16, "The number of requests to buffer") - req_size_b = Param.Int(16, "The number of requests to buffer") - resp_size_a = Param.Int(16, "The number of requests to buffer") - resp_size_b = Param.Int(16, "The number of requests to buffer") - delay = Param.Latency('0ns', "The latency of this bridge") - nack_delay = Param.Latency('0ns', "The latency of this bridge") - write_ack = Param.Bool(False, "Should this bridge ack writes") - fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") - fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py deleted file mode 100644 index 48dbbe307..000000000 --- a/src/python/m5/objects/Bus.py +++ /dev/null @@ -1,19 +0,0 @@ -from m5 import build_env -from m5.params import * -from m5.proxy import * -from MemObject import MemObject -from Device import BadAddr - -class Bus(MemObject): - type = 'Bus' - port = VectorPort("vector port for connecting devices") - bus_id = Param.Int(0, "blah") - clock = Param.Clock("1GHz", "bus clock speed") - width = Param.Int(64, "bus width (bytes)") - responder_set = Param.Bool(False, "Did the user specify a default responder.") - block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") - if build_env['FULL_SYSTEM']: - responder = BadAddr(pio_addr=0x0, pio_latency="1ps") - default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") - else: - default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py deleted file mode 100644 index d0ada7ee1..000000000 --- a/src/python/m5/objects/DiskImage.py +++ /dev/null @@ -1,16 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class DiskImage(SimObject): - type = 'DiskImage' - abstract = True - image_file = Param.String("disk image file") - read_only = Param.Bool(False, "read only image") - -class RawDiskImage(DiskImage): - type = 'RawDiskImage' - -class CowDiskImage(DiskImage): - type = 'CowDiskImage' - child = Param.DiskImage(RawDiskImage(read_only=True), - "child image") - table_size = Param.Int(65536, "initial table size") diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py deleted file mode 100644 index 916183bd7..000000000 --- a/src/python/m5/objects/FUPool.py +++ /dev/null @@ -1,12 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from FuncUnit import * -from FuncUnitConfig import * - -class FUPool(SimObject): - type = 'FUPool' - FUList = VectorParam.FUDesc("list of FU's for this pool") - -class DefaultFUPool(FUPool): - FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(), - WritePort(), RdWrPort(), IprPort() ] diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py deleted file mode 100644 index f0ad55f7a..000000000 --- a/src/python/m5/objects/FuncUnit.py +++ /dev/null @@ -1,18 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * - -class OpType(Enum): - vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', - 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', - 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] - -class OpDesc(SimObject): - type = 'OpDesc' - issueLat = Param.Int(1, "cycles until another can be issued") - opClass = Param.OpType("type of operation") - opLat = Param.Int(1, "cycles until result is available") - -class FUDesc(SimObject): - type = 'FUDesc' - count = Param.Int("number of these FU's available") - opList = VectorParam.OpDesc("operation classes for this FU type") diff --git a/src/python/m5/objects/FuncUnitConfig.py b/src/python/m5/objects/FuncUnitConfig.py deleted file mode 100644 index 43d7a4bb7..000000000 --- a/src/python/m5/objects/FuncUnitConfig.py +++ /dev/null @@ -1,41 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from FuncUnit import * - -class IntALU(FUDesc): - opList = [ OpDesc(opClass='IntAlu') ] - count = 6 - -class IntMultDiv(FUDesc): - opList = [ OpDesc(opClass='IntMult', opLat=3), - OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ] - count=2 - -class FP_ALU(FUDesc): - opList = [ OpDesc(opClass='FloatAdd', opLat=2), - OpDesc(opClass='FloatCmp', opLat=2), - OpDesc(opClass='FloatCvt', opLat=2) ] - count = 4 - -class FP_MultDiv(FUDesc): - opList = [ OpDesc(opClass='FloatMult', opLat=4), - OpDesc(opClass='FloatDiv', opLat=12, issueLat=12), - OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ] - count = 2 - -class ReadPort(FUDesc): - opList = [ OpDesc(opClass='MemRead') ] - count = 0 - -class WritePort(FUDesc): - opList = [ OpDesc(opClass='MemWrite') ] - count = 0 - -class RdWrPort(FUDesc): - opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] - count = 4 - -class IprPort(FUDesc): - opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ] - count = 1 - diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py deleted file mode 100644 index ef7e28785..000000000 --- a/src/python/m5/objects/Ide.py +++ /dev/null @@ -1,40 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from Pci import PciDevice, PciConfigData - -class IdeID(Enum): vals = ['master', 'slave'] - -class IdeControllerPciData(PciConfigData): - VendorID = 0x8086 - DeviceID = 0x7111 - Command = 0x0 - Status = 0x280 - Revision = 0x0 - ClassCode = 0x01 - SubClassCode = 0x01 - ProgIF = 0x85 - BAR0 = 0x00000001 - BAR1 = 0x00000001 - BAR2 = 0x00000001 - BAR3 = 0x00000001 - BAR4 = 0x00000001 - BAR5 = 0x00000001 - InterruptLine = 0x1f - InterruptPin = 0x01 - BAR0Size = '8B' - BAR1Size = '4B' - BAR2Size = '8B' - BAR3Size = '4B' - BAR4Size = '16B' - -class IdeDisk(SimObject): - type = 'IdeDisk' - delay = Param.Latency('1us', "Fixed disk delay in microseconds") - driveID = Param.IdeID('master', "Drive ID") - image = Param.DiskImage("Disk image") - -class IdeController(PciDevice): - type = 'IdeController' - disks = VectorParam.IdeDisk("IDE disks attached to this controller") - - configdata =IdeControllerPciData() diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py deleted file mode 100644 index 398ba47f9..000000000 --- a/src/python/m5/objects/IntrControl.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class IntrControl(SimObject): - type = 'IntrControl' - sys = Param.System(Parent.any, "the system we are part of") diff --git a/src/python/m5/objects/MemObject.py b/src/python/m5/objects/MemObject.py deleted file mode 100644 index 8982d553d..000000000 --- a/src/python/m5/objects/MemObject.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.SimObject import SimObject -from m5.SimObject import SimObject - -class MemObject(SimObject): - type = 'MemObject' - abstract = True diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py deleted file mode 100644 index 1219ddd4d..000000000 --- a/src/python/m5/objects/MemTest.py +++ /dev/null @@ -1,24 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5 import build_env - -class MemTest(SimObject): - type = 'MemTest' - max_loads = Param.Counter("number of loads to execute") - atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n") - memory_size = Param.Int(65536, "memory size") - percent_dest_unaligned = Param.Percent(50, - "percent of copy dest address that are unaligned") - percent_reads = Param.Percent(65, "target read percentage") - percent_source_unaligned = Param.Percent(50, - "percent of copy source address that are unaligned") - percent_functional = Param.Percent(50, "percent of access that are functional") - percent_uncacheable = Param.Percent(10, - "target uncacheable percentage") - progress_interval = Param.Counter(1000000, - "progress report interval (in accesses)") - trace_addr = Param.Addr(0, "address to trace") - - test = Port("Port to the memory system to test") - functional = Port("Port to the functional memory used for verification") diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py deleted file mode 100644 index c389e4a7f..000000000 --- a/src/python/m5/objects/PhysicalMemory.py +++ /dev/null @@ -1,30 +0,0 @@ -from m5.params import * -from m5.proxy import * -from MemObject import * - -class PhysicalMemory(MemObject): - type = 'PhysicalMemory' - port = Port("the access port") - functional = Port("Functional Access Port") - range = Param.AddrRange(AddrRange('128MB'), "Device Address") - file = Param.String('', "memory mapped file") - latency = Param.Latency('1t', "latency of an access") - zero = Param.Bool(False, "zero initialize memory") - -class DRAMMemory(PhysicalMemory): - type = 'DRAMMemory' - # Many of these should be observed from the configuration - cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed") - mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)") - mem_actpolicy = Param.String("open", "Open/Close policy") - memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct") - bus_width = Param.Int(16, "") - act_lat = Param.Int(2, "RAS to CAS delay") - cas_lat = Param.Int(1, "CAS delay") - war_lat = Param.Int(2, "write after read delay") - pre_lat = Param.Int(2, "precharge delay") - dpl_lat = Param.Int(2, "data in to precharge delay") - trc_lat = Param.Int(6, "row cycle delay") - num_banks = Param.Int(4, "Number of Banks") - num_cpus = Param.Int(4, "Number of CPUs connected to DRAM") - diff --git a/src/python/m5/objects/Platform.py b/src/python/m5/objects/Platform.py deleted file mode 100644 index ab2083eea..000000000 --- a/src/python/m5/objects/Platform.py +++ /dev/null @@ -1,7 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class Platform(SimObject): - type = 'Platform' - abstract = True - intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/src/python/m5/objects/Process.py b/src/python/m5/objects/Process.py deleted file mode 100644 index 79268e6f4..000000000 --- a/src/python/m5/objects/Process.py +++ /dev/null @@ -1,36 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class Process(SimObject): - type = 'Process' - abstract = True - output = Param.String('cout', 'filename for stdout/stderr') - system = Param.System(Parent.any, "system process will run on") - -class LiveProcess(Process): - type = 'LiveProcess' - executable = Param.String('', "executable (overrides cmd[0] if set)") - cmd = VectorParam.String("command line (executable plus arguments)") - env = VectorParam.String('', "environment settings") - cwd = Param.String('', "current working directory") - input = Param.String('cin', "filename for stdin") - uid = Param.Int(100, 'user id') - euid = Param.Int(100, 'effective user id') - gid = Param.Int(100, 'group id') - egid = Param.Int(100, 'effective group id') - pid = Param.Int(100, 'process id') - ppid = Param.Int(99, 'parent process id') - -class AlphaLiveProcess(LiveProcess): - type = 'AlphaLiveProcess' - -class SparcLiveProcess(LiveProcess): - type = 'SparcLiveProcess' - -class MipsLiveProcess(LiveProcess): - type = 'MipsLiveProcess' - -class EioProcess(Process): - type = 'EioProcess' - chkpt = Param.String('', "EIO checkpoint file name (optional)") - file = Param.String("EIO trace file name") diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py deleted file mode 100644 index 2b0e736e7..000000000 --- a/src/python/m5/objects/Root.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * - -class Root(SimObject): - type = 'Root' - dummy = Param.Int(0, "We don't support objects without params") diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py deleted file mode 100644 index dfad18eb6..000000000 --- a/src/python/m5/objects/SimConsole.py +++ /dev/null @@ -1,11 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * - -class SimConsole(SimObject): - type = 'SimConsole' - append_name = Param.Bool(True, "append name() to filename") - intr_control = Param.IntrControl(Parent.any, "interrupt controller") - port = Param.TcpPort(3456, "listen port") - number = Param.Int(0, "console number") - output = Param.String('console', "file to dump output to") diff --git a/src/python/m5/objects/SimpleDisk.py b/src/python/m5/objects/SimpleDisk.py deleted file mode 100644 index 099a77dbb..000000000 --- a/src/python/m5/objects/SimpleDisk.py +++ /dev/null @@ -1,7 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -class SimpleDisk(SimObject): - type = 'SimpleDisk' - disk = Param.DiskImage("Disk Image") - system = Param.System(Parent.any, "Sysetm Pointer") diff --git a/src/python/m5/objects/SparcTLB.py b/src/python/m5/objects/SparcTLB.py deleted file mode 100644 index 06d2a8231..000000000 --- a/src/python/m5/objects/SparcTLB.py +++ /dev/null @@ -1,14 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -class SparcTLB(SimObject): - type = 'SparcTLB' - abstract = True - size = Param.Int("TLB size") - -class SparcDTB(SparcTLB): - type = 'SparcDTB' - size = 64 - -class SparcITB(SparcTLB): - type = 'SparcITB' - size = 64 diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py deleted file mode 100644 index 810a320be..000000000 --- a/src/python/m5/objects/System.py +++ /dev/null @@ -1,68 +0,0 @@ -from m5.SimObject import SimObject -from m5.params import * -from m5.proxy import * -from m5 import build_env -from PhysicalMemory import * - -class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] - -class System(SimObject): - type = 'System' - physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") - mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") - if build_env['FULL_SYSTEM']: - boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, - "boot processor frequency") - init_param = Param.UInt64(0, "numerical value to pass into simulator") - boot_osflags = Param.String("a", "boot flags to pass to the kernel") - kernel = Param.String("", "file that contains the kernel code") - readfile = Param.String("", "file to read startup script from") - symbolfile = Param.String("", "file to get the symbols from") - -class AlphaSystem(System): - type = 'AlphaSystem' - console = Param.String("file that contains the console code") - pal = Param.String("file that contains palcode") - system_type = Param.UInt64("Type of system we are emulating") - system_rev = Param.UInt64("Revision of system we are emulating") - -class SparcSystem(System): - type = 'SparcSystem' - _rom_base = 0xfff0000000 - _nvram_base = 0x1f11000000 - _hypervisor_desc_base = 0x1f12080000 - _partition_desc_base = 0x1f12000000 - # ROM for OBP/Reset/Hypervisor - rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')), - "Memory to hold the ROM data") - # nvram - nvram = Param.PhysicalMemory( - PhysicalMemory(range = AddrRange(_nvram_base, size = '8kB')), - "Memory to hold the nvram data") - # hypervisor description - hypervisor_desc = Param.PhysicalMemory( - PhysicalMemory(range = AddrRange(_hypervisor_desc_base, size = '8kB')), - "Memory to hold the hypervisor description") - # partition description - partition_desc = Param.PhysicalMemory( - PhysicalMemory(range = AddrRange(_partition_desc_base, size = '8kB')), - "Memory to hold the partition description") - - reset_addr = Param.Addr(_rom_base, "Address to load ROM at") - hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base, - "Address to load hypervisor at") - openboot_addr = Param.Addr(Addr('512kB') + _rom_base, - "Address to load openboot at") - nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram") - hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base, - "Address for the hypervisor description") - partition_desc_addr = Param.Addr(_partition_desc_base, - "Address for the partition description") - - reset_bin = Param.String("file that contains the reset code") - hypervisor_bin = Param.String("file that contains the hypervisor code") - openboot_bin = Param.String("file that contains the openboot code") - nvram_bin = Param.String("file that contains the contents of nvram") - hypervisor_desc_bin = Param.String("file that contains the hypervisor description") - partition_desc_bin = Param.String("file that contains the partition description") - diff --git a/src/python/m5/objects/Uart.py b/src/python/m5/objects/Uart.py deleted file mode 100644 index 62062c6b1..000000000 --- a/src/python/m5/objects/Uart.py +++ /dev/null @@ -1,17 +0,0 @@ -from m5.params import * -from m5.proxy import * -from m5 import build_env -from Device import BasicPioDevice - -class Uart(BasicPioDevice): - type = 'Uart' - abstract = True - sim_console = Param.SimConsole(Parent.any, "The console") - -class Uart8250(Uart): - type = 'Uart8250' - -if build_env['ALPHA_TLASER']: - class Uart8530(Uart): - type = 'Uart8530' - diff --git a/src/python/m5/params.py b/src/python/m5/params.py index da7ddd65e..88b162874 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -348,7 +348,7 @@ class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100 class Float(ParamValue, float): - pass + cxx_type = 'double' class MemorySize(CheckedInt): cxx_type = 'uint64_t' diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc index 11141fa84..2a5f2b9fb 100644 --- a/src/python/swig/pyobject.cc +++ b/src/python/swig/pyobject.cc @@ -62,6 +62,7 @@ lookupPort(SimObject *so, const std::string &name, int i) /** * Connect the described MemObject ports. Called from Python via SWIG. + * The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports. */ int connectPorts(SimObject *o1, const std::string &name1, int i1, diff --git a/src/python/swig/sim_object.i b/src/python/swig/sim_object.i index b2af72c61..a1737c438 100644 --- a/src/python/swig/sim_object.i +++ b/src/python/swig/sim_object.i @@ -66,6 +66,7 @@ class System { private: System(); public: + SimObject::MemoryMode getMemoryMode(); void setMemoryMode(SimObject::MemoryMode mode); }; diff --git a/src/sim/Process.py b/src/sim/Process.py new file mode 100644 index 000000000..16be65fd4 --- /dev/null +++ b/src/sim/Process.py @@ -0,0 +1,51 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * + +class Process(SimObject): + type = 'Process' + abstract = True + output = Param.String('cout', 'filename for stdout/stderr') + system = Param.System(Parent.any, "system process will run on") + +class LiveProcess(Process): + type = 'LiveProcess' + executable = Param.String('', "executable (overrides cmd[0] if set)") + cmd = VectorParam.String("command line (executable plus arguments)") + env = VectorParam.String('', "environment settings") + cwd = Param.String('', "current working directory") + input = Param.String('cin', "filename for stdin") + uid = Param.Int(100, 'user id') + euid = Param.Int(100, 'effective user id') + gid = Param.Int(100, 'group id') + egid = Param.Int(100, 'effective group id') + pid = Param.Int(100, 'process id') + ppid = Param.Int(99, 'parent process id') diff --git a/src/sim/Root.py b/src/sim/Root.py new file mode 100644 index 000000000..fff998e0d --- /dev/null +++ b/src/sim/Root.py @@ -0,0 +1,34 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * + +class Root(SimObject): + type = 'Root' + dummy = Param.Int(0, "We don't support objects without params") diff --git a/src/sim/SConscript b/src/sim/SConscript index 46dc2c8dd..50f966bcf 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -30,6 +30,9 @@ Import('*') +SimObject('Root.py') +SimObject('System.py') + Source('async.cc') Source('builder.cc') Source('core.cc') @@ -50,5 +53,7 @@ Source('system.cc') if env['FULL_SYSTEM']: Source('pseudo_inst.cc') else: + SimObject('Process.py') + Source('process.cc') Source('syscall_emul.cc') diff --git a/src/sim/System.py b/src/sim/System.py new file mode 100644 index 000000000..b37e385c1 --- /dev/null +++ b/src/sim/System.py @@ -0,0 +1,48 @@ +# Copyright (c) 2005-2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * +from m5 import build_env +from PhysicalMemory import * + +class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] + +class System(SimObject): + type = 'System' + physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") + mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") + if build_env['FULL_SYSTEM']: + boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, + "boot processor frequency") + init_param = Param.UInt64(0, "numerical value to pass into simulator") + boot_osflags = Param.String("a", "boot flags to pass to the kernel") + kernel = Param.String("", "file that contains the kernel code") + readfile = Param.String("", "file to read startup script from") + symbolfile = Param.String("", "file to get the symbols from") diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index 974313968..6fbba46d5 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -293,13 +293,25 @@ class EventWrapper : public Event T *object; public: - EventWrapper(T *obj, bool del = false, EventQueue *q = &mainEventQueue, + EventWrapper(T *obj, bool del = false, + EventQueue *q = &mainEventQueue, Priority p = Default_Pri) : Event(q, p), object(obj) { if (del) setFlags(AutoDelete); } + + EventWrapper(T *obj, Tick t, bool del = false, + EventQueue *q = &mainEventQueue, + Priority p = Default_Pri) + : Event(q, p), object(obj) + { + if (del) + setFlags(AutoDelete); + schedule(t); + } + void process() { (object->*F)(); } }; diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index f56edef4a..6fe244acf 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 10 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -57,7 +57,8 @@ cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), - physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16)) + physmem = PhysicalMemory(), + membus = Bus(clock="500GHz", width=16)) # l2cache & bus system.toL2Bus = Bus(clock="500GHz", width=16) @@ -67,18 +68,12 @@ system.l2c.cpu_side = system.toL2Bus.port # connect l2c to membus system.l2c.mem_side = system.membus.port -which_port = 0 # add L1 caches for cpu in cpus: cpu.l1c = L1(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.test cpu.l1c.mem_side = system.toL2Bus.port - if which_port == 0: - system.funcmem.port = cpu.functional - which_port = 1 - else: - system.funcmem.functional = cpu.functional - + system.funcmem.port = cpu.functional # connect memory to membus system.physmem.port = system.membus.port diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 1e414294c..1ac9bd2e4 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -35,7 +35,7 @@ m5.AddToPath('../configs/common') # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -47,7 +47,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index d20a7e0c8..366a3eb0d 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -33,7 +33,7 @@ m5.AddToPath('../configs/common') class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index e8000cd0a..de0793d1c 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index a263bcf57..1fd0e8c3c 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 6c4b8232f..0ed985a17 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -32,13 +32,13 @@ from m5.objects import * class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 cpu = TimingSimpleCPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), - MyCache(size = '2MB')) + MyCache(size = '2MB', latency='10ns')) system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 7ed854f44..131095055 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -31,12 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) - -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 4859f30cf..595b1aeda 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -31,10 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = AtomicSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 0c8c3d523..47fba30ff 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -31,11 +31,51 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + + diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 9f532e3ae..999bde087 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -31,10 +31,50 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = TimingSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 2192c0d45..4de44cbb3 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out index 4c50c2a46..24d41aaa7 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 7e02db19e..21eca8681 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 74294088 # Number of BTB hits -global.BPredUnit.BTBLookups 83217138 # Number of BTB lookups -global.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 4320797 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 79655810 # Number of conditional branches predicted -global.BPredUnit.lookups 86600861 # Number of BP lookups -global.BPredUnit.usedRAS 1992384 # Number of times the RAS was used to get a target. -host_inst_rate 121760 # Simulator instruction rate (inst/s) -host_mem_usage 154560 # Number of bytes of host memory used -host_seconds 4644.82 # Real time elapsed on the host -host_tick_rate 28265671 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20253948 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 12668807 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 134508955 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 44216516 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 65796417 # Number of BTB hits +global.BPredUnit.BTBLookups 73152793 # Number of BTB lookups +global.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 4224786 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 70143727 # Number of conditional branches predicted +global.BPredUnit.lookups 75959317 # Number of BP lookups +global.BPredUnit.usedRAS 1707904 # Number of times the RAS was used to get a target. +host_inst_rate 95235 # Simulator instruction rate (inst/s) +host_mem_usage 154544 # Number of bytes of host memory used +host_seconds 5938.47 # Real time elapsed on the host +host_tick_rate 31305923 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 11533351 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 9283325 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 125815870 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 42503953 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.131289 # Number of seconds simulated -sim_ticks 131288904500 # Number of ticks simulated +sim_seconds 0.185909 # Number of seconds simulated +sim_ticks 185909249000 # Number of ticks simulated system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 25836005 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 21750592 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 248547939 +system.cpu.commit.COM:committed_per_cycle.samples 363164843 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 64112537 2579.48% - 1 73997996 2977.21% - 2 29649485 1192.91% - 3 7413919 298.29% - 4 16299890 655.80% - 5 20436719 822.24% - 6 3362671 135.29% - 7 7438717 299.29% - 8 25836005 1039.48% + 0 150226418 4136.59% + 1 99566964 2741.65% + 2 34056070 937.76% + 3 10333475 284.54% + 4 20301573 559.02% + 5 15829471 435.88% + 6 8882909 244.60% + 7 2217371 61.06% + 8 21750592 598.92% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 115049510 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4320164 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4224164 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 94497449 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 52370845 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.464286 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.464286 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 115538611 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2723.249468 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2089.628248 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114910502 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1710497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005436 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 628109 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 403470 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 469412000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 224639 # number of ReadReq MSHR misses +system.cpu.cpi 0.657443 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.657443 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 115591547 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3246.088003 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2434.144734 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 115095381 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1610598500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004292 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 496166 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 273177 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 542787500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001929 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 222989 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3076.718619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2314.396461 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38683248 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2363144500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.019469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 768073 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 511246 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 594399500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.006510 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 256827 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 539.249147 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 250 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 319.012661 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 1172 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 632000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 1000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 3474.707454 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2824.359825 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38691611 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2639770000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.019257 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 759710 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 502007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 727846000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006532 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 257703 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 427.272727 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 0 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 319.928337 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 1210 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 517000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154989932 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2917.701274 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency -system.cpu.dcache.demand_hits 153593750 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4073642000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.009008 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1396182 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 914716 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1063811500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003106 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 481466 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 155042868 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3384.385481 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency +system.cpu.dcache.demand_hits 153786992 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4250368500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008100 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1255876 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 775184 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1270633500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003100 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 480692 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 154989932 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2917.701274 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2209.525699 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 155042868 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3384.385481 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2643.342307 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 153593750 # number of overall hits -system.cpu.dcache.overall_miss_latency 4073642000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.009008 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1396182 # number of overall misses -system.cpu.dcache.overall_mshr_hits 914716 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1063811500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003106 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 481466 # number of overall MSHR misses +system.cpu.dcache.overall_hits 153786992 # number of overall hits +system.cpu.dcache.overall_miss_latency 4250368500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008100 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1255876 # number of overall misses +system.cpu.dcache.overall_mshr_hits 775184 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1270633500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003100 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 480692 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 477370 # number of replacements -system.cpu.dcache.sampled_refs 481466 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 476596 # number of replacements +system.cpu.dcache.sampled_refs 480692 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.510322 # Cycle average of tags in use -system.cpu.dcache.total_refs 153593750 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 24474000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 338333 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 34835558 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 676 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4837262 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 747469994 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 87926948 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 115162373 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 14029871 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2002 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 10623061 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 86600861 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 72219408 # Number of cache lines fetched -system.cpu.fetch.Cycles 200341434 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 435 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 760297798 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4883794 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.329810 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 72219408 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 76286472 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.895514 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4095.610639 # Cycle average of tags in use +system.cpu.dcache.total_refs 153786992 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 28323000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 338024 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 44010110 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 636 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3910489 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 686828869 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 203536444 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 106139742 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8653682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1958 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 9478548 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 75959317 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65390933 # Number of cache lines fetched +system.cpu.fetch.Cycles 182129217 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2901518 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 693889852 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4411999 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.204291 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65390933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 67504321 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.866206 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 262577811 +system.cpu.fetch.rateDist.samples 371818526 system.cpu.fetch.rateDist.min_value 0 - 0 134455787 5120.61% - 1 11289278 429.94% - 2 12199345 464.60% - 3 11605085 441.97% - 4 7894720 300.66% - 5 3823699 145.62% - 6 3913283 149.03% - 7 3555410 135.40% - 8 73841204 2812.16% + 0 255080243 6860.34% + 1 9944321 267.45% + 2 12043396 323.91% + 3 10077209 271.02% + 4 7005486 188.41% + 5 3160802 85.01% + 6 3551742 95.52% + 7 3151910 84.77% + 8 67803417 1823.56% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 72219408 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4241.833509 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3311.810155 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 72218459 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4025500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 949 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 3000500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 906 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 65390933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5347.983454 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4573.991031 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65389966 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 5171500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 967 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4080000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 892 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 79711.323400 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 73307.136771 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 72219408 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4241.833509 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency -system.cpu.icache.demand_hits 72218459 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4025500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses -system.cpu.icache.demand_misses 949 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 3000500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 906 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 65390933 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5347.983454 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency +system.cpu.icache.demand_hits 65389966 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 5171500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000015 # miss rate for demand accesses +system.cpu.icache.demand_misses 967 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4080000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 892 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 72219408 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4241.833509 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3311.810155 # average overall mshr miss latency +system.cpu.icache.overall_accesses 65390933 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5347.983454 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4573.991031 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 72218459 # number of overall hits -system.cpu.icache.overall_miss_latency 4025500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses -system.cpu.icache.overall_misses 949 # number of overall misses -system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 3000500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 906 # number of overall MSHR misses +system.cpu.icache.overall_hits 65389966 # number of overall hits +system.cpu.icache.overall_miss_latency 5171500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000015 # miss rate for overall accesses +system.cpu.icache.overall_misses 967 # number of overall misses +system.cpu.icache.overall_mshr_hits 75 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4080000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 892 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,63 +215,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.sampled_refs 906 # Sample count of references to valid blocks. +system.cpu.icache.replacements 33 # number of replacements +system.cpu.icache.sampled_refs 892 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 774.513861 # Cycle average of tags in use -system.cpu.icache.total_refs 72218459 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 761.711791 # Cycle average of tags in use +system.cpu.icache.total_refs 65389966 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 69153659 # Number of branches executed -system.cpu.iew.EXEC:nop 45896023 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.341699 # Inst execution rate -system.cpu.iew.EXEC:refs 168426251 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41748280 # Number of stores executed +system.cpu.idleCycles 2468 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67136036 # Number of branches executed +system.cpu.iew.EXEC:nop 41949449 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.608660 # Inst execution rate +system.cpu.iew.EXEC:refs 164353457 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41112797 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 525987328 # num instructions consuming a value -system.cpu.iew.WB:count 611675009 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.792003 # average fanout of values written-back +system.cpu.iew.WB:consumers 478961290 # num instructions consuming a value +system.cpu.iew.WB:count 594114153 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.812310 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 416583352 # num instructions producing a value -system.cpu.iew.WB:rate 2.329500 # insts written-back per cycle -system.cpu.iew.WB:sent 613682130 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4878985 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 11826 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 134508955 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2507193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 44216516 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 696353635 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 126677971 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11034988 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 614878076 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 389064913 # num instructions producing a value +system.cpu.iew.WB:rate 1.597861 # insts written-back per cycle +system.cpu.iew.WB:sent 594699658 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4485637 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10981 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 125815870 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6586227 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 42503953 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 654225210 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 123240660 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4346710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 598129643 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 518 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 14029871 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 4036 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8653682 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4417 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 4056 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10594878 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 23131 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 2615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 7105932 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 1847 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 1076564 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5809 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 19459445 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4403993 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 1076564 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 574744 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4304241 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 2.153847 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.153847 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 625913064 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 296430 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5860 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 10766360 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2691430 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 296430 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 519296 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3966341 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.521044 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.521044 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 602476353 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 452893161 72.36% # Type of FU issued - IntMult 6537 0.00% # Type of FU issued + IntAlu 435905994 72.35% # Type of FU issued + IntMult 6492 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 27 0.00% # Type of FU issued FloatCmp 5 0.00% # Type of FU issued @@ -279,17 +279,17 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 4 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 130507417 20.85% # Type of FU issued - MemWrite 42505908 6.79% # Type of FU issued + MemRead 124769613 20.71% # Type of FU issued + MemWrite 41794213 6.94% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 6267821 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010014 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 3485464 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005785 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 5230779 83.45% # attempts to use FU when none available - IntMult 183 0.00% # attempts to use FU when none available + IntAlu 2980889 85.52% # attempts to use FU when none available + IntMult 104 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available FloatCmp 0 0.00% # attempts to use FU when none available @@ -297,80 +297,80 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 663118 10.58% # attempts to use FU when none available - MemWrite 373741 5.96% # attempts to use FU when none available + MemRead 331227 9.50% # attempts to use FU when none available + MemWrite 173244 4.97% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 262577811 +system.cpu.iq.ISSUE:issued_per_cycle.samples 371818526 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 49543053 1886.80% - 1 42653619 1624.42% - 2 65996372 2513.40% - 3 28722982 1093.88% - 4 36210264 1379.03% - 5 20379063 776.12% - 6 16095665 612.99% - 7 2026950 77.19% - 8 949843 36.17% + 0 125625601 3378.68% + 1 89616652 2410.23% + 2 55904072 1503.53% + 3 46310572 1245.52% + 4 27240019 732.62% + 5 12675210 340.90% + 6 11517465 309.76% + 7 2752555 74.03% + 8 176380 4.74% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.383724 # Inst issue rate -system.cpu.iq.iqInstsAdded 650457589 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 625913064 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 83477196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 265708 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 44589775 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 482372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5974.559204 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2202.761362 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 456056 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 157226500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.054555 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 26316 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 57967868 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054555 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 26316 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 338333 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 338333 # number of Writeback hits +system.cpu.iq.ISSUE:rate 1.620351 # Inst issue rate +system.cpu.iq.iqInstsAdded 612275739 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 602476353 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 42659982 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 2623 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 21979774 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 481584 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 6174.721472 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2416.099471 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 455285 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 162389000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.054609 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 26299 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 63541000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054609 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 26299 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 338024 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 338024 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 30.186541 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 30.164987 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 482372 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5974.559204 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 456056 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 157226500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.054555 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 26316 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 481584 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 6174.721472 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 455285 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 162389000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.054609 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 26299 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 57967868 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.054555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 26316 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 63541000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.054609 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 26299 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 820705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5974.559204 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2202.761362 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 819608 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 6174.721472 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2416.099471 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 794389 # number of overall hits -system.cpu.l2cache.overall_miss_latency 157226500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.032065 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 26316 # number of overall misses +system.cpu.l2cache.overall_hits 793309 # number of overall hits +system.cpu.l2cache.overall_miss_latency 162389000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.032087 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 26299 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 57967868 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.032065 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 26316 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 63541000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.032087 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 26299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -382,31 +382,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 932 # number of replacements -system.cpu.l2cache.sampled_refs 26316 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 931 # number of replacements +system.cpu.l2cache.sampled_refs 26299 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 25073.756706 # Cycle average of tags in use -system.cpu.l2cache.total_refs 794389 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 25071.267749 # Cycle average of tags in use +system.cpu.l2cache.total_refs 793309 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 904 # number of writebacks -system.cpu.numCycles 262577811 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2682297 # Number of cycles rename is blocking +system.cpu.numCycles 371818526 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 11517489 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 30243185 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 96498295 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1942834 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 952429183 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 727912324 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 552445892 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 117213862 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 14029871 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32153216 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 88591003 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 50706382 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.timesIdled 3 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 32462126 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 206624315 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 21712 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 889109667 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 674900294 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 515718683 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 111518348 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8653682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 33504424 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 51863794 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 268 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 59569309 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.timesIdled 32 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini index 27aeb9034..e7acc71a6 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out index a8a9148d5..589507187 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt index 7c260dd71..5453dc099 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 964119 # Simulator instruction rate (inst/s) -host_mem_usage 148524 # Number of bytes of host memory used -host_seconds 624.26 # Real time elapsed on the host -host_tick_rate 482059313 # Simulator tick rate (ticks/s) +host_inst_rate 963880 # Simulator instruction rate (inst/s) +host_mem_usage 148548 # Number of bytes of host memory used +host_seconds 624.41 # Real time elapsed on the host +host_tick_rate 481939681 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated sim_seconds 0.300928 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini index f70ed5de3..f82815f7b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out index d4c1bde6e..5cab10662 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index 5fbf59915..9d4ab211d 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 642291 # Simulator instruction rate (inst/s) -host_mem_usage 153996 # Number of bytes of host memory used -host_seconds 937.05 # Real time elapsed on the host -host_tick_rate 404322160 # Simulator tick rate (ticks/s) +host_inst_rate 494073 # Simulator instruction rate (inst/s) +host_mem_usage 153964 # Number of bytes of host memory used +host_seconds 1218.16 # Real time elapsed on the host +host_tick_rate 624626994 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856965 # Number of instructions simulated -sim_seconds 0.378869 # Number of seconds simulated -sim_ticks 378869140000 # Number of ticks simulated +sim_seconds 0.760893 # Number of seconds simulated +sim_ticks 760892614000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2584.255983 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1584.255983 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12040.967639 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11040.967639 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 520035000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2423028000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 318803000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2221796000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2608.788455 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1608.788455 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12166.766996 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11166.766996 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 39197158 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 663057500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3092342000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.006442 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 254163 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 408894500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2838179000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.006442 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 254163 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2597.947935 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12111.178208 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency system.cpu.dcache.demand_hits 153509968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1183092500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5515370000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002958 # miss rate for demand accesses system.cpu.dcache.demand_misses 455395 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 727697500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5059975000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2597.947935 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1597.947935 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12111.178208 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11111.178208 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 153509968 # number of overall hits -system.cpu.dcache.overall_miss_latency 1183092500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5515370000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002958 # miss rate for overall accesses system.cpu.dcache.overall_misses 455395 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 727697500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5059975000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 451299 # number of replacements system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.423304 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.250869 # Cycle average of tags in use system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 102411000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 257148000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 325723 # number of writebacks system.cpu.icache.ReadReq_accesses 601856966 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3746.540881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2746.540881 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13969.811321 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12969.811321 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 601856171 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 2978500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 11106000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2183500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10311000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 601856966 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3746.540881 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13969.811321 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency system.cpu.icache.demand_hits 601856171 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 2978500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 11106000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 795 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2183500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10311000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 601856966 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3746.540881 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2746.540881 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13969.811321 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12969.811321 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 601856171 # number of overall hits -system.cpu.icache.overall_miss_latency 2978500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 11106000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 795 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2183500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10311000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 24 # number of replacements system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 674.110982 # Cycle average of tags in use +system.cpu.icache.tagsinuse 673.943506 # Cycle average of tags in use system.cpu.icache.total_refs 601856171 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 456190 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2564.564334 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1563.181738 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 430092 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 66930000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 339274000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.057209 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 26098 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 40795917 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 287078000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.057209 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 26098 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2564.564334 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 430092 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 66930000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 339274000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.057209 # miss rate for demand accesses system.cpu.l2cache.demand_misses 26098 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 40795917 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 287078000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.057209 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 26098 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 781913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2564.564334 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1563.181738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 755815 # number of overall hits -system.cpu.l2cache.overall_miss_latency 66930000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 339274000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.033377 # miss rate for overall accesses system.cpu.l2cache.overall_misses 26098 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 40795917 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 287078000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.033377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 26098 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 903 # number of replacements system.cpu.l2cache.sampled_refs 26098 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24878.910085 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24875.090462 # Cycle average of tags in use system.cpu.l2cache.total_refs 755815 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 883 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 378869140000 # number of cpu cycles simulated +system.cpu.numCycles 760892614000 # number of cpu cycles simulated system.cpu.num_insts 601856965 # Number of instructions executed system.cpu.num_refs 154862034 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini index 0a5320e76..144c9c7fe 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out index 24b104442..9c608a7e6 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt index c58a162a3..bdafc8603 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 687229 # Simulator instruction rate (inst/s) -host_mem_usage 149588 # Number of bytes of host memory used -host_seconds 2167.42 # Real time elapsed on the host -host_tick_rate 343614381 # Simulator tick rate (ticks/s) +host_inst_rate 723585 # Simulator instruction rate (inst/s) +host_mem_usage 149576 # Number of bytes of host memory used +host_seconds 2058.52 # Real time elapsed on the host +host_tick_rate 361792205 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514860 # Number of instructions simulated sim_seconds 0.744757 # Number of seconds simulated diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout index bf28090fa..b335083d4 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout @@ -36,8 +36,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 14:35:40 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 13:02:33 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-atomic tests/run.py long/00.gzip/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini index 52243641a..ad1db1010 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out index bcc607b12..d8a055b90 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 5a976b1e5..fc8b89b1e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 510352 # Simulator instruction rate (inst/s) -host_mem_usage 155048 # Number of bytes of host memory used -host_seconds 2918.60 # Real time elapsed on the host -host_tick_rate 353062922 # Simulator tick rate (ticks/s) +host_inst_rate 529254 # Simulator instruction rate (inst/s) +host_mem_usage 154916 # Number of bytes of host memory used +host_seconds 2814.36 # Real time elapsed on the host +host_tick_rate 733354350 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514860 # Number of instructions simulated -sim_seconds 1.030450 # Number of seconds simulated -sim_ticks 1030449926500 # Number of ticks simulated +sim_seconds 2.063927 # Number of seconds simulated +sim_ticks 2063926516000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 402511688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2729.300186 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1729.300186 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12044.273310 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11044.273310 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 402318208 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 528065000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2330326000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 193480 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 334585000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2136846000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 193480 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3071.428571 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2071.428571 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 12285.714286 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11285.714286 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 21500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 86000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 14500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 79000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166846642 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2724.587576 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1724.587576 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12168.472925 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11168.472925 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 166586897 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 707698000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3160700000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 259745 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 447953000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2900955000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 259745 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 569358330 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2726.599371 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12115.452590 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency system.cpu.dcache.demand_hits 568905105 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1235763000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 5491026000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses system.cpu.dcache.demand_misses 453225 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 782538000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5037801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 453225 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 569358330 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2726.599371 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1726.599371 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12115.452590 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11115.452590 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 568905105 # number of overall hits -system.cpu.dcache.overall_miss_latency 1235763000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 5491026000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses system.cpu.dcache.overall_misses 453225 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 782538000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5037801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 453225 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 449136 # number of replacements system.cpu.dcache.sampled_refs 453232 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.694265 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.630445 # Cycle average of tags in use system.cpu.dcache.total_refs 568906424 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 112631000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 274426000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 316447 # number of writebacks system.cpu.icache.ReadReq_accesses 1489514861 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3687.613843 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2687.613843 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13859.744991 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12859.744991 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1489513763 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 4049000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 15218000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 1098 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2951000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 14120000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 1098 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1489514861 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3687.613843 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13859.744991 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency system.cpu.icache.demand_hits 1489513763 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 4049000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 15218000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 1098 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2951000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 14120000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 1098 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1489514861 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3687.613843 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2687.613843 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13859.744991 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12859.744991 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1489513763 # number of overall hits -system.cpu.icache.overall_miss_latency 4049000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 15218000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 1098 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2951000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 14120000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 1098 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 115 # number of replacements system.cpu.icache.sampled_refs 1098 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 891.763656 # Cycle average of tags in use +system.cpu.icache.tagsinuse 891.684170 # Cycle average of tags in use system.cpu.icache.total_refs 1489513763 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 454330 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2631.120103 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1629.899651 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 427145 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 71527000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 353405000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.059835 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 27185 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44308822 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 299035000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.059835 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 27185 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 316447 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 454330 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2631.120103 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 427145 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 71527000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 353405000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.059835 # miss rate for demand accesses system.cpu.l2cache.demand_misses 27185 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 44308822 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 299035000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.059835 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 27185 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 770777 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2630.249320 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1629.899651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12995.697580 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 743583 # number of overall hits -system.cpu.l2cache.overall_miss_latency 71527000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 353405000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.035281 # miss rate for overall accesses system.cpu.l2cache.overall_misses 27194 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 44308822 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 299035000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.035270 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 27185 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2632 # number of replacements system.cpu.l2cache.sampled_refs 27185 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 24268.399126 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 24267.041661 # Cycle average of tags in use system.cpu.l2cache.total_refs 743583 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 2531 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1030449926500 # number of cpu cycles simulated +system.cpu.numCycles 2063926516000 # number of cpu cycles simulated system.cpu.num_insts 1489514860 # Number of instructions executed system.cpu.num_refs 569359656 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout index 6f0bc150a..3741c6499 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout @@ -36,9 +36,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 14:35:40 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 13:36:53 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1030449926500 because target called exit() +Exiting @ tick 2063926516000 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini index 368feb9a9..9b8d69888 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out index 24228b2bd..8a5c9fd62 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt index 7e603ae8c..530572b5d 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 658093 # Simulator instruction rate (inst/s) -host_mem_usage 149896 # Number of bytes of host memory used -host_seconds 2613.00 # Real time elapsed on the host -host_tick_rate 329046277 # Simulator tick rate (ticks/s) +host_inst_rate 686638 # Simulator instruction rate (inst/s) +host_mem_usage 149820 # Number of bytes of host memory used +host_seconds 2504.37 # Real time elapsed on the host +host_tick_rate 343319148 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1719594534 # Number of instructions simulated sim_seconds 0.859797 # Number of seconds simulated diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout index f52ad5eac..bd861b307 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout @@ -25,8 +25,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 15:11:49 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 14:23:47 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-atomic tests/run.py long/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini index 6e102e359..9beb527ea 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out index 970fa6992..5d5cc71c1 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index 988dc8a7f..c95331047 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 462859 # Simulator instruction rate (inst/s) -host_mem_usage 155288 # Number of bytes of host memory used -host_seconds 3715.16 # Real time elapsed on the host -host_tick_rate 345995852 # Simulator tick rate (ticks/s) +host_inst_rate 480485 # Simulator instruction rate (inst/s) +host_mem_usage 155316 # Number of bytes of host memory used +host_seconds 3578.87 # Real time elapsed on the host +host_tick_rate 745845171 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1719594534 # Number of instructions simulated -sim_seconds 1.285430 # Number of seconds simulated -sim_ticks 1285429818500 # Number of ticks simulated +sim_seconds 2.669285 # Number of seconds simulated +sim_ticks 2669284585000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 607807189 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3129.930590 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2129.930590 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12893.226605 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11893.226605 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 594739458 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 40901091000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 168485217000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.021500 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 13067731 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 27833360000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 155417486000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.021500 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 13067731 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15448 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3090.909091 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2090.909091 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 13090.909091 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 12090.909091 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15437 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 34000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 144000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000712 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 11 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 23000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 133000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000712 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 11 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166970997 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2764.531806 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1764.531806 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12404.292450 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11404.292450 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 165264000 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4719047500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 21174090000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010223 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1706997 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3012050500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 19467093000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010223 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1706997 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 774778186 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3087.714271 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12836.737637 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency system.cpu.dcache.demand_hits 760003458 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 45620138500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 189659307000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.019070 # miss rate for demand accesses system.cpu.dcache.demand_misses 14774728 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 30845410500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 174884579000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.019070 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 14774728 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 774778186 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3087.714271 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2087.714271 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12836.737637 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11836.737637 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 760003458 # number of overall hits -system.cpu.dcache.overall_miss_latency 45620138500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 189659307000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.019070 # miss rate for overall accesses system.cpu.dcache.overall_misses 14774728 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 30845410500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 174884579000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.019070 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 14774728 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 14770643 # number of replacements system.cpu.dcache.sampled_refs 14774739 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.607725 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4094.628585 # Cycle average of tags in use system.cpu.dcache.total_refs 760018895 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1932183000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 3913237000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 4191356 # number of writebacks system.cpu.icache.ReadReq_accesses 1719594535 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3753.607103 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2753.607103 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13991.120977 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12991.120977 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1719593634 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3382000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 12606000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 901 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2481000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11705000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1719594535 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3753.607103 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13991.120977 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency system.cpu.icache.demand_hits 1719593634 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3382000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 12606000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses system.cpu.icache.demand_misses 901 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2481000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11705000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1719594535 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3753.607103 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2753.607103 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13991.120977 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12991.120977 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1719593634 # number of overall hits -system.cpu.icache.overall_miss_latency 3382000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 12606000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses system.cpu.icache.overall_misses 901 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2481000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11705000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 31 # number of replacements system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 737.434314 # Cycle average of tags in use +system.cpu.icache.tagsinuse 737.715884 # Cycle average of tags in use system.cpu.icache.total_refs 1719593634 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 14775639 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2607.028468 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1605.780536 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.785859 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.785859 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8592784 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 16118879000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 80375791000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.418449 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 6182855 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9928308213 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 68010081000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.418449 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 6182855 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 4191356 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 14775639 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2607.028468 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.785859 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8592784 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16118879000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 80375791000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.418449 # miss rate for demand accesses system.cpu.l2cache.demand_misses 6182855 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9928308213 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 68010081000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.418449 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 6182855 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 18966995 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2595.599252 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1605.780536 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12942.794779 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.785859 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 12756915 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16118879000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 80375791000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.327415 # miss rate for overall accesses system.cpu.l2cache.overall_misses 6210080 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9928308213 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 68010081000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.325980 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 6182855 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 6150087 # number of replacements system.cpu.l2cache.sampled_refs 6182855 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26097.875810 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 26129.060966 # Cycle average of tags in use system.cpu.l2cache.total_refs 12756915 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 390549075000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 806915893000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1069081 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1285429818500 # number of cpu cycles simulated +system.cpu.numCycles 2669284585000 # number of cpu cycles simulated system.cpu.num_insts 1719594534 # Number of instructions executed system.cpu.num_refs 774793634 # Number of memory references system.cpu.workload.PROG:num_syscalls 632 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout index d1c7d6062..272fc2ce1 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout @@ -25,9 +25,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 15:24:20 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 15:05:32 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1285429818500 because target called exit() +Exiting @ tick 2669284585000 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index 29e352b0e..af33f850b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out index c04c0d11b..cea0c0402 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index ce046cea7..f3f9842a2 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 38358431 # Number of BTB hits -global.BPredUnit.BTBLookups 50162851 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1146 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 6112182 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 38942362 # Number of conditional branches predicted -global.BPredUnit.lookups 68824046 # Number of BP lookups -global.BPredUnit.usedRAS 14094584 # Number of times the RAS was used to get a target. -host_inst_rate 88313 # Simulator instruction rate (inst/s) -host_mem_usage 157144 # Number of bytes of host memory used -host_seconds 4252.75 # Real time elapsed on the host -host_tick_rate 26084457 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 79078987 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 58020753 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 131723270 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 96432918 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 36408912 # Number of BTB hits +global.BPredUnit.BTBLookups 43706931 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1105 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 5391565 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 33884568 # Number of conditional branches predicted +global.BPredUnit.lookups 59377619 # Number of BP lookups +global.BPredUnit.usedRAS 11768977 # Number of times the RAS was used to get a target. +host_inst_rate 72337 # Simulator instruction rate (inst/s) +host_mem_usage 157124 # Number of bytes of host memory used +host_seconds 5192.02 # Real time elapsed on the host +host_tick_rate 28301038 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 55015552 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 43012918 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 120933927 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 90962569 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 375574812 # Number of instructions simulated -sim_seconds 0.110931 # Number of seconds simulated -sim_ticks 110930737500 # Number of ticks simulated -system.cpu.commit.COM:branches 44587533 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 15191652 # number cycles where commit BW limit reached +sim_insts 375574819 # Number of instructions simulated +sim_seconds 0.146939 # Number of seconds simulated +sim_ticks 146939447000 # Number of ticks simulated +system.cpu.commit.COM:branches 44587532 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 12019969 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 203296876 +system.cpu.commit.COM:committed_per_cycle.samples 280687503 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 83055980 4085.45% - 1 37801777 1859.44% - 2 20090473 988.23% - 3 18525905 911.27% - 4 11216575 551.73% - 5 8853752 435.51% - 6 5489461 270.02% - 7 3071301 151.07% - 8 15191652 747.26% + 0 153383398 5464.56% + 1 43042738 1533.48% + 2 19983570 711.95% + 3 20747693 739.17% + 4 12078292 430.31% + 5 11042042 393.39% + 6 5000100 178.14% + 7 3389701 120.76% + 8 12019969 428.23% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 398664587 # Number of instructions committed +system.cpu.commit.COM:count 398664594 # Number of instructions committed system.cpu.commit.COM:loads 100651995 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 6107953 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 398664587 # The number of committed instructions +system.cpu.commit.branchMispredicts 5387368 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 122897297 # The number of squashed insts skipped by commit -system.cpu.committedInsts 375574812 # Number of Instructions Simulated -system.cpu.committedInsts_total 375574812 # Number of Instructions Simulated -system.cpu.cpi 0.590725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.590725 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 96817111 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4478.552279 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3669.007021 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 96815619 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 6682000 # number of ReadReq miss cycles +system.cpu.commit.commitSquashedInsts 80492961 # The number of squashed insts skipped by commit +system.cpu.committedInsts 375574819 # Number of Instructions Simulated +system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated +system.cpu.cpi 0.782478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.782478 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 96341397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5402.232747 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4689.672802 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 96339919 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 7984500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000015 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1492 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 495 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3658000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1478 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 4586500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 997 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 978 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4580.037179 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3751.017852 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73511046 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 44348500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000132 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 9683 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6490 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 11977000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 5858.789942 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4984.052533 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73511622 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 53356000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000124 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 9107 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5909 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 15939000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3193 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 3198 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40650.755370 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40673.261734 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 170337840 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4566.487696 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency -system.cpu.dcache.demand_hits 170326665 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 51030500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000066 # miss rate for demand accesses -system.cpu.dcache.demand_misses 11175 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6985 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 15635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 169862126 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5795.040151 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169851541 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 61340500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000062 # miss rate for demand accesses +system.cpu.dcache.demand_misses 10585 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6409 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 20525500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4190 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 170337840 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4566.487696 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3731.503580 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 169862126 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5795.040151 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4915.110153 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 170326665 # number of overall hits -system.cpu.dcache.overall_miss_latency 51030500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000066 # miss rate for overall accesses -system.cpu.dcache.overall_misses 11175 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6985 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 15635000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 169851541 # number of overall hits +system.cpu.dcache.overall_miss_latency 61340500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000062 # miss rate for overall accesses +system.cpu.dcache.overall_misses 10585 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6409 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 20525500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4190 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 787 # number of replacements -system.cpu.dcache.sampled_refs 4190 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 781 # number of replacements +system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3304.118717 # Cycle average of tags in use -system.cpu.dcache.total_refs 170326665 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3294.483088 # Cycle average of tags in use +system.cpu.dcache.total_refs 169851541 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 642 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 19129336 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4391 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 12122968 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 582055742 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 80258799 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 100428895 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 18564601 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12469 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 3479847 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 68824046 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 70113587 # Number of cache lines fetched -system.cpu.fetch.Cycles 177754526 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1413 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 605291130 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6551564 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.310212 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 70113587 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 52453015 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.728239 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 637 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 7091571 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4262 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 10528111 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 508290393 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 182764130 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 90473414 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 13191511 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 12840 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 358389 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 59377619 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 61063139 # Number of cache lines fetched +system.cpu.fetch.Cycles 154416855 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 2298760 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 522129068 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 5723447 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.202048 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 61063139 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 48177889 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.776680 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 221861478 +system.cpu.fetch.rateDist.samples 293879015 system.cpu.fetch.rateDist.min_value 0 - 0 114220541 5148.28% - 1 8239331 371.37% - 2 8549373 385.35% - 3 6969058 314.12% - 4 16046109 723.25% - 5 8875051 400.03% - 6 9195050 414.45% - 7 2819832 127.10% - 8 46947133 2116.06% + 0 200525300 6823.40% + 1 7846897 267.01% + 2 7291722 248.12% + 3 6200462 210.99% + 4 13845529 471.13% + 5 7438768 253.12% + 6 7492914 254.97% + 7 2335483 79.47% + 8 40901940 1391.80% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 70113587 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3851.773227 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2889.186432 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 70109583 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15422500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000057 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4004 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 83 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11328500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000056 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3921 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 61063139 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5151.654640 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4230.492813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 61059120 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 20704500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4019 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 16482000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 17880.536343 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 15672.258727 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 70113587 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3851.773227 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency -system.cpu.icache.demand_hits 70109583 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15422500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000057 # miss rate for demand accesses -system.cpu.icache.demand_misses 4004 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 83 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11328500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000056 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3921 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 61063139 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5151.654640 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency +system.cpu.icache.demand_hits 61059120 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 20704500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000066 # miss rate for demand accesses +system.cpu.icache.demand_misses 4019 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 16482000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 70113587 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3851.773227 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2889.186432 # average overall mshr miss latency +system.cpu.icache.overall_accesses 61063139 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5151.654640 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4230.492813 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 70109583 # number of overall hits -system.cpu.icache.overall_miss_latency 15422500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000057 # miss rate for overall accesses -system.cpu.icache.overall_misses 4004 # number of overall misses -system.cpu.icache.overall_mshr_hits 83 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11328500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000056 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3921 # number of overall MSHR misses +system.cpu.icache.overall_hits 61059120 # number of overall hits +system.cpu.icache.overall_miss_latency 20704500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000066 # miss rate for overall accesses +system.cpu.icache.overall_misses 4019 # number of overall misses +system.cpu.icache.overall_mshr_hits 123 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 16482000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 1998 # number of replacements -system.cpu.icache.sampled_refs 3921 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1976 # number of replacements +system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1828.295849 # Cycle average of tags in use -system.cpu.icache.total_refs 70109583 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1822.947356 # Cycle average of tags in use +system.cpu.icache.total_refs 61059120 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles -2 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 52992725 # Number of branches executed -system.cpu.iew.EXEC:nop 29946505 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.944645 # Inst execution rate -system.cpu.iew.EXEC:refs 194719104 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 80042784 # Number of stores executed +system.cpu.idleCycles 6367 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 50329288 # Number of branches executed +system.cpu.iew.EXEC:nop 26718868 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.409679 # Inst execution rate +system.cpu.iew.EXEC:refs 190324589 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 79889528 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 297392817 # num instructions consuming a value -system.cpu.iew.WB:count 427980775 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.704330 # average fanout of values written-back +system.cpu.iew.WB:consumers 266244037 # num instructions consuming a value +system.cpu.iew.WB:count 411128901 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.717332 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 209462789 # num instructions producing a value -system.cpu.iew.WB:rate 1.929045 # insts written-back per cycle -system.cpu.iew.WB:sent 430386834 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6770153 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2285856 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 131723270 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 248 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6165269 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 96432918 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 521561792 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 114676320 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 13198323 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 431441879 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 131901 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 190985280 # num instructions producing a value +system.cpu.iew.WB:rate 1.398973 # insts written-back per cycle +system.cpu.iew.WB:sent 411485990 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6032644 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1137801 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 120933927 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 222 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6771454 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 90962569 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 479157588 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 110435061 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10298797 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 414275208 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 25295 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 18564601 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 554549 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 21083 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 13191511 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 115109 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 10646448 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 56371 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 7097511 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 3223 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 636490 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 215134 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 31071275 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 22901516 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 636490 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1000963 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5769190 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.692835 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.692835 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 444640202 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 404889 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176320 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 20281932 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 17431167 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 404889 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 802823 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5229821 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.277991 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.277991 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 424574005 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 33581 0.01% # Type of FU issued - IntAlu 177043734 39.82% # Type of FU issued - IntMult 2204532 0.50% # Type of FU issued + IntAlu 163144501 38.43% # Type of FU issued + IntMult 2125088 0.50% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 36105087 8.12% # Type of FU issued - FloatCmp 7997969 1.80% # Type of FU issued - FloatCvt 3013999 0.68% # Type of FU issued - FloatMult 17176525 3.86% # Type of FU issued - FloatDiv 1578480 0.36% # Type of FU issued + FloatAdd 34659405 8.16% # Type of FU issued + FloatCmp 7790033 1.83% # Type of FU issued + FloatCvt 2881594 0.68% # Type of FU issued + FloatMult 16618307 3.91% # Type of FU issued + FloatDiv 1566111 0.37% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 116850777 26.28% # Type of FU issued - MemWrite 82635518 18.58% # Type of FU issued + MemRead 113765764 26.80% # Type of FU issued + MemWrite 81989621 19.31% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 12556872 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.028241 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 9576176 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.022555 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 57761 0.46% # attempts to use FU when none available + IntAlu 12415 0.13% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 28133 0.22% # attempts to use FU when none available - FloatCmp 21849 0.17% # attempts to use FU when none available - FloatCvt 3461 0.03% # attempts to use FU when none available - FloatMult 3478872 27.70% # attempts to use FU when none available - FloatDiv 916669 7.30% # attempts to use FU when none available + FloatAdd 46832 0.49% # attempts to use FU when none available + FloatCmp 11338 0.12% # attempts to use FU when none available + FloatCvt 25702 0.27% # attempts to use FU when none available + FloatMult 2984764 31.17% # attempts to use FU when none available + FloatDiv 331535 3.46% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 6621449 52.73% # attempts to use FU when none available - MemWrite 1428678 11.38% # attempts to use FU when none available + MemRead 4942933 51.62% # attempts to use FU when none available + MemWrite 1220657 12.75% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 221861478 +system.cpu.iq.ISSUE:issued_per_cycle.samples 293879015 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 66879354 3014.46% - 1 37689855 1698.80% - 2 36617552 1650.47% - 3 29239458 1317.92% - 4 27293259 1230.19% - 5 13755301 620.00% - 6 5789291 260.94% - 7 3467682 156.30% - 8 1129726 50.92% + 0 129735390 4414.59% + 1 52072154 1771.89% + 2 39787134 1353.86% + 3 29621395 1007.95% + 4 21763636 740.56% + 5 12600620 428.77% + 6 4911147 167.11% + 7 2561440 87.16% + 8 826099 28.11% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.004134 # Inst issue rate -system.cpu.iq.iqInstsAdded 491615039 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 444640202 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 248 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 114649126 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1134366 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 83844967 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 8108 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3327.551159 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1909.064236 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 729 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 24554000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.910089 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7379 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 14086985 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7379 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 642 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 642 # number of Writeback hits +system.cpu.iq.ISSUE:rate 1.444724 # Inst issue rate +system.cpu.iq.iqInstsAdded 452438498 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 424574005 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 222 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 75756994 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1109878 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 55099010 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4677.770224 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2436.233855 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 715 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 34405000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.911400 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7355 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 17918500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911400 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7355 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 637 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 637 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.185798 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.183821 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8108 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3327.551159 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 729 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 24554000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.910089 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7379 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4677.770224 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 715 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 34405000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.911400 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7355 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14086985 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.910089 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7379 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.911400 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7355 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8750 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3327.551159 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1909.064236 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4677.770224 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2436.233855 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1371 # number of overall hits -system.cpu.l2cache.overall_miss_latency 24554000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.843314 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7379 # number of overall misses +system.cpu.l2cache.overall_hits 1352 # number of overall hits +system.cpu.l2cache.overall_miss_latency 34405000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.844723 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7355 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14086985 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.843314 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7379 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.844723 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7355 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,30 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7379 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7355 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6669.459869 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1371 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 6644.823451 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1352 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 221861478 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 6569281 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 259532333 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1971772 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 86889182 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 8681438 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 731270765 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 559458182 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 360795698 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 96896401 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 18564601 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 12635219 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 101263365 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 306794 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37801 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 32486829 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 267 # count of temporary serializing insts renamed -system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.numCycles 293879015 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 3715266 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 115195 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 185747540 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2602652 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 654991501 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 496454048 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 320284080 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 87805227 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 13191511 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 3048084 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 60751739 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 371387 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37057 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 7965999 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 243 # count of temporary serializing insts renamed +system.cpu.timesIdled 133 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout index 68b00def4..50ed34325 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.100000 +OO-style eon Time= 0.133333 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini index ba3b61431..58022eaf1 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out index de3317258..b7319250f 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt index 3892be109..2e2beec40 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 844104 # Simulator instruction rate (inst/s) +host_inst_rate 828868 # Simulator instruction rate (inst/s) host_mem_usage 151076 # Number of bytes of host memory used -host_seconds 472.29 # Real time elapsed on the host -host_tick_rate 422051705 # Simulator tick rate (ticks/s) +host_seconds 480.97 # Real time elapsed on the host +host_tick_rate 414433819 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664597 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini index bc260bf15..ca3706b7b 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out index 0a9655414..c3af4f4b3 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 552adff15..28c7cc183 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,65 +1,65 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 557007 # Simulator instruction rate (inst/s) -host_mem_usage 156576 # Number of bytes of host memory used -host_seconds 715.73 # Real time elapsed on the host -host_tick_rate 396092779 # Simulator tick rate (ticks/s) +host_inst_rate 579996 # Simulator instruction rate (inst/s) +host_mem_usage 156556 # Number of bytes of host memory used +host_seconds 687.36 # Real time elapsed on the host +host_tick_rate 824955659 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 398664597 # Number of instructions simulated -sim_seconds 0.283494 # Number of seconds simulated -sim_ticks 283494379000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 94754489 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3630.526316 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2630.526316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 94753539 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3449000 # number of ReadReq miss cycles +sim_insts 398664611 # Number of instructions simulated +sim_seconds 0.567040 # Number of seconds simulated +sim_ticks 567040254000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13741.052632 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 13054000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2499000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 12104000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3618.988132 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2618.988132 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517527 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11588000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 13962.523423 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12962.523423 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 44708000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 8386000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 41506000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40527.713391 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 168275218 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3621.628131 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168271066 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15037000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13911.849711 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 57762000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10885000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 53610000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 168275218 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3621.628131 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2621.628131 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13911.849711 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12911.849711 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168271066 # number of overall hits -system.cpu.dcache.overall_miss_latency 15037000 # number of overall miss cycles +system.cpu.dcache.overall_hits 168271068 # number of overall hits +system.cpu.dcache.overall_miss_latency 57762000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_misses 4152 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10885000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 53610000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,52 +76,52 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 764 # number of replacements system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3289.772430 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271066 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3289.654807 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks -system.cpu.icache.ReadReq_accesses 398664598 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3633.814321 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2633.814321 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 398660925 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13347000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 398664612 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 13745.167438 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12745.167438 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 398660939 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 50486000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 9674000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 46813000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 108538.231691 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 108538.235502 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 398664598 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3633.814321 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency -system.cpu.icache.demand_hits 398660925 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13347000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 398664612 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 13745.167438 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency +system.cpu.icache.demand_hits 398660939 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 50486000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9674000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 46813000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 398664598 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3633.814321 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2633.814321 # average overall mshr miss latency +system.cpu.icache.overall_accesses 398664612 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 13745.167438 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12745.167438 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 398660925 # number of overall hits -system.cpu.icache.overall_miss_latency 13347000 # number of overall miss cycles +system.cpu.icache.overall_hits 398660939 # number of overall hits +system.cpu.icache.overall_miss_latency 50486000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_misses 3673 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9674000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 46813000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1769 # number of replacements system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1795.510184 # Cycle average of tags in use -system.cpu.icache.total_refs 398660925 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1795.458615 # Cycle average of tags in use +system.cpu.icache.total_refs 398660939 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 7825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2707.276275 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1705.023697 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19422000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 93262000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.916805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 7174 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12231840 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 78914000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 7174 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2707.276275 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19422000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 93262000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.916805 # miss rate for demand accesses system.cpu.l2cache.demand_misses 7174 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12231840 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 78914000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.916805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 7174 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 8450 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2707.276275 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1705.023697 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1276 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19422000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 93262000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.848994 # miss rate for overall accesses system.cpu.l2cache.overall_misses 7174 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12231840 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 78914000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.848994 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 7174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,14 +203,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 7174 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6483.699084 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 6483.455048 # Cycle average of tags in use system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 283494379000 # number of cpu cycles simulated -system.cpu.num_insts 398664597 # Number of instructions executed -system.cpu.num_refs 174183399 # Number of memory references +system.cpu.numCycles 567040254000 # number of cpu cycles simulated +system.cpu.num_insts 398664611 # Number of instructions executed +system.cpu.num_refs 174183401 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout index 1e8a0ac6f..f9d497506 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout @@ -1,2 +1,2 @@ Eon, Version 1.1 -OO-style eon Time= 0.283333 +OO-style eon Time= 0.566667 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index dc1116a7e..1b858fca2 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out index ef449bf6d..0e4ea1cb5 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt index 5fa1b5726..0f58a9003 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 855453 # Simulator instruction rate (inst/s) -host_mem_usage 151192 # Number of bytes of host memory used -host_seconds 2348.45 # Real time elapsed on the host -host_tick_rate 427726617 # Simulator tick rate (ticks/s) +host_inst_rate 855891 # Simulator instruction rate (inst/s) +host_mem_usage 151228 # Number of bytes of host memory used +host_seconds 2347.25 # Real time elapsed on the host +host_tick_rate 427945543 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987607 # Number of instructions simulated sim_seconds 1.004494 # Number of seconds simulated diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 6f1f78d48..dd36bbf60 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out index 1c3b86ae3..676b65128 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index afc2c695a..6aa1ee5aa 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 594701 # Simulator instruction rate (inst/s) -host_mem_usage 156660 # Number of bytes of host memory used -host_seconds 3378.14 # Real time elapsed on the host -host_tick_rate 405574512 # Simulator tick rate (ticks/s) +host_inst_rate 622738 # Simulator instruction rate (inst/s) +host_mem_usage 156744 # Number of bytes of host memory used +host_seconds 3226.05 # Real time elapsed on the host +host_tick_rate 852686846 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987607 # Number of instructions simulated -sim_seconds 1.370090 # Number of seconds simulated -sim_ticks 1370089513500 # Number of ticks simulated +sim_seconds 2.750814 # Number of seconds simulated +sim_ticks 2750814393000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3511.656558 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2511.656558 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13971.031250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12971.031250 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5120669500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 20372446000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3662477500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 18914254000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3914.581944 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2914.581944 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13873.860351 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12873.860351 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 281662000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 998252000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 209710000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 926300000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3530.603329 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13966.461980 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5402331500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 21370698000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3872187500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 19840554000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3530.603329 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2530.603329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13966.461980 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12966.461980 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 720334778 # number of overall hits -system.cpu.dcache.overall_miss_latency 5402331500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 21370698000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_misses 1530144 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3872187500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 19840554000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 1526048 # number of replacements system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.457388 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.422371 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 325153000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 702832000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2952.765194 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1952.765194 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12448.659872 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11448.659872 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 31287500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 131906000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 20691500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 121310000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2952.765194 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12448.659872 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 31287500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 131906000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 20691500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 121310000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2952.765194 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1952.765194 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12448.659872 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11448.659872 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2008977012 # number of overall hits -system.cpu.icache.overall_miss_latency 31287500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 131906000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses system.cpu.icache.overall_misses 10596 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 20691500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 121310000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9046 # number of replacements system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1478.638648 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.610505 # Cycle average of tags in use system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2545.120588 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1544.109658 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3835145500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19589206000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2326760167 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 16575482000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2545.120588 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3835145500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 19589206000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2326760167 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 16575482000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2543.307872 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1544.109658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12990.740986 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 107393 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3835145500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 19589206000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses system.cpu.l2cache.overall_misses 1507936 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2326760167 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 16575482000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 1474094 # number of replacements system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32754.836517 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32753.638584 # Cycle average of tags in use system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 1084960000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 2394479000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66804 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1370089513500 # number of cpu cycles simulated +system.cpu.numCycles 2750814393000 # number of cpu cycles simulated system.cpu.num_insts 2008987607 # Number of instructions executed system.cpu.num_refs 722390435 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 6aa726853..8c32bfa79 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out index e22560975..071b401c0 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index 91b29d8d9..bf6f402cd 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 7744324 # Number of BTB hits -global.BPredUnit.BTBLookups 13591046 # Number of BTB lookups -global.BPredUnit.RASInCorrect 32932 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 452723 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10077718 # Number of conditional branches predicted -global.BPredUnit.lookups 15489897 # Number of BP lookups -global.BPredUnit.usedRAS 1844517 # Number of times the RAS was used to get a target. -host_inst_rate 108228 # Simulator instruction rate (inst/s) -host_mem_usage 159488 # Number of bytes of host memory used -host_seconds 735.41 # Real time elapsed on the host -host_tick_rate 23792996 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 12942665 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 11520420 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 21780362 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 15866784 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 7411086 # Number of BTB hits +global.BPredUnit.BTBLookups 13158968 # Number of BTB lookups +global.BPredUnit.RASInCorrect 32147 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 450892 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 9746581 # Number of conditional branches predicted +global.BPredUnit.lookups 14988034 # Number of BP lookups +global.BPredUnit.usedRAS 1776543 # Number of times the RAS was used to get a target. +host_inst_rate 99683 # Simulator instruction rate (inst/s) +host_mem_usage 159476 # Number of bytes of host memory used +host_seconds 798.45 # Real time elapsed on the host +host_tick_rate 35303213 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 9747985 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 9298064 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 21418262 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 15459606 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.017498 # Number of seconds simulated -sim_ticks 17497602000 # Number of ticks simulated +sim_seconds 0.028188 # Number of seconds simulated +sim_ticks 28187684500 # Number of ticks simulated system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 4260073 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3230574 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 33996100 +system.cpu.commit.COM:committed_per_cycle.samples 55590975 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 8358440 2458.65% - 1 8230566 2421.03% - 2 4712162 1386.09% - 3 3108634 914.41% - 4 2121957 624.18% - 5 1131901 332.95% - 6 1374606 404.34% - 7 697761 205.25% - 8 4260073 1253.11% + 0 26501535 4767.24% + 1 10970497 1973.43% + 2 5466463 983.34% + 3 3506601 630.79% + 4 2372940 426.86% + 5 1558557 280.36% + 6 1098347 197.58% + 7 885461 159.28% + 8 3230574 581.13% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20379399 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 356682 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 355366 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 6565781 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4551161 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.439684 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.439684 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 19603173 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4020.633151 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2686.323277 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19458721 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 580788500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007369 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 144452 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 82734 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 165794500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003148 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61718 # number of ReadReq MSHR misses +system.cpu.cpi 0.708309 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.708309 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 20049834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 4729.134904 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3349.390829 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19907503 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 673102500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007099 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 142331 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 80854 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 205910500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003066 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61477 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2642.114676 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3379.334983 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13777457 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2208596500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.057202 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 835920 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 692465 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 484782500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009817 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143455 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 3029.723364 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4119.889460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14053363 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1696687500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.038322 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 560014 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 416536 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 591113500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143478 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 161.990993 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.699134 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34216550 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2845.231198 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33236178 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 2789385000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.028652 # miss rate for demand accesses -system.cpu.dcache.demand_misses 980372 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 775199 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 650577000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005996 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 205173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 34663211 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3374.111014 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33960866 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2369790000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020262 # miss rate for demand accesses +system.cpu.dcache.demand_misses 702345 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 497390 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 797024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005913 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 204955 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34216550 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2845.231198 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3170.870436 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 34663211 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3374.111014 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3888.775585 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33236178 # number of overall hits -system.cpu.dcache.overall_miss_latency 2789385000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.028652 # miss rate for overall accesses -system.cpu.dcache.overall_misses 980372 # number of overall misses -system.cpu.dcache.overall_mshr_hits 775199 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 650577000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005996 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 205173 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33960866 # number of overall hits +system.cpu.dcache.overall_miss_latency 2369790000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020262 # miss rate for overall accesses +system.cpu.dcache.overall_misses 702345 # number of overall misses +system.cpu.dcache.overall_mshr_hits 497390 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 797024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005913 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 204955 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 201077 # number of replacements -system.cpu.dcache.sampled_refs 205173 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200859 # number of replacements +system.cpu.dcache.sampled_refs 204955 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4079.993551 # Cycle average of tags in use -system.cpu.dcache.total_refs 33236178 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 90338000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147781 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1516721 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 98391 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3463978 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 98144908 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 14320248 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 17547399 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 999107 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 287801 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 611733 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 15489897 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 12778073 # Number of cache lines fetched -system.cpu.fetch.Cycles 31147667 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 14471 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 99913909 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 465674 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.442629 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 12778073 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9588841 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.855074 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4080.110580 # Cycle average of tags in use +system.cpu.dcache.total_refs 33960866 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 144827000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147753 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 583473 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 97307 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3380270 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 95203508 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37386702 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 17614461 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 784542 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 292514 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 6340 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 14988034 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 12416477 # Number of cache lines fetched +system.cpu.fetch.Cycles 30119953 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 260035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 96279919 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 467393 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.265861 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 12416477 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 9187629 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.707832 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 34995208 +system.cpu.fetch.rateDist.samples 56375518 system.cpu.fetch.rateDist.min_value 0 - 0 16625619 4750.83% - 1 1365816 390.29% - 2 1258616 359.65% - 3 1410956 403.19% - 4 3900976 1114.72% - 5 1678758 479.71% - 6 612174 174.93% - 7 1011089 288.92% - 8 7131204 2037.77% + 0 38672046 6859.72% + 1 1321940 234.49% + 2 1201428 213.11% + 3 1338454 237.42% + 4 3789980 672.27% + 5 1624217 288.11% + 6 592859 105.16% + 7 975150 172.97% + 8 6859444 1216.74% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 12778073 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2888.242687 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1894.538715 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 12690553 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 252779000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006849 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 87520 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 654 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 164571000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006798 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 86866 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 12416477 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3477.694454 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2488.876340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 12330467 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 299116500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006927 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 86010 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1011 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 211552000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006846 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 84999 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 146.093443 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 145.066024 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 12778073 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2888.242687 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency -system.cpu.icache.demand_hits 12690553 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 252779000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006849 # miss rate for demand accesses -system.cpu.icache.demand_misses 87520 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 654 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 164571000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006798 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 86866 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 12416477 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3477.694454 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency +system.cpu.icache.demand_hits 12330467 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 299116500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006927 # miss rate for demand accesses +system.cpu.icache.demand_misses 86010 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1011 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 211552000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006846 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 84999 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 12778073 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2888.242687 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1894.538715 # average overall mshr miss latency +system.cpu.icache.overall_accesses 12416477 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3477.694454 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2488.876340 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 12690553 # number of overall hits -system.cpu.icache.overall_miss_latency 252779000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006849 # miss rate for overall accesses -system.cpu.icache.overall_misses 87520 # number of overall misses -system.cpu.icache.overall_mshr_hits 654 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 164571000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006798 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 86866 # number of overall MSHR misses +system.cpu.icache.overall_hits 12330467 # number of overall hits +system.cpu.icache.overall_miss_latency 299116500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006927 # miss rate for overall accesses +system.cpu.icache.overall_misses 86010 # number of overall misses +system.cpu.icache.overall_mshr_hits 1011 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 211552000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006846 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 84999 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,80 +215,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 84818 # number of replacements -system.cpu.icache.sampled_refs 86866 # Sample count of references to valid blocks. +system.cpu.icache.replacements 82951 # number of replacements +system.cpu.icache.sampled_refs 84999 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1921.828467 # Cycle average of tags in use -system.cpu.icache.total_refs 12690553 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 15230287000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 1918.432617 # Cycle average of tags in use +system.cpu.icache.total_refs 12330467 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 24669337000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 6484 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14304724 # Number of branches executed -system.cpu.iew.EXEC:nop 9152219 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.363053 # Inst execution rate -system.cpu.iew.EXEC:refs 36160680 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15116998 # Number of stores executed +system.cpu.idleCycles 25301 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14196900 # Number of branches executed +system.cpu.iew.EXEC:nop 9006488 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.455602 # Inst execution rate +system.cpu.iew.EXEC:refs 36045074 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15052480 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 43283574 # num instructions consuming a value -system.cpu.iew.WB:count 82548148 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757836 # average fanout of values written-back +system.cpu.iew.WB:consumers 39431808 # num instructions consuming a value +system.cpu.iew.WB:count 81784655 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.769564 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32801872 # num instructions producing a value -system.cpu.iew.WB:rate 2.358841 # insts written-back per cycle -system.cpu.iew.WB:sent 82621578 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 398195 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 20355 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 21780362 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 4681 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 352010 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 15866784 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 94903979 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21043682 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 752566 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 82695525 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 5889 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 30345313 # num instructions producing a value +system.cpu.iew.WB:rate 1.450712 # insts written-back per cycle +system.cpu.iew.WB:sent 81828309 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 387091 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 10156 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 21418262 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 4652 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 597409 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 15459606 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 92891480 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 20992594 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 333391 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 82060341 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 141 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 132 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 999107 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 7135 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 784542 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 478 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1325562 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2239 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 828061 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 554 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16849 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1491 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1400963 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1022165 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16849 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 105190 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 293005 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 2.274362 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.274362 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 83448091 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 19340 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1425 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1038863 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 614987 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19340 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 103732 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 283359 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.411814 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.411814 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 82393732 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 46687810 55.95% # Type of FU issued - IntMult 45238 0.05% # Type of FU issued + IntAlu 45892607 55.70% # Type of FU issued + IntMult 44107 0.05% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 120004 0.14% # Type of FU issued + FloatAdd 116900 0.14% # Type of FU issued FloatCmp 87 0.00% # Type of FU issued - FloatCvt 122290 0.15% # Type of FU issued + FloatCvt 120453 0.15% # Type of FU issued FloatMult 50 0.00% # Type of FU issued - FloatDiv 37770 0.05% # Type of FU issued + FloatDiv 37768 0.05% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 21206489 25.41% # Type of FU issued - MemWrite 15228353 18.25% # Type of FU issued + MemRead 21065064 25.57% # Type of FU issued + MemWrite 15116696 18.35% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 1422206 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017043 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 898002 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010899 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 169452 11.91% # attempts to use FU when none available + IntAlu 168043 18.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 649726 45.68% # attempts to use FU when none available - MemWrite 603028 42.40% # attempts to use FU when none available + MemRead 309725 34.49% # attempts to use FU when none available + MemWrite 420234 46.80% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 34995208 +system.cpu.iq.ISSUE:issued_per_cycle.samples 56375518 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 5876071 1679.11% - 1 8518834 2434.29% - 2 6419045 1834.26% - 3 4436708 1267.80% - 4 4423684 1264.08% - 5 2554091 729.84% - 6 1512126 432.10% - 7 794096 226.92% - 8 460553 131.60% + 0 22612550 4011.06% + 1 13769796 2442.51% + 2 7834961 1389.78% + 3 4029672 714.79% + 4 3712649 658.56% + 5 1993297 353.57% + 6 1449259 257.07% + 7 434309 77.04% + 8 539025 95.61% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.384558 # Inst issue rate -system.cpu.iq.iqInstsAdded 85747079 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 83448091 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 4681 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 5951026 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 23998 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 98 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4012087 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 291992 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3325.548649 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1922.235296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 122257 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 564462000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.581300 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 169735 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 326270608 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.581300 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 169735 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147781 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147317 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 1.461516 # Inst issue rate +system.cpu.iq.iqInstsAdded 83880340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 82393732 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 4652 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4104955 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 35761 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 69 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2730801 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 289883 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4226.385671 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2218.670959 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 120272 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 716841500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.585102 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 169611 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 376311000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.585102 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 169611 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147292 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.003120 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 461 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.003120 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 461 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.588205 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.577516 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 291992 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3325.548649 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 122257 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 564462000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.581300 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 169735 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 289883 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4226.385671 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 120272 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 716841500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.585102 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 169611 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 326270608 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.581300 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 169735 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 376311000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.585102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 169611 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 439773 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3316.482471 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1922.235296 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 437636 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4214.929559 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2218.670959 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 269574 # number of overall hits -system.cpu.l2cache.overall_miss_latency 564462000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.387016 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 170199 # number of overall misses +system.cpu.l2cache.overall_hits 267564 # number of overall hits +system.cpu.l2cache.overall_miss_latency 716841500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.388615 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 170072 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 326270608 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.385960 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 169735 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 376311000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.387562 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 169611 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,31 +386,31 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 136967 # number of replacements -system.cpu.l2cache.sampled_refs 169735 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 136843 # number of replacements +system.cpu.l2cache.sampled_refs 169611 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32064.700481 # Cycle average of tags in use -system.cpu.l2cache.total_refs 269574 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 8508988000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115938 # number of writebacks -system.cpu.numCycles 34995208 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 201241 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 32058.525051 # Cycle average of tags in use +system.cpu.l2cache.total_refs 267564 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 13792867000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115936 # number of writebacks +system.cpu.numCycles 56375518 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 238131 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31178 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 14721876 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1110145 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 117085470 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 96973574 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 58152082 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 17754494 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 999107 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1242602 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 5605201 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 75888 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 4701 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2792735 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 4699 # count of temporary serializing insts renamed -system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31030 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 37626801 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 240022 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 113729051 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 94390828 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 56605918 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 17378620 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 784542 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 281505 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4059037 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 65919 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 4656 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 641192 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 4654 # count of temporary serializing insts renamed +system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index 57d9578d2..5339d79af 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out index fbb08bf4b..bf2c5c795 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt index 8a03d8929..16fb6367e 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 842354 # Simulator instruction rate (inst/s) -host_mem_usage 152996 # Number of bytes of host memory used -host_seconds 104.87 # Real time elapsed on the host -host_tick_rate 421175511 # Simulator tick rate (ticks/s) +host_inst_rate 840697 # Simulator instruction rate (inst/s) +host_mem_usage 152968 # Number of bytes of host memory used +host_seconds 105.08 # Real time elapsed on the host +host_tick_rate 420346781 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated sim_seconds 0.044170 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini index 2f49c7692..4c8661842 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out index c1faaa3e6..c0cb264bc 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 939083267..107c46644 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 562157 # Simulator instruction rate (inst/s) -host_mem_usage 158620 # Number of bytes of host memory used -host_seconds 157.15 # Real time elapsed on the host -host_tick_rate 396922606 # Simulator tick rate (ticks/s) +host_inst_rate 585395 # Simulator instruction rate (inst/s) +host_mem_usage 158604 # Number of bytes of host memory used +host_seconds 150.91 # Real time elapsed on the host +host_tick_rate 839295251 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated -sim_seconds 0.062375 # Number of seconds simulated -sim_ticks 62374966500 # Number of ticks simulated +sim_seconds 0.126657 # Number of seconds simulated +sim_ticks 126656575000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3130.058422 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2130.058422 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12987.854851 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11987.854851 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 190198000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 789207000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 129433000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 728442000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3436.431765 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2436.431765 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13826.199000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12826.199000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 493396000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1985138000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 349818000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1841560000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3345.326241 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13576.902561 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 683594000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2774345000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 479251000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2570002000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3345.326241 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2345.326241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13576.902561 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12576.902561 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34685672 # number of overall hits -system.cpu.dcache.overall_miss_latency 683594000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2774345000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_misses 204343 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 479251000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2570002000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 200247 # number of replacements system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4082.118898 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4081.697925 # Cycle average of tags in use system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 307192000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 661090000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2831.355644 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1831.355644 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12197.393898 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11197.393898 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 216417500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 932320000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 139981500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 855884000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2831.355644 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12197.393898 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 216417500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 932320000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 139981500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 855884000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2831.355644 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1831.355644 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12197.393898 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11197.393898 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 88264239 # number of overall hits -system.cpu.icache.overall_miss_latency 216417500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 932320000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 139981500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 855884000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 74391 # number of replacements system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1880.010701 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1878.885583 # Cycle average of tags in use system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2532.769537 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1531.091909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.768790 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.768790 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 427222500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 2192775000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 258261521 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1855419000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2532.769537 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.768790 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 427222500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2192775000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 258261521 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1855419000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2526.209820 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1531.091909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12966.100192 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.768790 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 259377 # number of overall hits -system.cpu.l2cache.overall_miss_latency 427222500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2192775000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses system.cpu.l2cache.overall_misses 169116 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 258261521 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1855419000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 135910 # number of replacements system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32002.173981 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31979.717205 # Cycle average of tags in use system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 30452104000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 61925078000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 115911 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 62374966500 # number of cpu cycles simulated +system.cpu.numCycles 126656575000 # number of cpu cycles simulated system.cpu.num_insts 88340674 # Number of instructions executed system.cpu.num_refs 35224019 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 7932bf16f..da377104f 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out index b69343874..4d97fe26f 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt index 37d044e8d..9dd2e7465 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 644632 # Simulator instruction rate (inst/s) -host_mem_usage 151548 # Number of bytes of host memory used -host_seconds 211.36 # Real time elapsed on the host -host_tick_rate 322315545 # Simulator tick rate (ticks/s) +host_inst_rate 672762 # Simulator instruction rate (inst/s) +host_mem_usage 151516 # Number of bytes of host memory used +host_seconds 202.52 # Real time elapsed on the host +host_tick_rate 336380340 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated sim_seconds 0.068123 # Number of seconds simulated diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout index 794510e19..13addb638 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 15:55:23 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:40:43 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-atomic tests/run.py long/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini index 1bc14e993..ff1b40886 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out index cb469d872..c2fb507ae 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 4e8db9778..bf74220de 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 466766 # Simulator instruction rate (inst/s) -host_mem_usage 157052 # Number of bytes of host memory used -host_seconds 291.90 # Real time elapsed on the host -host_tick_rate 335938336 # Simulator tick rate (ticks/s) +host_inst_rate 480067 # Simulator instruction rate (inst/s) +host_mem_usage 157016 # Number of bytes of host memory used +host_seconds 283.81 # Real time elapsed on the host +host_tick_rate 698858124 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136246936 # Number of instructions simulated -sim_seconds 0.098059 # Number of seconds simulated -sim_ticks 98059078500 # Number of ticks simulated +sim_seconds 0.198342 # Number of seconds simulated +sim_ticks 198341876000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3241.706786 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2241.706786 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13005.210051 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12005.210051 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 37185812 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 147462000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 591594000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 45489 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 101973000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 546105000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 45489 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3166.666667 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2166.666667 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 12800 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11800 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 47500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 192000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000942 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 32500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 177000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000942 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 15 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3588.938331 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2588.938331 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13928.024036 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12928.024036 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 20759130 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 377463000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1464866000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.005041 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 105174 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 272289000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1359692000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.005041 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 105174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3484.100277 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13649.402972 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency system.cpu.dcache.demand_hits 57944942 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 524925000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2056460000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002593 # miss rate for demand accesses system.cpu.dcache.demand_misses 150663 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 374262000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1905797000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3484.100277 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2484.100277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13649.402972 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12649.402972 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 57944942 # number of overall hits -system.cpu.dcache.overall_miss_latency 524925000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2056460000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_misses 150663 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 374262000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1905797000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 146582 # number of replacements system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4090.058697 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4089.719370 # Cycle average of tags in use system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 224414000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 500116000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107279 # number of writebacks system.cpu.icache.ReadReq_accesses 136246937 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2800.327765 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1800.327765 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12107.905937 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11107.905937 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 136059913 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 523728500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2264469000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.001373 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 336704500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2077445000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.001373 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 136246937 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2800.327765 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12107.905937 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency system.cpu.icache.demand_hits 136059913 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 523728500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2264469000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.001373 # miss rate for demand accesses system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 336704500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2077445000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.001373 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 136246937 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2800.327765 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1800.327765 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12107.905937 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11107.905937 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 136059913 # number of overall hits -system.cpu.icache.overall_miss_latency 523728500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2264469000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.001373 # miss rate for overall accesses system.cpu.icache.overall_misses 187024 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 336704500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2077445000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.001373 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 184976 # number of replacements system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 2008.440865 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2007.901723 # Cycle average of tags in use system.cpu.icache.total_refs 136059913 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 69827484000 # Cycle when the warmup percentage was hit. +system.cpu.icache.warmup_cycle 141263674000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 337636 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2644.770157 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1643.366085 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12999.502521 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10999.502521 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 202957 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 356195000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1750760000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.398888 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 134679 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 221326901 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 1481402000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.398888 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 134679 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 107279 # number of Writeback accesses(hits+misses) @@ -178,29 +178,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 337636 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2644.770157 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12999.502521 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency system.cpu.l2cache.demand_hits 202957 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 356195000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1750760000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.398888 # miss rate for demand accesses system.cpu.l2cache.demand_misses 134679 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 221326901 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1481402000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.398888 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 134679 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 444915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2634.831752 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1643.366085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12950.653539 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10999.502521 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 309728 # number of overall hits -system.cpu.l2cache.overall_miss_latency 356195000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1750760000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.303849 # miss rate for overall accesses system.cpu.l2cache.overall_misses 135187 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 221326901 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1481402000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.302707 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 134679 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -217,12 +217,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 101911 # number of replacements system.cpu.l2cache.sampled_refs 134679 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32141.182824 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32127.015431 # Cycle average of tags in use system.cpu.l2cache.total_refs 309728 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 20627583000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 41711518000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 82918 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 98059078500 # number of cpu cycles simulated +system.cpu.numCycles 198341876000 # number of cpu cycles simulated system.cpu.num_insts 136246936 # Number of instructions executed system.cpu.num_refs 58111522 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout index 08ec05c3a..c635e0e4b 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 15:58:57 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:44:06 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 98059078500 because target called exit() +Exiting @ tick 198341876000 because target called exit() diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 9e383ca33..105e8c6e2 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out index 4a5aeccf1..ea4848b9b 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 227b79a7b..dccb62bee 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 264221270 # Number of BTB hits -global.BPredUnit.BTBLookups 273071573 # Number of BTB lookups -global.BPredUnit.RASInCorrect 122 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 19541079 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 228439261 # Number of conditional branches predicted -global.BPredUnit.lookups 295748685 # Number of BP lookups -global.BPredUnit.usedRAS 20371548 # Number of times the RAS was used to get a target. -host_inst_rate 108663 # Simulator instruction rate (inst/s) -host_mem_usage 154628 # Number of bytes of host memory used -host_seconds 15976.47 # Real time elapsed on the host -host_tick_rate 25821276 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 80477635 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 37646176 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 533254174 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 186471924 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 236329759 # Number of BTB hits +global.BPredUnit.BTBLookups 244099867 # Number of BTB lookups +global.BPredUnit.RASInCorrect 116 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 19342549 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 203388054 # Number of conditional branches predicted +global.BPredUnit.lookups 265702680 # Number of BP lookups +global.BPredUnit.usedRAS 19620183 # Number of times the RAS was used to get a target. +host_inst_rate 104740 # Simulator instruction rate (inst/s) +host_mem_usage 154596 # Number of bytes of host memory used +host_seconds 16574.74 # Real time elapsed on the host +host_tick_rate 38540500 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 53067106 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 26767467 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 497279728 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 174034666 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.412533 # Number of seconds simulated -sim_ticks 412532848500 # Number of ticks simulated +sim_seconds 0.638799 # Number of seconds simulated +sim_ticks 638798750000 # Number of ticks simulated system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 78248119 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 60317471 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 772086758 +system.cpu.commit.COM:committed_per_cycle.samples 1240430038 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 242551958 3141.51% - 1 161050324 2085.91% - 2 101638189 1316.41% - 3 63812257 826.49% - 4 43982002 569.65% - 5 37612088 487.15% - 6 28299494 366.53% - 7 14892327 192.88% - 8 78248119 1013.46% + 0 616961832 4973.77% + 1 236071207 1903.14% + 2 130159070 1049.31% + 3 77572840 625.37% + 4 40072787 323.06% + 5 42334502 341.29% + 6 22413470 180.69% + 7 14526859 117.11% + 8 60317471 486.26% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 445666361 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 606571343 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 19540581 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19342064 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 358953852 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 213160886 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.475256 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.475256 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 463286594 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3710.591477 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2550.415742 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 454594407 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 32253155000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.018762 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 8692187 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1395111 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 18610577500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.015751 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7297076 # number of ReadReq MSHR misses +system.cpu.cpi 0.735925 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.735925 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 460303357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3955.169300 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2868.381634 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 451791924 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 33664158500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.018491 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 8511433 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1219244 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 20916781000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.015842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7292189 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 6275.157749 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8072.319138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 157494886 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 20291450500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.020118 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3233616 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1350145 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 15203979000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011718 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1883471 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs 1064.957356 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets 500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 66.672421 # Average number of references to valid blocks. -system.cpu.dcache.blocked_no_mshrs 75157 # number of cycles access was blocked -system.cpu.dcache.blocked_no_targets 5468 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_mshrs 80039000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles_no_targets 2734000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 6699.535635 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 8433.632873 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 157310932 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 22896132000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.021263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 3417570 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1533904 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 15886147500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1883666 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs 1092.259997 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 571.397227 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 66.381046 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 62416 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 56970 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 68174500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 32552500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 624015096 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4405.959540 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency -system.cpu.dcache.demand_hits 612089293 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 52544605500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.019111 # miss rate for demand accesses -system.cpu.dcache.demand_misses 11925803 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2745256 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33814556500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.014712 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9180547 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 621031859 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4741.409697 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency +system.cpu.dcache.demand_hits 609102856 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 56560290500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.019208 # miss rate for demand accesses +system.cpu.dcache.demand_misses 11929003 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2753148 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 36802928500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.014775 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9175855 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 624015096 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4405.959540 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3683.283414 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 621031859 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4741.409697 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4010.844602 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 612089293 # number of overall hits -system.cpu.dcache.overall_miss_latency 52544605500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.019111 # miss rate for overall accesses -system.cpu.dcache.overall_misses 11925803 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2745256 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33814556500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.014712 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9180547 # number of overall MSHR misses +system.cpu.dcache.overall_hits 609102856 # number of overall hits +system.cpu.dcache.overall_miss_latency 56560290500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.019208 # miss rate for overall accesses +system.cpu.dcache.overall_misses 11929003 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2753148 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 36802928500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.014775 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9175855 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 9176451 # number of replacements -system.cpu.dcache.sampled_refs 9180547 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9171759 # number of replacements +system.cpu.dcache.sampled_refs 9175855 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4083.178096 # Cycle average of tags in use -system.cpu.dcache.total_refs 612089293 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4996762000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2245686 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 22551440 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 546 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 44940582 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2380682647 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 322635695 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 423064703 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 52978940 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1700 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 3834921 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 295748685 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 302488728 # Number of cache lines fetched -system.cpu.fetch.Cycles 741391553 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2447585283 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 20057035 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.358455 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 302488728 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 284592818 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.966534 # Number of inst fetches per cycle +system.cpu.dcache.tagsinuse 4081.309726 # Cycle average of tags in use +system.cpu.dcache.total_refs 609102856 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 8881811000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2245633 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 27333658 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 501 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 42431183 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2163062948 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 823856490 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 388659524 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 37167487 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1638 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 580367 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 265702680 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 277957843 # Number of cache lines fetched +system.cpu.fetch.Cycles 672748425 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10624598 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2197044125 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 19810424 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.207971 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 277957843 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 255949942 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.719668 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 825065699 +system.cpu.fetch.rateDist.samples 1277597526 system.cpu.fetch.rateDist.min_value 0 - 0 386162878 4680.39% - 1 30694739 372.03% - 2 18778429 227.60% - 3 29987039 363.45% - 4 87656406 1062.42% - 5 50975460 617.84% - 6 28097158 340.54% - 7 26422023 320.24% - 8 166291567 2015.49% + 0 882806946 6909.90% + 1 27356477 214.12% + 2 16416749 128.50% + 3 27123610 212.30% + 4 80197027 627.72% + 5 46838848 366.62% + 6 25144427 196.81% + 7 24073126 188.42% + 8 147640316 1155.61% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 302488728 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4286.486486 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3340.579710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 302487803 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3965000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 277957843 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5447.729673 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4641.891892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 277956896 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 5159000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 925 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 28 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2996500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 947 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 59 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4122000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 897 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 888 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 337221.630992 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 313014.522523 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 302488728 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4286.486486 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency -system.cpu.icache.demand_hits 302487803 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3965000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 277957843 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5447.729673 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency +system.cpu.icache.demand_hits 277956896 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 5159000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses -system.cpu.icache.demand_misses 925 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 28 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2996500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 947 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 4122000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 897 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 888 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 302488728 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4286.486486 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3340.579710 # average overall mshr miss latency +system.cpu.icache.overall_accesses 277957843 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5447.729673 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4641.891892 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 302487803 # number of overall hits -system.cpu.icache.overall_miss_latency 3965000 # number of overall miss cycles +system.cpu.icache.overall_hits 277956896 # number of overall hits +system.cpu.icache.overall_miss_latency 5159000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses -system.cpu.icache.overall_misses 925 # number of overall misses -system.cpu.icache.overall_mshr_hits 28 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2996500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 947 # number of overall misses +system.cpu.icache.overall_mshr_hits 59 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 4122000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 897 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 888 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,79 +216,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 897 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 888 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 700.392428 # Cycle average of tags in use -system.cpu.icache.total_refs 302487803 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 691.554117 # Cycle average of tags in use +system.cpu.icache.total_refs 277956896 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 498 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 240658046 # Number of branches executed -system.cpu.iew.EXEC:nop 109011682 # number of nop insts executed -system.cpu.iew.EXEC:rate 2.343638 # Inst execution rate -system.cpu.iew.EXEC:refs 670450767 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 171332493 # Number of stores executed +system.cpu.idleCycles 973 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 231142223 # Number of branches executed +system.cpu.iew.EXEC:nop 101615397 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.460942 # Inst execution rate +system.cpu.iew.EXEC:refs 650877785 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 168419462 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1329316260 # num instructions consuming a value -system.cpu.iew.WB:count 1919496913 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.807674 # average fanout of values written-back +system.cpu.iew.WB:consumers 1210814193 # num instructions consuming a value +system.cpu.iew.WB:count 1847797148 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.819076 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1073654377 # num instructions producing a value -system.cpu.iew.WB:rate 2.326478 # insts written-back per cycle -system.cpu.iew.WB:sent 1925768214 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21262198 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 271227 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 533254174 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 16376681 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 186471924 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2178733969 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 499118274 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42707495 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1933655185 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3473 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 991749121 # num instructions producing a value +system.cpu.iew.WB:rate 1.446306 # insts written-back per cycle +system.cpu.iew.WB:sent 1849274792 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 20085867 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1985372 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 497279728 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 38 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 27992821 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 174034666 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2032941045 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 482458323 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 14098084 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1866495371 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 77 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 253 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 52978940 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 31539 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 1402 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 37167487 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 36044 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 331862 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 34494542 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 128095 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 409084 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 20784106 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 401249 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 361683 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 87587813 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 25566942 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 361683 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 691850 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 20570348 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 2.104128 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.104128 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 1976362680 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 306932 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 51613367 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 13129684 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 306932 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 672336 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 19413531 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.358835 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.358835 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 1880593455 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 1288510764 65.20% # Type of FU issued + IntAlu 1224165146 65.09% # Type of FU issued IntMult 78 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 234 0.00% # Type of FU issued + FloatAdd 199 0.00% # Type of FU issued FloatCmp 15 0.00% # Type of FU issued - FloatCvt 154 0.00% # Type of FU issued - FloatMult 14 0.00% # Type of FU issued + FloatCvt 141 0.00% # Type of FU issued + FloatMult 13 0.00% # Type of FU issued FloatDiv 24 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 513015840 25.96% # Type of FU issued - MemWrite 174835557 8.85% # Type of FU issued + MemRead 487297898 25.91% # Type of FU issued + MemWrite 169129941 8.99% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 18092397 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009154 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 14841221 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007892 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 2424231 13.40% # attempts to use FU when none available + IntAlu 753308 5.08% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -297,84 +297,84 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 11434785 63.20% # attempts to use FU when none available - MemWrite 4233381 23.40% # attempts to use FU when none available + MemRead 10126775 68.23% # attempts to use FU when none available + MemWrite 3961138 26.69% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 825065699 +system.cpu.iq.ISSUE:issued_per_cycle.samples 1277597526 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 201043450 2436.70% - 1 117715520 1426.74% - 2 151671107 1838.29% - 3 100094924 1213.18% - 4 99857816 1210.30% - 5 89528622 1085.11% - 6 51943929 629.57% - 7 9400422 113.94% - 8 3809909 46.18% + 0 550473495 4308.66% + 1 242915598 1901.35% + 2 174612702 1366.73% + 3 111937959 876.16% + 4 91216702 713.97% + 5 63235343 494.96% + 6 32411117 253.69% + 7 9228529 72.23% + 8 1566081 12.26% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 2.395400 # Inst issue rate -system.cpu.iq.iqInstsAdded 2069722245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1976362680 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 325012863 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1550012 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 175292310 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 9181444 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4578.076271 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1904.625556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7012219 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 9930877500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.236262 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 2169225 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4131561371 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236262 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 2169225 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2245686 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2216531 # number of Writeback hits -system.cpu.l2cache.Writeback_miss_rate 0.012983 # miss rate for Writeback accesses -system.cpu.l2cache.Writeback_misses 29155 # number of Writeback misses -system.cpu.l2cache.Writeback_mshr_miss_rate 0.012983 # mshr miss rate for Writeback accesses -system.cpu.l2cache.Writeback_mshr_misses 29155 # number of Writeback MSHR misses +system.cpu.iq.ISSUE:rate 1.471976 # Inst issue rate +system.cpu.iq.iqInstsAdded 1931325610 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1880593455 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 179510503 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 87058 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 101093002 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 9176743 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5323.405393 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2210.600583 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7008183 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 11544124000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.236310 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 2168560 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4793820000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236310 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 2168560 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2245633 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2216502 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.012972 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 29131 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.012972 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 29131 # number of Writeback MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.254400 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.253830 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9181444 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4578.076271 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7012219 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9930877500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.236262 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2169225 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9176743 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5323.405393 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7008183 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 11544124000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.236310 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2168560 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4131561371 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.236262 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2169225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4793820000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.236310 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2168560 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 11427130 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4517.361648 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1904.625556 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 11422376 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5252.842188 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2210.600583 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 9228750 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9930877500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.192383 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2198380 # number of overall misses +system.cpu.l2cache.overall_hits 9224685 # number of overall hits +system.cpu.l2cache.overall_miss_latency 11544124000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.192402 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2197691 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4131561371 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.189831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2169225 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4793820000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.189852 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2168560 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -386,32 +386,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 2136457 # number of replacements -system.cpu.l2cache.sampled_refs 2169225 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2135792 # number of replacements +system.cpu.l2cache.sampled_refs 2168560 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31578.699946 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9228750 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 29958824000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1039499 # number of writebacks -system.cpu.numCycles 825065699 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 6100420 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 31406.160078 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9224685 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 53019662000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1039396 # number of writebacks +system.cpu.numCycles 1277597526 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 16292159 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 4850719 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 338099779 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 9291025 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 1319 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 2964381647 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2307795213 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1730632745 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 411108509 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 52978940 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 16777593 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 354429782 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 458 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 47 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 42678716 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 4365074 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 834284464 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 6221923 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 448 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 2711841153 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2114466649 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1591248178 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 378627043 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 37167487 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 11225904 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 215045215 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 469 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 45 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 21611838 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.timesIdled 27 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index d1eaa2267..ab96f2ec5 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out index 19f234143..fc081bf5e 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt index fbe8bb0a6..4bc7b8152 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 929031 # Simulator instruction rate (inst/s) -host_mem_usage 148624 # Number of bytes of host memory used -host_seconds 1958.79 # Real time elapsed on the host -host_tick_rate 464515386 # Simulator tick rate (ticks/s) +host_inst_rate 918892 # Simulator instruction rate (inst/s) +host_mem_usage 148632 # Number of bytes of host memory used +host_seconds 1980.41 # Real time elapsed on the host +host_tick_rate 459446111 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780129 # Number of instructions simulated sim_seconds 0.909890 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 2f9e86a73..41806d538 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out index 7cc7b0b90..55a09db2b 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index eb696cc14..009ee213d 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 623968 # Simulator instruction rate (inst/s) -host_mem_usage 154076 # Number of bytes of host memory used -host_seconds 2916.46 # Real time elapsed on the host -host_tick_rate 423514548 # Simulator tick rate (ticks/s) +host_inst_rate 637714 # Simulator instruction rate (inst/s) +host_mem_usage 154060 # Number of bytes of host memory used +host_seconds 2853.60 # Real time elapsed on the host +host_tick_rate 886477792 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780129 # Number of instructions simulated -sim_seconds 1.235165 # Number of seconds simulated -sim_ticks 1235165291000 # Number of ticks simulated +sim_seconds 2.529655 # Number of seconds simulated +sim_ticks 2529654621000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2978.629098 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 1978.629098 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 12378.042992 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11378.042992 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 21512892500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 89399351000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 14290478500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 82176937000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2992.340366 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 1992.340366 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 12836.520018 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11836.520018 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5653488500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24252294000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3764168500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 22362974000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2981.472133 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 12473.108302 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 27166381000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 113651645000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 18054647000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 104539911000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2981.472133 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 1981.472133 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 12473.108302 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11473.108302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 596212431 # number of overall hits -system.cpu.dcache.overall_miss_latency 27166381000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 113651645000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_misses 9111734 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 18054647000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 104539911000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 9107638 # number of replacements system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4078.615858 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.970916 # Cycle average of tags in use system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 20287970000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 40631938000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 2244708 # number of writebacks system.cpu.icache.ReadReq_accesses 1819780130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3779.301746 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2779.301746 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13987.531172 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12987.531172 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 1819779328 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3031000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 11218000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 2229000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10416000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 1819780130 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3779.301746 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13987.531172 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency system.cpu.icache.demand_hits 1819779328 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3031000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 11218000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses system.cpu.icache.demand_misses 802 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2229000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10416000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 1819780130 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3779.301746 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2779.301746 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13987.531172 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12987.531172 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 1819779328 # number of overall hits -system.cpu.icache.overall_miss_latency 3031000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 11218000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses system.cpu.icache.overall_misses 802 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2229000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10416000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 611.013893 # Cycle average of tags in use +system.cpu.icache.tagsinuse 611.364745 # Cycle average of tags in use system.cpu.icache.total_refs 1819779328 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 9112536 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2722.045846 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.036352 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 12996.354425 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 10996.354425 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 6952383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 5880035500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 28074114000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.237053 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 2160153 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3713381532 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 23753808000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.237053 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 2160153 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses) @@ -168,29 +168,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2722.045846 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 12996.354425 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency system.cpu.l2cache.demand_hits 6952383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 5880035500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 28074114000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.237053 # miss rate for demand accesses system.cpu.l2cache.demand_misses 2160153 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3713381532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 23753808000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.237053 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 2160153 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 11357244 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2685.867535 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.036352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 12823.621788 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 10996.354425 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 9167994 # number of overall hits -system.cpu.l2cache.overall_miss_latency 5880035500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 28074114000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.192762 # miss rate for overall accesses system.cpu.l2cache.overall_misses 2189250 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3713381532 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 23753808000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.190200 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 2160153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -207,12 +207,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 2127385 # number of replacements system.cpu.l2cache.sampled_refs 2160153 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31158.106837 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 31194.155037 # Cycle average of tags in use system.cpu.l2cache.total_refs 9167994 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 122436614000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.warmup_cycle 245730069000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 1038202 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1235165291000 # number of cpu cycles simulated +system.cpu.numCycles 2529654621000 # number of cpu cycles simulated system.cpu.num_insts 1819780129 # Number of instructions executed system.cpu.num_refs 606571345 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 04020c643..72c4312d9 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out index 50da468a0..e3bf50f10 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 8e2806190..8dcfd61cf 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 14247678 # Number of BTB hits -global.BPredUnit.BTBLookups 18312009 # Number of BTB lookups -global.BPredUnit.RASInCorrect 1187 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1953985 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 15742663 # Number of conditional branches predicted -global.BPredUnit.lookups 20998495 # Number of BP lookups -global.BPredUnit.usedRAS 1857732 # Number of times the RAS was used to get a target. -host_inst_rate 58248 # Simulator instruction rate (inst/s) -host_mem_usage 156992 # Number of bytes of host memory used -host_seconds 1445.19 # Real time elapsed on the host -host_tick_rate 23712867 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 20592604 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 6080799 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 35412339 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 11200166 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 11874522 # Number of BTB hits +global.BPredUnit.BTBLookups 15445749 # Number of BTB lookups +global.BPredUnit.RASInCorrect 1158 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1931947 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 13190559 # Number of conditional branches predicted +global.BPredUnit.lookups 17824174 # Number of BP lookups +global.BPredUnit.usedRAS 1655464 # Number of times the RAS was used to get a target. +host_inst_rate 74830 # Simulator instruction rate (inst/s) +host_mem_usage 156844 # Number of bytes of host memory used +host_seconds 1124.95 # Real time elapsed on the host +host_tick_rate 39347975 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 14674251 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 4294265 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 31675298 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 10012759 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.034270 # Number of seconds simulated -sim_ticks 34269677000 # Number of ticks simulated +sim_seconds 0.044264 # Number of seconds simulated +sim_ticks 44264420500 # Number of ticks simulated system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3363462 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2948022 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 59572652 +system.cpu.commit.COM:committed_per_cycle.samples 81602250 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 25280039 4243.56% - 1 15284536 2565.70% - 2 7326530 1229.85% - 3 3334393 559.72% - 4 2152142 361.26% - 5 1242273 208.53% - 6 890288 149.45% - 7 698989 117.33% - 8 3363462 564.60% + 0 44887304 5500.74% + 1 17052684 2089.73% + 2 8186225 1003.19% + 3 3991011 489.08% + 4 1764745 216.26% + 5 1325913 162.48% + 6 892255 109.34% + 7 554091 67.90% + 8 2948022 361.27% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 20034413 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1941454 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1919652 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 63250167 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 46410426 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.814203 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.814203 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 23612894 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4229.600000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3389.648438 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23612269 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2643500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 625 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 113 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1735500 # number of ReadReq MSHR miss cycles +system.cpu.cpi 1.051666 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051666 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 23047695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5314.424635 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4545.725646 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23047078 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3279000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 617 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 114 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2286500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 503 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3064.490759 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3618.087558 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493474 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 23379000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001173 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 7629 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 5893 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 6281000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 3836.081210 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4946.808511 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493764 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 28153000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001129 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7339 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5600 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8602500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1736 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13392.234431 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13176.111508 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 30113997 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3152.713836 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency -system.cpu.dcache.demand_hits 30105743 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26022500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000274 # miss rate for demand accesses -system.cpu.dcache.demand_misses 8254 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6006 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8016500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2248 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 29548798 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3950.729010 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29540842 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 31432000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000269 # miss rate for demand accesses +system.cpu.dcache.demand_misses 7956 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5714 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 10889000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 30113997 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3152.713836 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3566.058719 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 29548798 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3950.729010 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4856.824264 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 30105743 # number of overall hits -system.cpu.dcache.overall_miss_latency 26022500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000274 # miss rate for overall accesses -system.cpu.dcache.overall_misses 8254 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6006 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8016500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2248 # number of overall MSHR misses +system.cpu.dcache.overall_hits 29540842 # number of overall hits +system.cpu.dcache.overall_miss_latency 31432000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000269 # miss rate for overall accesses +system.cpu.dcache.overall_misses 7956 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5714 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 10889000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -118,92 +118,92 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 162 # number of replacements -system.cpu.dcache.sampled_refs 2248 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 163 # number of replacements +system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1463.572116 # Cycle average of tags in use -system.cpu.dcache.total_refs 30105743 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1457.683096 # Cycle average of tags in use +system.cpu.dcache.total_refs 29540842 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 106 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 6099480 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13208 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3247204 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 173741531 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 23444029 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 28861256 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8966698 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 40444 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1167888 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 20998495 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 20206829 # Number of cache lines fetched -system.cpu.fetch.Cycles 51475298 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 3593 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 180749377 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2035048 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.306371 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 20206829 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 16105410 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.637162 # Number of inst fetches per cycle +system.cpu.dcache.writebacks 107 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 2294607 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12777 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 2890400 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 151561971 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 53136009 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 26139582 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 6926673 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 40541 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 32053 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 17824174 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 18016265 # Number of cache lines fetched +system.cpu.fetch.Cycles 44691424 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 975254 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 154588435 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2011658 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.201337 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 18016265 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13529986 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.746191 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 68539351 +system.cpu.fetch.rateDist.samples 88528924 system.cpu.fetch.rateDist.min_value 0 - 0 37270886 5437.88% - 1 3420236 499.02% - 2 1457458 212.65% - 3 2151808 313.95% - 4 4198050 612.50% - 5 1495508 218.20% - 6 1665097 242.94% - 7 1343985 196.09% - 8 15536323 2266.77% + 0 61853767 6986.84% + 1 2838595 320.64% + 2 1299355 146.77% + 3 1865057 210.67% + 4 3537974 399.64% + 5 1231942 139.16% + 6 1400771 158.23% + 7 1171977 132.38% + 8 13329486 1505.66% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 20206829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3070.200019 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2096.460002 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 20196480 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 31773500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000512 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10349 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 236 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 21201500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000500 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10113 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 18016265 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3877.692156 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2918.898279 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 18006143 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 39250000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000562 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10122 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 301 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 28666500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000545 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 9821 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1997.080985 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1833.432746 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 20206829 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3070.200019 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency -system.cpu.icache.demand_hits 20196480 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 31773500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000512 # miss rate for demand accesses -system.cpu.icache.demand_misses 10349 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 236 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21201500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000500 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10113 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 18016265 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3877.692156 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency +system.cpu.icache.demand_hits 18006143 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 39250000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000562 # miss rate for demand accesses +system.cpu.icache.demand_misses 10122 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 28666500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000545 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 9821 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 20206829 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3070.200019 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2096.460002 # average overall mshr miss latency +system.cpu.icache.overall_accesses 18016265 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3877.692156 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2918.898279 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 20196480 # number of overall hits -system.cpu.icache.overall_miss_latency 31773500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000512 # miss rate for overall accesses -system.cpu.icache.overall_misses 10349 # number of overall misses -system.cpu.icache.overall_mshr_hits 236 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21201500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000500 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10113 # number of overall MSHR misses +system.cpu.icache.overall_hits 18006143 # number of overall hits +system.cpu.icache.overall_miss_latency 39250000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000562 # miss rate for overall accesses +system.cpu.icache.overall_misses 10122 # number of overall misses +system.cpu.icache.overall_mshr_hits 301 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 28666500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000545 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 9821 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,162 +215,162 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 8192 # number of replacements -system.cpu.icache.sampled_refs 10113 # Sample count of references to valid blocks. +system.cpu.icache.replacements 7904 # number of replacements +system.cpu.icache.sampled_refs 9821 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1564.702526 # Cycle average of tags in use -system.cpu.icache.total_refs 20196480 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1549.418815 # Cycle average of tags in use +system.cpu.icache.total_refs 18006143 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 2998 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 13347594 # Number of branches executed -system.cpu.iew.EXEC:nop 13508406 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.523954 # Inst execution rate -system.cpu.iew.EXEC:refs 32463851 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7352116 # Number of stores executed +system.cpu.idleCycles 7902 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12543861 # Number of branches executed +system.cpu.iew.EXEC:nop 11949352 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.130385 # Inst execution rate +system.cpu.iew.EXEC:refs 31528912 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7145648 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 95064439 # num instructions consuming a value -system.cpu.iew.WB:count 103132878 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.721353 # average fanout of values written-back +system.cpu.iew.WB:consumers 87529341 # num instructions consuming a value +system.cpu.iew.WB:count 98214425 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.729574 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 68574976 # num instructions producing a value -system.cpu.iew.WB:rate 1.504725 # insts written-back per cycle -system.cpu.iew.WB:sent 104172184 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2117203 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 606505 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 35412339 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 444 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 632938 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 11200166 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 155150547 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 25111735 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2600272 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 104450796 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 226857 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 63859133 # num instructions producing a value +system.cpu.iew.WB:rate 1.109405 # insts written-back per cycle +system.cpu.iew.WB:sent 99107976 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2078247 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 190251 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 31675298 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 411 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2578287 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10012759 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 138313092 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24383264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1412890 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 100071797 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 38223 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8966698 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 304686 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 6926673 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 64568 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 1001916 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 10875 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 828690 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 779 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 88969 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9698 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 15377926 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4697471 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 88969 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 207130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1910073 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.228195 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.228195 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 107051068 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 84249 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9673 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11640885 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3510064 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 84249 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 193948 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1884299 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.950872 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.950872 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 101484687 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 7 0.00% # Type of FU issued - IntAlu 66598699 62.21% # Type of FU issued - IntMult 478232 0.45% # Type of FU issued + IntAlu 62609480 61.69% # Type of FU issued + IntMult 467679 0.46% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2814666 2.63% # Type of FU issued - FloatCmp 115604 0.11% # Type of FU issued - FloatCvt 2391391 2.23% # Type of FU issued - FloatMult 308778 0.29% # Type of FU issued - FloatDiv 755076 0.71% # Type of FU issued - FloatSqrt 324 0.00% # Type of FU issued - MemRead 26034990 24.32% # Type of FU issued - MemWrite 7553301 7.06% # Type of FU issued + FloatAdd 2780950 2.74% # Type of FU issued + FloatCmp 115557 0.11% # Type of FU issued + FloatCvt 2364134 2.33% # Type of FU issued + FloatMult 305451 0.30% # Type of FU issued + FloatDiv 755050 0.74% # Type of FU issued + FloatSqrt 320 0.00% # Type of FU issued + MemRead 24826231 24.46% # Type of FU issued + MemWrite 7259828 7.15% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 2233247 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.020862 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 1739512 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017141 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 352978 15.81% # attempts to use FU when none available + IntAlu 236478 13.59% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available - FloatAdd 856 0.04% # attempts to use FU when none available - FloatCmp 8 0.00% # attempts to use FU when none available - FloatCvt 3654 0.16% # attempts to use FU when none available - FloatMult 2325 0.10% # attempts to use FU when none available - FloatDiv 987087 44.20% # attempts to use FU when none available + FloatAdd 1 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 223 0.01% # attempts to use FU when none available + FloatMult 1629 0.09% # attempts to use FU when none available + FloatDiv 705159 40.54% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 766963 34.34% # attempts to use FU when none available - MemWrite 119376 5.35% # attempts to use FU when none available + MemRead 710061 40.82% # attempts to use FU when none available + MemWrite 85961 4.94% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 68539351 +system.cpu.iq.ISSUE:issued_per_cycle.samples 88528924 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 25564605 3729.92% - 1 14833050 2164.17% - 2 10859904 1584.48% - 3 6945297 1013.33% - 4 5154135 752.00% - 5 2881350 420.39% - 6 1567848 228.75% - 7 633355 92.41% - 8 99807 14.56% + 0 43673541 4933.25% + 1 18286123 2065.55% + 2 11155754 1260.13% + 3 6962814 786.50% + 4 4628513 522.82% + 5 2073707 234.24% + 6 1255435 141.81% + 7 360879 40.76% + 8 132158 14.93% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.561892 # Inst issue rate -system.cpu.iq.iqInstsAdded 141641697 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 107051068 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 444 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 56891185 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 501220 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 55 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 52161048 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 12360 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3103.922717 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1864.884465 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7236 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 15904500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.414563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 5124 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9555668 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.414563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 5124 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.iq.ISSUE:rate 1.146345 # Inst issue rate +system.cpu.iq.iqInstsAdded 126363329 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 101484687 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 411 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 41115515 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 151595 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 37587907 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 12063 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4597.386006 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2450.176887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 6975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 23391500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.421786 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 5088 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 12466500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.421786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 5088 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.432865 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.391903 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12360 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3103.922717 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7236 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 15904500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.414563 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12063 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4597.386006 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6975 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 23391500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.421786 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5088 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9555668 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.414563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12466500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.421786 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5088 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 12466 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3103.922717 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1864.884465 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 12170 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4597.386006 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2450.176887 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7342 # number of overall hits -system.cpu.l2cache.overall_miss_latency 15904500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.411038 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5124 # number of overall misses +system.cpu.l2cache.overall_hits 7082 # number of overall hits +system.cpu.l2cache.overall_miss_latency 23391500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.418077 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5088 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9555668 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.411038 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12466500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.418077 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5088 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -383,30 +383,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 5124 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 5088 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3431.784338 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7342 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3405.740601 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7082 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 68539351 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2079138 # Number of cycles rename is blocking +system.cpu.numCycles 88528924 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1217757 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1661115 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 25239317 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1954833 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 215732838 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 167129936 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 122925813 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28288722 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8966698 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 3960770 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 54498452 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 484 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 9920797 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 473 # count of temporary serializing insts renamed -system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 511469 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 54000366 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 581686 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 190129267 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 147303303 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 108348051 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 25314451 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 6926673 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1065045 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 39920690 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 4632 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 447 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2624388 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 437 # count of temporary serializing insts renamed +system.cpu.timesIdled 98 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 24a71167b..3cb797e6a 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out index 296e0472f..47defa937 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt index b11bd8cad..acfa7c9dd 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 754988 # Simulator instruction rate (inst/s) -host_mem_usage 150624 # Number of bytes of host memory used -host_seconds 121.73 # Real time elapsed on the host -host_tick_rate 377492666 # Simulator tick rate (ticks/s) +host_inst_rate 935813 # Simulator instruction rate (inst/s) +host_mem_usage 150648 # Number of bytes of host memory used +host_seconds 98.21 # Real time elapsed on the host +host_tick_rate 467904361 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini index cd04983c0..7edcc9166 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out index 3089af658..3ed492885 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index b45fb965e..9f5824722 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 335846 # Simulator instruction rate (inst/s) -host_mem_usage 156240 # Number of bytes of host memory used -host_seconds 273.71 # Real time elapsed on the host -host_tick_rate 216396349 # Simulator tick rate (ticks/s) +host_inst_rate 651405 # Simulator instruction rate (inst/s) +host_mem_usage 156232 # Number of bytes of host memory used +host_seconds 141.08 # Real time elapsed on the host +host_tick_rate 840119018 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated -sim_seconds 0.059229 # Number of seconds simulated -sim_ticks 59229023000 # Number of ticks simulated +sim_seconds 0.118528 # Number of seconds simulated +sim_ticks 118527938000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3629.746835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2629.746835 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13776.371308 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12776.371308 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1720500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 6530000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1246500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6056000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3602.116705 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2602.116705 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13970.251716 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12970.251716 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 6296500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 24420000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4548500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 22672000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3608.010801 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13928.892889 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency system.cpu.dcache.demand_hits 26495079 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 8017000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 30950000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses system.cpu.dcache.demand_misses 2222 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5795000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 28728000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2222 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3608.010801 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2608.010801 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13928.892889 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12928.892889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26495079 # number of overall hits -system.cpu.dcache.overall_miss_latency 8017000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 30950000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_misses 2222 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5795000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 28728000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2222 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.710869 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.614290 # Cycle average of tags in use system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks system.cpu.icache.ReadReq_accesses 91903058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3077.908343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2077.908343 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12615.981199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11615.981199 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 91894548 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 26193000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 107362000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 17683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 98852000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 91903058 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3077.908343 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12615.981199 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency system.cpu.icache.demand_hits 91894548 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 26193000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 107362000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 17683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 98852000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 91903058 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3077.908343 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2077.908343 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12615.981199 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11615.981199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 91894548 # number of overall hits -system.cpu.icache.overall_miss_latency 26193000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 107362000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses system.cpu.icache.overall_misses 8510 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 17683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 98852000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 6681 # number of replacements system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1418.735069 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1418.637331 # Cycle average of tags in use system.cpu.icache.total_refs 91894548 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 10732 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2703.820319 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1702.820319 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 5968 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12881000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 61932000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.443906 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 4764 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8112236 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 52404000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.443906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 4764 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses) @@ -164,29 +164,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2703.820319 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 12881000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 61932000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.443906 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4764 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8112236 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 52404000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.443906 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4764 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 10836 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2703.820319 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1702.820319 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 6072 # number of overall hits -system.cpu.l2cache.overall_miss_latency 12881000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 61932000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.439646 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4764 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8112236 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 52404000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.439646 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -203,12 +203,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 4764 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3173.029647 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3172.809799 # Cycle average of tags in use system.cpu.l2cache.total_refs 6072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 59229023000 # number of cpu cycles simulated +system.cpu.numCycles 118527938000 # number of cpu cycles simulated system.cpu.num_insts 91903057 # Number of instructions executed system.cpu.num_refs 26537109 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 5aa5f86fe..3dcf027c2 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out index f078d661c..d448056f4 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt index 5532c6dba..c41d3b35f 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 668374 # Simulator instruction rate (inst/s) -host_mem_usage 150556 # Number of bytes of host memory used -host_seconds 289.41 # Real time elapsed on the host -host_tick_rate 334186387 # Simulator tick rate (ticks/s) +host_inst_rate 673586 # Simulator instruction rate (inst/s) +host_mem_usage 150548 # Number of bytes of host memory used +host_seconds 287.17 # Real time elapsed on the host +host_tick_rate 336792536 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated sim_seconds 0.096718 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout index 2cdcc205c..f878587c3 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout @@ -18,8 +18,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 16:03:50 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:48:51 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic tests/run.py long/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-atomic/smred.sav diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini index ec76ab996..2a87cb78d 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out index dbecb5fa5..f79151c21 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index 2c6679b72..0f4d2b473 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 490451 # Simulator instruction rate (inst/s) -host_mem_usage 156012 # Number of bytes of host memory used -host_seconds 394.40 # Real time elapsed on the host -host_tick_rate 342594746 # Simulator tick rate (ticks/s) +host_inst_rate 500598 # Simulator instruction rate (inst/s) +host_mem_usage 156000 # Number of bytes of host memory used +host_seconds 386.41 # Real time elapsed on the host +host_tick_rate 699597163 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435973 # Number of instructions simulated -sim_seconds 0.135121 # Number of seconds simulated -sim_ticks 135120940500 # Number of ticks simulated +sim_seconds 0.270332 # Number of seconds simulated +sim_ticks 270331639000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 57734138 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3786.144578 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2786.144578 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 57733640 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1885500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 6972000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 6474000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 3500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 2500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 14000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 13000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 3500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 14000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.000045 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 2500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 13000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.000045 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 18976414 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3587.016575 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2587.016575 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 13987.108656 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12987.108656 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 18975328 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3895500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 15190000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000057 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1086 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2809500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 14104000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000057 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1086 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 76710552 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3649.621212 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13991.161616 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency system.cpu.dcache.demand_hits 76708968 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 5781000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 22162000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses system.cpu.dcache.demand_misses 1584 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4197000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 20578000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1584 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 76710552 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3649.621212 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2649.621212 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13991.161616 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12991.161616 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 76708968 # number of overall hits -system.cpu.dcache.overall_miss_latency 5781000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 22162000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_misses 1584 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4197000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 20578000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1584 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 26 # number of replacements system.cpu.dcache.sampled_refs 1585 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1237.515646 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1237.473868 # Cycle average of tags in use system.cpu.dcache.total_refs 76731373 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 23 # number of writebacks system.cpu.icache.ReadReq_accesses 193435974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3066.269971 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2066.269971 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 12584.365830 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11584.365830 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 193423706 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 37617000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 154385000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000063 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 12268 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 25349000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 142117000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000063 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 12268 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 193435974 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3066.269971 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 12584.365830 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency system.cpu.icache.demand_hits 193423706 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 37617000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 154385000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000063 # miss rate for demand accesses system.cpu.icache.demand_misses 12268 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 25349000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 142117000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000063 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 12268 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 193435974 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3066.269971 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2066.269971 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 12584.365830 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11584.365830 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 193423706 # number of overall hits -system.cpu.icache.overall_miss_latency 37617000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 154385000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000063 # miss rate for overall accesses system.cpu.icache.overall_misses 12268 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 25349000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 142117000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000063 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 12268 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -148,19 +148,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 10342 # number of replacements system.cpu.icache.sampled_refs 12268 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1591.858190 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1591.809550 # Cycle average of tags in use system.cpu.icache.total_refs 193423706 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 13852 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2720.824463 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1719.824463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8685 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14058500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 67171000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.373015 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 5167 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8886333 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 56837000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.373015 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 5167 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses) @@ -174,29 +174,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 13852 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2720.824463 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8685 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14058500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 67171000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.373015 # miss rate for demand accesses system.cpu.l2cache.demand_misses 5167 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8886333 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 56837000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.373015 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 5167 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 13875 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2720.824463 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1719.824463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8708 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14058500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 67171000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.372396 # miss rate for overall accesses system.cpu.l2cache.overall_misses 5167 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8886333 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 56837000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.372396 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 5167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -213,12 +213,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 5167 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3507.285738 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3507.169610 # Cycle average of tags in use system.cpu.l2cache.total_refs 8708 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 135120940500 # number of cpu cycles simulated +system.cpu.numCycles 270331639000 # number of cpu cycles simulated system.cpu.num_insts 193435973 # Number of instructions executed system.cpu.num_refs 76732959 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout index eb4e3bbfa..316a2c0d3 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout @@ -18,11 +18,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 27 2007 14:35:32 -M5 started Fri Apr 27 16:08:41 2007 +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 16:53:38 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second -Exiting @ tick 135120940500 because target called exit() +Exiting @ tick 270331639000 because target called exit() diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini index a5e3f40d7..d0738b960 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini @@ -33,9 +33,14 @@ symbolfile= [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=100 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=8 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[14] side_b=system.membus.port[2] @@ -111,6 +116,7 @@ sys=system [system.iobus] type=Bus children=responder +block_size=64 bus_id=0 clock=2 responder_set=false @@ -137,6 +143,7 @@ pio=system.iobus.default [system.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=2 responder_set=false diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out index d7c3ccbd9..bc35fc4e7 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.out @@ -69,6 +69,7 @@ bus_id=1 clock=2 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -103,10 +104,15 @@ zero=true [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=100 +nack_delay=8 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -361,6 +367,7 @@ bus_id=0 clock=2 width=64 responder_set=false +block_size=64 [system.iobus.responder] type=IsaFake diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt index 1e1ba049c..5229bd3a6 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 571923 # Simulator instruction rate (inst/s) -host_mem_usage 373992 # Number of bytes of host memory used -host_seconds 3905.40 # Real time elapsed on the host -host_tick_rate 571972 # Simulator tick rate (ticks/s) +host_inst_rate 584673 # Simulator instruction rate (inst/s) +host_mem_usage 374168 # Number of bytes of host memory used +host_seconds 3820.23 # Real time elapsed on the host +host_tick_rate 584723 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 2233583679 # Number of instructions simulated sim_seconds 1.116889 # Number of seconds simulated diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr index d07f16195..cf3ec3bba 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr @@ -3,10132 +3,10 @@ Warning: rounding error > tolerance Warning: rounding error > tolerance 0.002000 rounded to 0 warn: No kernel set for full system simulation. Assuming you know what you're doing... +Listening for t1000 connection on port 3456 Listening for t1000 connection on port 3457 -Listening for t1000 connection on port 3458 -0: system.remote_gdb.listener: listening for remote gdb on port 7001 +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: Ignoring write to SPARC ERROR regsiter warn: Ignoring write to SPARC ERROR regsiter warn: Don't know what interrupt to clear for console. -warn: Attempted to set the CWP to 31 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 -warn: Attempted to set the CWP to 18446744073709551615 with NWindows = 8 diff --git a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout index 0639edaa5..ef048f157 100644 --- a/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout +++ b/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 30 2007 12:26:45 -M5 started Fri Mar 30 12:26:47 2007 +M5 compiled May 15 2007 17:08:10 +M5 started Tue May 15 17:08:12 2007 M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic Global frequency set at 2000000000 ticks per second diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 2a139492e..f2617931a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -100,7 +99,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -276,7 +274,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -315,7 +312,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,11 +361,12 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index 8155faf63..7cb2e7d7d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -274,20 +275,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -312,20 +312,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -350,13 +349,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 86aa4129f..e1bed0c51 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,40 +1,39 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 606 # Number of BTB hits -global.BPredUnit.BTBLookups 1858 # Number of BTB lookups -global.BPredUnit.RASInCorrect 54 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 415 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1270 # Number of conditional branches predicted -global.BPredUnit.lookups 2195 # Number of BP lookups -global.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -host_inst_rate 22780 # Simulator instruction rate (inst/s) -host_mem_usage 154084 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host -host_tick_rate 14337041 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 31 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 138 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2061 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1230 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 524 # Number of BTB hits +global.BPredUnit.BTBLookups 1590 # Number of BTB lookups +global.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 422 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1093 # Number of conditional branches predicted +global.BPredUnit.lookups 1843 # Number of BP lookups +global.BPredUnit.usedRAS 241 # Number of times the RAS was used to get a target. +host_inst_rate 7145 # Simulator instruction rate (inst/s) +host_seconds 0.79 # Real time elapsed on the host +host_tick_rate 5828052 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 127 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1876 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1144 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 3543500 # Number of ticks simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 4588000 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 121 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 104 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6315 +system.cpu.commit.COM:committed_per_cycle.samples 8514 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 4255 6737.93% - 1 915 1448.93% - 2 408 646.08% - 3 162 256.53% - 4 140 221.69% - 5 91 144.10% - 6 121 191.61% - 7 102 161.52% - 8 121 191.61% + 0 6195 7276.25% + 1 1158 1360.11% + 2 469 550.86% + 3 176 206.72% + 4 131 153.86% + 5 99 116.28% + 6 109 128.02% + 7 73 85.74% + 8 104 122.15% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,69 +42,69 @@ system.cpu.commit.COM:loads 979 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1791 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 341 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4458 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3588 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.260537 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.260537 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4941.176471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4361.386139 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1380 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 672000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.089710 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 440500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.066623 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses +system.cpu.cpi 1.635604 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.635604 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5928.571429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5385 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1342 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 788500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.090169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 538500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.067797 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3265.671642 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3819.444444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 477 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 1094000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.412562 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 335 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 275000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 4501.457726 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 469 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1544000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.422414 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 343 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 373500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 10.734104 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.468208 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2328 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3749.469214 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1857 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1766000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.202320 # miss rate for demand accesses -system.cpu.dcache.demand_misses 471 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 298 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 715500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.074313 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2287 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1811 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 2332500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.208133 # miss rate for demand accesses +system.cpu.dcache.demand_misses 476 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 303 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 912000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.075645 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2328 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3749.469214 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4135.838150 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2287 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4900.210084 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 5271.676301 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1857 # number of overall hits -system.cpu.dcache.overall_miss_latency 1766000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.202320 # miss rate for overall accesses -system.cpu.dcache.overall_misses 471 # number of overall misses -system.cpu.dcache.overall_mshr_hits 298 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 715500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.074313 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 1811 # number of overall hits +system.cpu.dcache.overall_miss_latency 2332500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.208133 # miss rate for overall accesses +system.cpu.dcache.overall_misses 476 # number of overall misses +system.cpu.dcache.overall_mshr_hits 303 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 912000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.075645 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,89 +120,89 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 111.557376 # Cycle average of tags in use -system.cpu.dcache.total_refs 1857 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 112.670676 # Cycle average of tags in use +system.cpu.dcache.total_refs 1811 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 381 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 172 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12164 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3741 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2151 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 772 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 244 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 43 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2195 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1616 # Number of cache lines fetched -system.cpu.fetch.Cycles 3951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 151 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13452 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 448 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.309678 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1616 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 912 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.897856 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 389 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 144 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10499 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 6230 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1848 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 682 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 228 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 1843 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1471 # Number of cache lines fetched +system.cpu.fetch.Cycles 3451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11450 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 455 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.200391 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 765 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.244971 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 7088 +system.cpu.fetch.rateDist.samples 9197 system.cpu.fetch.rateDist.min_value 0 - 0 4755 6708.52% - 1 197 277.93% - 2 177 249.72% - 3 163 229.97% - 4 234 330.14% - 5 170 239.84% - 6 198 279.35% - 7 114 160.84% - 8 1080 1523.70% + 0 7219 7849.30% + 1 167 181.58% + 2 147 159.83% + 3 129 140.26% + 4 200 217.46% + 5 139 151.14% + 6 181 196.80% + 7 99 107.64% + 8 916 995.98% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1616 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4068.597561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3148.089172 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1334500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.202970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 328 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 988500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.194307 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 314 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1471 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5375.757576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4524.038462 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1141 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1774000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.224337 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1411500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.212101 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.101911 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.657051 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1616 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4068.597561 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency -system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1334500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.202970 # miss rate for demand accesses -system.cpu.icache.demand_misses 328 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 14 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 988500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.194307 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 314 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1471 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency +system.cpu.icache.demand_hits 1141 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1774000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.224337 # miss rate for demand accesses +system.cpu.icache.demand_misses 330 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 18 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1411500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.212101 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1616 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4068.597561 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3148.089172 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1471 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5375.757576 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4524.038462 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1288 # number of overall hits -system.cpu.icache.overall_miss_latency 1334500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.202970 # miss rate for overall accesses -system.cpu.icache.overall_misses 328 # number of overall misses -system.cpu.icache.overall_mshr_hits 14 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 988500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.194307 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 314 # number of overall MSHR misses +system.cpu.icache.overall_hits 1141 # number of overall hits +system.cpu.icache.overall_miss_latency 1774000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.224337 # miss rate for overall accesses +system.cpu.icache.overall_misses 330 # number of overall misses +system.cpu.icache.overall_mshr_hits 18 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1411500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.212101 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -216,78 +215,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 166.037293 # Cycle average of tags in use -system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.938349 # Cycle average of tags in use +system.cpu.icache.total_refs 1141 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 1203 # Number of branches executed -system.cpu.iew.EXEC:nop 41 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.125423 # Inst execution rate -system.cpu.iew.EXEC:refs 2585 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.idleCycles 2475 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1148 # Number of branches executed +system.cpu.iew.EXEC:nop 40 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.837338 # Inst execution rate +system.cpu.iew.EXEC:refs 2524 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 977 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5598 # num instructions consuming a value -system.cpu.iew.WB:count 7767 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.741872 # average fanout of values written-back +system.cpu.iew.WB:consumers 5205 # num instructions consuming a value +system.cpu.iew.WB:count 7402 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.742747 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4153 # num instructions producing a value -system.cpu.iew.WB:rate 1.095796 # insts written-back per cycle -system.cpu.iew.WB:sent 7849 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2061 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 240 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10115 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1596 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 554 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7977 # Number of executed instructions +system.cpu.iew.WB:producers 3866 # num instructions producing a value +system.cpu.iew.WB:rate 0.804828 # insts written-back per cycle +system.cpu.iew.WB:sent 7467 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 374 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1876 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1144 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9245 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1547 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 280 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 772 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 682 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1082 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.793313 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.793313 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8531 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 897 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 332 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.611395 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.611395 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 7981 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5713 66.97% # Type of FU issued + No_OpClass 2 0.03% # Type of FU issued + IntAlu 5322 66.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued - FloatAdd 2 0.02% # Type of FU issued + FloatAdd 2 0.03% # Type of FU issued FloatCmp 0 0.00% # Type of FU issued FloatCvt 0 0.00% # Type of FU issued FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1773 20.78% # Type of FU issued - MemWrite 1040 12.19% # Type of FU issued + MemRead 1662 20.82% # Type of FU issued + MemWrite 992 12.43% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 128 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.015004 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 106 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.013282 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 7 5.47% # attempts to use FU when none available + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 0 0.00% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 78 60.94% # attempts to use FU when none available - MemWrite 43 33.59% # attempts to use FU when none available + MemRead 71 66.98% # attempts to use FU when none available + MemWrite 35 33.02% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 7088 +system.cpu.iq.ISSUE:issued_per_cycle.samples 9197 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 4068 5739.28% - 1 771 1087.75% - 2 763 1076.47% - 3 485 684.26% - 4 504 711.06% - 5 295 416.20% - 6 144 203.16% - 7 40 56.43% - 8 18 25.40% + 0 5952 6471.68% + 1 1107 1203.65% + 2 919 999.24% + 3 442 480.59% + 4 375 407.74% + 5 250 271.83% + 6 115 125.04% + 7 26 28.27% + 8 11 11.96% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.203584 # Inst issue rate -system.cpu.iq.iqInstsAdded 10051 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8531 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4086 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2494 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 485 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3318.556701 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1934.377320 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1609500 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.867783 # Inst issue rate +system.cpu.iq.iqInstsAdded 9183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 7981 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 3171 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2045 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 483 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4639.751553 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2463.768116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2241000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 485 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 938173 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 483 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1190000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 485 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 483 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3318.556701 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 483 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1609500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2241000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 483 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 938173 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1190000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 483 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3318.556701 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1934.377320 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 483 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4639.751553 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2463.768116 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1609500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2241000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 485 # number of overall misses +system.cpu.l2cache.overall_misses 483 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 938173 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1190000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 483 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,28 +379,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 485 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 483 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 277.255174 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 278.222582 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 7088 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 3 # Number of cycles rename is blocking +system.cpu.numCycles 9197 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 15 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3933 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 65 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14798 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11577 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8671 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2005 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 772 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 115 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4620 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 260 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 396 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IdleCycles 6383 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 70 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 12854 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 10031 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 7485 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1746 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 682 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 101 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3434 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 270 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 380 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed +system.cpu.timesIdled 25 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index eeba3846f..d935401d2 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:06 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:32 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 3543500 because target called exit() +Exiting @ tick 4588000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index 26009ca4f..e4dfe86d3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -48,11 +48,12 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index f8e40871a..117159126 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index 0f64469e9..f1c7bd968 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 357156 # Simulator instruction rate (inst/s) -host_mem_usage 148180 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 171417285 # Simulator tick rate (ticks/s) +host_inst_rate 93019 # Simulator instruction rate (inst/s) +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 46199079 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 5acc408a3..58fc0e374 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:08 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:34 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 025531062..47315cc1d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -45,7 +44,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -84,7 +82,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -123,7 +120,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,11 +169,12 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index fa1054e9e..f7852a616 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -92,20 +94,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -130,20 +131,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -168,11 +168,10 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index afdac247d..1b70f10b3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,31 +1,30 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 215467 # Simulator instruction rate (inst/s) -host_mem_usage 153656 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 193088667 # Simulator tick rate (ticks/s) +host_inst_rate 54390 # Simulator instruction rate (inst/s) +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 126525357 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5135000 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13168000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3750 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1288000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 253000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1196000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3582.191781 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2582.191781 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 261500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1022000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 188500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 949000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +36,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3675.757576 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 606500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 2310000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 441500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2145000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3675.757576 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2675.757576 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1626 # number of overall hits -system.cpu.dcache.overall_miss_latency 606500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 2310000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 441500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2145000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +75,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 105.359700 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.640117 # Cycle average of tags in use system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3729.241877 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2729.241877 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13960.288809 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12960.288809 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1033000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3867000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.049087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 756000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3590000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.049087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +98,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5643 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3729.241877 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.demand_hits 5366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1033000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3867000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.049087 # miss rate for demand accesses system.cpu.icache.demand_misses 277 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 756000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3590000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.049087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5643 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3729.241877 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2729.241877 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13960.288809 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12960.288809 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5366 # number of overall hits -system.cpu.icache.overall_miss_latency 1033000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3867000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.049087 # miss rate for overall accesses system.cpu.icache.overall_misses 277 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 756000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3590000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.049087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +137,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 131.245403 # Cycle average of tags in use +system.cpu.icache.tagsinuse 129.241810 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 441 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2712.018141 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1711.018141 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1196000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5733000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 754559 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4851000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +160,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2712.018141 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1196000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5733000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 754559 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2712.018141 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1711.018141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1196000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5733000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 754559 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +199,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 236.577060 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 232.802947 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5135000 # number of cpu cycles simulated +system.cpu.numCycles 13168000 # number of cpu cycles simulated system.cpu.num_insts 5642 # Number of instructions executed system.cpu.num_refs 1792 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index a79e87c66..501ba5063 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:09 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:35 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5135000 because target called exit() +Exiting @ tick 13168000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 1e3b2746e..e3080f9e5 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -100,7 +99,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -276,7 +274,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -315,7 +312,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,11 +361,12 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 5df02e4ff..0cb6591c8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -274,20 +275,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -312,20 +312,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -350,13 +349,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index d3074bcf9..6dd4c291d 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -1,40 +1,39 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 162 # Number of BTB hits -global.BPredUnit.BTBLookups 671 # Number of BTB lookups -global.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 427 # Number of conditional branches predicted -global.BPredUnit.lookups 860 # Number of BP lookups -global.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -host_inst_rate 31252 # Simulator instruction rate (inst/s) -host_mem_usage 153592 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 21107113 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. +global.BPredUnit.BTBHits 132 # Number of BTB hits +global.BPredUnit.BTBLookups 584 # Number of BTB lookups +global.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 208 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 376 # Number of conditional branches predicted +global.BPredUnit.lookups 738 # Number of BP lookups +global.BPredUnit.usedRAS 140 # Number of times the RAS was used to get a target. +host_inst_rate 8881 # Simulator instruction rate (inst/s) +host_seconds 0.27 # Real time elapsed on the host +host_tick_rate 7632084 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 8 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 692 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 385 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 608 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 357 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 1619000 # Number of ticks simulated +sim_ticks 2053000 # Number of ticks simulated system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 59 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 41 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 2977 +system.cpu.commit.COM:committed_per_cycle.samples 3906 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 2102 7060.80% - 1 212 712.13% - 2 297 997.65% - 3 114 382.94% - 4 83 278.80% - 5 58 194.83% - 6 30 100.77% - 7 22 73.90% - 8 59 198.19% + 0 2949 7549.92% + 1 266 681.00% + 2 333 852.53% + 3 131 335.38% + 4 74 189.45% + 5 64 163.85% + 6 29 74.24% + 7 19 48.64% + 8 41 104.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,70 +42,70 @@ system.cpu.commit.COM:loads 415 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 138 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 128 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1420 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 978 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.356933 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.356933 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 537 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4625 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3811.475410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 465 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 333000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.134078 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 232500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.113594 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.cpi 1.721408 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.721408 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5456.521739 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4737.288136 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 445 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 376500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.134241 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 69 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 279500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114786 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 59 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 5013.888889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4520.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 361000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 108500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 5669.014085 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5020 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 223 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 402500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.241497 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 71 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 46 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 125500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.085034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 25 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.082353 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.952381 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 831 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4819.444444 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency -system.cpu.dcache.demand_hits 687 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 694000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.173285 # miss rate for demand accesses -system.cpu.dcache.demand_misses 144 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 59 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 341000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.102286 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 808 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency +system.cpu.dcache.demand_hits 668 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 779000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.173267 # miss rate for demand accesses +system.cpu.dcache.demand_misses 140 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 405000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.103960 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 84 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 831 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4819.444444 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 4011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 808 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5564.285714 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4821.428571 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 687 # number of overall hits -system.cpu.dcache.overall_miss_latency 694000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.173285 # miss rate for overall accesses -system.cpu.dcache.overall_misses 144 # number of overall misses -system.cpu.dcache.overall_mshr_hits 59 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 341000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.102286 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses +system.cpu.dcache.overall_hits 668 # number of overall hits +system.cpu.dcache.overall_miss_latency 779000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.173267 # miss rate for overall accesses +system.cpu.dcache.overall_misses 140 # number of overall misses +system.cpu.dcache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 405000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.103960 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 84 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,90 +118,89 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 84 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 50.824604 # Cycle average of tags in use -system.cpu.dcache.total_refs 687 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 51.851940 # Cycle average of tags in use +system.cpu.dcache.total_refs 668 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 83 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4642 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 2009 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 884 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 261 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 313 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 860 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 736 # Number of cache lines fetched -system.cpu.fetch.Cycles 1668 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 78 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5463 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 230 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.265514 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 736 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 336 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.686632 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 95 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 123 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 4033 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 3045 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 767 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 202 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 298 # Number of squashed instructions handled by decode +system.cpu.fetch.Branches 738 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 654 # Number of cache lines fetched +system.cpu.fetch.Cycles 1440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 120 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 4685 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 218 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.179606 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 654 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 272 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.140180 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 3239 +system.cpu.fetch.rateDist.samples 4109 system.cpu.fetch.rateDist.min_value 0 - 0 2309 7128.74% - 1 47 145.11% - 2 82 253.16% - 3 70 216.12% - 4 128 395.18% - 5 58 179.07% - 6 37 114.23% - 7 46 142.02% - 8 462 1426.37% + 0 3325 8091.99% + 1 32 77.88% + 2 74 180.09% + 3 53 128.99% + 4 99 240.93% + 5 49 119.25% + 6 38 92.48% + 7 35 85.18% + 8 404 983.21% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4129.533679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 3209.677419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 543 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 797000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.262228 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 193 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 597000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.252717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 654 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5296.019900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4553.763441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 453 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1064500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.307339 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 201 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 847000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.284404 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.919355 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.435484 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 736 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4129.533679 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency -system.cpu.icache.demand_hits 543 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 797000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.262228 # miss rate for demand accesses -system.cpu.icache.demand_misses 193 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 597000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.252717 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 654 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency +system.cpu.icache.demand_hits 453 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1064500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.307339 # miss rate for demand accesses +system.cpu.icache.demand_misses 201 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 15 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 847000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.284404 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 736 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4129.533679 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 3209.677419 # average overall mshr miss latency +system.cpu.icache.overall_accesses 654 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5296.019900 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4553.763441 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 543 # number of overall hits -system.cpu.icache.overall_miss_latency 797000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.262228 # miss rate for overall accesses -system.cpu.icache.overall_misses 193 # number of overall misses -system.cpu.icache.overall_mshr_hits 7 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 597000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.252717 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 453 # number of overall hits +system.cpu.icache.overall_miss_latency 1064500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.307339 # miss rate for overall accesses +system.cpu.icache.overall_misses 201 # number of overall misses +system.cpu.icache.overall_mshr_hits 15 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 847000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.284404 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -218,58 +216,59 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 104.079729 # Cycle average of tags in use -system.cpu.icache.total_refs 543 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 106.237740 # Cycle average of tags in use +system.cpu.icache.total_refs 453 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 535 # Number of branches executed -system.cpu.iew.EXEC:nop 256 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.978388 # Inst execution rate -system.cpu.iew.EXEC:refs 913 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 339 # Number of stores executed +system.cpu.idleCycles 2992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 501 # Number of branches executed +system.cpu.iew.EXEC:nop 234 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.727184 # Inst execution rate +system.cpu.iew.EXEC:refs 878 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 333 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1857 # num instructions consuming a value -system.cpu.iew.WB:count 3126 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.787291 # average fanout of values written-back +system.cpu.iew.WB:consumers 1652 # num instructions consuming a value +system.cpu.iew.WB:count 2914 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.799637 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1462 # num instructions producing a value -system.cpu.iew.WB:rate 0.965113 # insts written-back per cycle -system.cpu.iew.WB:sent 3139 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 156 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1321 # num instructions producing a value +system.cpu.iew.WB:rate 0.709175 # insts written-back per cycle +system.cpu.iew.WB:sent 2931 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 135 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 692 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 99 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 385 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4013 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 208 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3169 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 608 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 357 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 3571 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 545 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 87 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2988 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 261 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 202 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 22 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 277 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 91 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 193 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 63 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 103 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.736956 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.736956 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 3377 # Type of FU issued +system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.580920 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.580920 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 3075 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 0 0.00% # Type of FU issued - IntAlu 2413 71.45% # Type of FU issued + No_OpClass 0 0.00% # Type of FU issued + IntAlu 2178 70.83% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +277,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 617 18.27% # Type of FU issued - MemWrite 346 10.25% # Type of FU issued + MemRead 561 18.24% # Type of FU issued + MemWrite 335 10.89% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 37 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010956 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011382 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 1 2.70% # attempts to use FU when none available + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 2 5.71% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,43 +295,42 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 14 37.84% # attempts to use FU when none available - MemWrite 22 59.46% # attempts to use FU when none available + MemRead 12 34.29% # attempts to use FU when none available + MemWrite 21 60.00% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 3239 +system.cpu.iq.ISSUE:issued_per_cycle.samples 4109 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 2006 6193.27% - 1 362 1117.63% - 2 258 796.54% - 3 236 728.62% - 4 193 595.86% - 5 111 342.70% - 6 53 163.63% - 7 14 43.22% - 8 6 18.52% + 0 2849 6933.56% + 1 475 1156.00% + 2 270 657.09% + 3 217 528.11% + 4 159 386.96% + 5 86 209.30% + 6 34 82.75% + 7 13 31.64% + 8 6 14.60% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.042606 # Inst issue rate -system.cpu.iq.iqInstsAdded 3751 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3377 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1220 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 564 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 271 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3298.892989 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1993.811808 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 894000 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.748357 # Inst issue rate +system.cpu.iq.iqInstsAdded 3330 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3075 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 790 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 409 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 270 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4522.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2388.888889 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 1221000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 271 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 540323 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 270 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 645000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 271 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 270 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -341,32 +339,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3298.892989 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 894000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 1221000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 540323 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 645000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3298.892989 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1993.811808 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4522.222222 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2388.888889 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 894000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 1221000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 271 # number of overall misses +system.cpu.l2cache.overall_misses 270 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 540323 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 645000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -379,27 +377,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 271 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 270 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 155.098898 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 158.236294 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 3239 # number of cpu cycles simulated +system.cpu.numCycles 4109 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 2100 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 3116 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5014 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4443 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3193 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 795 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 261 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1425 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 76 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:RenameLookups 4416 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3886 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2777 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 696 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 202 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 6 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1009 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 89 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 9 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 55 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 7 # count of temporary serializing insts renamed +system.cpu.timesIdled 8 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr index e582c15a8..9f8e7c2e9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr @@ -1,4 +1,3 @@ -0: system.remote_gdb.listener: listening for remote gdb on port 7001 warn: Entering event queue @ 0. Starting simulation... warn: Increasing stack size by one page. warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...) diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 835f03aa2..60520dc0c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:10 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:36 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 1619000 because target called exit() +Exiting @ tick 2053000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 3e6a662e6..61db8446a 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -48,11 +48,12 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index a2be80e9b..acc734991 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index 16257c237..29351d427 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 254768 # Simulator instruction rate (inst/s) -host_mem_usage 147764 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 121316260 # Simulator tick rate (ticks/s) +host_inst_rate 111994 # Simulator instruction rate (inst/s) +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 55017079 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index ddbbe3d32..f76500526 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:10 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:37 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1288500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index 52183bdb1..5a336ab13 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -45,7 +44,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -84,7 +82,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -123,7 +120,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,11 +169,12 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 05d289a63..241630ead 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -92,20 +94,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -130,20 +131,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -168,11 +168,10 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 8671d784f..621520fa3 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,31 +1,30 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 125225 # Simulator instruction rate (inst/s) -host_mem_usage 153176 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 116347710 # Simulator tick rate (ticks/s) +host_inst_rate 51133 # Simulator instruction rate (inst/s) +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 127514531 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2444000 # Number of ticks simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 6472000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3890.909091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2890.909091 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 214000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 770000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 159000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 715000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3722.222222 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 100500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 378000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 73500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 351000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +36,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3835.365854 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 314500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1148000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 232500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1066000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3835.365854 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2835.365854 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.overall_miss_latency 314500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1148000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 232500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1066000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +75,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 51.430454 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 50.002941 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3733.128834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2733.128834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 608500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 2282000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 445500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 2119000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +98,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3733.128834 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 608500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 2282000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses system.cpu.icache.demand_misses 163 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 445500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 2119000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3733.128834 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2733.128834 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 2416 # number of overall hits -system.cpu.icache.overall_miss_latency 608500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 2282000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses system.cpu.icache.overall_misses 163 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 445500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 2119000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +137,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 89.421061 # Cycle average of tags in use +system.cpu.icache.tagsinuse 86.067224 # Cycle average of tags in use system.cpu.icache.total_refs 2416 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2767.346939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1766.346939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 678000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 3185000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 432755 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 2695000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +160,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2767.346939 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 678000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3185000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 432755 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2767.346939 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1766.346939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 678000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 3185000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 245 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 432755 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +199,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 140.951761 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 136.108021 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2444000 # number of cpu cycles simulated +system.cpu.numCycles 6472000 # number of cpu cycles simulated system.cpu.num_insts 2578 # Number of instructions executed system.cpu.num_refs 710 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index d2bc8bfb7..1c6780cf0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:11 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:37 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 2444000 because target called exit() +Exiting @ tick 6472000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini index 80ef56747..ea3ba751b 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out index 9f8b84468..06a3d271d 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt index daf99515d..6a0c251b5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 7127 # Simulator instruction rate (inst/s) -host_mem_usage 148488 # Number of bytes of host memory used -host_seconds 0.79 # Real time elapsed on the host -host_tick_rate 3561193 # Simulator tick rate (ticks/s) +host_inst_rate 535701 # Simulator instruction rate (inst/s) +host_mem_usage 148368 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 257653061 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout index b975f8f18..7fb23e5a5 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:47:32 -M5 started Sun Apr 22 20:47:35 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2828000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini index 29fcae5de..a5d4e6583 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out index d5d160f1e..3f8a51cf4 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index 71b0896dd..41bb7c8b7 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 224031 # Simulator instruction rate (inst/s) -host_mem_usage 153864 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 205051803 # Simulator tick rate (ticks/s) +host_inst_rate 273338 # Simulator instruction rate (inst/s) +host_mem_usage 153844 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 633390216 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5264500 # Number of ticks simulated +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13362000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3762.195122 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2762.195122 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 308500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 1148000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 226500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 1066000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3690 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2690 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 184500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 700000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 134500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 650000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3734.848485 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 493000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1848000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 361000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1716000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3734.848485 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2734.848485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1922 # number of overall hits -system.cpu.dcache.overall_miss_latency 493000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1848000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 361000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1716000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 86.050916 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 85.283494 # Cycle average of tags in use system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3740.924092 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2740.924092 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13986.798680 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12986.798680 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1133500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 4238000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 830500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3935000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3740.924092 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1133500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 4238000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses system.cpu.icache.demand_misses 303 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 830500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3935000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3740.924092 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2740.924092 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13986.798680 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12986.798680 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 5355 # number of overall hits -system.cpu.icache.overall_miss_latency 1133500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 4238000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses system.cpu.icache.overall_misses 303 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 830500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3935000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,19 +138,19 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 137.160443 # Cycle average of tags in use +system.cpu.icache.tagsinuse 136.309471 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2743.648961 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1742.648961 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1188000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 5629000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 754567 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4763000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -162,29 +162,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2743.648961 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1188000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5629000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 754567 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2743.648961 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1742.648961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1188000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5629000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 754567 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -201,12 +201,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 224.535228 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.872415 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5264500 # number of cpu cycles simulated +system.cpu.numCycles 13362000 # number of cpu cycles simulated system.cpu.num_insts 5657 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 1cc143ec3..6b688641a 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:47:32 -M5 started Sun Apr 22 20:47:36 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 12:54:05 +M5 started Tue May 15 12:54:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5264500 because target called exit() +Exiting @ tick 13362000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index 5d4dafee7..0e142e6ce 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out index 1a521c678..1666790d0 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index bbc3d0e4f..8e0baaf8b 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 16183 # Simulator instruction rate (inst/s) -host_mem_usage 149132 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 8071210 # Simulator tick rate (ticks/s) +host_inst_rate 439375 # Simulator instruction rate (inst/s) +host_mem_usage 149124 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 211870315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated sim_seconds 0.000002 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index 84e837005..9e1770f92 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:04 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 2431000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 4371849c9..fdb2bc3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out index b02683337..89910d3c9 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index c6b55a6f2..839307810 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,31 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 189060 # Simulator instruction rate (inst/s) -host_mem_usage 154496 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 164285984 # Simulator tick rate (ticks/s) +host_inst_rate 239687 # Simulator instruction rate (inst/s) +host_mem_usage 154512 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 542234464 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4863 # Number of instructions simulated -sim_seconds 0.000004 # Number of seconds simulated -sim_ticks 4347500 # Number of ticks simulated +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11221000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3740.740741 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2740.740741 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 13796.296296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12796.296296 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 202000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 745000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 148000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 691000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2625 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 304500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1176000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.127080 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 84 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 220500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1092000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.127080 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 84 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3670.289855 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.demand_hits 1131 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 506500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1921000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.108747 # miss rate for demand accesses system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 368500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1783000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.108747 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3670.289855 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2670.289855 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 13920.289855 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12920.289855 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1131 # number of overall hits -system.cpu.dcache.overall_miss_latency 506500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1921000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.108747 # miss rate for overall accesses system.cpu.dcache.overall_misses 138 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 368500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1783000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.108747 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.314216 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.705022 # Cycle average of tags in use system.cpu.dcache.total_refs 1131 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 4864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3796.875000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2796.875000 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13914.062500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12914.062500 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 4608 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 972000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3562000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.052632 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 716000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3306000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 4864 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3796.875000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.demand_hits 4608 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 972000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3562000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.052632 # miss rate for demand accesses system.cpu.icache.demand_misses 256 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 716000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3306000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 4864 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3796.875000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2796.875000 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13914.062500 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12914.062500 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 4608 # number of overall hits -system.cpu.icache.overall_miss_latency 972000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3562000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.052632 # miss rate for overall accesses system.cpu.icache.overall_misses 256 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 716000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3306000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 114.238100 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.172725 # Cycle average of tags in use system.cpu.icache.total_refs 4608 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2760.869565 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1759.869565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1079500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5083000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 391 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 688109 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4301000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 391 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2760.869565 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5083000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 391 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 688109 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4301000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2760.869565 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1759.869565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1079500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5083000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 391 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 688109 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4301000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 391 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 197.030867 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.304892 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4347500 # number of cpu cycles simulated +system.cpu.numCycles 11221000 # number of cpu cycles simulated system.cpu.num_insts 4863 # Number of instructions executed system.cpu.num_refs 1269 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 6a58f8e2a..65bf4abca 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:05 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:05 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4347500 because target called exit() +Exiting @ tick 11221000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5e1ced152..e9dddb505 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -100,7 +99,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -276,7 +274,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -315,7 +312,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -379,11 +377,12 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out index f04ad4ffd..45b063eb3 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload0] type=LiveProcess @@ -265,7 +266,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -290,20 +291,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -328,20 +328,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -366,13 +365,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -380,4 +378,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index b44194dff..dc1fcc248 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,48 +1,47 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 687 # Number of BTB hits -global.BPredUnit.BTBLookups 3480 # Number of BTB lookups -global.BPredUnit.RASInCorrect 113 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1086 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2328 # Number of conditional branches predicted -global.BPredUnit.lookups 4062 # Number of BP lookups -global.BPredUnit.usedRAS 562 # Number of times the RAS was used to get a target. -host_inst_rate 49679 # Simulator instruction rate (inst/s) -host_mem_usage 154724 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host -host_tick_rate 20293608 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +global.BPredUnit.BTBHits 674 # Number of BTB hits +global.BPredUnit.BTBLookups 3410 # Number of BTB lookups +global.BPredUnit.RASInCorrect 118 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1115 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2318 # Number of conditional branches predicted +global.BPredUnit.lookups 3964 # Number of BP lookups +global.BPredUnit.usedRAS 532 # Number of times the RAS was used to get a target. +host_inst_rate 8215 # Simulator instruction rate (inst/s) +host_seconds 1.37 # Real time elapsed on the host +host_tick_rate 4009351 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 19 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1911 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1079 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1058 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.conflictingStores 59 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1898 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1088 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1090 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11247 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4600500 # Number of ticks simulated +sim_ticks 5490000 # Number of ticks simulated system.cpu.commit.COM:branches 1724 # Number of branches committed system.cpu.commit.COM:branches_0 862 # Number of branches committed system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 179 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 165 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9158 +system.cpu.commit.COM:committed_per_cycle.samples 10929 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 4902 5352.70% - 1 1725 1883.60% - 2 937 1023.15% - 3 472 515.40% - 4 355 387.64% - 5 234 255.51% - 6 234 255.51% - 7 120 131.03% - 8 179 195.46% + 0 6410 5865.13% + 1 2019 1847.38% + 2 999 914.08% + 3 454 415.41% + 4 300 274.50% + 5 246 225.09% + 6 200 183.00% + 7 136 124.44% + 8 165 150.97% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -61,141 +60,133 @@ system.cpu.commit.COM:refs_1 1791 # Nu system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 843 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 874 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 7371 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7769 # The number of squashed insts skipped by commit system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 1.636671 # CPI: Cycles Per Instruction -system.cpu.cpi_1 1.636380 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.818263 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2909 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 2909 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 6520.912548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency_0 6520.912548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6121.212121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6121.212121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2646 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2646 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1715000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 1715000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.090409 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate_0 0.090409 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 263 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 263 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 1212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.068065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068065 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 198 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 198 # number of ReadReq MSHR misses +system.cpu.cpi_0 1.952516 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.952169 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976171 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2969 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 7072.992701 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 6972.361809 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2695 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 1938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.092287 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 274 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 1387500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.067026 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4509.846827 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency_0 4509.846827 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4681.506849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 4681.506849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1167 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1167 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2061000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 2061000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.281404 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate_0 0.281404 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 457 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 457 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 311 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 311 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 683500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 683500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_avg_miss_latency_0 5352.409639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 5859.589041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1126 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 2665500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.306650 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 498 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 855500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 855500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 146 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.084302 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.075362 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4533 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4533 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 4593 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4593 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 5244.444444 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 5244.444444 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3813 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 3821 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 3821 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3776000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 3776000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 4603500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 4603500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.158835 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.158835 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.168082 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 720 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 720 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 772 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 772 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 427 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 427 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1895500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 1895500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 2243000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 2243000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.075888 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.075888 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075114 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 345 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4533 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4533 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 4593 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4593 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 5244.444444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 5244.444444 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 5963.082902 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 5510.174419 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 5510.174419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 6501.449275 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3813 # number of overall hits -system.cpu.dcache.overall_hits_0 3813 # number of overall hits +system.cpu.dcache.overall_hits 3821 # number of overall hits +system.cpu.dcache.overall_hits_0 3821 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 3776000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 3776000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 4603500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 4603500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.158835 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.158835 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.168082 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 720 # number of overall misses -system.cpu.dcache.overall_misses_0 720 # number of overall misses +system.cpu.dcache.overall_misses 772 # number of overall misses +system.cpu.dcache.overall_misses_0 772 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 376 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 427 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 427 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1895500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 1895500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 2243000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 2243000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.075888 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.075888 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075114 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 345 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -215,153 +206,149 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 344 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 345 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 218.590181 # Cycle average of tags in use -system.cpu.dcache.total_refs 3813 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 221.724795 # Cycle average of tags in use +system.cpu.dcache.total_refs 3821 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1876 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 260 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 354 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22033 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 11054 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3598 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1407 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 337 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 284 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 4062 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2946 # Number of cache lines fetched -system.cpu.fetch.Cycles 6973 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 24430 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1145 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.441378 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2946 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1249 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.654569 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 1857 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 251 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 21806 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 14535 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3658 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1498 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 351 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 145 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 3964 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2983 # Number of cache lines fetched +system.cpu.fetch.Cycles 6940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 525 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 24033 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1178 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.361053 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2983 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1206 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.188997 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 9203 +system.cpu.fetch.rateDist.samples 10979 system.cpu.fetch.rateDist.min_value 0 - 0 5177 5625.34% - 1 291 316.20% - 2 234 254.26% - 3 263 285.78% - 4 314 341.19% - 5 294 319.46% - 6 311 337.93% - 7 262 284.69% - 8 2057 2235.14% + 0 7023 6396.76% + 1 285 259.59% + 2 224 204.03% + 3 248 225.89% + 4 335 305.13% + 5 281 255.94% + 6 301 274.16% + 7 251 228.62% + 8 2031 1849.90% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 2946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 2946 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 4950.682853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency_0 4950.682853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 4079.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 4079.838710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2287 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2287 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 3262500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.223693 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate_0 0.223693 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 659 # number of ReadReq misses -system.cpu.icache.ReadReq_misses_0 659 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 39 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2529500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 2529500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.210455 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.210455 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 620 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 620 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2983 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 5910.313901 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 5152.173913 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2314 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 3954000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.224271 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 669 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 669 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 3199500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.208180 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 621 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.688710 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.726248 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2946 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 2946 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 2983 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2983 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 4950.682853 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 4950.682853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2287 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2287 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2314 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2314 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3262500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 3262500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3954000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 3954000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.223693 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.223693 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.224271 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_misses 659 # number of demand (read+write) misses -system.cpu.icache.demand_misses_0 659 # number of demand (read+write) misses +system.cpu.icache.demand_misses 669 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 669 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 39 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 48 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2529500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 2529500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3199500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 3199500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.210455 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.210455 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.208180 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 620 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 620 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 621 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2946 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 2946 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 2983 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2983 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 4950.682853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 4950.682853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 5910.313901 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 4079.838710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 4079.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 5152.173913 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2287 # number of overall hits -system.cpu.icache.overall_hits_0 2287 # number of overall hits +system.cpu.icache.overall_hits 2314 # number of overall hits +system.cpu.icache.overall_hits_0 2314 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 3262500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 3262500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3954000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 3954000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.223693 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.223693 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.224271 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_misses 659 # number of overall misses -system.cpu.icache.overall_misses_0 659 # number of overall misses +system.cpu.icache.overall_misses 669 # number of overall misses +system.cpu.icache.overall_misses_0 669 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 39 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 39 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 48 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2529500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 2529500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3199500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 3199500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.210455 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.210455 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.208180 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 620 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 620 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 621 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -381,104 +368,104 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 9 # number of replacements system.cpu.icache.replacements_0 9 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 620 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 621 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 315.428279 # Cycle average of tags in use -system.cpu.icache.total_refs 2287 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 322.894952 # Cycle average of tags in use +system.cpu.icache.total_refs 2314 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles -1 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2339 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1175 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1164 # Number of branches executed -system.cpu.iew.EXEC:nop 72 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 36 # number of nop insts executed +system.cpu.idleCycles 1998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2367 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1185 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1182 # Number of branches executed +system.cpu.iew.EXEC:nop 73 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 37 # number of nop insts executed system.cpu.iew.EXEC:nop_1 36 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.666196 # Inst execution rate -system.cpu.iew.EXEC:refs 4928 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2490 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2438 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1865 # Number of stores executed +system.cpu.iew.EXEC:rate 1.416158 # Inst execution rate +system.cpu.iew.EXEC:refs 4978 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2514 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2464 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1867 # Number of stores executed system.cpu.iew.EXEC:stores_0 938 # Number of stores executed -system.cpu.iew.EXEC:stores_1 927 # Number of stores executed +system.cpu.iew.EXEC:stores_1 929 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10157 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5143 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5014 # num instructions consuming a value -system.cpu.iew.WB:count 14949 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7544 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7405 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.769912 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.768229 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.771639 # average fanout of values written-back +system.cpu.iew.WB:consumers 10219 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5113 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5106 # num instructions consuming a value +system.cpu.iew.WB:count 14974 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7532 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7442 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.526960 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.762957 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.764003 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7820 # num instructions producing a value -system.cpu.iew.WB:producers_0 3951 # num instructions producing a value -system.cpu.iew.WB:producers_1 3869 # num instructions producing a value -system.cpu.iew.WB:rate 1.624362 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.819733 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.804629 # insts written-back per cycle -system.cpu.iew.WB:sent 15070 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7606 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7464 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 927 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 6 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3744 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 587 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2137 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 18669 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3063 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1552 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1511 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1008 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 15334 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 7802 # num instructions producing a value +system.cpu.iew.WB:producers_0 3901 # num instructions producing a value +system.cpu.iew.WB:producers_1 3901 # num instructions producing a value +system.cpu.iew.WB:rate 1.363876 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.686037 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.677840 # insts written-back per cycle +system.cpu.iew.WB:sent 15105 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7590 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7515 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 941 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 7 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3823 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 501 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2178 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19078 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3111 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1576 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1535 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 864 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15548 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1407 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1498 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 42 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 56 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 932 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 267 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 946 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 276 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 49 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 38 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 57 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 54 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 246 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 113 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 753 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 174 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.610996 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.611105 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.222101 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8271 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 919 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 278 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 117 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 761 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 180 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.512160 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.512251 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024410 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8232 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5600 67.71% # Type of FU issued + No_OpClass 2 0.02% # Type of FU issued + IntAlu 5551 67.43% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +474,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1701 20.57% # Type of FU issued - MemWrite 965 11.67% # Type of FU issued + MemRead 1704 20.70% # Type of FU issued + MemWrite 972 11.81% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8071 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 8180 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist - (null) 2 0.02% # Type of FU issued - IntAlu 5485 67.96% # Type of FU issued + No_OpClass 2 0.02% # Type of FU issued + IntAlu 5536 67.68% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +491,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1640 20.32% # Type of FU issued - MemWrite 941 11.66% # Type of FU issued + MemRead 1681 20.55% # Type of FU issued + MemWrite 958 11.71% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 16342 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 16412 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist - (null) 4 0.02% # Type of FU issued - IntAlu 11085 67.83% # Type of FU issued + No_OpClass 4 0.02% # Type of FU issued + IntAlu 11087 67.55% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +508,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3341 20.44% # Type of FU issued - MemWrite 1906 11.66% # Type of FU issued + MemRead 3385 20.63% # Type of FU issued + MemWrite 1930 11.76% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 95 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 89 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011259 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.005813 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005446 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 92 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010968 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.005606 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005362 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist - (null) 0 0.00% # attempts to use FU when none available - IntAlu 11 5.98% # attempts to use FU when none available + No_OpClass 0 0.00% # attempts to use FU when none available + IntAlu 16 8.89% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,108 +530,104 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 108 58.70% # attempts to use FU when none available - MemWrite 65 35.33% # attempts to use FU when none available + MemRead 97 53.89% # attempts to use FU when none available + MemWrite 67 37.22% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 9203 +system.cpu.iq.ISSUE:issued_per_cycle.samples 10979 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3452 3750.95% - 1 1399 1520.16% - 2 1479 1607.08% - 3 1070 1162.66% - 4 845 918.18% - 5 528 573.73% - 6 290 315.11% - 7 105 114.09% - 8 35 38.03% + 0 4788 4361.05% + 1 1816 1654.07% + 2 1657 1509.24% + 3 1039 946.35% + 4 774 704.98% + 5 501 456.33% + 6 289 263.23% + 7 90 81.97% + 8 25 22.77% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.775725 # Inst issue rate -system.cpu.iq.iqInstsAdded 18557 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 16342 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 6288 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3616 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 4143.899896 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency_0 4143.899896 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2323.820647 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2323.820647 # average ReadReq mshr miss latency +system.cpu.iq.ISSUE:rate 1.494854 # Inst issue rate +system.cpu.iq.iqInstsAdded 18963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16412 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6896 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 963 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 5220.374220 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 2725.051975 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits_0 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 3974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.998958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate_0 0.998958 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses_0 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2228544 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2228544 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.998958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998958 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses_0 959 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 5022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.998962 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 962 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2621500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.998962 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 962 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 962 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.001043 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.001040 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 960 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 960 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 963 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 963 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 4143.899896 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 4143.899896 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_0 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3974000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 3974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5022000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 5022000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.998958 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.998958 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.998962 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_misses 959 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses_0 959 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 962 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 962 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2228544 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 2228544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 2621500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 2621500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.998958 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.998958 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.998962 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses_0 959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 962 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 960 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 960 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 963 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 963 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 4143.899896 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 4143.899896 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 5220.374220 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2323.820647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2323.820647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 2725.051975 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency @@ -652,26 +635,26 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> system.cpu.l2cache.overall_hits 1 # number of overall hits system.cpu.l2cache.overall_hits_0 1 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3974000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 3974000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5022000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 5022000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.998958 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.998958 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.998962 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_misses 959 # number of overall misses -system.cpu.l2cache.overall_misses_0 959 # number of overall misses +system.cpu.l2cache.overall_misses 962 # number of overall misses +system.cpu.l2cache.overall_misses_0 962 # number of overall misses system.cpu.l2cache.overall_misses_1 0 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2228544 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 2228544 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 2621500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 2621500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.998958 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.998958 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.998962 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses_0 959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 962 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -691,33 +674,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements_0 0 # number of replacements system.cpu.l2cache.replacements_1 0 # number of replacements -system.cpu.l2cache.sampled_refs 959 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 962 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 534.228654 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 545.133409 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 9203 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 514 # Number of cycles rename is blocking +system.cpu.numCycles 10979 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 614 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 11467 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 762 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 26335 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 20742 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 15622 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3447 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1407 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 876 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7520 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 508 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 14840 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 684 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26359 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 20748 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15612 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3480 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1498 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 744 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7510 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 517 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2622 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:skidInsts 2147 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index ea08dc448..6f3d2a7c5 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:11 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:38 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 4600500 because target called exit() +Exiting @ tick 5490000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 1f1e7a355..61102139c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -91,8 +91,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -267,8 +266,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -306,8 +304,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -339,6 +336,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -363,6 +361,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out index ac1dcb9ba..70564f749 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -249,7 +250,7 @@ type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -280,14 +281,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=20 write_buffers=8 @@ -318,14 +318,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -356,7 +355,6 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.toL2Bus] type=Bus @@ -364,4 +362,5 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 8359db0f2..7859d5c2b 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 3154 # Number of BTB hits -global.BPredUnit.BTBLookups 9574 # Number of BTB lookups +global.BPredUnit.BTBHits 2726 # Number of BTB hits +global.BPredUnit.BTBLookups 7230 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2047 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 10459 # Number of conditional branches predicted -global.BPredUnit.lookups 10459 # Number of BP lookups +global.BPredUnit.condIncorrect 2062 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 7954 # Number of conditional branches predicted +global.BPredUnit.lookups 7954 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 26468 # Simulator instruction rate (inst/s) -host_mem_usage 154944 # Number of bytes of host memory used -host_seconds 0.41 # Real time elapsed on the host -host_tick_rate 32157366 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. +host_inst_rate 37089 # Simulator instruction rate (inst/s) +host_mem_usage 154932 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 53780846 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 10 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3573 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 3440 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 3198 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 2970 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13345500 # Number of ticks simulated +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 15931500 # Number of ticks simulated system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 164 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 146 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 23147 +system.cpu.commit.COM:committed_per_cycle.samples 28801 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 17950 7754.78% - 1 2912 1258.05% - 2 993 429.00% - 3 424 183.18% - 4 287 123.99% - 5 235 101.53% - 6 103 44.50% - 7 79 34.13% - 8 164 70.85% + 0 23411 8128.54% + 1 2862 993.72% + 2 1174 407.62% + 3 608 211.10% + 4 359 124.65% + 5 123 42.71% + 6 103 35.76% + 7 15 5.21% + 8 146 50.69% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 1462 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2760 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2047 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2062 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 18321 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14297 # The number of squashed insts skipped by commit system.cpu.committedInsts 10976 # Number of Instructions Simulated system.cpu.committedInsts_total 10976 # Number of Instructions Simulated -system.cpu.cpi 2.431851 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.431851 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2813 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 4311.764706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3546.153846 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2728 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 366500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.030217 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 85 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 230500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.023107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses +system.cpu.cpi 2.903061 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.903061 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2743 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 5392.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4696.969697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2659 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 453000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.030623 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 84 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 310000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.024061 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4645.408163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3470.930233 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1096 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 910500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.151703 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 196 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 110 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 298500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 5505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4802.325581 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1092 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 1101000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.154799 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 200 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 114 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 413000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 25.364238 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 24.717105 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4105 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4544.483986 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3824 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1277000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.068453 # miss rate for demand accesses -system.cpu.dcache.demand_misses 281 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.036784 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 4035 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 5471.830986 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency +system.cpu.dcache.demand_hits 3751 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1554000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.070384 # miss rate for demand accesses +system.cpu.dcache.demand_misses 284 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.037670 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4105 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4544.483986 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3503.311258 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 4035 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 5471.830986 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 4756.578947 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3824 # number of overall hits -system.cpu.dcache.overall_miss_latency 1277000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.068453 # miss rate for overall accesses -system.cpu.dcache.overall_misses 281 # number of overall misses -system.cpu.dcache.overall_mshr_hits 130 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 529000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.036784 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses +system.cpu.dcache.overall_hits 3751 # number of overall hits +system.cpu.dcache.overall_miss_latency 1554000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.070384 # miss rate for overall accesses +system.cpu.dcache.overall_misses 284 # number of overall misses +system.cpu.dcache.overall_mshr_hits 132 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 723000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.037670 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 112.362185 # Cycle average of tags in use -system.cpu.dcache.total_refs 3830 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 113.439038 # Cycle average of tags in use +system.cpu.dcache.total_refs 3757 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4942 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 48420 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8618 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 9347 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 3545 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 240 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 10459 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 5440 # Number of cache lines fetched -system.cpu.fetch.Cycles 16262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 55152 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2110 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.391840 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 5440 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 3154 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.066237 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 4602 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 38937 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 16098 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 7883 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 3063 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 218 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 7954 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4933 # Number of cache lines fetched +system.cpu.fetch.Cycles 14166 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 44421 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2121 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.249623 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4933 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 2726 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.394081 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 26692 +system.cpu.fetch.rateDist.samples 31864 system.cpu.fetch.rateDist.min_value 0 - 0 15871 5945.98% - 1 2250 842.95% - 2 637 238.65% - 3 971 363.78% - 4 550 206.05% - 5 848 317.70% - 6 962 360.41% - 7 321 120.26% - 8 4282 1604.23% + 0 22632 7102.69% + 1 2187 686.35% + 2 562 176.37% + 3 869 272.72% + 4 521 163.51% + 5 770 241.65% + 6 886 278.06% + 7 243 76.26% + 8 3194 1002.39% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 5440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3939.473684 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2944.591029 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5060 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1497000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.069853 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 380 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1116000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.069669 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 4933 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 5310.666667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 4396.174863 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 4558 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1991500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.076019 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 375 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1609000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.074194 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 13.350923 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12.453552 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5440 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3939.473684 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency -system.cpu.icache.demand_hits 5060 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1497000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.069853 # miss rate for demand accesses -system.cpu.icache.demand_misses 380 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1116000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.069669 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 379 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 4933 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 5310.666667 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency +system.cpu.icache.demand_hits 4558 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1991500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.076019 # miss rate for demand accesses +system.cpu.icache.demand_misses 375 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 9 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1609000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.074194 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 366 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5440 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3939.473684 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2944.591029 # average overall mshr miss latency +system.cpu.icache.overall_accesses 4933 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 5310.666667 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 4396.174863 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5060 # number of overall hits -system.cpu.icache.overall_miss_latency 1497000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.069853 # miss rate for overall accesses -system.cpu.icache.overall_misses 380 # number of overall misses -system.cpu.icache.overall_mshr_hits 1 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1116000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.069669 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 379 # number of overall MSHR misses +system.cpu.icache.overall_hits 4558 # number of overall hits +system.cpu.icache.overall_miss_latency 1991500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.076019 # miss rate for overall accesses +system.cpu.icache.overall_misses 375 # number of overall misses +system.cpu.icache.overall_mshr_hits 9 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1609000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.074194 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 366 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,60 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 379 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 366 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 242.916499 # Cycle average of tags in use -system.cpu.icache.total_refs 5060 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 233.760012 # Cycle average of tags in use +system.cpu.icache.total_refs 4558 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 3713 # Number of branches executed +system.cpu.idleCycles 499 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 3548 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.830061 # Inst execution rate -system.cpu.iew.EXEC:refs 5553 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2589 # Number of stores executed +system.cpu.iew.EXEC:rate 0.670318 # Inst execution rate +system.cpu.iew.EXEC:refs 5385 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2502 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10966 # num instructions consuming a value -system.cpu.iew.WB:count 21367 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.799836 # average fanout of values written-back +system.cpu.iew.WB:consumers 10159 # num instructions consuming a value +system.cpu.iew.WB:count 20199 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790629 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8771 # num instructions producing a value -system.cpu.iew.WB:rate 0.800502 # insts written-back per cycle -system.cpu.iew.WB:sent 21712 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2654 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 8032 # num instructions producing a value +system.cpu.iew.WB:rate 0.633913 # insts written-back per cycle +system.cpu.iew.WB:sent 20448 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2568 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3573 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 630 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1509 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 3440 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 29298 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2964 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3437 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 22156 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 3198 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 610 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2750 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2970 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 25274 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2883 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 21359 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 3545 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 3063 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 75 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2111 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 2142 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 75 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1624 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.411209 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.411209 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 25593 # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 52 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1736 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1672 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 52 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1610 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.344464 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.344464 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 22822 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist - (null) 1919 7.50% # Type of FU issued - IntAlu 17231 67.33% # Type of FU issued + (null) 1826 8.00% # Type of FU issued + IntAlu 15247 66.81% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -277,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3429 13.40% # Type of FU issued - MemWrite 3014 11.78% # Type of FU issued + MemRead 3042 13.33% # Type of FU issued + MemWrite 2707 11.86% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 238 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009299 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 190 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008325 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available - IntAlu 99 41.60% # attempts to use FU when none available + IntAlu 50 26.32% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -295,43 +296,43 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 22 9.24% # attempts to use FU when none available - MemWrite 117 49.16% # attempts to use FU when none available + MemRead 25 13.16% # attempts to use FU when none available + MemWrite 115 60.53% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 26692 +system.cpu.iq.ISSUE:issued_per_cycle.samples 31864 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 17644 6610.22% - 1 3262 1222.09% - 2 1371 513.64% - 3 1071 401.24% - 4 1568 587.44% - 5 925 346.55% - 6 579 216.92% - 7 171 64.06% - 8 101 37.84% + 0 22879 7180.20% + 1 3824 1200.10% + 2 1304 409.24% + 3 1251 392.61% + 4 1252 392.92% + 5 751 235.69% + 6 414 129.93% + 7 122 38.29% + 8 67 21.03% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.958827 # Inst issue rate -system.cpu.iq.iqInstsAdded 28668 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 25593 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 630 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 15737 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 303 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 7975 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 526 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3018.060837 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1812.857414 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1587500 # number of ReadReq miss cycles +system.cpu.iq.ISSUE:rate 0.716231 # Inst issue rate +system.cpu.iq.iqInstsAdded 24664 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 22822 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 610 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 11119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 5685 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 514 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 4458.171206 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2373.540856 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 2291500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 526 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 953563 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 514 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1220000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 526 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 514 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. @@ -340,32 +341,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 526 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3018.060837 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 514 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 4458.171206 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1587500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 2291500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 526 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 514 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 953563 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1220000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 526 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 514 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 526 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3018.060837 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1812.857414 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 514 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 4458.171206 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2373.540856 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1587500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 2291500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 526 # number of overall misses +system.cpu.l2cache.overall_misses 514 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 953563 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 1220000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 526 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses 514 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -378,28 +379,28 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 526 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 514 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 353.661697 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 345.564898 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 26692 # number of cpu cycles simulated +system.cpu.numCycles 31864 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 8631 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 59097 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 39751 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 31999 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 9086 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 3545 # Number of cycles rename is squashing -system.cpu.rename.RENAME:SquashedInsts 8167 # Number of squashed instructions processed by rename -system.cpu.rename.RENAME:UnblockCycles 716 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 22131 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 4224 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 665 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4954 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 658 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:IdleCycles 16082 # Number of cycles rename is idle +system.cpu.rename.RENAME:RenameLookups 44650 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 29655 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 24195 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 7618 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 3063 # Number of cycles rename is squashing +system.cpu.rename.RENAME:SquashedInsts 8815 # Number of squashed instructions processed by rename +system.cpu.rename.RENAME:UnblockCycles 684 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 14327 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 3915 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 631 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4702 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 623 # count of temporary serializing insts renamed +system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index 0bb67880e..0b6e54449 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:05 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:06 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 13345500 because target called exit() +Exiting @ tick 15931500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index 7e9c12db2..5493b952f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -48,6 +48,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out index 29915233b..c1a77ba0d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index 22ea72ebd..468b3f0a1 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 430012 # Simulator instruction rate (inst/s) -host_mem_usage 149064 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 207711772 # Simulator tick rate (ticks/s) +host_inst_rate 563720 # Simulator instruction rate (inst/s) +host_mem_usage 149048 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 276035132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated sim_seconds 0.000005 # Number of seconds simulated diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index 66bfb4931..01c59e833 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:06 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 5500000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 394f564a5..2e2789f26 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -171,6 +169,7 @@ uid=100 [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out index 9d999c4c3..df1a9c852 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=LiveProcess @@ -61,13 +62,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -98,14 +100,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -136,14 +137,13 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -174,5 +174,4 @@ prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index aef9433e6..33502bf5c 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 285170 # Simulator instruction rate (inst/s) -host_mem_usage 154424 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 211576923 # Simulator tick rate (ticks/s) +host_inst_rate 346412 # Simulator instruction rate (inst/s) +host_mem_usage 154396 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +host_tick_rate 598818775 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 11001 # Number of instructions simulated -sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 8251500 # Number of ticks simulated +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 19264000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3712.962963 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 200500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 756000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 146500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 702000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3676.136364 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2676.136364 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 1204 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 323500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1232000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.068111 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 88 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1144000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.068111 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 88 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3690.140845 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 2612 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 524000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 1988000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.051561 # miss rate for demand accesses system.cpu.dcache.demand_misses 142 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 382000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 1846000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.051561 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3690.140845 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2690.140845 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 2612 # number of overall hits -system.cpu.dcache.overall_miss_latency 524000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 1988000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.051561 # miss rate for overall accesses system.cpu.dcache.overall_misses 142 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 382000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 1846000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.051561 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 106.692969 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.809387 # Cycle average of tags in use system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 11002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3743.816254 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2743.816254 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 13922.261484 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 12922.261484 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 10719 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1059500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 3940000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.025723 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 776500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 3657000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.025723 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 11002 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3743.816254 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 13922.261484 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency system.cpu.icache.demand_hits 10719 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1059500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 3940000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.025723 # miss rate for demand accesses system.cpu.icache.demand_misses 283 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 776500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 3657000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.025723 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 11002 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3743.816254 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2743.816254 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 13922.261484 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 12922.261484 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 10719 # number of overall hits -system.cpu.icache.overall_miss_latency 1059500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 3940000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.025723 # miss rate for overall accesses system.cpu.icache.overall_misses 283 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 776500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 3657000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.025723 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -140,18 +140,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 170.449932 # Cycle average of tags in use +system.cpu.icache.tagsinuse 163.879834 # Cycle average of tags in use system.cpu.icache.total_refs 10719 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 423 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2730.496454 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1729.496454 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 5499000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 423 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 731577 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 4653000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 423 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -163,29 +163,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 423 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2730.496454 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1155000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 5499000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 731577 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 423 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2730.496454 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1729.496454 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1155000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 5499000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 423 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 731577 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -202,12 +202,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 423 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 276.385948 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 266.922506 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 8251500 # number of cpu cycles simulated +system.cpu.numCycles 19264000 # number of cpu cycles simulated system.cpu.num_insts 11001 # Number of instructions executed system.cpu.num_refs 2760 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index dd4d8d282..c2d31ed8f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -16,9 +16,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2007 20:15:56 -M5 started Sun Apr 22 20:26:07 2007 -M5 executing on zamp.eecs.umich.edu +M5 compiled May 15 2007 13:02:31 +M5 started Tue May 15 17:00:07 2007 +M5 executing on zizzer.eecs.umich.edu command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 8251500 because target called exit() +Exiting @ tick 19264000 because target called exit() diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 8145ecdc4..2d3b1a754 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -5,8 +5,8 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -21,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu0] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -51,21 +56,109 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -85,13 +178,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -99,7 +280,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -118,7 +299,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -140,27 +321,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -200,6 +421,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -209,7 +457,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -220,7 +468,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -235,7 +483,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -245,19 +493,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -302,7 +552,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -318,7 +568,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -334,7 +584,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -350,7 +600,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -366,7 +616,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -382,7 +632,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -398,7 +648,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -414,7 +664,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -430,7 +680,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -446,7 +696,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -462,7 +712,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -478,7 +728,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -494,7 +744,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -510,7 +760,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -526,7 +776,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -542,7 +792,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -558,7 +808,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -574,7 +824,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -590,7 +840,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -607,7 +857,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -615,13 +865,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -665,9 +917,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -678,7 +930,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -696,7 +948,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index e0c23706f..1461f2550 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -11,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -27,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -43,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -55,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=100000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -78,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -96,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -121,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -129,6 +172,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -152,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -160,6 +287,90 @@ function_trace=false function_trace_start=0 simulate_stalls=false +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img @@ -173,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -188,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -203,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -218,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -233,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -248,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -256,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -288,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -308,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -323,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -331,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -346,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -361,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -376,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -391,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -406,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -421,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -436,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -451,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -469,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -510,12 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -524,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -543,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -558,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -566,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -581,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -632,18 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index 2a3b3163d..033bc257f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,89 +1,255 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 674184 # Simulator instruction rate (inst/s) -host_mem_usage 251408 # Number of bytes of host memory used -host_seconds 93.63 # Real time elapsed on the host -host_tick_rate 39952215 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 63122441 # Number of instructions simulated -sim_seconds 1.870326 # Number of seconds simulated -sim_ticks 3740651174 # Number of ticks simulated +host_inst_rate 110028 # Simulator instruction rate (inst/s) +host_seconds 573.73 # Real time elapsed on the host +host_tick_rate 3259967057 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63125943 # Number of instructions simulated +sim_seconds 1.870335 # Number of seconds simulated +sim_ticks 1870335097000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9163941 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits 7464208 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate 0.185481 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1699733 # number of ReadReq misses +system.cpu0.dcache.WriteReq_accesses 5933396 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits 5646723 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate 0.048315 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 286673 # number of WriteReq misses +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.625609 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15097337 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13110931 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.131573 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1986406 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15097337 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13110931 # number of overall hits +system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.131573 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1986406 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1699733 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 2 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 689 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 4128 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 122 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2691 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 241 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 227 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 21 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 14 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1359 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 725 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 282337 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2517 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1819 # write misses to shared blocks +system.cpu0.dcache.replacements 1978969 # number of replacements +system.cpu0.dcache.sampled_refs 1979481 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 504.827576 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13115267 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 0 # number of writebacks system.cpu0.dtb.accesses 698037 # DTB accesses system.cpu0.dtb.acv 251 # DTB access violations -system.cpu0.dtb.hits 15071957 # DTB hits +system.cpu0.dtb.hits 15082969 # DTB hits system.cpu0.dtb.misses 7805 # DTB misses system.cpu0.dtb.read_accesses 508987 # DTB read accesses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_hits 9142249 # DTB read hits +system.cpu0.dtb.read_hits 9148390 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.write_accesses 189050 # DTB write accesses system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_hits 5929708 # DTB write hits +system.cpu0.dtb.write_hits 5934579 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.idle_fraction 0.984720 # Percentage of idle cycles -system.cpu0.itb.accesses 3857497 # ITB accesses +system.cpu0.icache.ReadReq_accesses 57190172 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits 56305300 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate 0.015472 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 884872 # number of ReadReq misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 63.637052 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57190172 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.demand_hits 56305300 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015472 # miss rate for demand accesses +system.cpu0.icache.demand_misses 884872 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57190172 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56305300 # number of overall hits +system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015472 # miss rate for overall accesses +system.cpu0.icache.overall_misses 884872 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 884872 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 25821 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 13268 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 78 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 6 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 884276 # number of replacements +system.cpu0.icache.sampled_refs 884788 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 511.244752 # Cycle average of tags in use +system.cpu0.icache.total_refs 56305300 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles +system.cpu0.itb.accesses 3858835 # ITB accesses system.cpu0.itb.acv 127 # ITB acv -system.cpu0.itb.hits 3854012 # ITB hits +system.cpu0.itb.hits 3855350 # ITB hits system.cpu0.itb.misses 3485 # ITB misses -system.cpu0.kern.callpal 183119 # number of callpals executed +system.cpu0.kern.callpal 183272 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 111 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal_swpctx 3759 2.05% 2.12% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal_swpipl 167881 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal_rdps 6134 3.35% 97.17% # number of callpals executed +system.cpu0.kern.callpal_swpipl 168017 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal_rdusp 7 0.00% 97.17% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 196948 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6163 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174714 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 70932 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 197101 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 174850 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 101623 58.17% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 141281 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 69565 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 101695 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 69557 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3740650759 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3706243742 99.08% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 40220 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 164088 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1899 0.00% 99.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 34200810 0.91% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808642 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.980728 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1870334889500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1853125118000 99.08% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 17106668000 0.91% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.684461 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_31 0.684606 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.mode_good_kernel 1155 system.cpu0.kern.mode_good_user 1156 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 7088 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches system.cpu0.kern.mode_switch_user 1156 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.280325 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.162951 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.162906 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3738736759 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 1913998 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1869377889500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3760 # number of times the context was actually changed +system.cpu0.kern.swap_context 3762 # number of times the context was actually changed system.cpu0.kern.syscall 226 # number of syscalls executed system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed @@ -115,82 +281,249 @@ system.cpu0.kern.syscall_98 2 0.88% 97.35% # nu system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015280 # Percentage of non-idle cycles -system.cpu0.numCycles 57155598 # number of cpu cycles simulated -system.cpu0.num_insts 57151986 # Number of instructions executed -system.cpu0.num_refs 15311384 # Number of memory references +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.numCycles 57193784 # number of cpu cycles simulated +system.cpu0.num_insts 57190172 # Number of instructions executed +system.cpu0.num_refs 15322419 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1167383 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits 1124444 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate 0.036782 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 42939 # number of ReadReq misses +system.cpu1.dcache.WriteReq_accesses 749650 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits 723062 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate 0.035467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 26588 # number of WriteReq misses +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.277705 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1917033 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1847506 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.036268 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 69527 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1917033 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1847506 # number of overall hits +system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.036268 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 69527 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 42939 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 939 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 2438 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 337 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 61769 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 103 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 275 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 44 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 39 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1538 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2755 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 24475 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 641 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1472 # write misses to shared blocks +system.cpu1.dcache.replacements 62341 # number of replacements +system.cpu1.dcache.sampled_refs 62660 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 391.945837 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1834541 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851266669500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 0 # number of writebacks system.cpu1.dtb.accesses 323622 # DTB accesses system.cpu1.dtb.acv 116 # DTB access violations -system.cpu1.dtb.hits 1925043 # DTB hits +system.cpu1.dtb.hits 1914885 # DTB hits system.cpu1.dtb.misses 3692 # DTB misses system.cpu1.dtb.read_accesses 220342 # DTB read accesses system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_hits 1169160 # DTB read hits +system.cpu1.dtb.read_hits 1163439 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.write_accesses 103280 # DTB write accesses system.cpu1.dtb.write_acv 58 # DTB write access violations -system.cpu1.dtb.write_hits 755883 # DTB write hits +system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles -system.cpu1.itb.accesses 1471216 # ITB accesses +system.cpu1.icache.ReadReq_accesses 5935771 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits 5832135 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate 0.017460 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 103636 # number of ReadReq misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 56.289849 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5935771 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.demand_hits 5832135 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017460 # miss rate for demand accesses +system.cpu1.icache.demand_misses 103636 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5935771 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5832135 # number of overall hits +system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017460 # miss rate for overall accesses +system.cpu1.icache.overall_misses 103636 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 103636 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 17328 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 199395 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 25 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 103097 # number of replacements +system.cpu1.icache.sampled_refs 103609 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 427.126314 # Cycle average of tags in use +system.cpu1.icache.total_refs 5832135 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868932665500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.itb.accesses 1469938 # ITB accesses system.cpu1.itb.acv 57 # ITB acv -system.cpu1.itb.hits 1469677 # ITB hits +system.cpu1.itb.hits 1468399 # ITB hits system.cpu1.itb.misses 1539 # ITB misses -system.cpu1.kern.callpal 32267 # number of callpals executed +system.cpu1.kern.callpal 32131 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal_swpctx 472 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal_swpipl 26358 81.69% 83.25% # number of callpals executed -system.cpu1.kern.callpal_rdps 2589 8.02% 91.28% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 91.28% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.01% 91.29% # number of callpals executed -system.cpu1.kern.callpal_rdusp 2 0.01% 91.30% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 91.31% # number of callpals executed -system.cpu1.kern.callpal_rti 2608 8.08% 99.39% # number of callpals executed +system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed +system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed +system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 30985 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 10388 33.53% 33.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 1907 6.15% 39.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 111 0.36% 40.04% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 18579 59.96% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 22663 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3740237191 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3718224753 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 164002 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 28353 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21820083 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.731418 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.999037 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1870124001500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1859122583000 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.552613 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 613 +system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 612 system.cpu1.kern.mode_good_user 580 -system.cpu1.kern.mode_good_idle 33 -system.cpu1.kern.mode_switch_kernel 1034 # number of protection mode switches +system.cpu1.kern.mode_good_idle 32 +system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches system.cpu1.kern.mode_switch_user 580 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 2048 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.334790 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.592843 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.016113 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 2786521 0.07% 0.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1016578 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3735960321 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 473 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 1373909500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1868002152500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 471 # number of times the context was actually changed system.cpu1.kern.syscall 100 # number of syscalls executed system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed @@ -209,10 +542,10 @@ system.cpu1.kern.syscall_71 24 24.00% 89.00% # nu system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles -system.cpu1.numCycles 5972051 # number of cpu cycles simulated -system.cpu1.num_insts 5970455 # Number of instructions executed -system.cpu1.num_refs 1936828 # Number of memory references +system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles +system.cpu1.numCycles 5937367 # number of cpu cycles simulated +system.cpu1.num_insts 5935771 # Number of instructions executed +system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -225,6 +558,68 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306245 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 181107 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.408621 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 125138 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2724155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1782852 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.345539 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941303 # number of ReadReq misses +system.l2c.Writeback_accesses 427632 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 427632 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.242866 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2724155 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 1782852 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.345539 # miss rate for demand accesses +system.l2c.demand_misses 941303 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3151787 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 2210484 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.298657 # miss rate for overall accesses +system.l2c.overall_misses 941303 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 1000779 # number of replacements +system.l2c.sampled_refs 1066159 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.575355 # Cycle average of tags in use +system.l2c.total_refs 2391252 # Total number of references to valid blocks. +system.l2c.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr index 111ccf4f1..3e1cbc554 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr @@ -1,7 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... -warn: 195723: Trying to launch CPU number 1! +warn: 97861500: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index 9ec0f1c3f..e4b69d1d0 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:53:05 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Global frequency set at 2000000000 ticks per second +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 01:04:58 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3740651174 because m5_exit instruction encountered +Exiting @ tick 1870335097000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 26242f3b3..0347fbde9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -5,8 +5,8 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 console=/dist/m5/system/binaries/console init_param=0 @@ -21,17 +21,22 @@ system_type=34 [system.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -51,13 +56,101 @@ progress_interval=0 simulate_stalls=false system=system width=1 -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -65,7 +158,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -84,7 +177,7 @@ read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -106,27 +199,67 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder +block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -166,6 +299,33 @@ type=RawDiskImage image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -175,7 +335,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -186,7 +346,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -201,7 +361,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -211,19 +371,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -268,7 +430,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -284,7 +446,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -300,7 +462,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -316,7 +478,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -332,7 +494,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -348,7 +510,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -364,7 +526,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -380,7 +542,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -396,7 +558,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -412,7 +574,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -428,7 +590,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -444,7 +606,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -460,7 +622,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -476,7 +638,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -492,7 +654,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -508,7 +670,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -524,7 +686,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -540,7 +702,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -556,7 +718,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -573,7 +735,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -581,13 +743,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -631,9 +795,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -644,7 +808,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -662,7 +826,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index 7a0f99013..a196b7dc6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -11,7 +11,7 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=atomic kernel=/dist/m5/system/binaries/vmlinux @@ -27,9 +27,10 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -43,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -55,12 +56,54 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=100000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage @@ -78,7 +121,7 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage @@ -96,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage @@ -111,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -126,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -141,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -156,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -171,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -186,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -194,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -241,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false width=1 @@ -257,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -277,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -292,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -300,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -315,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -330,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -345,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -360,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -375,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -390,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -405,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -420,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -438,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -479,12 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -493,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -512,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -527,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -535,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -550,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -601,18 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true +block_size=64 + +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index de848de68..a2ea188c7 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,31 +1,198 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1069072 # Simulator instruction rate (inst/s) -host_mem_usage 251484 # Number of bytes of host memory used -host_seconds 56.13 # Real time elapsed on the host -host_tick_rate 65146530 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60007301 # Number of instructions simulated -sim_seconds 1.828354 # Number of seconds simulated -sim_ticks 3656708271 # Number of ticks simulated +host_inst_rate 109117 # Simulator instruction rate (inst/s) +host_seconds 549.94 # Real time elapsed on the host +host_tick_rate 3324672454 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60007317 # Number of instructions simulated +sim_seconds 1.828355 # Number of seconds simulated +sim_ticks 1828355481500 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9723333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits 7984499 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate 0.178831 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1738834 # number of ReadReq misses +system.cpu.dcache.WriteReq_accesses 6349447 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits 6045093 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate 0.047934 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304354 # number of WriteReq misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.866570 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16072780 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_hits 14029592 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127121 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2043188 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16072780 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14029592 # number of overall hits +system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127121 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2043188 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1738834 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 1 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 10 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 2 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 124 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304342 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2042663 # number of replacements +system.cpu.dcache.sampled_refs 2043175 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.997801 # Cycle average of tags in use +system.cpu.dcache.total_refs 14029604 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16053817 # DTB hits +system.cpu.dtb.hits 16053818 # DTB hits system.cpu.dtb.misses 11471 # DTB misses system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9703849 # DTB read hits +system.cpu.dtb.read_hits 9703850 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6349968 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.icache.ReadReq_accesses 60007317 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits 59087263 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate 0.015332 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 920054 # number of ReadReq misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 64.229545 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60007317 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_hits 59087263 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015332 # miss rate for demand accesses +system.cpu.icache.demand_misses 920054 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60007317 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59087263 # number of overall hits +system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015332 # miss rate for overall accesses +system.cpu.icache.overall_misses 920054 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 920054 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 643 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1039 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 105 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 9 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 919427 # number of replacements +system.cpu.icache.sampled_refs 919939 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 511.214820 # Cycle average of tags in use +system.cpu.icache.total_refs 59087263 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0.983588 # Percentage of idle cycles -system.cpu.itb.accesses 4979206 # ITB accesses +system.cpu.itb.accesses 4979217 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4974200 # ITB hits +system.cpu.itb.hits 4974211 # ITB hits system.cpu.itb.misses 5006 # ITB misses -system.cpu.kern.callpal 192138 # number of callpals executed +system.cpu.kern.callpal 192139 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed @@ -33,7 +200,7 @@ system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal_swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal_swpipl 175209 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal_swpipl 175210 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal_rdps 6770 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed @@ -43,41 +210,40 @@ system.cpu.kern.callpal_rti 5202 2.71% 99.64% # nu system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211276 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211277 # number of hwrei instructions executed system.cpu.kern.inst.quiesce 6240 # number of quiesce instructions executed -system.cpu.kern.ipl_count 182520 # number of times we switched to this ipl +system.cpu.kern.ipl_count 182521 # number of times we switched to this ipl system.cpu.kern.ipl_count_0 74815 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count_22 1865 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 105597 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 105598 57.86% 100.00% # number of times we switched to this ipl system.cpu.kern.ipl_good 149004 # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_0 73448 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_22 1865 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_31 73448 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3656707856 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3622172407 99.06% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 40220 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 160390 0.00% 99.06% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 34334839 0.94% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.816371 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks 1828355274000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1811087543000 99.06% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 20110000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 80195000 0.00% 99.06% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 17167426000 0.94% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_used_0 0.981728 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.695550 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1907 -system.cpu.kern.mode_good_user 1736 +system.cpu.kern.ipl_used_31 0.695543 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1908 +system.cpu.kern.mode_good_user 1737 system.cpu.kern.mode_good_idle 171 system.cpu.kern.mode_switch_kernel 5948 # number of protection mode switches -system.cpu.kern.mode_switch_user 1736 # number of protection mode switches +system.cpu.kern.mode_switch_user 1737 # number of protection mode switches system.cpu.kern.mode_switch_idle 2097 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389940 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.320612 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good 1.402325 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.320780 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 53668047 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 2930128 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3600109679 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_kernel 26834026500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1800056177500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed @@ -111,9 +277,9 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 60012491 # number of cpu cycles simulated -system.cpu.num_insts 60007301 # Number of instructions executed -system.cpu.num_refs 16302128 # Number of memory references +system.cpu.numCycles 60012507 # number of cpu cycles simulated +system.cpu.num_insts 60007317 # Number of instructions executed +system.cpu.num_refs 16302129 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -126,6 +292,68 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304342 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits 187346 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate 0.384423 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116996 # number of ReadExReq misses +system.l2c.ReadReq_accesses 2658871 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits 1717827 # number of ReadReq hits +system.l2c.ReadReq_miss_rate 0.353926 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941044 # number of ReadReq misses +system.l2c.Writeback_accesses 428885 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 428885 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.205900 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2658871 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.demand_hits 1717827 # number of demand (read+write) hits +system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.353926 # miss rate for demand accesses +system.l2c.demand_misses 941044 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3087756 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.l2c.overall_hits 2146712 # number of overall hits +system.l2c.overall_miss_latency 0 # number of overall miss cycles +system.l2c.overall_miss_rate 0.304766 # miss rate for overall accesses +system.l2c.overall_misses 941044 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 0 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992432 # number of replacements +system.l2c.sampled_refs 1057820 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65517.661064 # Cycle average of tags in use +system.l2c.total_refs 2333445 # Total number of references to valid blocks. +system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 0 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr index 969291745..f34493a86 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr @@ -1,5 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index c3a1cb464..6a6b8d735 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:52:08 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Global frequency set at 2000000000 ticks per second +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 00:55:45 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3656708271 because m5_exit instruction encountered +Exiting @ tick 1828355481500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 8e1ba179d..552344dcb 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -5,14 +5,14 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/Users/ali/work/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/Users/ali/work/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/Users/ali/work/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -21,10 +21,10 @@ system_type=34 [system.bridge] type=Bridge -delay=0 +delay=50000 fix_partial_write_a=false fix_partial_write_b=true -nack_delay=0 +nack_delay=4000 req_size_a=16 req_size_b=16 resp_size_a=16 @@ -35,8 +35,8 @@ side_b=system.membus.port[0] [system.cpu0] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -54,21 +54,109 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu0.dtb] type=AlphaDTB size=64 +[system.cpu0.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu0.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu0.itb] type=AlphaITB size=48 [system.cpu1] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=1 defer_registration=false do_checkpoint_insts=true @@ -86,13 +174,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[5] -icache_port=system.membus.port[4] +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.port[4] + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu1.dtb] type=AlphaDTB size=64 +[system.cpu1.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.port[3] + +[system.cpu1.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu1.itb] type=AlphaITB size=48 @@ -100,7 +276,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -113,13 +289,13 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -132,7 +308,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -143,27 +319,65 @@ sys=system type=Bus block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port +port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -200,9 +414,36 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -212,7 +453,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -223,7 +464,7 @@ type=AlphaConsole cpu=system.cpu0 disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -238,7 +479,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -248,21 +489,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 -max_backoff_delay=20000 -min_backoff_delay=8 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -307,7 +548,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -323,7 +564,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -339,7 +580,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -355,7 +596,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -371,7 +612,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -387,7 +628,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -403,7 +644,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -419,7 +660,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -435,7 +676,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -451,7 +692,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -467,7 +708,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -483,7 +724,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -499,7 +740,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -515,7 +756,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -531,7 +772,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -547,7 +788,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -563,7 +804,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -579,7 +820,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -595,7 +836,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -612,7 +853,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -620,15 +861,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 -max_backoff_delay=20000 -min_backoff_delay=8 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -672,9 +913,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -685,7 +926,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -703,7 +944,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index 890030c19..bb98fee3e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -11,12 +11,12 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing -kernel=/Users/ali/work/system/binaries/vmlinux -console=/Users/ali/work/system/binaries/console -pal=/Users/ali/work/system/binaries/ts_osfpal +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -27,7 +27,7 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false block_size=64 @@ -44,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -56,21 +56,58 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=100000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge req_size_a=16 req_size_b=16 resp_size_a=16 resp_size_b=16 -delay=0 -nack_delay=0 +delay=50000 +nack_delay=4000 write_ack=false fix_partial_write_a=false fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -84,11 +121,11 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -102,7 +139,7 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.cpu0.itb] type=AlphaITB @@ -127,7 +164,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -135,6 +172,90 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu0.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu0.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu0.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu0.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.cpu1.itb] type=AlphaITB size=48 @@ -158,7 +279,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -166,9 +287,93 @@ function_trace=false function_trace_start=0 // simulate_stalls not specified +[system.cpu1.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu1.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu1.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu1.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -179,7 +384,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -194,7 +399,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -209,7 +414,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -224,7 +429,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -239,7 +444,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -254,7 +459,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -262,8 +467,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -294,12 +499,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu0 platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -314,7 +519,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -329,7 +534,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -337,7 +542,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -352,7 +557,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -367,7 +572,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -382,7 +587,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -397,7 +602,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -412,7 +617,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -427,7 +632,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -442,7 +647,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -457,7 +662,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -475,7 +680,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -516,14 +721,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -532,9 +737,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -551,7 +756,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -566,7 +771,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -574,7 +779,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -589,7 +794,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -640,21 +845,44 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true block_size=64 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index e808b031d..0e86983a6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,221 +1,603 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 159511 # Simulator instruction rate (inst/s) -host_seconds 408.44 # Real time elapsed on the host -host_tick_rate 9737848 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 65151264 # Number of instructions simulated -sim_seconds 1.988681 # Number of seconds simulated -sim_ticks 3977362808 # Number of ticks simulated -system.cpu0.dtb.accesses 676531 # DTB accesses -system.cpu0.dtb.acv 306 # DTB access violations -system.cpu0.dtb.hits 12726999 # DTB hits -system.cpu0.dtb.misses 8261 # DTB misses -system.cpu0.dtb.read_accesses 494241 # DTB read accesses -system.cpu0.dtb.read_acv 184 # DTB read access violations -system.cpu0.dtb.read_hits 7906690 # DTB read hits -system.cpu0.dtb.read_misses 7534 # DTB read misses -system.cpu0.dtb.write_accesses 182290 # DTB write accesses -system.cpu0.dtb.write_acv 122 # DTB write access violations -system.cpu0.dtb.write_hits 4820309 # DTB write hits -system.cpu0.dtb.write_misses 727 # DTB write misses -system.cpu0.idle_fraction 0.930953 # Percentage of idle cycles -system.cpu0.itb.accesses 3412195 # ITB accesses -system.cpu0.itb.acv 161 # ITB acv -system.cpu0.itb.hits 3408362 # ITB hits -system.cpu0.itb.misses 3833 # ITB misses -system.cpu0.kern.callpal 142550 # number of callpals executed +host_inst_rate 62524 # Simulator instruction rate (inst/s) +host_seconds 1011.60 # Real time elapsed on the host +host_tick_rate 1928760125 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 63248814 # Number of instructions simulated +sim_seconds 1.951129 # Number of seconds simulated +sim_ticks 1951129131000 # Number of ticks simulated +system.cpu0.dcache.ReadReq_accesses 9299202 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 13073.177688 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12073.152824 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 7589849 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 22346675500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.183817 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 1709353 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_miss_latency 20637280000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.183817 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 1709353 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable 6873 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu0.dcache.ReadResp_mshr_uncacheable_latency 841915000 # number of ReadResp MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_accesses 6016348 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 12644.438594 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 11630.972878 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 5727689 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 3649931000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.047979 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 288659 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 3357385000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.047979 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 288659 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable 9698 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu0.dcache.WriteResp_mshr_uncacheable_latency 1186164500 # number of WriteResp MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 6.687909 # Average number of references to valid blocks. +system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.demand_accesses 15315550 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 13317538 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 25996606500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.130456 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 1998012 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 23994665000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.130456 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 1998012 # number of demand (read+write) MSHR misses +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.overall_accesses 15315550 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 13011.236419 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 12009.269714 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_hits 13317538 # number of overall hits +system.cpu0.dcache.overall_miss_latency 25996606500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.130456 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 1998012 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 23994665000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.130456 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 1998012 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses 16571 # number of overall MSHR uncacheable misses +system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.dcache.protocol.read_invalid 1709421 # read misses to invalid blocks +system.cpu0.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.dcache.protocol.snoop_read_exclusive 908 # read snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_read_modified 3762 # read snoops on modified blocks +system.cpu0.dcache.protocol.snoop_read_owned 72 # read snoops on owned blocks +system.cpu0.dcache.protocol.snoop_read_shared 2297 # read snoops on shared blocks +system.cpu0.dcache.protocol.snoop_readex_exclusive 235 # readEx snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_readex_modified 207 # readEx snoops on modified blocks +system.cpu0.dcache.protocol.snoop_readex_owned 15 # readEx snoops on owned blocks +system.cpu0.dcache.protocol.snoop_readex_shared 7 # readEx snoops on shared blocks +system.cpu0.dcache.protocol.snoop_upgrade_owned 1074 # upgrade snoops on owned blocks +system.cpu0.dcache.protocol.snoop_upgrade_shared 726 # upgradee snoops on shared blocks +system.cpu0.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.dcache.protocol.write_invalid 284810 # write misses to invalid blocks +system.cpu0.dcache.protocol.write_owned 2533 # write misses to owned blocks +system.cpu0.dcache.protocol.write_shared 1354 # write misses to shared blocks +system.cpu0.dcache.replacements 1991354 # number of replacements +system.cpu0.dcache.sampled_refs 1991866 # Sample count of references to valid blocks. +system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.tagsinuse 503.775443 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13321418 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 57953000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 401606 # number of writebacks +system.cpu0.dtb.accesses 719860 # DTB accesses +system.cpu0.dtb.acv 289 # DTB access violations +system.cpu0.dtb.hits 15299767 # DTB hits +system.cpu0.dtb.misses 8485 # DTB misses +system.cpu0.dtb.read_accesses 524201 # DTB read accesses +system.cpu0.dtb.read_acv 174 # DTB read access violations +system.cpu0.dtb.read_hits 9282693 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses +system.cpu0.dtb.write_accesses 195659 # DTB write accesses +system.cpu0.dtb.write_acv 115 # DTB write access violations +system.cpu0.dtb.write_hits 6017074 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses +system.cpu0.icache.ReadReq_accesses 57872551 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 12029.752588 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11029.000057 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 56957639 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 11006165000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.015809 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 914912 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_miss_latency 10090564500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.015809 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 914912 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu0.icache.avg_refs 62.632934 # Average number of references to valid blocks. +system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.demand_accesses 57872551 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.demand_hits 56957639 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 11006165000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.015809 # miss rate for demand accesses +system.cpu0.icache.demand_misses 914912 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 10090564500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.015809 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 914912 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses 57872551 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 12029.752588 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 11029.000057 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits 56957639 # number of overall hits +system.cpu0.icache.overall_miss_latency 11006165000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.015809 # miss rate for overall accesses +system.cpu0.icache.overall_misses 914912 # number of overall misses +system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 10090564500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.015809 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 914912 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu0.icache.protocol.read_invalid 915158 # read misses to invalid blocks +system.cpu0.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu0.icache.protocol.snoop_read_exclusive 4652 # read snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu0.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu0.icache.protocol.snoop_read_shared 8768 # read snoops on shared blocks +system.cpu0.icache.protocol.snoop_readex_exclusive 121 # readEx snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu0.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu0.icache.protocol.snoop_readex_shared 1 # readEx snoops on shared blocks +system.cpu0.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu0.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu0.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu0.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu0.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu0.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu0.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu0.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu0.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu0.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu0.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu0.icache.replacements 908876 # number of replacements +system.cpu0.icache.sampled_refs 909388 # Sample count of references to valid blocks. +system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.tagsinuse 508.806183 # Cycle average of tags in use +system.cpu0.icache.total_refs 56957639 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 34906249000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 0 # number of writebacks +system.cpu0.idle_fraction 0.943968 # Percentage of idle cycles +system.cpu0.itb.accesses 3944641 # ITB accesses +system.cpu0.itb.acv 143 # ITB acv +system.cpu0.itb.hits 3940800 # ITB hits +system.cpu0.itb.misses 3841 # ITB misses +system.cpu0.kern.callpal 187118 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 572 0.40% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # number of callpals executed -system.cpu0.kern.callpal_swpctx 2878 2.02% 2.42% # number of callpals executed -system.cpu0.kern.callpal_tbi 47 0.03% 2.46% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal_swpipl 127700 89.58% 92.04% # number of callpals executed -system.cpu0.kern.callpal_rdps 6611 4.64% 96.68% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_wrusp 3 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal_rdusp 8 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal_rti 4215 2.96% 99.65% # number of callpals executed -system.cpu0.kern.callpal_callsys 355 0.25% 99.90% # number of callpals executed -system.cpu0.kern.callpal_imb 147 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 96 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal_swpctx 3865 2.07% 2.12% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 2.14% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 2.15% # number of callpals executed +system.cpu0.kern.callpal_swpipl 171254 91.52% 93.67% # number of callpals executed +system.cpu0.kern.callpal_rdps 6635 3.55% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.21% # number of callpals executed +system.cpu0.kern.callpal_wrusp 4 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rdusp 7 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal_rti 4694 2.51% 99.73% # number of callpals executed +system.cpu0.kern.callpal_callsys 356 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal_imb 149 0.08% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 157735 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6620 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 134538 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 53716 39.93% 39.93% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 131 0.10% 40.02% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 2009 1.49% 41.52% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 482 0.36% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78200 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 108740 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 53300 49.02% 49.02% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 131 0.12% 49.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 2009 1.85% 50.98% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 482 0.44% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 52818 48.57% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3976579702 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3843619308 96.66% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 123584 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1873872 0.05% 96.71% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.74% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 129761186 3.26% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808247 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.992256 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 201983 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6162 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 178054 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72322 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 131 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 1968 1.11% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 103627 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 144005 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 70953 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 1968 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 70947 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 1951128432000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 1894864204500 97.12% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 72482500 0.00% 97.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 564462000 0.03% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 4114000 0.00% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 55623169000 2.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used_0 0.981071 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.675422 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1193 -system.cpu0.kern.mode_good_user 1193 +system.cpu0.kern.ipl_used_31 0.684638 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1230 +system.cpu0.kern.mode_good_user 1231 system.cpu0.kern.mode_good_idle 0 -system.cpu0.kern.mode_switch_kernel 6700 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1193 # number of protection mode switches +system.cpu0.kern.mode_switch_kernel 7215 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1231 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.302293 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.178060 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.170478 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3965295376 99.76% 99.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 9600934 0.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 1947973402000 99.84% 99.84% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3155028000 0.16% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2879 # number of times the context was actually changed -system.cpu0.kern.syscall 216 # number of syscalls executed -system.cpu0.kern.syscall_2 7 3.24% 3.24% # number of syscalls executed -system.cpu0.kern.syscall_3 18 8.33% 11.57% # number of syscalls executed -system.cpu0.kern.syscall_4 3 1.39% 12.96% # number of syscalls executed -system.cpu0.kern.syscall_6 30 13.89% 26.85% # number of syscalls executed -system.cpu0.kern.syscall_12 1 0.46% 27.31% # number of syscalls executed -system.cpu0.kern.syscall_15 1 0.46% 27.78% # number of syscalls executed -system.cpu0.kern.syscall_17 9 4.17% 31.94% # number of syscalls executed -system.cpu0.kern.syscall_19 6 2.78% 34.72% # number of syscalls executed -system.cpu0.kern.syscall_20 4 1.85% 36.57% # number of syscalls executed -system.cpu0.kern.syscall_23 2 0.93% 37.50% # number of syscalls executed -system.cpu0.kern.syscall_24 4 1.85% 39.35% # number of syscalls executed -system.cpu0.kern.syscall_33 7 3.24% 42.59% # number of syscalls executed -system.cpu0.kern.syscall_41 2 0.93% 43.52% # number of syscalls executed -system.cpu0.kern.syscall_45 36 16.67% 60.19% # number of syscalls executed -system.cpu0.kern.syscall_47 4 1.85% 62.04% # number of syscalls executed -system.cpu0.kern.syscall_48 8 3.70% 65.74% # number of syscalls executed -system.cpu0.kern.syscall_54 9 4.17% 69.91% # number of syscalls executed -system.cpu0.kern.syscall_58 1 0.46% 70.37% # number of syscalls executed -system.cpu0.kern.syscall_59 6 2.78% 73.15% # number of syscalls executed -system.cpu0.kern.syscall_71 28 12.96% 86.11% # number of syscalls executed -system.cpu0.kern.syscall_73 3 1.39% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_74 8 3.70% 91.20% # number of syscalls executed -system.cpu0.kern.syscall_87 1 0.46% 91.67% # number of syscalls executed -system.cpu0.kern.syscall_90 2 0.93% 92.59% # number of syscalls executed -system.cpu0.kern.syscall_92 7 3.24% 95.83% # number of syscalls executed -system.cpu0.kern.syscall_97 2 0.93% 96.76% # number of syscalls executed -system.cpu0.kern.syscall_98 2 0.93% 97.69% # number of syscalls executed -system.cpu0.kern.syscall_132 2 0.93% 98.61% # number of syscalls executed -system.cpu0.kern.syscall_144 1 0.46% 99.07% # number of syscalls executed -system.cpu0.kern.syscall_147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.069047 # Percentage of non-idle cycles -system.cpu0.numCycles 3976579942 # number of cpu cycles simulated -system.cpu0.num_insts 50252314 # Number of instructions executed -system.cpu0.num_refs 12958725 # Number of memory references -system.cpu1.dtb.accesses 346252 # DTB accesses -system.cpu1.dtb.acv 67 # DTB access violations -system.cpu1.dtb.hits 4740996 # DTB hits -system.cpu1.dtb.misses 3345 # DTB misses -system.cpu1.dtb.read_accesses 235843 # DTB read accesses -system.cpu1.dtb.read_acv 26 # DTB read access violations -system.cpu1.dtb.read_hits 2707487 # DTB read hits -system.cpu1.dtb.read_misses 2918 # DTB read misses -system.cpu1.dtb.write_accesses 110409 # DTB write accesses -system.cpu1.dtb.write_acv 41 # DTB write access violations -system.cpu1.dtb.write_hits 2033509 # DTB write hits -system.cpu1.dtb.write_misses 427 # DTB write misses -system.cpu1.idle_fraction 0.974578 # Percentage of idle cycles -system.cpu1.itb.accesses 2097175 # ITB accesses -system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 2095903 # ITB hits -system.cpu1.itb.misses 1272 # ITB misses -system.cpu1.kern.callpal 80960 # number of callpals executed +system.cpu0.kern.swap_context 3866 # number of times the context was actually changed +system.cpu0.kern.syscall 224 # number of syscalls executed +system.cpu0.kern.syscall_2 6 2.68% 2.68% # number of syscalls executed +system.cpu0.kern.syscall_3 19 8.48% 11.16% # number of syscalls executed +system.cpu0.kern.syscall_4 3 1.34% 12.50% # number of syscalls executed +system.cpu0.kern.syscall_6 30 13.39% 25.89% # number of syscalls executed +system.cpu0.kern.syscall_12 1 0.45% 26.34% # number of syscalls executed +system.cpu0.kern.syscall_15 1 0.45% 26.79% # number of syscalls executed +system.cpu0.kern.syscall_17 10 4.46% 31.25% # number of syscalls executed +system.cpu0.kern.syscall_19 6 2.68% 33.93% # number of syscalls executed +system.cpu0.kern.syscall_20 4 1.79% 35.71% # number of syscalls executed +system.cpu0.kern.syscall_23 2 0.89% 36.61% # number of syscalls executed +system.cpu0.kern.syscall_24 4 1.79% 38.39% # number of syscalls executed +system.cpu0.kern.syscall_33 8 3.57% 41.96% # number of syscalls executed +system.cpu0.kern.syscall_41 2 0.89% 42.86% # number of syscalls executed +system.cpu0.kern.syscall_45 39 17.41% 60.27% # number of syscalls executed +system.cpu0.kern.syscall_47 4 1.79% 62.05% # number of syscalls executed +system.cpu0.kern.syscall_48 7 3.12% 65.18% # number of syscalls executed +system.cpu0.kern.syscall_54 9 4.02% 69.20% # number of syscalls executed +system.cpu0.kern.syscall_58 1 0.45% 69.64% # number of syscalls executed +system.cpu0.kern.syscall_59 5 2.23% 71.88% # number of syscalls executed +system.cpu0.kern.syscall_71 32 14.29% 86.16% # number of syscalls executed +system.cpu0.kern.syscall_73 3 1.34% 87.50% # number of syscalls executed +system.cpu0.kern.syscall_74 9 4.02% 91.52% # number of syscalls executed +system.cpu0.kern.syscall_87 1 0.45% 91.96% # number of syscalls executed +system.cpu0.kern.syscall_90 2 0.89% 92.86% # number of syscalls executed +system.cpu0.kern.syscall_92 7 3.12% 95.98% # number of syscalls executed +system.cpu0.kern.syscall_97 2 0.89% 96.87% # number of syscalls executed +system.cpu0.kern.syscall_98 2 0.89% 97.77% # number of syscalls executed +system.cpu0.kern.syscall_132 2 0.89% 98.66% # number of syscalls executed +system.cpu0.kern.syscall_144 1 0.45% 99.11% # number of syscalls executed +system.cpu0.kern.syscall_147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.056032 # Percentage of non-idle cycles +system.cpu0.numCycles 1951129131000 # number of cpu cycles simulated +system.cpu0.num_insts 57872550 # Number of instructions executed +system.cpu0.num_refs 15541096 # Number of memory references +system.cpu1.dcache.ReadReq_accesses 1052558 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 11119.734481 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10119.576119 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 1014670 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 421304500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.035996 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses 37888 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_miss_latency 383410500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035996 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 37888 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable 120 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu1.dcache.ReadResp_mshr_uncacheable_latency 14641500 # number of ReadResp MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_accesses 677186 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 11920.138166 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 10843.231096 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 653157 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 286429000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.035484 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 24029 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 260552000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.035484 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 24029 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable 2496 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu1.dcache.WriteResp_mshr_uncacheable_latency 304596500 # number of WriteResp MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 29.876823 # Average number of references to valid blocks. +system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses 1729744 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 1667827 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 707733500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.035795 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 61917 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 643962500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.035795 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 61917 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses 1729744 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 11430.358383 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 10400.415072 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits 1667827 # number of overall hits +system.cpu1.dcache.overall_miss_latency 707733500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.035795 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 61917 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 643962500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.035795 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 61917 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_misses 2616 # number of overall MSHR uncacheable misses +system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.dcache.protocol.read_invalid 37951 # read misses to invalid blocks +system.cpu1.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.dcache.protocol.snoop_read_exclusive 906 # read snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_read_modified 1965 # read snoops on modified blocks +system.cpu1.dcache.protocol.snoop_read_owned 254 # read snoops on owned blocks +system.cpu1.dcache.protocol.snoop_read_shared 65869 # read snoops on shared blocks +system.cpu1.dcache.protocol.snoop_readex_exclusive 191 # readEx snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_readex_modified 198 # readEx snoops on modified blocks +system.cpu1.dcache.protocol.snoop_readex_owned 48 # readEx snoops on owned blocks +system.cpu1.dcache.protocol.snoop_readex_shared 42 # readEx snoops on shared blocks +system.cpu1.dcache.protocol.snoop_upgrade_owned 1132 # upgrade snoops on owned blocks +system.cpu1.dcache.protocol.snoop_upgrade_shared 2716 # upgradee snoops on shared blocks +system.cpu1.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.dcache.protocol.write_invalid 22206 # write misses to invalid blocks +system.cpu1.dcache.protocol.write_owned 601 # write misses to owned blocks +system.cpu1.dcache.protocol.write_shared 1247 # write misses to shared blocks +system.cpu1.dcache.replacements 55360 # number of replacements +system.cpu1.dcache.sampled_refs 55749 # Sample count of references to valid blocks. +system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.tagsinuse 388.749341 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1665603 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1935095598000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 27663 # number of writebacks +system.cpu1.dtb.accesses 302878 # DTB accesses +system.cpu1.dtb.acv 84 # DTB access violations +system.cpu1.dtb.hits 1728432 # DTB hits +system.cpu1.dtb.misses 3106 # DTB misses +system.cpu1.dtb.read_accesses 205838 # DTB read accesses +system.cpu1.dtb.read_acv 36 # DTB read access violations +system.cpu1.dtb.read_hits 1049360 # DTB read hits +system.cpu1.dtb.read_misses 2750 # DTB read misses +system.cpu1.dtb.write_accesses 97040 # DTB write accesses +system.cpu1.dtb.write_acv 48 # DTB write access violations +system.cpu1.dtb.write_hits 679072 # DTB write hits +system.cpu1.dtb.write_misses 356 # DTB write misses +system.cpu1.icache.ReadReq_accesses 5376264 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 12045.939531 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11045.466957 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 5281041 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 1147050500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.017712 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 95223 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency 1051782500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.017712 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 95223 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu1.icache.avg_refs 57.662729 # Average number of references to valid blocks. +system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses 5376264 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.demand_hits 5281041 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 1147050500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.017712 # miss rate for demand accesses +system.cpu1.icache.demand_misses 95223 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 1051782500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.017712 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 95223 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses 5376264 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 12045.939531 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11045.466957 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits 5281041 # number of overall hits +system.cpu1.icache.overall_miss_latency 1147050500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.017712 # miss rate for overall accesses +system.cpu1.icache.overall_misses 95223 # number of overall misses +system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 1051782500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.017712 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 95223 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu1.icache.protocol.read_invalid 97341 # read misses to invalid blocks +system.cpu1.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu1.icache.protocol.snoop_read_exclusive 39627 # read snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu1.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu1.icache.protocol.snoop_read_shared 214588 # read snoops on shared blocks +system.cpu1.icache.protocol.snoop_readex_exclusive 26 # readEx snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu1.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu1.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu1.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu1.icache.protocol.snoop_upgrade_shared 2 # upgradee snoops on shared blocks +system.cpu1.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu1.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu1.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu1.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu1.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu1.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu1.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu1.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu1.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu1.icache.replacements 91073 # number of replacements +system.cpu1.icache.sampled_refs 91585 # Sample count of references to valid blocks. +system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.tagsinuse 420.500398 # Cycle average of tags in use +system.cpu1.icache.total_refs 5281041 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1947911714000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 0 # number of writebacks +system.cpu1.idle_fraction 0.995322 # Percentage of idle cycles +system.cpu1.itb.accesses 1399877 # ITB accesses +system.cpu1.itb.acv 41 # ITB acv +system.cpu1.itb.hits 1398631 # ITB hits +system.cpu1.itb.misses 1246 # ITB misses +system.cpu1.kern.callpal 29847 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 482 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal_swpctx 2289 2.83% 3.43% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71572 88.40% 91.85% # number of callpals executed -system.cpu1.kern.callpal_rdps 2303 2.84% 94.69% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_rdusp 1 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.00% 94.70% # number of callpals executed -system.cpu1.kern.callpal_rti 4092 5.05% 99.76% # number of callpals executed -system.cpu1.kern.callpal_callsys 162 0.20% 99.96% # number of callpals executed -system.cpu1.kern.callpal_imb 33 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal_wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal_swpctx 375 1.26% 1.29% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.03% 1.32% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.02% 1.34% # number of callpals executed +system.cpu1.kern.callpal_swpipl 24461 81.95% 83.30% # number of callpals executed +system.cpu1.kern.callpal_rdps 2201 7.37% 90.67% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 90.68% # number of callpals executed +system.cpu1.kern.callpal_wrusp 3 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.01% 90.69% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 90.70% # number of callpals executed +system.cpu1.kern.callpal_rti 2582 8.65% 99.35% # number of callpals executed +system.cpu1.kern.callpal_callsys 161 0.54% 99.89% # number of callpals executed +system.cpu1.kern.callpal_imb 31 0.10% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 88242 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 2815 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 78238 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30461 38.93% 38.93% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 2001 2.56% 41.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 572 0.73% 42.22% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45204 57.78% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 61001 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29500 48.36% 48.36% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 2001 3.28% 51.64% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 572 0.94% 52.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 28928 47.42% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3977361024 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3855399740 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1871566 0.05% 96.98% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 1461344 0.04% 97.02% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118628374 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.779685 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.968451 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 36385 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 2332 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 29103 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 9344 32.11% 32.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 1963 6.75% 38.85% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 96 0.33% 39.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 17700 60.82% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 20635 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 9336 45.24% 45.24% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 1963 9.51% 54.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 96 0.47% 55.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 9240 44.78% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 1950372731000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 1911409272000 98.00% 98.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 494740000 0.03% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 52316000 0.00% 98.03% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 38416403000 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used_0 0.999144 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.639943 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 1058 -system.cpu1.kern.mode_good_user 562 -system.cpu1.kern.mode_good_idle 496 -system.cpu1.kern.mode_switch_kernel 2397 # number of protection mode switches -system.cpu1.kern.mode_switch_user 562 # number of protection mode switches -system.cpu1.kern.mode_switch_idle 3035 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.353020 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.441385 # fraction of useful protection mode switches +system.cpu1.kern.ipl_used_31 0.522034 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 538 +system.cpu1.kern.mode_good_user 517 +system.cpu1.kern.mode_good_idle 21 +system.cpu1.kern.mode_switch_kernel 884 # number of protection mode switches +system.cpu1.kern.mode_switch_user 517 # number of protection mode switches +system.cpu1.kern.mode_switch_idle 2075 # number of protection mode switches +system.cpu1.kern.mode_switch_good 1.618718 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.608597 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle 0.163427 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 64032120 1.61% 1.61% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 5754658 0.14% 1.75% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3907574238 98.25% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2290 # number of times the context was actually changed -system.cpu1.kern.syscall 110 # number of syscalls executed -system.cpu1.kern.syscall_2 1 0.91% 0.91% # number of syscalls executed -system.cpu1.kern.syscall_3 12 10.91% 11.82% # number of syscalls executed -system.cpu1.kern.syscall_4 1 0.91% 12.73% # number of syscalls executed -system.cpu1.kern.syscall_6 12 10.91% 23.64% # number of syscalls executed -system.cpu1.kern.syscall_17 6 5.45% 29.09% # number of syscalls executed -system.cpu1.kern.syscall_19 4 3.64% 32.73% # number of syscalls executed -system.cpu1.kern.syscall_20 2 1.82% 34.55% # number of syscalls executed -system.cpu1.kern.syscall_23 2 1.82% 36.36% # number of syscalls executed -system.cpu1.kern.syscall_24 2 1.82% 38.18% # number of syscalls executed -system.cpu1.kern.syscall_33 4 3.64% 41.82% # number of syscalls executed -system.cpu1.kern.syscall_45 18 16.36% 58.18% # number of syscalls executed -system.cpu1.kern.syscall_47 2 1.82% 60.00% # number of syscalls executed -system.cpu1.kern.syscall_48 2 1.82% 61.82% # number of syscalls executed -system.cpu1.kern.syscall_54 1 0.91% 62.73% # number of syscalls executed -system.cpu1.kern.syscall_59 1 0.91% 63.64% # number of syscalls executed -system.cpu1.kern.syscall_71 26 23.64% 87.27% # number of syscalls executed -system.cpu1.kern.syscall_74 8 7.27% 94.55% # number of syscalls executed -system.cpu1.kern.syscall_90 1 0.91% 95.45% # number of syscalls executed -system.cpu1.kern.syscall_92 2 1.82% 97.27% # number of syscalls executed -system.cpu1.kern.syscall_132 2 1.82% 99.09% # number of syscalls executed -system.cpu1.kern.syscall_144 1 0.91% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.025422 # Percentage of non-idle cycles -system.cpu1.numCycles 3977362808 # number of cpu cycles simulated -system.cpu1.num_insts 14898950 # Number of instructions executed -system.cpu1.num_refs 4770935 # Number of memory references +system.cpu1.kern.mode_switch_good_idle 0.010120 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 3563216000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1513259000 0.08% 0.26% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 1945257297000 99.74% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 376 # number of times the context was actually changed +system.cpu1.kern.syscall 102 # number of syscalls executed +system.cpu1.kern.syscall_2 2 1.96% 1.96% # number of syscalls executed +system.cpu1.kern.syscall_3 11 10.78% 12.75% # number of syscalls executed +system.cpu1.kern.syscall_4 1 0.98% 13.73% # number of syscalls executed +system.cpu1.kern.syscall_6 12 11.76% 25.49% # number of syscalls executed +system.cpu1.kern.syscall_17 5 4.90% 30.39% # number of syscalls executed +system.cpu1.kern.syscall_19 4 3.92% 34.31% # number of syscalls executed +system.cpu1.kern.syscall_20 2 1.96% 36.27% # number of syscalls executed +system.cpu1.kern.syscall_23 2 1.96% 38.24% # number of syscalls executed +system.cpu1.kern.syscall_24 2 1.96% 40.20% # number of syscalls executed +system.cpu1.kern.syscall_33 3 2.94% 43.14% # number of syscalls executed +system.cpu1.kern.syscall_45 15 14.71% 57.84% # number of syscalls executed +system.cpu1.kern.syscall_47 2 1.96% 59.80% # number of syscalls executed +system.cpu1.kern.syscall_48 3 2.94% 62.75% # number of syscalls executed +system.cpu1.kern.syscall_54 1 0.98% 63.73% # number of syscalls executed +system.cpu1.kern.syscall_59 2 1.96% 65.69% # number of syscalls executed +system.cpu1.kern.syscall_71 22 21.57% 87.25% # number of syscalls executed +system.cpu1.kern.syscall_74 7 6.86% 94.12% # number of syscalls executed +system.cpu1.kern.syscall_90 1 0.98% 95.10% # number of syscalls executed +system.cpu1.kern.syscall_92 2 1.96% 97.06% # number of syscalls executed +system.cpu1.kern.syscall_132 2 1.96% 99.02% # number of syscalls executed +system.cpu1.kern.syscall_144 1 0.98% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.004678 # Percentage of non-idle cycles +system.cpu1.numCycles 1950372761000 # number of cpu cycles simulated +system.cpu1.num_insts 5376264 # Number of instructions executed +system.cpu1.num_refs 1738417 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -228,6 +610,91 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 306499 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 12998.029396 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 10997.988681 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 183694 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1596223000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.400670 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 122805 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1350608000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.400670 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 122805 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2751323 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 12999.901707 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 10999.990968 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1810263 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12233687500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.342039 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 941060 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 10351530500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.342035 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 941049 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6993 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 779629500 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 12194 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1356619000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429269 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429256 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.000030 # miss rate for Writeback accesses +system.l2c.Writeback_misses 13 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.000030 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 13 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.277768 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2751323 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 12999.901707 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.demand_hits 1810263 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12233687500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.342039 # miss rate for demand accesses +system.l2c.demand_misses 941060 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10351530500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.342035 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 941049 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3180592 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 12999.722126 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 10999.990968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2239519 # number of overall hits +system.l2c.overall_miss_latency 12233687500 # number of overall miss cycles +system.l2c.overall_miss_rate 0.295880 # miss rate for overall accesses +system.l2c.overall_misses 941073 # number of overall misses +system.l2c.overall_mshr_hits 11 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10351530500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.295872 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 941049 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 19187 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 998318 # number of replacements +system.l2c.sampled_refs 1063854 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65469.787238 # Cycle average of tags in use +system.l2c.total_refs 2423213 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3064127000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 79556 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr index 9d86a655e..af0df3710 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr @@ -1,7 +1,5 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 warn: Entering event queue @ 0. Starting simulation... -warn: 1082476: Trying to launch CPU number 1! +warn: 423901000: Trying to launch CPU number 1! diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index ebf8b13c8..68b58c461 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:57:20 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Global frequency set at 2000000000 ticks per second +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 01:30:38 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3977364868 because m5_exit instruction encountered +Exiting @ tick 1951129131000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 65aa9c7e6..c726f11fe 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -5,14 +5,14 @@ dummy=0 [system] type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami -boot_cpu_frequency=1 +children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/Users/ali/work/system/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/Users/ali/work/system/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/Users/ali/work/system/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -21,10 +21,10 @@ system_type=34 [system.bridge] type=Bridge -delay=0 +delay=50000 fix_partial_write_a=false fix_partial_write_b=true -nack_delay=0 +nack_delay=4000 req_size_a=16 req_size_b=16 resp_size_a=16 @@ -35,8 +35,8 @@ side_b=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb -clock=1 +children=dcache dtb icache itb +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -54,13 +54,101 @@ phase=0 profile=0 progress_interval=0 system=system -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=4 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.toL2Bus.port[2] + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi [system.cpu.dtb] type=AlphaDTB size=64 +[system.cpu.icache] +type=BaseCache +children=protocol +adaptive_compression=false +assoc=1 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=1000 +lifo=false +max_miss_count=0 +mshrs=4 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +repl=Null +size=32768 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.toL2Bus.port[1] + +[system.cpu.icache.protocol] +type=CoherenceProtocol +do_upgrades=true +protocol=moesi + [system.cpu.itb] type=AlphaITB size=48 @@ -68,7 +156,7 @@ size=48 [system.disk0] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk0.image @@ -81,13 +169,13 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] type=IdeDisk children=image -delay=2000 +delay=1000000 driveID=master image=system.disk2.image @@ -100,7 +188,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -111,27 +199,65 @@ sys=system type=Bus block_size=64 bus_id=0 -clock=2 +clock=1000 responder_set=true width=64 default=system.tsunami.pciconfig.pio port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma +[system.l2c] +type=BaseCache +adaptive_compression=false +assoc=8 +block_size=64 +compressed_bus=false +compression_latency=0 +hash_delay=1 +latency=10000 +lifo=false +max_miss_count=0 +mshrs=92 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=4194304 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.port[0] +mem_side=system.membus.port[2] + [system.membus] type=Bus children=responder block_size=64 bus_id=1 -clock=2 +clock=1000 responder_set=false width=64 default=system.membus.responder.pio -port=system.bridge.side_b system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 platform=system.tsunami ret_bad_addr=true @@ -168,9 +294,36 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true +[system.toL2Bus] +type=Bus +children=responder +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +default=system.toL2Bus.responder.pio +port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +platform=system.tsunami +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.toL2Bus.default + [system.tsunami] type=Tsunami children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart @@ -180,7 +333,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -191,7 +344,7 @@ type=AlphaConsole cpu=system.cpu disk=system.simple_disk pio_addr=8804682956800 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -206,7 +359,7 @@ peer=Null type=NSGigE children=configdata clock=0 -config_latency=40 +config_latency=20000 configdata=system.tsunami.ethernet.configdata dma_data_free=false dma_desc_free=false @@ -216,21 +369,21 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 -intr_delay=20000 -max_backoff_delay=20000 -min_backoff_delay=8 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami rss=false -rx_delay=2000 +rx_delay=1000000 rx_fifo_size=524288 rx_filter=true rx_thread=false system=system -tx_delay=2000 +tx_delay=1000000 tx_fifo_size=524288 tx_thread=false config=system.iobus.port[28] @@ -275,7 +428,7 @@ VendorID=4107 [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 platform=system.tsunami ret_bad_addr=false @@ -291,7 +444,7 @@ pio=system.iobus.port[9] [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -307,7 +460,7 @@ pio=system.iobus.port[20] [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -323,7 +476,7 @@ pio=system.iobus.port[21] [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -339,7 +492,7 @@ pio=system.iobus.port[10] [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -355,7 +508,7 @@ pio=system.iobus.port[12] [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -371,7 +524,7 @@ pio=system.iobus.port[13] [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -387,7 +540,7 @@ pio=system.iobus.port[14] [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -403,7 +556,7 @@ pio=system.iobus.port[15] [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -419,7 +572,7 @@ pio=system.iobus.port[16] [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -435,7 +588,7 @@ pio=system.iobus.port[17] [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -451,7 +604,7 @@ pio=system.iobus.port[18] [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -467,7 +620,7 @@ pio=system.iobus.port[19] [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -483,7 +636,7 @@ pio=system.iobus.port[11] [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -499,7 +652,7 @@ pio=system.iobus.port[8] [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -515,7 +668,7 @@ pio=system.iobus.port[3] [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -531,7 +684,7 @@ pio=system.iobus.port[4] [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -547,7 +700,7 @@ pio=system.iobus.port[5] [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -563,7 +716,7 @@ pio=system.iobus.port[6] [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 platform=system.tsunami ret_bad_addr=false @@ -580,7 +733,7 @@ pio=system.iobus.port[7] type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system pio=system.iobus.port[22] @@ -588,15 +741,15 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController children=configdata -config_latency=40 +config_latency=20000 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 -max_backoff_delay=20000 -min_backoff_delay=8 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system config=system.iobus.port[30] @@ -640,9 +793,9 @@ VendorID=32902 [system.tsunami.io] type=TsunamiIO -frequency=1953125 +frequency=976562500 pio_addr=8804615847936 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -653,7 +806,7 @@ pio=system.iobus.port[23] [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -671,7 +824,7 @@ pio=system.iobus.default [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index 1034abd0e..e0e32bce4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -11,12 +11,12 @@ zero=false [system] type=LinuxAlphaSystem -boot_cpu_frequency=1 +boot_cpu_frequency=500 physmem=system.physmem mem_mode=timing -kernel=/Users/ali/work/system/binaries/vmlinux -console=/Users/ali/work/system/binaries/console -pal=/Users/ali/work/system/binaries/ts_osfpal +kernel=/dist/m5/system/binaries/vmlinux +console=/dist/m5/system/binaries/console +pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -27,7 +27,7 @@ system_rev=1024 [system.membus] type=Bus bus_id=1 -clock=2 +clock=1000 width=64 responder_set=false block_size=64 @@ -44,7 +44,7 @@ intrctrl=system.intrctrl [system.membus.responder] type=IsaFake pio_addr=0 -pio_latency=0 +pio_latency=1 pio_size=8 ret_bad_addr=true update_data=false @@ -56,21 +56,58 @@ ret_data64=18446744073709551615 platform=system.tsunami system=system +[system.l2c] +type=BaseCache +size=4194304 +assoc=8 +block_size=64 +latency=10000 +mshrs=92 +tgts_per_mshr=16 +write_buffers=8 +prioritizeRequests=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=100000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + [system.bridge] type=Bridge req_size_a=16 req_size_b=16 resp_size_a=16 resp_size_b=16 -delay=0 -nack_delay=0 +delay=50000 +nack_delay=4000 write_ack=false fix_partial_write_a=false fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -84,11 +121,11 @@ read_only=false type=IdeDisk image=system.disk0.image driveID=master -delay=2000 +delay=1000000 [system.disk2.image.child] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -102,11 +139,11 @@ read_only=false type=IdeDisk image=system.disk2.image driveID=master -delay=2000 +delay=1000000 [system.simple_disk.disk] type=RawDiskImage -image_file=/Users/ali/work/system/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -117,7 +154,7 @@ disk=system.simple_disk.disk [system.tsunami.fake_uart1] type=IsaFake pio_addr=8804615848696 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -132,7 +169,7 @@ system=system [system.tsunami.fake_uart2] type=IsaFake pio_addr=8804615848936 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -147,7 +184,7 @@ system=system [system.tsunami.fake_uart3] type=IsaFake pio_addr=8804615848680 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -162,7 +199,7 @@ system=system [system.tsunami.fake_uart4] type=IsaFake pio_addr=8804615848944 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -177,7 +214,7 @@ system=system [system.tsunami.fake_ppc] type=IsaFake pio_addr=8804615848891 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -192,7 +229,7 @@ system=system [system.tsunami.cchip] type=TsunamiCChip pio_addr=8803072344064 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -200,8 +237,8 @@ tsunami=system.tsunami [system.tsunami.io] type=TsunamiIO pio_addr=8804615847936 -pio_latency=2 -frequency=1953125 +pio_latency=1000 +frequency=976562500 platform=system.tsunami system=system time=2009 1 1 0 0 0 3 1 @@ -247,7 +284,7 @@ profile=0 do_quiesce=true do_checkpoint_insts=true do_statistics_insts=true -clock=1 +clock=500 phase=0 defer_registration=false // width not specified @@ -263,12 +300,12 @@ pio_addr=8804682956800 system=system cpu=system.cpu platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.fake_ata1] type=IsaFake pio_addr=8804615848304 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -283,7 +320,7 @@ system=system [system.tsunami.fake_ata0] type=IsaFake pio_addr=8804615848432 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -298,7 +335,7 @@ system=system [system.tsunami.pchip] type=TsunamiPChip pio_addr=8802535473152 -pio_latency=2 +pio_latency=1000 platform=system.tsunami system=system tsunami=system.tsunami @@ -306,7 +343,7 @@ tsunami=system.tsunami [system.tsunami.fake_pnp_read3] type=IsaFake pio_addr=8804615848643 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -321,7 +358,7 @@ system=system [system.tsunami.fake_pnp_read2] type=IsaFake pio_addr=8804615848579 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -336,7 +373,7 @@ system=system [system.tsunami.fake_pnp_read1] type=IsaFake pio_addr=8804615848515 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -351,7 +388,7 @@ system=system [system.tsunami.fake_pnp_read0] type=IsaFake pio_addr=8804615848451 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -366,7 +403,7 @@ system=system [system.tsunami.fake_pnp_read7] type=IsaFake pio_addr=8804615848899 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -381,7 +418,7 @@ system=system [system.tsunami.fake_pnp_read6] type=IsaFake pio_addr=8804615848835 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -396,7 +433,7 @@ system=system [system.tsunami.fake_pnp_read5] type=IsaFake pio_addr=8804615848771 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -411,7 +448,7 @@ system=system [system.tsunami.fake_pnp_read4] type=IsaFake pio_addr=8804615848707 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -426,7 +463,7 @@ system=system [system.tsunami.fake_pnp_write] type=IsaFake pio_addr=8804615850617 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -444,7 +481,7 @@ devicename=FrameBuffer pio_addr=8804615848912 system=system platform=system.tsunami -pio_latency=2 +pio_latency=1000 [system.tsunami.ethernet.configdata] type=PciConfigData @@ -485,14 +522,14 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 clock=0 dma_desc_free=false dma_data_free=false @@ -501,9 +538,9 @@ dma_write_delay=0 dma_read_factor=0 dma_write_factor=0 dma_no_allocate=true -intr_delay=20000 -rx_delay=2000 -tx_delay=2000 +intr_delay=10000000 +rx_delay=1000000 +tx_delay=1000000 rx_fifo_size=524288 tx_fifo_size=524288 rx_filter=true @@ -520,7 +557,7 @@ device=system.tsunami.ethernet [system.tsunami.fake_OROM] type=IsaFake pio_addr=8796093677568 -pio_latency=2 +pio_latency=1000 pio_size=393216 ret_bad_addr=false update_data=false @@ -535,7 +572,7 @@ system=system [system.tsunami.uart] type=Uart8250 pio_addr=8804615848952 -pio_latency=2 +pio_latency=1000 platform=system.tsunami sim_console=system.sim_console system=system @@ -543,7 +580,7 @@ system=system [system.tsunami.fake_sm_chip] type=IsaFake pio_addr=8804615848816 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -558,7 +595,7 @@ system=system [system.tsunami.fake_pnp_addr] type=IsaFake pio_addr=8804615848569 -pio_latency=2 +pio_latency=1000 pio_size=8 ret_bad_addr=false update_data=false @@ -609,21 +646,128 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami -min_backoff_delay=8 -max_backoff_delay=20000 +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=2 -config_latency=40 +pio_latency=1000 +config_latency=20000 disks=system.disk0 system.disk2 +[system.toL2Bus] +type=Bus +bus_id=0 +clock=1000 +width=64 +responder_set=false +block_size=64 + +[system.toL2Bus.responder] +type=IsaFake +pio_addr=0 +pio_latency=1 +pio_size=8 +ret_bad_addr=true +update_data=false +warn_access= +ret_data8=255 +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +platform=system.tsunami +system=system + [system.iobus] type=Bus bus_id=0 -clock=2 +clock=1000 width=64 responder_set=true block_size=64 +[system.cpu.icache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.icache] +type=BaseCache +size=32768 +assoc=1 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.icache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + +[system.cpu.dcache.protocol] +type=CoherenceProtocol +protocol=moesi +do_upgrades=true + +[system.cpu.dcache] +type=BaseCache +size=32768 +assoc=4 +block_size=64 +latency=1000 +mshrs=4 +tgts_per_mshr=8 +write_buffers=8 +prioritizeRequests=false +protocol=system.cpu.dcache.protocol +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10000 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false + diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 466fb2d27..f72789e4b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,83 +1,274 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 233672 # Simulator instruction rate (inst/s) -host_seconds 257.14 # Real time elapsed on the host -host_tick_rate 15108417 # Simulator tick rate (ticks/s) -sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60085488 # Number of instructions simulated -sim_seconds 1.942464 # Number of seconds simulated -sim_ticks 3884928812 # Number of ticks simulated -system.cpu.dtb.accesses 1020784 # DTB accesses +host_inst_rate 62427 # Simulator instruction rate (inst/s) +host_seconds 961.73 # Real time elapsed on the host +host_tick_rate 1983042717 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60037406 # Number of instructions simulated +sim_seconds 1.907146 # Number of seconds simulated +sim_ticks 1907146437000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 9726331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 13065.219101 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12065.192690 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 7984648 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 22755470000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.179069 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1741683 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 21013741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.179069 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1741683 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.cpu.dcache.ReadResp_mshr_uncacheable_latency 824099000 # number of ReadResp MSHR uncacheable cycles +system.cpu.dcache.WriteReq_accesses 6350552 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 12768.106941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11768.067509 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6046235 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3885552000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.047920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 304317 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 3581223000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.047920 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 304317 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.cpu.dcache.WriteResp_mshr_uncacheable_latency 1154484000 # number of WriteResp MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 6.857760 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 16076883 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.demand_hits 14030883 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26641022000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.127263 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2046000 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 24594964000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.127263 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2046000 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 16076883 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 13021.027370 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12020.999022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 14030883 # number of overall hits +system.cpu.dcache.overall_miss_latency 26641022000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.127263 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2046000 # number of overall misses +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 24594964000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.127263 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2046000 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.dcache.protocol.read_invalid 1741683 # read misses to invalid blocks +system.cpu.dcache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.dcache.protocol.snoop_read_exclusive 9 # read snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_read_modified 15 # read snoops on modified blocks +system.cpu.dcache.protocol.snoop_read_owned 4 # read snoops on owned blocks +system.cpu.dcache.protocol.snoop_read_shared 92 # read snoops on shared blocks +system.cpu.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blocks +system.cpu.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.dcache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blocks +system.cpu.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.dcache.protocol.write_invalid 304305 # write misses to invalid blocks +system.cpu.dcache.protocol.write_owned 8 # write misses to owned blocks +system.cpu.dcache.protocol.write_shared 4 # write misses to shared blocks +system.cpu.dcache.replacements 2045476 # number of replacements +system.cpu.dcache.sampled_refs 2045988 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 511.987904 # Cycle average of tags in use +system.cpu.dcache.total_refs 14030895 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 57945000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 429989 # number of writebacks +system.cpu.dtb.accesses 1020787 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16070353 # DTB hits -system.cpu.dtb.misses 11466 # DTB misses -system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.hits 16057425 # DTB hits +system.cpu.dtb.misses 11471 # DTB misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9714571 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9706740 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6355782 # DTB write hits +system.cpu.dtb.write_hits 6350685 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.idle_fraction 0.921526 # Percentage of idle cycles -system.cpu.itb.accesses 4985698 # ITB accesses +system.cpu.icache.ReadReq_accesses 60037407 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 12029.456206 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11028.713640 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 59110217 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11153591500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.015444 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 927190 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 10225713000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.015444 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 927190 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 63.763003 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 60037407 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.demand_hits 59110217 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11153591500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.015444 # miss rate for demand accesses +system.cpu.icache.demand_misses 927190 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10225713000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.015444 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 927190 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 60037407 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 12029.456206 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11028.713640 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 59110217 # number of overall hits +system.cpu.icache.overall_miss_latency 11153591500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.015444 # miss rate for overall accesses +system.cpu.icache.overall_misses 927190 # number of overall misses +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10225713000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.015444 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 927190 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks +system.cpu.icache.protocol.read_invalid 927190 # read misses to invalid blocks +system.cpu.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks +system.cpu.icache.protocol.snoop_read_exclusive 644 # read snoops on exclusive blocks +system.cpu.icache.protocol.snoop_read_modified 0 # read snoops on modified blocks +system.cpu.icache.protocol.snoop_read_owned 0 # read snoops on owned blocks +system.cpu.icache.protocol.snoop_read_shared 1040 # read snoops on shared blocks +system.cpu.icache.protocol.snoop_readex_exclusive 146 # readEx snoops on exclusive blocks +system.cpu.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blocks +system.cpu.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blocks +system.cpu.icache.protocol.snoop_readex_shared 2 # readEx snoops on shared blocks +system.cpu.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blocks +system.cpu.icache.protocol.snoop_upgrade_shared 12 # upgradee snoops on shared blocks +system.cpu.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks +system.cpu.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks +system.cpu.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks +system.cpu.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks +system.cpu.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks +system.cpu.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks +system.cpu.icache.protocol.write_invalid 0 # write misses to invalid blocks +system.cpu.icache.protocol.write_owned 0 # write misses to owned blocks +system.cpu.icache.protocol.write_shared 0 # write misses to shared blocks +system.cpu.icache.replacements 926519 # number of replacements +system.cpu.icache.sampled_refs 927030 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 508.761542 # Cycle average of tags in use +system.cpu.icache.total_refs 59110217 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 34634685000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.idle_fraction 0.940784 # Percentage of idle cycles +system.cpu.itb.accesses 4977586 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4980688 # ITB hits -system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193483 # number of callpals executed +system.cpu.itb.hits 4972580 # ITB hits +system.cpu.itb.misses 5006 # ITB misses +system.cpu.kern.callpal 192752 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4144 2.14% 2.14% # number of callpals executed -system.cpu.kern.callpal_tbi 54 0.03% 2.17% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 2.18% # number of callpals executed -system.cpu.kern.callpal_swpipl 176511 91.23% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6861 3.55% 96.95% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed -system.cpu.kern.callpal_wrusp 7 0.00% 96.95% # number of callpals executed -system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rti 5187 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal_swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed +system.cpu.kern.callpal_swpipl 175824 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal_rdps 6824 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal_rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal_rti 5148 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212605 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6153 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183792 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75069 40.84% 40.84% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 131 0.07% 40.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1962 1.07% 41.98% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106630 58.02% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149497 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73702 49.30% 49.30% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1962 1.31% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73702 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3884927028 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3757863794 96.73% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 112456 0.00% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 918216 0.02% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126032562 3.24% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.813403 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.981790 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211836 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6181 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183027 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74862 40.90% 40.90% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 131 0.07% 40.97% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 1923 1.05% 42.02% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106111 57.98% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149044 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73495 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 1923 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73495 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 1907145727000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 1851261210000 97.07% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 73754500 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 531976500 0.03% 97.10% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 55278786000 2.90% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used_0 0.981740 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691194 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1895 -system.cpu.kern.mode_good_user 1742 -system.cpu.kern.mode_good_idle 153 -system.cpu.kern.mode_switch_kernel 5935 # number of protection mode switches -system.cpu.kern.mode_switch_user 1742 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2062 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389157 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319292 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.692624 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1910 +system.cpu.kern.mode_good_user 1740 +system.cpu.kern.mode_good_idle 170 +system.cpu.kern.mode_switch_kernel 5894 # number of protection mode switches +system.cpu.kern.mode_switch_user 1740 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch_good 1.405165 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.324058 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.074200 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 112890486 2.91% 2.91% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 15209884 0.39% 3.30% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3756826650 96.70% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4145 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 42657550000 2.24% 2.24% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4648649000 0.24% 2.48% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 1859839526000 97.52% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -109,10 +300,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.078474 # Percentage of non-idle cycles -system.cpu.numCycles 3884928812 # number of cpu cycles simulated -system.cpu.num_insts 60085488 # Number of instructions executed -system.cpu.num_refs 16318244 # Number of memory references +system.cpu.not_idle_fraction 0.059216 # Percentage of non-idle cycles +system.cpu.numCycles 1907146437000 # number of cpu cycles simulated +system.cpu.num_insts 60037406 # Number of instructions executed +system.cpu.num_refs 16305563 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -125,6 +316,86 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.l2c.ReadExReq_accesses 304305 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 13000.153945 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 11000.153945 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 187380 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 1520043000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.384236 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 116925 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 1286193000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.384236 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 116925 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 2668854 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 13000.065889 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 11000.065889 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 1727874 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 12232802000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.352578 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 940980 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 10350842000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.352578 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 940980 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 6727 # number of ReadReq MSHR uncacheable +system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency +system.l2c.ReadResp_mshr_uncacheable_latency 750102000 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 9438 # number of WriteReq MSHR uncacheable +system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency +system.l2c.WriteResp_mshr_uncacheable_latency 1050666000 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 429989 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 429989 # number of Writeback hits +system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.l2c.avg_refs 2.216875 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses 2668854 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.demand_hits 1727874 # number of demand (read+write) hits +system.l2c.demand_miss_latency 12232802000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.352578 # miss rate for demand accesses +system.l2c.demand_misses 940980 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 10350842000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.352578 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 940980 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses 3098843 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 13000.065889 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 11000.065889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency +system.l2c.overall_hits 2157863 # number of overall hits +system.l2c.overall_miss_latency 12232802000 # number of overall miss cycles +system.l2c.overall_miss_rate 0.303655 # miss rate for overall accesses +system.l2c.overall_misses 940980 # number of overall misses +system.l2c.overall_mshr_hits 0 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 10350842000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.303655 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 940980 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses 16165 # number of overall MSHR uncacheable misses +system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.l2c.replacements 992369 # number of replacements +system.l2c.sampled_refs 1057905 # Sample count of references to valid blocks. +system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.tagsinuse 65468.856552 # Cycle average of tags in use +system.l2c.total_refs 2345243 # Total number of references to valid blocks. +system.l2c.warmup_cycle 3045832000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 74072 # number of writebacks system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr index 969291745..f34493a86 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr @@ -1,5 +1,3 @@ -Warning: rounding error > tolerance - 0.002000 rounded to 0 Listening for system connection on port 3456 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 427d90ea3..db9ad862d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 13:54:39 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Global frequency set at 2000000000 ticks per second +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 01:14:34 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing +Global frequency set at 1000000000000 ticks per second 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 3883112324 because m5_exit instruction encountered +Exiting @ tick 1907146437000 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index 0c1dbb0ba..a89c6ef26 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -39,11 +39,12 @@ system=system [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 5e988f3f9..73c363bc4 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=EioProcess diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index bc0a96087..5747db5c2 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 689098 # Simulator instruction rate (inst/s) -host_mem_usage 147724 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host -host_tick_rate 344128671 # Simulator tick rate (ticks/s) +host_inst_rate 188118 # Simulator instruction rate (inst/s) +host_seconds 2.66 # Real time elapsed on the host +host_tick_rate 94046824 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index 47ee09274..01450bbce 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:12 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:41 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 249999500 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index eef4c0a1a..e20143b89 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -36,8 +36,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -45,7 +44,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -75,8 +74,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=10 @@ -84,7 +82,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -114,8 +112,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=10000 lifo=false max_miss_count=0 mshrs=10 @@ -123,7 +120,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -147,6 +144,7 @@ mem_side=system.membus.port[1] [system.cpu.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false @@ -162,11 +160,12 @@ system=system [system.membus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=false width=64 -port=system.physmem.port system.cpu.l2cache.mem_side +port=system.physmem.port[0] system.cpu.l2cache.mem_side [system.physmem] type=PhysicalMemory diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index e897b733f..e85a0bee1 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -20,6 +20,7 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.workload] type=EioProcess @@ -52,13 +53,14 @@ bus_id=0 clock=1000 width=64 responder_set=false +block_size=64 [system.cpu.icache] type=BaseCache size=131072 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -83,20 +85,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.dcache] type=BaseCache size=262144 assoc=2 block_size=64 -latency=1 +latency=1000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -121,20 +122,19 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu.l2cache] type=BaseCache size=2097152 assoc=2 block_size=64 -latency=1 +latency=10000 mshrs=10 tgts_per_mshr=5 write_buffers=8 @@ -159,11 +159,10 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index a6caa5891..2ec710e81 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,31 +1,30 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 518674 # Simulator instruction rate (inst/s) -host_mem_usage 153108 # Number of bytes of host memory used -host_seconds 0.96 # Real time elapsed on the host -host_tick_rate 355827019 # Simulator tick rate (ticks/s) +host_inst_rate 83773 # Simulator instruction rate (inst/s) +host_seconds 5.97 # Real time elapsed on the host +host_tick_rate 115920990 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated -sim_seconds 0.000343 # Number of seconds simulated -sim_ticks 343161000 # Number of ticks simulated +sim_seconds 0.000692 # Number of seconds simulated +sim_ticks 691915000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3793.650794 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2793.650794 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1195000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4410000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 880000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4095000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3600.719424 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2600.719424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 500500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 1946000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 361500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1807000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +36,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3734.581498 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1695500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 6356000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1241500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5902000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3734.581498 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 180321 # number of overall hits -system.cpu.dcache.overall_miss_latency 1695500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 6356000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1241500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5902000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -76,18 +75,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 291.533202 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 290.922203 # Cycle average of tags in use system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3739.454094 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2739.454094 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1507000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 5642000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 1104000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 5239000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -99,29 +98,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3739.454094 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1507000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 5642000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses system.cpu.icache.demand_misses 403 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1104000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 5239000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3739.454094 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_hits 499597 # number of overall hits -system.cpu.icache.overall_miss_latency 1507000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 5642000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses system.cpu.icache.overall_misses 403 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1104000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 5239000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,18 +137,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 268.106513 # Cycle average of tags in use +system.cpu.icache.tagsinuse 267.665433 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2736.872812 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1735.872812 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 2345500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_miss_latency 11141000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1487643 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 9427000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -161,29 +160,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2736.872812 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2345500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 11141000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1487643 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 9427000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2736.872812 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2345500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 11141000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1487643 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 9427000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -200,12 +199,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 559.642213 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 558.588875 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 343161000 # number of cpu cycles simulated +system.cpu.numCycles 691915000 # number of cpu cycles simulated system.cpu.num_insts 500000 # Number of instructions executed system.cpu.num_refs 182203 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 8126fb0fb..a580fa457 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,9 +7,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:14 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:44 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing Global frequency set at 1000000000000 ticks per second -Exiting @ tick 343161000 because a thread reached the max instruction count +Exiting @ tick 691915000 because a thread reached the max instruction count diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 363cb64d4..e30600052 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -22,7 +22,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.port +functional=system.funcmem.port[0] test=system.cpu0.l1c.cpu_side [system.cpu0.l1c] @@ -34,8 +34,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -43,7 +42,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -83,7 +82,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[1] test=system.cpu1.l1c.cpu_side [system.cpu1.l1c] @@ -95,8 +94,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -104,7 +102,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -144,7 +142,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[2] test=system.cpu2.l1c.cpu_side [system.cpu2.l1c] @@ -156,8 +154,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -165,7 +162,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -205,7 +202,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[3] test=system.cpu3.l1c.cpu_side [system.cpu3.l1c] @@ -217,8 +214,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -226,7 +222,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -266,7 +262,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[4] test=system.cpu4.l1c.cpu_side [system.cpu4.l1c] @@ -278,8 +274,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -287,7 +282,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -327,7 +322,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[5] test=system.cpu5.l1c.cpu_side [system.cpu5.l1c] @@ -339,8 +334,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -348,7 +342,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -388,7 +382,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[6] test=system.cpu6.l1c.cpu_side [system.cpu6.l1c] @@ -400,8 +394,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -409,7 +402,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -449,7 +442,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[7] test=system.cpu7.l1c.cpu_side [system.cpu7.l1c] @@ -461,8 +454,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=1 +latency=1000 lifo=false max_miss_count=0 mshrs=12 @@ -470,7 +462,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=10000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -503,8 +495,7 @@ file= latency=1 range=0:134217727 zero=false -functional=system.cpu7.functional -port=system.cpu0.functional +port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional [system.l2c] type=BaseCache @@ -514,8 +505,7 @@ block_size=64 compressed_bus=false compression_latency=0 hash_delay=1 -hit_latency=1 -latency=10 +latency=10000 lifo=false max_miss_count=0 mshrs=92 @@ -523,7 +513,7 @@ prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 -prefetch_latency=10 +prefetch_latency=100000 prefetch_miss=false prefetch_past_page=false prefetch_policy=none @@ -547,11 +537,12 @@ mem_side=system.membus.port[0] [system.membus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=false width=16 -port=system.l2c.mem_side system.physmem.port +port=system.l2c.mem_side system.physmem.port[0] [system.physmem] type=PhysicalMemory @@ -563,6 +554,7 @@ port=system.membus.port[1] [system.toL2Bus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=false diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out index b3f4ec871..6bf1f2712 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out @@ -20,13 +20,14 @@ bus_id=0 clock=2 width=16 responder_set=false +block_size=64 [system.l2c] type=BaseCache size=65536 assoc=8 block_size=64 -latency=10 +latency=10000 mshrs=92 tgts_per_mshr=16 write_buffers=8 @@ -51,13 +52,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=100000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu6] type=MemTest @@ -82,7 +82,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -107,13 +107,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu4] type=MemTest @@ -138,7 +137,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -163,13 +162,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu5] type=MemTest @@ -194,7 +192,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -219,13 +217,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu2] type=MemTest @@ -250,7 +247,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -275,13 +272,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu3] type=MemTest @@ -306,7 +302,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -331,13 +327,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu0] type=MemTest @@ -362,7 +357,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -387,13 +382,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.cpu1] type=MemTest @@ -418,7 +412,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -443,13 +437,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.funcmem] type=PhysicalMemory @@ -481,7 +474,7 @@ type=BaseCache size=32768 assoc=4 block_size=64 -latency=1 +latency=1000 mshrs=12 tgts_per_mshr=8 write_buffers=8 @@ -506,13 +499,12 @@ prefetch_access=false prefetcher_size=100 prefetch_past_page=false prefetch_serial_squash=false -prefetch_latency=10 +prefetch_latency=10000 prefetch_degree=1 prefetch_policy=none prefetch_cache_check_push=true prefetch_use_cpu_id=true prefetch_data_accesses_only=false -hit_latency=1 [system.toL2Bus] type=Bus @@ -520,4 +512,5 @@ bus_id=0 clock=2 width=16 responder_set=false +block_size=64 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index 285ab3702..752268088 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,73 +1,72 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 303680 # Number of bytes of host memory used -host_seconds 32.50 # Real time elapsed on the host -host_tick_rate 177110 # Simulator tick rate (ticks/s) +host_seconds 37943.64 # Real time elapsed on the host +host_tick_rate 2223 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5755736 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 45048 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 959.688548 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 884.132516 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_hits 7543 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 35993119 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.832556 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37505 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 33159390 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.832556 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37505 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable 9815 # number of ReadReq MSHR uncacheable +sim_seconds 0.000084 # Number of seconds simulated +sim_ticks 84350509 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44421 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 14010.391786 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 12986.475734 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7291 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 520205847 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.835866 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37130 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 482187844 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.835866 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37130 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable 9916 # number of ReadReq MSHR uncacheable system.cpu0.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 17521633 # number of ReadResp MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24308 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 862.246942 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 778.821396 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_hits 1173 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 19948083 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.951744 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23135 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 18018033 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.951744 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23135 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable 5428 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 255520881 # number of ReadResp MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 23898 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 12904.605270 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 11399.917485 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_hits 1090 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 294328237 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.954389 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 22808 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 260009318 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.954389 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 22808 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable 5184 # number of WriteReq MSHR uncacheable system.cpu0.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 10755873 # number of WriteResp MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 81.366905 # average number of cycles each access was blocked +system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 154702333 # number of WriteResp MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 1194.948852 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.417208 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 69811 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.407238 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69093 # number of cycles access was blocked system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 5680305 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 82562601 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 69356 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 922.513226 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8716 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 55941202 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.874330 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60640 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68319 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 13589.610664 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8381 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 814534084 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.877325 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 59938 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 51177423 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.874330 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60640 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 742197162 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.877325 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 59938 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 69356 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 922.513226 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency +system.cpu0.l1c.overall_accesses 68319 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 13589.610664 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 12382.748206 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8716 # number of overall hits -system.cpu0.l1c.overall_miss_latency 55941202 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.874330 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60640 # number of overall misses +system.cpu0.l1c.overall_hits 8381 # number of overall hits +system.cpu0.l1c.overall_miss_latency 814534084 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.877325 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 59938 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 51177423 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.874330 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60640 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_miss_latency 742197162 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.877325 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 59938 # number of overall MSHR misses system.cpu0.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_misses 15243 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses 15100 # number of overall MSHR uncacheable misses system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -78,103 +77,103 @@ system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu0.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu0.l1c.protocol.read_invalid 109554 # read misses to invalid blocks +system.cpu0.l1c.protocol.read_invalid 1761660 # read misses to invalid blocks system.cpu0.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu0.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu0.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu0.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu0.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu0.l1c.protocol.snoop_read_exclusive 2807 # read snoops on exclusive blocks -system.cpu0.l1c.protocol.snoop_read_modified 12380 # read snoops on modified blocks -system.cpu0.l1c.protocol.snoop_read_owned 7157 # read snoops on owned blocks -system.cpu0.l1c.protocol.snoop_read_shared 22767 # read snoops on shared blocks -system.cpu0.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks -system.cpu0.l1c.protocol.snoop_readex_modified 6851 # readEx snoops on modified blocks -system.cpu0.l1c.protocol.snoop_readex_owned 3877 # readEx snoops on owned blocks -system.cpu0.l1c.protocol.snoop_readex_shared 12465 # readEx snoops on shared blocks -system.cpu0.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks -system.cpu0.l1c.protocol.snoop_upgrade_shared 2994 # upgradee snoops on shared blocks +system.cpu0.l1c.protocol.snoop_read_exclusive 2836 # read snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_read_modified 12378 # read snoops on modified blocks +system.cpu0.l1c.protocol.snoop_read_owned 7300 # read snoops on owned blocks +system.cpu0.l1c.protocol.snoop_read_shared 1749577 # read snoops on shared blocks +system.cpu0.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks +system.cpu0.l1c.protocol.snoop_readex_modified 6692 # readEx snoops on modified blocks +system.cpu0.l1c.protocol.snoop_readex_owned 4009 # readEx snoops on owned blocks +system.cpu0.l1c.protocol.snoop_readex_shared 12550 # readEx snoops on shared blocks +system.cpu0.l1c.protocol.snoop_upgrade_owned 790 # upgrade snoops on owned blocks +system.cpu0.l1c.protocol.snoop_upgrade_shared 3004 # upgradee snoops on shared blocks system.cpu0.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu0.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu0.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu0.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu0.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu0.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu0.l1c.protocol.write_invalid 60706 # write misses to invalid blocks -system.cpu0.l1c.protocol.write_owned 1361 # write misses to owned blocks -system.cpu0.l1c.protocol.write_shared 4416 # write misses to shared blocks -system.cpu0.l1c.replacements 27529 # number of replacements -system.cpu0.l1c.sampled_refs 27883 # Sample count of references to valid blocks. +system.cpu0.l1c.protocol.write_invalid 940728 # write misses to invalid blocks +system.cpu0.l1c.protocol.write_owned 1344 # write misses to owned blocks +system.cpu0.l1c.protocol.write_shared 4484 # write misses to shared blocks +system.cpu0.l1c.replacements 27160 # number of replacements +system.cpu0.l1c.sampled_refs 27495 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 342.460043 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11633 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 342.709273 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11197 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 10915 # number of writebacks +system.cpu0.l1c.writebacks 10716 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99586 # number of read accesses completed -system.cpu0.num_writes 53803 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44416 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 969.343786 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 893.327484 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_hits 7486 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 35797866 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.831457 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 36930 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 32990584 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831457 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 36930 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable 9894 # number of ReadReq MSHR uncacheable +system.cpu0.num_reads 98012 # number of read accesses completed +system.cpu0.num_writes 53207 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44893 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 13909.754864 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 12900.185775 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7579 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 519028593 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.831176 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37314 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 481357532 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831176 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37314 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable 9811 # number of ReadReq MSHR uncacheable system.cpu1.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 17663360 # number of ReadResp MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24084 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 871.179293 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 786.258930 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_hits 1155 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 19975270 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.952043 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 22929 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 18028131 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.952043 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 22929 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable 5271 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 251708747 # number of ReadResp MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24614 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 12788.679753 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 11344.205121 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_hits 1257 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 298705193 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.948932 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23357 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 264966599 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.948932 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23357 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable 5453 # number of WriteReq MSHR uncacheable system.cpu1.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 10523322 # number of WriteResp MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 82.260179 # average number of cycles each access was blocked +system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 163813954 # number of WriteResp MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 1183.149435 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.414867 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 68941 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.414323 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69763 # number of cycles access was blocked system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 5671099 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 82540054 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 68500 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 931.741860 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8641 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 55773136 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.873854 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 59859 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 69507 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 13478.165615 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8836 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 817733786 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.872876 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60671 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 51018715 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.873854 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 59859 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 746324131 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.872876 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60671 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 68500 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 931.741860 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency +system.cpu1.l1c.overall_accesses 69507 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 13478.165615 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 12301.167461 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8641 # number of overall hits -system.cpu1.l1c.overall_miss_latency 55773136 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.873854 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 59859 # number of overall misses +system.cpu1.l1c.overall_hits 8836 # number of overall hits +system.cpu1.l1c.overall_miss_latency 817733786 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.872876 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60671 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 51018715 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.873854 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 59859 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_miss_latency 746324131 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.872876 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60671 # number of overall MSHR misses system.cpu1.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_misses 15165 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses 15264 # number of overall MSHR uncacheable misses system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -185,103 +184,103 @@ system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu1.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu1.l1c.protocol.read_invalid 114228 # read misses to invalid blocks +system.cpu1.l1c.protocol.read_invalid 1717891 # read misses to invalid blocks system.cpu1.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu1.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu1.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu1.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu1.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu1.l1c.protocol.snoop_read_exclusive 2718 # read snoops on exclusive blocks -system.cpu1.l1c.protocol.snoop_read_modified 12396 # read snoops on modified blocks -system.cpu1.l1c.protocol.snoop_read_owned 7348 # read snoops on owned blocks -system.cpu1.l1c.protocol.snoop_read_shared 23222 # read snoops on shared blocks -system.cpu1.l1c.protocol.snoop_readex_exclusive 1497 # readEx snoops on exclusive blocks -system.cpu1.l1c.protocol.snoop_readex_modified 6706 # readEx snoops on modified blocks -system.cpu1.l1c.protocol.snoop_readex_owned 3865 # readEx snoops on owned blocks -system.cpu1.l1c.protocol.snoop_readex_shared 12512 # readEx snoops on shared blocks -system.cpu1.l1c.protocol.snoop_upgrade_owned 852 # upgrade snoops on owned blocks -system.cpu1.l1c.protocol.snoop_upgrade_shared 2973 # upgradee snoops on shared blocks +system.cpu1.l1c.protocol.snoop_read_exclusive 2925 # read snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_read_modified 12701 # read snoops on modified blocks +system.cpu1.l1c.protocol.snoop_read_owned 7436 # read snoops on owned blocks +system.cpu1.l1c.protocol.snoop_read_shared 1669937 # read snoops on shared blocks +system.cpu1.l1c.protocol.snoop_readex_exclusive 1611 # readEx snoops on exclusive blocks +system.cpu1.l1c.protocol.snoop_readex_modified 6726 # readEx snoops on modified blocks +system.cpu1.l1c.protocol.snoop_readex_owned 3965 # readEx snoops on owned blocks +system.cpu1.l1c.protocol.snoop_readex_shared 12596 # readEx snoops on shared blocks +system.cpu1.l1c.protocol.snoop_upgrade_owned 860 # upgrade snoops on owned blocks +system.cpu1.l1c.protocol.snoop_upgrade_shared 2979 # upgradee snoops on shared blocks system.cpu1.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu1.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu1.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu1.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu1.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu1.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu1.l1c.protocol.write_invalid 61595 # write misses to invalid blocks -system.cpu1.l1c.protocol.write_owned 1320 # write misses to owned blocks -system.cpu1.l1c.protocol.write_shared 4183 # write misses to shared blocks -system.cpu1.l1c.replacements 27139 # number of replacements -system.cpu1.l1c.sampled_refs 27498 # Sample count of references to valid blocks. +system.cpu1.l1c.protocol.write_invalid 914774 # write misses to invalid blocks +system.cpu1.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu1.l1c.protocol.write_shared 4382 # write misses to shared blocks +system.cpu1.l1c.replacements 27806 # number of replacements +system.cpu1.l1c.sampled_refs 28164 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 341.113569 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11408 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 345.545872 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11669 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10884 # number of writebacks +system.cpu1.l1c.writebacks 11204 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98821 # number of read accesses completed -system.cpu1.num_writes 53366 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 45016 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 956.031371 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 880.781951 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_hits 7529 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 35838748 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.832748 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37487 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 33017873 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832748 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable 9887 # number of ReadReq MSHR uncacheable +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 54335 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44489 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 14018.031231 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 12993.788573 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7507 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 518414831 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.831262 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 36982 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 480536289 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.831262 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 36982 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable system.cpu2.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 17582637 # number of ReadResp MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24456 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 859.707355 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 777.777296 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_hits 1165 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 20023444 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.952363 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23291 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 18115211 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.952363 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23291 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable 5362 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 253484666 # number of ReadResp MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24340 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 12765.385606 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 11318.971789 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_hits 1122 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 296386723 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.953903 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23218 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 262803887 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.953903 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23218 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable 5480 # number of WriteReq MSHR uncacheable system.cpu2.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 10583136 # number of WriteResp MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 81.152375 # average number of cycles each access was blocked +system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 165110755 # number of WriteResp MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 1190.317505 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.404365 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 69867 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.414721 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69202 # number of cycles access was blocked system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 5669873 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 82372352 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 69472 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 919.118628 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8694 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 55862192 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.874856 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60778 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68829 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 13534.909535 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8629 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 814801554 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.874631 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60200 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 51133084 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.874856 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60778 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 743340176 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.874631 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60200 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 69472 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 919.118628 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency +system.cpu2.l1c.overall_accesses 68829 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 13534.909535 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 12347.843455 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8694 # number of overall hits -system.cpu2.l1c.overall_miss_latency 55862192 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.874856 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60778 # number of overall misses +system.cpu2.l1c.overall_hits 8629 # number of overall hits +system.cpu2.l1c.overall_miss_latency 814801554 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.874631 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60200 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 51133084 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.874856 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60778 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_miss_latency 743340176 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.874631 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60200 # number of overall MSHR misses system.cpu2.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_misses 15249 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses 15341 # number of overall MSHR uncacheable misses system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -292,103 +291,103 @@ system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu2.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu2.l1c.protocol.read_invalid 111528 # read misses to invalid blocks +system.cpu2.l1c.protocol.read_invalid 1818161 # read misses to invalid blocks system.cpu2.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu2.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu2.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu2.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu2.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu2.l1c.protocol.snoop_read_exclusive 2757 # read snoops on exclusive blocks -system.cpu2.l1c.protocol.snoop_read_modified 12587 # read snoops on modified blocks -system.cpu2.l1c.protocol.snoop_read_owned 7252 # read snoops on owned blocks -system.cpu2.l1c.protocol.snoop_read_shared 22967 # read snoops on shared blocks -system.cpu2.l1c.protocol.snoop_readex_exclusive 1579 # readEx snoops on exclusive blocks -system.cpu2.l1c.protocol.snoop_readex_modified 6680 # readEx snoops on modified blocks -system.cpu2.l1c.protocol.snoop_readex_owned 3891 # readEx snoops on owned blocks -system.cpu2.l1c.protocol.snoop_readex_shared 12468 # readEx snoops on shared blocks -system.cpu2.l1c.protocol.snoop_upgrade_owned 850 # upgrade snoops on owned blocks -system.cpu2.l1c.protocol.snoop_upgrade_shared 2951 # upgradee snoops on shared blocks +system.cpu2.l1c.protocol.snoop_read_exclusive 2846 # read snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_read_modified 12505 # read snoops on modified blocks +system.cpu2.l1c.protocol.snoop_read_owned 7354 # read snoops on owned blocks +system.cpu2.l1c.protocol.snoop_read_shared 1719896 # read snoops on shared blocks +system.cpu2.l1c.protocol.snoop_readex_exclusive 1512 # readEx snoops on exclusive blocks +system.cpu2.l1c.protocol.snoop_readex_modified 6836 # readEx snoops on modified blocks +system.cpu2.l1c.protocol.snoop_readex_owned 4066 # readEx snoops on owned blocks +system.cpu2.l1c.protocol.snoop_readex_shared 12494 # readEx snoops on shared blocks +system.cpu2.l1c.protocol.snoop_upgrade_owned 828 # upgrade snoops on owned blocks +system.cpu2.l1c.protocol.snoop_upgrade_shared 2975 # upgradee snoops on shared blocks system.cpu2.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu2.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu2.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu2.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu2.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu2.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu2.l1c.protocol.write_invalid 57618 # write misses to invalid blocks -system.cpu2.l1c.protocol.write_owned 1263 # write misses to owned blocks -system.cpu2.l1c.protocol.write_shared 4251 # write misses to shared blocks -system.cpu2.l1c.replacements 28062 # number of replacements -system.cpu2.l1c.sampled_refs 28405 # Sample count of references to valid blocks. +system.cpu2.l1c.protocol.write_invalid 1061132 # write misses to invalid blocks +system.cpu2.l1c.protocol.write_owned 1410 # write misses to owned blocks +system.cpu2.l1c.protocol.write_shared 4436 # write misses to shared blocks +system.cpu2.l1c.replacements 27337 # number of replacements +system.cpu2.l1c.sampled_refs 27674 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 344.040679 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11486 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 343.290844 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11477 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 11295 # number of writebacks +system.cpu2.l1c.writebacks 10872 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 54133 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44504 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 968.772953 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 892.914985 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_hits 7428 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 35918226 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.833094 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37076 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 33105716 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833094 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37076 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable 9876 # number of ReadReq MSHR uncacheable +system.cpu2.num_reads 98887 # number of read accesses completed +system.cpu2.num_writes 53640 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44566 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 14066.553951 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 13052.525235 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7375 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 523149208 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.834515 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37191 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 485436466 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.834515 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable system.cpu3.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 17594905 # number of ReadResp MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24087 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 868.499565 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 784.537397 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_hits 1117 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 19949435 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.953626 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 22970 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 18020824 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.953626 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 22970 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable 5355 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 252799971 # number of ReadResp MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24030 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 12807.474484 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 11345.837164 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_hits 1142 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 293137476 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.952476 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 22888 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 259683521 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.952476 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 22888 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable 5294 # number of WriteReq MSHR uncacheable system.cpu3.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 10637792 # number of WriteResp MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 82.097897 # average number of cycles each access was blocked +system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 159218905 # number of WriteResp MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 1193.729049 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.411489 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69124 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.411345 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69160 # number of cycles access was blocked system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 5674935 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 82558301 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 68591 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 930.414366 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8545 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 55867661 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.875421 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60046 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68596 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 13586.888663 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8517 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 816286684 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.875838 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60079 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 51126540 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.875421 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60046 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 745119987 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.875838 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60079 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 68591 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 930.414366 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency +system.cpu3.l1c.overall_accesses 68596 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 13586.888663 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 12402.336707 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8545 # number of overall hits -system.cpu3.l1c.overall_miss_latency 55867661 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.875421 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60046 # number of overall misses +system.cpu3.l1c.overall_hits 8517 # number of overall hits +system.cpu3.l1c.overall_miss_latency 816286684 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.875838 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60079 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 51126540 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.875421 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60046 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_miss_latency 745119987 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.875838 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60079 # number of overall MSHR misses system.cpu3.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_misses 15231 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses 15114 # number of overall MSHR uncacheable misses system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -399,103 +398,103 @@ system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu3.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu3.l1c.protocol.read_invalid 110901 # read misses to invalid blocks +system.cpu3.l1c.protocol.read_invalid 1894373 # read misses to invalid blocks system.cpu3.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu3.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu3.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu3.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu3.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu3.l1c.protocol.snoop_read_exclusive 2843 # read snoops on exclusive blocks -system.cpu3.l1c.protocol.snoop_read_modified 12490 # read snoops on modified blocks -system.cpu3.l1c.protocol.snoop_read_owned 7235 # read snoops on owned blocks -system.cpu3.l1c.protocol.snoop_read_shared 23011 # read snoops on shared blocks -system.cpu3.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks -system.cpu3.l1c.protocol.snoop_readex_modified 6732 # readEx snoops on modified blocks -system.cpu3.l1c.protocol.snoop_readex_owned 3954 # readEx snoops on owned blocks -system.cpu3.l1c.protocol.snoop_readex_shared 12354 # readEx snoops on shared blocks -system.cpu3.l1c.protocol.snoop_upgrade_owned 858 # upgrade snoops on owned blocks -system.cpu3.l1c.protocol.snoop_upgrade_shared 3087 # upgradee snoops on shared blocks +system.cpu3.l1c.protocol.snoop_read_exclusive 2902 # read snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_read_modified 12291 # read snoops on modified blocks +system.cpu3.l1c.protocol.snoop_read_owned 7221 # read snoops on owned blocks +system.cpu3.l1c.protocol.snoop_read_shared 1743434 # read snoops on shared blocks +system.cpu3.l1c.protocol.snoop_readex_exclusive 1553 # readEx snoops on exclusive blocks +system.cpu3.l1c.protocol.snoop_readex_modified 6822 # readEx snoops on modified blocks +system.cpu3.l1c.protocol.snoop_readex_owned 3914 # readEx snoops on owned blocks +system.cpu3.l1c.protocol.snoop_readex_shared 12477 # readEx snoops on shared blocks +system.cpu3.l1c.protocol.snoop_upgrade_owned 867 # upgrade snoops on owned blocks +system.cpu3.l1c.protocol.snoop_upgrade_shared 3008 # upgradee snoops on shared blocks system.cpu3.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu3.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu3.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu3.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu3.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu3.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu3.l1c.protocol.write_invalid 59061 # write misses to invalid blocks -system.cpu3.l1c.protocol.write_owned 1261 # write misses to owned blocks -system.cpu3.l1c.protocol.write_shared 4235 # write misses to shared blocks -system.cpu3.l1c.replacements 27216 # number of replacements -system.cpu3.l1c.sampled_refs 27556 # Sample count of references to valid blocks. +system.cpu3.l1c.protocol.write_invalid 1046634 # write misses to invalid blocks +system.cpu3.l1c.protocol.write_owned 1364 # write misses to owned blocks +system.cpu3.l1c.protocol.write_shared 4484 # write misses to shared blocks +system.cpu3.l1c.replacements 27286 # number of replacements +system.cpu3.l1c.sampled_refs 27624 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 341.602377 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11339 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 342.290575 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11363 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10831 # number of writebacks +system.cpu3.l1c.writebacks 10681 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98893 # number of read accesses completed -system.cpu3.num_writes 53654 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44272 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 976.655364 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 901.292278 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_hits 7468 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 35944824 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.831316 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 36804 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 33171161 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831316 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 36804 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable 9822 # number of ReadReq MSHR uncacheable +system.cpu3.num_reads 99322 # number of read accesses completed +system.cpu3.num_writes 53280 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 13943.186039 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 12937.718615 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7581 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 521335726 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.831425 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37390 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 483741299 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831425 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37390 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable 9931 # number of ReadReq MSHR uncacheable system.cpu4.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 17532387 # number of ReadResp MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 23994 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 874.063859 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 788.017488 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_hits 1178 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 19942641 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.950904 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 22816 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 17979407 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.950904 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 22816 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable 5315 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 254015216 # number of ReadResp MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24134 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 12764.573629 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 11273.971841 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_hits 1086 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 294197893 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.955001 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23048 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 259842503 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.955001 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23048 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable 5390 # number of WriteReq MSHR uncacheable system.cpu4.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 10563676 # number of WriteResp MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 82.703233 # average number of cycles each access was blocked +system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 161643344 # number of WriteResp MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 1186.636056 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.416368 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 68707 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.410931 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69637 # number of cycles access was blocked system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 5682291 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 82633775 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68266 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 937.394582 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8646 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 55887465 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.873348 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 59620 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 69105 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 13493.722807 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8667 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 815533619 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.874582 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60438 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 51150568 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.873348 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 59620 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 743583802 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.874582 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60438 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 68266 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 937.394582 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency +system.cpu4.l1c.overall_accesses 69105 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 13493.722807 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 12303.249644 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8646 # number of overall hits -system.cpu4.l1c.overall_miss_latency 55887465 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.873348 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 59620 # number of overall misses +system.cpu4.l1c.overall_hits 8667 # number of overall hits +system.cpu4.l1c.overall_miss_latency 815533619 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.874582 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60438 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 51150568 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.873348 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 59620 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_miss_latency 743583802 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.874582 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60438 # number of overall MSHR misses system.cpu4.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_misses 15137 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses 15321 # number of overall MSHR uncacheable misses system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -506,103 +505,103 @@ system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu4.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu4.l1c.protocol.read_invalid 113154 # read misses to invalid blocks +system.cpu4.l1c.protocol.read_invalid 1830675 # read misses to invalid blocks system.cpu4.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu4.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu4.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu4.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu4.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu4.l1c.protocol.snoop_read_exclusive 2804 # read snoops on exclusive blocks -system.cpu4.l1c.protocol.snoop_read_modified 12453 # read snoops on modified blocks -system.cpu4.l1c.protocol.snoop_read_owned 7418 # read snoops on owned blocks -system.cpu4.l1c.protocol.snoop_read_shared 23136 # read snoops on shared blocks -system.cpu4.l1c.protocol.snoop_readex_exclusive 1528 # readEx snoops on exclusive blocks -system.cpu4.l1c.protocol.snoop_readex_modified 6607 # readEx snoops on modified blocks -system.cpu4.l1c.protocol.snoop_readex_owned 3922 # readEx snoops on owned blocks -system.cpu4.l1c.protocol.snoop_readex_shared 12524 # readEx snoops on shared blocks -system.cpu4.l1c.protocol.snoop_upgrade_owned 843 # upgrade snoops on owned blocks -system.cpu4.l1c.protocol.snoop_upgrade_shared 2904 # upgradee snoops on shared blocks +system.cpu4.l1c.protocol.snoop_read_exclusive 2847 # read snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_read_modified 12499 # read snoops on modified blocks +system.cpu4.l1c.protocol.snoop_read_owned 7458 # read snoops on owned blocks +system.cpu4.l1c.protocol.snoop_read_shared 1765770 # read snoops on shared blocks +system.cpu4.l1c.protocol.snoop_readex_exclusive 1560 # readEx snoops on exclusive blocks +system.cpu4.l1c.protocol.snoop_readex_modified 6711 # readEx snoops on modified blocks +system.cpu4.l1c.protocol.snoop_readex_owned 3919 # readEx snoops on owned blocks +system.cpu4.l1c.protocol.snoop_readex_shared 12526 # readEx snoops on shared blocks +system.cpu4.l1c.protocol.snoop_upgrade_owned 902 # upgrade snoops on owned blocks +system.cpu4.l1c.protocol.snoop_upgrade_shared 3023 # upgradee snoops on shared blocks system.cpu4.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu4.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu4.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu4.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu4.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu4.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu4.l1c.protocol.write_invalid 59622 # write misses to invalid blocks -system.cpu4.l1c.protocol.write_owned 1265 # write misses to owned blocks -system.cpu4.l1c.protocol.write_shared 4187 # write misses to shared blocks -system.cpu4.l1c.replacements 27000 # number of replacements -system.cpu4.l1c.sampled_refs 27346 # Sample count of references to valid blocks. +system.cpu4.l1c.protocol.write_invalid 854606 # write misses to invalid blocks +system.cpu4.l1c.protocol.write_owned 1318 # write misses to owned blocks +system.cpu4.l1c.protocol.write_shared 4519 # write misses to shared blocks +system.cpu4.l1c.replacements 27664 # number of replacements +system.cpu4.l1c.sampled_refs 28012 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 342.121323 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11386 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 344.185288 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11511 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10847 # number of writebacks +system.cpu4.l1c.writebacks 10935 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98882 # number of read accesses completed -system.cpu4.num_writes 53288 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44218 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 975.652027 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 898.818359 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_hits 7310 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 36009365 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.834683 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 36908 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 33173588 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.834683 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 36908 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable 9866 # number of ReadReq MSHR uncacheable +system.cpu4.num_reads 99841 # number of read accesses completed +system.cpu4.num_writes 54005 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 45075 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 13980.675167 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 12974.186518 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7588 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 524093570 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.831658 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37487 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 486363330 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831658 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable 9769 # number of ReadReq MSHR uncacheable system.cpu5.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 17625443 # number of ReadResp MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 23923 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 873.308611 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 788.173188 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_hits 1150 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 19887857 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.951929 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 22773 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 17949068 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.951929 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 22773 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable 5207 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 252483534 # number of ReadResp MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24120 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 12733.111936 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 11249.826210 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_hits 1098 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 293141703 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.954478 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23022 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 258993499 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.954478 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23022 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable 5232 # number of WriteReq MSHR uncacheable system.cpu5.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 10374807 # number of WriteResp MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 82.590363 # average number of cycles each access was blocked +system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 155064988 # number of WriteResp MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 1188.349008 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.413664 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 68944 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.414917 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69537 # number of cycles access was blocked system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 5694110 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 82634225 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 68141 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 936.599956 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8460 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 55897222 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.875846 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 59681 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 69195 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 13506.011883 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8686 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 817235273 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.874471 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60509 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 51122656 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.875846 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 59681 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 745356829 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.874471 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60509 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 68141 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 936.599956 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency +system.cpu5.l1c.overall_accesses 69195 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 13506.011883 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 12318.115140 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8460 # number of overall hits -system.cpu5.l1c.overall_miss_latency 55897222 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.875846 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 59681 # number of overall misses +system.cpu5.l1c.overall_hits 8686 # number of overall hits +system.cpu5.l1c.overall_miss_latency 817235273 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.874471 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60509 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 51122656 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.875846 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 59681 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_miss_latency 745356829 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.874471 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60509 # number of overall MSHR misses system.cpu5.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_misses 15073 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses 15001 # number of overall MSHR uncacheable misses system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -613,103 +612,103 @@ system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu5.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu5.l1c.protocol.read_invalid 114279 # read misses to invalid blocks +system.cpu5.l1c.protocol.read_invalid 1718821 # read misses to invalid blocks system.cpu5.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu5.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu5.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu5.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu5.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu5.l1c.protocol.snoop_read_exclusive 2860 # read snoops on exclusive blocks -system.cpu5.l1c.protocol.snoop_read_modified 12253 # read snoops on modified blocks -system.cpu5.l1c.protocol.snoop_read_owned 7231 # read snoops on owned blocks -system.cpu5.l1c.protocol.snoop_read_shared 23182 # read snoops on shared blocks -system.cpu5.l1c.protocol.snoop_readex_exclusive 1499 # readEx snoops on exclusive blocks -system.cpu5.l1c.protocol.snoop_readex_modified 6757 # readEx snoops on modified blocks -system.cpu5.l1c.protocol.snoop_readex_owned 3896 # readEx snoops on owned blocks -system.cpu5.l1c.protocol.snoop_readex_shared 12461 # readEx snoops on shared blocks -system.cpu5.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks -system.cpu5.l1c.protocol.snoop_upgrade_shared 3020 # upgradee snoops on shared blocks +system.cpu5.l1c.protocol.snoop_read_exclusive 2926 # read snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_read_modified 12465 # read snoops on modified blocks +system.cpu5.l1c.protocol.snoop_read_owned 7201 # read snoops on owned blocks +system.cpu5.l1c.protocol.snoop_read_shared 1810557 # read snoops on shared blocks +system.cpu5.l1c.protocol.snoop_readex_exclusive 1622 # readEx snoops on exclusive blocks +system.cpu5.l1c.protocol.snoop_readex_modified 6690 # readEx snoops on modified blocks +system.cpu5.l1c.protocol.snoop_readex_owned 3947 # readEx snoops on owned blocks +system.cpu5.l1c.protocol.snoop_readex_shared 12574 # readEx snoops on shared blocks +system.cpu5.l1c.protocol.snoop_upgrade_owned 818 # upgrade snoops on owned blocks +system.cpu5.l1c.protocol.snoop_upgrade_shared 3092 # upgradee snoops on shared blocks system.cpu5.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu5.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu5.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu5.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu5.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu5.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu5.l1c.protocol.write_invalid 60969 # write misses to invalid blocks -system.cpu5.l1c.protocol.write_owned 1349 # write misses to owned blocks -system.cpu5.l1c.protocol.write_shared 4191 # write misses to shared blocks -system.cpu5.l1c.replacements 26828 # number of replacements -system.cpu5.l1c.sampled_refs 27196 # Sample count of references to valid blocks. +system.cpu5.l1c.protocol.write_invalid 914561 # write misses to invalid blocks +system.cpu5.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu5.l1c.protocol.write_shared 4534 # write misses to shared blocks +system.cpu5.l1c.replacements 27551 # number of replacements +system.cpu5.l1c.sampled_refs 27914 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 340.865502 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11250 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 344.440637 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11582 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10567 # number of writebacks +system.cpu5.l1c.writebacks 10931 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 97882 # number of read accesses completed -system.cpu5.num_writes 52965 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 967.006541 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 890.563660 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_hits 7514 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 36221164 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.832915 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37457 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 33357843 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832915 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37457 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable 9684 # number of ReadReq MSHR uncacheable +system.cpu5.num_reads 99674 # number of read accesses completed +system.cpu5.num_writes 53393 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44595 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 14001.082353 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 12995.526917 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7462 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 519902191 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.832672 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37133 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 482562901 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832672 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37133 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable 9820 # number of ReadReq MSHR uncacheable system.cpu6.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 17275344 # number of ReadResp MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 23996 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 873.777515 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 790.631514 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_hits 1181 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 19935234 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.950783 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 22815 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 18038258 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.950783 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 22815 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable 5345 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 251671127 # number of ReadResp MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24364 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 12854.640783 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 11385.598176 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_hits 1222 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 297482097 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.949844 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23142 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 263485513 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.949844 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23142 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable 5447 # number of WriteReq MSHR uncacheable system.cpu6.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 10602140 # number of WriteResp MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 82.071085 # average number of cycles each access was blocked +system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 163399316 # number of WriteResp MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 1189.328084 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.412251 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 69157 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.411043 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 69345 # number of cycles access was blocked system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 5675790 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 82473956 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 68967 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 931.716187 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8695 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 56156398 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.873925 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60272 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68959 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 13560.917263 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8684 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 817384288 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.874070 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60275 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 51396101 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.873925 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60272 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 746048414 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.874070 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60275 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 68967 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 931.716187 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency +system.cpu6.l1c.overall_accesses 68959 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 13560.917263 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 12377.410436 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8695 # number of overall hits -system.cpu6.l1c.overall_miss_latency 56156398 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.873925 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60272 # number of overall misses +system.cpu6.l1c.overall_hits 8684 # number of overall hits +system.cpu6.l1c.overall_miss_latency 817384288 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.874070 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60275 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 51396101 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.873925 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60272 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_miss_latency 746048414 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.874070 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60275 # number of overall MSHR misses system.cpu6.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_misses 15029 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses 15267 # number of overall MSHR uncacheable misses system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -720,103 +719,103 @@ system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu6.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu6.l1c.protocol.read_invalid 114488 # read misses to invalid blocks +system.cpu6.l1c.protocol.read_invalid 1894590 # read misses to invalid blocks system.cpu6.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu6.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu6.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu6.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu6.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu6.l1c.protocol.snoop_read_exclusive 2876 # read snoops on exclusive blocks -system.cpu6.l1c.protocol.snoop_read_modified 12371 # read snoops on modified blocks -system.cpu6.l1c.protocol.snoop_read_owned 7223 # read snoops on owned blocks -system.cpu6.l1c.protocol.snoop_read_shared 23305 # read snoops on shared blocks -system.cpu6.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks -system.cpu6.l1c.protocol.snoop_readex_modified 6693 # readEx snoops on modified blocks -system.cpu6.l1c.protocol.snoop_readex_owned 3909 # readEx snoops on owned blocks -system.cpu6.l1c.protocol.snoop_readex_shared 12446 # readEx snoops on shared blocks -system.cpu6.l1c.protocol.snoop_upgrade_owned 833 # upgrade snoops on owned blocks -system.cpu6.l1c.protocol.snoop_upgrade_shared 2948 # upgradee snoops on shared blocks +system.cpu6.l1c.protocol.snoop_read_exclusive 2887 # read snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_read_modified 12551 # read snoops on modified blocks +system.cpu6.l1c.protocol.snoop_read_owned 7188 # read snoops on owned blocks +system.cpu6.l1c.protocol.snoop_read_shared 1703425 # read snoops on shared blocks +system.cpu6.l1c.protocol.snoop_readex_exclusive 1550 # readEx snoops on exclusive blocks +system.cpu6.l1c.protocol.snoop_readex_modified 6733 # readEx snoops on modified blocks +system.cpu6.l1c.protocol.snoop_readex_owned 3926 # readEx snoops on owned blocks +system.cpu6.l1c.protocol.snoop_readex_shared 12456 # readEx snoops on shared blocks +system.cpu6.l1c.protocol.snoop_upgrade_owned 800 # upgrade snoops on owned blocks +system.cpu6.l1c.protocol.snoop_upgrade_shared 3156 # upgradee snoops on shared blocks system.cpu6.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu6.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu6.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu6.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu6.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu6.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu6.l1c.protocol.write_invalid 58413 # write misses to invalid blocks -system.cpu6.l1c.protocol.write_owned 1374 # write misses to owned blocks -system.cpu6.l1c.protocol.write_shared 4109 # write misses to shared blocks -system.cpu6.l1c.replacements 27477 # number of replacements -system.cpu6.l1c.sampled_refs 27835 # Sample count of references to valid blocks. +system.cpu6.l1c.protocol.write_invalid 987928 # write misses to invalid blocks +system.cpu6.l1c.protocol.write_owned 1405 # write misses to owned blocks +system.cpu6.l1c.protocol.write_shared 4406 # write misses to shared blocks +system.cpu6.l1c.replacements 27613 # number of replacements +system.cpu6.l1c.sampled_refs 27946 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 342.134742 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11475 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 344.860122 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11487 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 10759 # number of writebacks +system.cpu6.l1c.writebacks 11073 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99303 # number of read accesses completed -system.cpu6.num_writes 53385 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44438 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 975.306986 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 899.340271 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_hits 7394 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 36129272 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.833611 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37044 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 33315161 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833611 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37044 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable +system.cpu6.num_reads 98723 # number of read accesses completed +system.cpu6.num_writes 53876 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 44990 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 13952.283047 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 12937.789329 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7505 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 523001330 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.833185 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37485 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 484973033 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833185 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37485 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable 10001 # number of ReadReq MSHR uncacheable system.cpu7.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 17576395 # number of ReadResp MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 23999 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 861.568979 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 776.580264 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_hits 1137 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 19697190 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.952623 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 22862 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 17754178 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.952623 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 22862 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable 5386 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 257188342 # number of ReadResp MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24083 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 12615.682417 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 11155.458639 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_hits 1163 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 289151441 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.951709 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 22920 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 255683112 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.951709 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 22920 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable 5323 # number of WriteReq MSHR uncacheable system.cpu7.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 10720857 # number of WriteResp MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 82.167211 # average number of cycles each access was blocked +system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 159397105 # number of WriteResp MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 1185.864523 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.419292 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 68907 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.413879 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69665 # number of cycles access was blocked system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 5661896 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 82613252 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 68437 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 931.901012 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8531 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 55826462 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.875345 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 59906 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 69073 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 13445.124923 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8668 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 812152771 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.874510 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60405 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 51069339 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.875345 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 59906 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 740656145 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.874510 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60405 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 68437 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 931.901012 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency +system.cpu7.l1c.overall_accesses 69073 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 13445.124923 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 12261.503932 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8531 # number of overall hits -system.cpu7.l1c.overall_miss_latency 55826462 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.875345 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 59906 # number of overall misses +system.cpu7.l1c.overall_hits 8668 # number of overall hits +system.cpu7.l1c.overall_miss_latency 812152771 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.874510 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60405 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 51069339 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.875345 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 59906 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_miss_latency 740656145 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.874510 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60405 # number of overall MSHR misses system.cpu7.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_misses 15247 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses 15324 # number of overall MSHR uncacheable misses system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -827,111 +826,111 @@ system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu7.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks -system.cpu7.l1c.protocol.read_invalid 115064 # read misses to invalid blocks +system.cpu7.l1c.protocol.read_invalid 1929884 # read misses to invalid blocks system.cpu7.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks system.cpu7.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks system.cpu7.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks system.cpu7.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks system.cpu7.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks -system.cpu7.l1c.protocol.snoop_read_exclusive 2793 # read snoops on exclusive blocks -system.cpu7.l1c.protocol.snoop_read_modified 12588 # read snoops on modified blocks -system.cpu7.l1c.protocol.snoop_read_owned 7412 # read snoops on owned blocks -system.cpu7.l1c.protocol.snoop_read_shared 23048 # read snoops on shared blocks -system.cpu7.l1c.protocol.snoop_readex_exclusive 1548 # readEx snoops on exclusive blocks -system.cpu7.l1c.protocol.snoop_readex_modified 6593 # readEx snoops on modified blocks -system.cpu7.l1c.protocol.snoop_readex_owned 3944 # readEx snoops on owned blocks -system.cpu7.l1c.protocol.snoop_readex_shared 12404 # readEx snoops on shared blocks -system.cpu7.l1c.protocol.snoop_upgrade_owned 919 # upgrade snoops on owned blocks -system.cpu7.l1c.protocol.snoop_upgrade_shared 2959 # upgradee snoops on shared blocks +system.cpu7.l1c.protocol.snoop_read_exclusive 2904 # read snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_read_modified 12387 # read snoops on modified blocks +system.cpu7.l1c.protocol.snoop_read_owned 7174 # read snoops on owned blocks +system.cpu7.l1c.protocol.snoop_read_shared 1782059 # read snoops on shared blocks +system.cpu7.l1c.protocol.snoop_readex_exclusive 1587 # readEx snoops on exclusive blocks +system.cpu7.l1c.protocol.snoop_readex_modified 6687 # readEx snoops on modified blocks +system.cpu7.l1c.protocol.snoop_readex_owned 3842 # readEx snoops on owned blocks +system.cpu7.l1c.protocol.snoop_readex_shared 12759 # readEx snoops on shared blocks +system.cpu7.l1c.protocol.snoop_upgrade_owned 792 # upgrade snoops on owned blocks +system.cpu7.l1c.protocol.snoop_upgrade_shared 3085 # upgradee snoops on shared blocks system.cpu7.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks system.cpu7.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks system.cpu7.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks system.cpu7.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks system.cpu7.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks system.cpu7.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks -system.cpu7.l1c.protocol.write_invalid 58173 # write misses to invalid blocks -system.cpu7.l1c.protocol.write_owned 1351 # write misses to owned blocks -system.cpu7.l1c.protocol.write_shared 4494 # write misses to shared blocks -system.cpu7.l1c.replacements 27080 # number of replacements -system.cpu7.l1c.sampled_refs 27420 # Sample count of references to valid blocks. +system.cpu7.l1c.protocol.write_invalid 930930 # write misses to invalid blocks +system.cpu7.l1c.protocol.write_owned 1422 # write misses to owned blocks +system.cpu7.l1c.protocol.write_shared 4465 # write misses to shared blocks +system.cpu7.l1c.replacements 27486 # number of replacements +system.cpu7.l1c.sampled_refs 27827 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 342.061742 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11497 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 344.310963 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11517 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10789 # number of writebacks +system.cpu7.l1c.writebacks 10979 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98350 # number of read accesses completed -system.cpu7.num_writes 53282 # number of write accesses completed -system.l2c.ReadExReq_accesses 75399 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 89.483714 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 6.467886 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits 39632 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 3200564 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 0.474370 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 35767 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 231311 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 0.474317 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 35763 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 138997 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 89.683271 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 6.196645 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits 72568 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 5957570 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.477917 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 66429 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 411544 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.477809 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 66414 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable +system.cpu7.num_reads 99734 # number of read accesses completed +system.cpu7.num_writes 53652 # number of write accesses completed +system.l2c.ReadExReq_accesses 75160 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 10115.633652 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 6085.503709 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits 39620 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 359509620 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate 0.472858 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses 35540 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 220 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 214939991 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate 0.469931 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 35320 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 138762 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 10150.344064 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 6129.500996 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits 72597 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 671597515 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.476824 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 66165 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 406 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 403069856 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.473898 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 65759 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable 78927 # number of ReadReq MSHR uncacheable system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency -system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable +system.l2c.ReadResp_mshr_uncacheable_latency 484683934 # number of ReadResp MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable 42802 # number of WriteReq MSHR uncacheable system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency -system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles -system.l2c.Writeback_accesses 86614 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 18299 # number of Writeback hits -system.l2c.Writeback_miss_rate 0.788729 # miss rate for Writeback accesses -system.l2c.Writeback_misses 68315 # number of Writeback misses -system.l2c.Writeback_mshr_miss_rate 0.788729 # mshr miss rate for Writeback accesses -system.l2c.Writeback_mshr_misses 68315 # number of Writeback MSHR misses -system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.l2c.WriteResp_mshr_uncacheable_latency 248118294 # number of WriteResp MSHR uncacheable cycles +system.l2c.Writeback_accesses 86706 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits 18948 # number of Writeback hits +system.l2c.Writeback_miss_rate 0.781468 # miss rate for Writeback accesses +system.l2c.Writeback_misses 67758 # number of Writeback misses +system.l2c.Writeback_mshr_miss_rate 0.781468 # mshr miss rate for Writeback accesses +system.l2c.Writeback_mshr_misses 67758 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs 3278 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 1.277186 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked +system.l2c.avg_refs 1.297661 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 3 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 9834 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 138997 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 89.683271 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency -system.l2c.demand_hits 72568 # number of demand (read+write) hits -system.l2c.demand_miss_latency 5957570 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.477917 # miss rate for demand accesses -system.l2c.demand_misses 66429 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 411544 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.477809 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 66414 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 138762 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 10150.344064 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency +system.l2c.demand_hits 72597 # number of demand (read+write) hits +system.l2c.demand_miss_latency 671597515 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.476824 # miss rate for demand accesses +system.l2c.demand_misses 66165 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 406 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 403069856 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.473898 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 65759 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 225611 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 44.213991 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency +system.l2c.overall_accesses 225468 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 5014.803394 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 6129.500996 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency -system.l2c.overall_hits 90867 # number of overall hits -system.l2c.overall_miss_latency 5957570 # number of overall miss cycles -system.l2c.overall_miss_rate 0.597240 # miss rate for overall accesses -system.l2c.overall_misses 134744 # number of overall misses -system.l2c.overall_mshr_hits 15 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 411544 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.294374 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 66414 # number of overall MSHR misses +system.l2c.overall_hits 91545 # number of overall hits +system.l2c.overall_miss_latency 671597515 # number of overall miss cycles +system.l2c.overall_miss_rate 0.593978 # miss rate for overall accesses +system.l2c.overall_misses 133923 # number of overall misses +system.l2c.overall_mshr_hits 406 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 403069856 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.291656 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 65759 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 121364 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses 121729 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue @@ -941,12 +940,12 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 101153 # number of replacements -system.l2c.sampled_refs 102177 # Sample count of references to valid blocks. +system.l2c.replacements 100054 # number of replacements +system.l2c.sampled_refs 101078 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1022.647312 # Cycle average of tags in use -system.l2c.total_refs 130499 # Total number of references to valid blocks. -system.l2c.warmup_cycle 31838 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 15786 # number of writebacks +system.l2c.tagsinuse 1023.099242 # Cycle average of tags in use +system.l2c.total_refs 131165 # Total number of references to valid blocks. +system.l2c.warmup_cycle 296156 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 16243 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr index 16580296b..d45294bbb 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -1,74 +1,74 @@ warn: Entering event queue @ 0. Starting simulation... -system.cpu2: completed 10000 read accesses @573559 -system.cpu1: completed 10000 read accesses @574452 -system.cpu4: completed 10000 read accesses @578704 -system.cpu6: completed 10000 read accesses @579414 -system.cpu0: completed 10000 read accesses @588706 -system.cpu5: completed 10000 read accesses @590846 -system.cpu7: completed 10000 read accesses @592958 -system.cpu3: completed 10000 read accesses @604807 -system.cpu2: completed 20000 read accesses @1142209 -system.cpu1: completed 20000 read accesses @1143294 -system.cpu6: completed 20000 read accesses @1150506 -system.cpu4: completed 20000 read accesses @1152288 -system.cpu0: completed 20000 read accesses @1160537 -system.cpu3: completed 20000 read accesses @1175338 -system.cpu5: completed 20000 read accesses @1175648 -system.cpu7: completed 20000 read accesses @1180960 -system.cpu6: completed 30000 read accesses @1716218 -system.cpu3: completed 30000 read accesses @1728281 -system.cpu1: completed 30000 read accesses @1735983 -system.cpu0: completed 30000 read accesses @1736422 -system.cpu2: completed 30000 read accesses @1739692 -system.cpu4: completed 30000 read accesses @1746362 -system.cpu5: completed 30000 read accesses @1766199 -system.cpu7: completed 30000 read accesses @1783424 -system.cpu6: completed 40000 read accesses @2281651 -system.cpu0: completed 40000 read accesses @2300760 -system.cpu3: completed 40000 read accesses @2312993 -system.cpu2: completed 40000 read accesses @2314026 -system.cpu4: completed 40000 read accesses @2332178 -system.cpu1: completed 40000 read accesses @2336380 -system.cpu5: completed 40000 read accesses @2349370 -system.cpu7: completed 40000 read accesses @2365352 -system.cpu6: completed 50000 read accesses @2863317 -system.cpu0: completed 50000 read accesses @2878182 -system.cpu2: completed 50000 read accesses @2884989 -system.cpu3: completed 50000 read accesses @2897940 -system.cpu4: completed 50000 read accesses @2918842 -system.cpu1: completed 50000 read accesses @2929102 -system.cpu5: completed 50000 read accesses @2938269 -system.cpu7: completed 50000 read accesses @2944872 -system.cpu6: completed 60000 read accesses @3435715 -system.cpu2: completed 60000 read accesses @3454809 -system.cpu0: completed 60000 read accesses @3462986 -system.cpu3: completed 60000 read accesses @3485243 -system.cpu4: completed 60000 read accesses @3498361 -system.cpu1: completed 60000 read accesses @3501000 -system.cpu5: completed 60000 read accesses @3516984 -system.cpu7: completed 60000 read accesses @3517323 -system.cpu6: completed 70000 read accesses @4032530 -system.cpu0: completed 70000 read accesses @4041457 -system.cpu2: completed 70000 read accesses @4043695 -system.cpu7: completed 70000 read accesses @4070977 -system.cpu1: completed 70000 read accesses @4075964 -system.cpu4: completed 70000 read accesses @4076518 -system.cpu3: completed 70000 read accesses @4082470 -system.cpu5: completed 70000 read accesses @4104778 -system.cpu0: completed 80000 read accesses @4610101 -system.cpu2: completed 80000 read accesses @4622528 -system.cpu6: completed 80000 read accesses @4627690 -system.cpu1: completed 80000 read accesses @4654033 -system.cpu4: completed 80000 read accesses @4661016 -system.cpu3: completed 80000 read accesses @4662752 -system.cpu7: completed 80000 read accesses @4668924 -system.cpu5: completed 80000 read accesses @4689767 -system.cpu2: completed 90000 read accesses @5186824 -system.cpu0: completed 90000 read accesses @5189006 -system.cpu6: completed 90000 read accesses @5214829 -system.cpu1: completed 90000 read accesses @5229787 -system.cpu3: completed 90000 read accesses @5235400 -system.cpu4: completed 90000 read accesses @5240445 -system.cpu7: completed 90000 read accesses @5254426 -system.cpu5: completed 90000 read accesses @5292462 -system.cpu2: completed 100000 read accesses @5755736 +system.cpu7: completed 10000 read accesses @8253930 +system.cpu1: completed 10000 read accesses @8325085 +system.cpu6: completed 10000 read accesses @8427313 +system.cpu4: completed 10000 read accesses @8438233 +system.cpu2: completed 10000 read accesses @8458126 +system.cpu5: completed 10000 read accesses @8549800 +system.cpu3: completed 10000 read accesses @8559995 +system.cpu0: completed 10000 read accesses @8593654 +system.cpu7: completed 20000 read accesses @16744182 +system.cpu1: completed 20000 read accesses @16774744 +system.cpu4: completed 20000 read accesses @16786220 +system.cpu3: completed 20000 read accesses @16787358 +system.cpu5: completed 20000 read accesses @16795808 +system.cpu6: completed 20000 read accesses @16836913 +system.cpu2: completed 20000 read accesses @17031052 +system.cpu0: completed 20000 read accesses @17126654 +system.cpu5: completed 30000 read accesses @24892576 +system.cpu6: completed 30000 read accesses @24903300 +system.cpu3: completed 30000 read accesses @24935860 +system.cpu4: completed 30000 read accesses @25020642 +system.cpu1: completed 30000 read accesses @25031726 +system.cpu7: completed 30000 read accesses @25112091 +system.cpu2: completed 30000 read accesses @25235960 +system.cpu0: completed 30000 read accesses @25505209 +system.cpu5: completed 40000 read accesses @33191203 +system.cpu6: completed 40000 read accesses @33273684 +system.cpu4: completed 40000 read accesses @33345526 +system.cpu3: completed 40000 read accesses @33406412 +system.cpu7: completed 40000 read accesses @33509130 +system.cpu1: completed 40000 read accesses @33509218 +system.cpu2: completed 40000 read accesses @33664822 +system.cpu0: completed 40000 read accesses @33869626 +system.cpu5: completed 50000 read accesses @41488848 +system.cpu4: completed 50000 read accesses @41582702 +system.cpu7: completed 50000 read accesses @41828988 +system.cpu3: completed 50000 read accesses @41829496 +system.cpu1: completed 50000 read accesses @41849534 +system.cpu6: completed 50000 read accesses @41982608 +system.cpu2: completed 50000 read accesses @42197798 +system.cpu0: completed 50000 read accesses @42443468 +system.cpu5: completed 60000 read accesses @49751344 +system.cpu4: completed 60000 read accesses @49783100 +system.cpu1: completed 60000 read accesses @49918062 +system.cpu7: completed 60000 read accesses @49929008 +system.cpu3: completed 60000 read accesses @50173996 +system.cpu6: completed 60000 read accesses @50351766 +system.cpu2: completed 60000 read accesses @50352657 +system.cpu0: completed 60000 read accesses @50789771 +system.cpu4: completed 70000 read accesses @58352386 +system.cpu5: completed 70000 read accesses @58394758 +system.cpu7: completed 70000 read accesses @58570698 +system.cpu1: completed 70000 read accesses @58764169 +system.cpu3: completed 70000 read accesses @58764648 +system.cpu2: completed 70000 read accesses @58921714 +system.cpu6: completed 70000 read accesses @58929984 +system.cpu0: completed 70000 read accesses @59567320 +system.cpu1: completed 80000 read accesses @67092786 +system.cpu5: completed 80000 read accesses @67153667 +system.cpu4: completed 80000 read accesses @67153760 +system.cpu7: completed 80000 read accesses @67207042 +system.cpu3: completed 80000 read accesses @67238507 +system.cpu2: completed 80000 read accesses @67633112 +system.cpu6: completed 80000 read accesses @67664637 +system.cpu0: completed 80000 read accesses @68437288 +system.cpu1: completed 90000 read accesses @75679048 +system.cpu4: completed 90000 read accesses @75680280 +system.cpu7: completed 90000 read accesses @75751053 +system.cpu5: completed 90000 read accesses @75781514 +system.cpu3: completed 90000 read accesses @75844118 +system.cpu2: completed 90000 read accesses @76346671 +system.cpu6: completed 90000 read accesses @76491728 +system.cpu0: completed 90000 read accesses @77376872 +system.cpu1: completed 100000 read accesses @84350509 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index ea4812a6d..a77db6fb9 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,15 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2007 21:50:58 -M5 started Sat Apr 21 21:51:15 2007 -M5 executing on zamp.eecs.umich.edu -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest -warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional -warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional -warning: overwriting port funcmem.functional value cpu3.functional with cpu4.functional -warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional -warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional -warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional +M5 compiled Jun 10 2007 14:06:20 +M5 started Sun Jun 10 14:22:51 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second -Exiting @ tick 5755736 because Maximum number of loads reached! +Exiting @ tick 84350509 because Maximum number of loads reached! diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index a14d4767e..c16d67687 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,16 +14,21 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 [drivesys.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=drivesys.iobus.port[0] side_b=drivesys.membus.port[0] @@ -106,6 +111,7 @@ sys=drivesys [drivesys.iobus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=true @@ -116,12 +122,13 @@ port=drivesys.bridge.side_a drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pi [drivesys.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=1000 responder_set=false width=64 default=drivesys.membus.responder.pio -port=drivesys.bridge.side_b drivesys.physmem.port drivesys.cpu.icache_port drivesys.cpu.dcache_port +port=drivesys.bridge.side_b drivesys.physmem.port[0] drivesys.cpu.icache_port drivesys.cpu.dcache_port [drivesys.membus.responder] type=IsaFake @@ -212,6 +219,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 @@ -584,6 +593,8 @@ children=configdata config_latency=20000 configdata=drivesys.tsunami.ide.configdata disks=drivesys.disk0 drivesys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 @@ -693,16 +704,21 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 [testsys.bridge] type=Bridge -delay=0 -queue_size_a=16 -queue_size_b=16 +delay=50000 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=4000 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=testsys.iobus.port[0] side_b=testsys.membus.port[0] @@ -785,6 +801,7 @@ sys=testsys [testsys.iobus] type=Bus +block_size=64 bus_id=0 clock=1000 responder_set=true @@ -795,12 +812,13 @@ port=testsys.bridge.side_a testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio t [testsys.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=1000 responder_set=false width=64 default=testsys.membus.responder.pio -port=testsys.bridge.side_b testsys.physmem.port testsys.cpu.icache_port testsys.cpu.dcache_port +port=testsys.bridge.side_b testsys.physmem.port[0] testsys.cpu.icache_port testsys.cpu.dcache_port [testsys.membus.responder] type=IsaFake @@ -891,6 +909,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:02 intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 @@ -1263,6 +1283,8 @@ children=configdata config_latency=20000 configdata=testsys.tsunami.ide.configdata disks=testsys.disk0 testsys.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out index f9fd380da..1ed581be9 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out @@ -18,7 +18,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-stream-client.rcS +readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-stream-client.rcS symbolfile= init_param=0 system_type=34 @@ -30,6 +30,7 @@ bus_id=1 clock=1000 width=64 responder_set=false +block_size=64 [testsys.intrctrl] type=IntrControl @@ -57,10 +58,15 @@ system=testsys [testsys.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [testsys.disk0.image.child] type=RawDiskImage @@ -479,6 +485,8 @@ BAR5Size=0 type=NSGigE system=testsys platform=testsys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=testsys.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -601,6 +609,8 @@ BAR5Size=0 type=IdeController system=testsys platform=testsys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=testsys.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -615,6 +625,7 @@ bus_id=0 clock=1000 width=64 responder_set=true +block_size=64 [drivesys.physmem] type=PhysicalMemory @@ -632,7 +643,7 @@ kernel=/dist/m5/system/binaries/vmlinux console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 -readfile=/z/saidi/work/m5.newmem/configs/boot/netperf-server.rcS +readfile=/Users/nate/work/m5/outgoing/configs/boot/netperf-server.rcS symbolfile= init_param=0 system_type=34 @@ -686,6 +697,8 @@ BAR5Size=0 type=NSGigE system=drivesys platform=drivesys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=drivesys.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -736,6 +749,7 @@ bus_id=1 clock=1000 width=64 responder_set=false +block_size=64 [drivesys.membus.responder] type=IsaFake @@ -754,10 +768,15 @@ system=drivesys [drivesys.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 -delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 +delay=50000 +nack_delay=4000 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [drivesys.disk0.image.child] type=RawDiskImage @@ -1229,6 +1248,8 @@ BAR5Size=0 type=IdeController system=drivesys platform=drivesys.tsunami +min_backoff_delay=4000 +max_backoff_delay=10000000 configdata=drivesys.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -1243,4 +1264,5 @@ bus_id=0 clock=1000 width=64 responder_set=true +block_size=64 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index 8ef183435..e6bc6fb19 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -39,12 +39,11 @@ drivesys.cpu.kern.ipl_good_0 1189 45.85% 45.85% # nu drivesys.cpu.kern.ipl_good_21 10 0.39% 46.24% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_22 205 7.91% 54.15% # number of times we switched to this ipl from a different ipl drivesys.cpu.kern.ipl_good_31 1189 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks 199572064520 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks_0 199571744808 100.00% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks 199572412849 # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks_0 199572093137 100.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_21 1620 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_ticks_31 300462 0.00% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_used 0.618707 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl @@ -55,13 +54,13 @@ drivesys.cpu.kern.mode_good_idle 3 drivesys.cpu.kern.mode_switch_kernel 174 # number of protection mode switches drivesys.cpu.kern.mode_switch_user 107 # number of protection mode switches drivesys.cpu.kern.mode_switch_idle 218 # number of protection mode switches -drivesys.cpu.kern.mode_switch_good 0.440882 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good 1.645945 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_kernel 0.632184 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good_idle 0.013761 # fraction of useful protection mode switches drivesys.cpu.kern.mode_ticks_kernel 263256 0.24% 0.24% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_user 1278343 1.18% 1.43% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks_idle 106485080 98.57% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_user 1278343 1.16% 1.40% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks_idle 108485080 98.60% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 70 # number of times the context was actually changed drivesys.cpu.kern.syscall 22 # number of syscalls executed drivesys.cpu.kern.syscall_2 1 4.55% 4.55% # number of syscalls executed @@ -101,9 +100,9 @@ drivesys.tsunami.ethernet.coalescedTotal 1 # av drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -drivesys.tsunami.ethernet.descDMAReads 5 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 4 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 120 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 96 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped drivesys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU @@ -131,7 +130,7 @@ drivesys.tsunami.ethernet.totalRxOk 0 # to drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -drivesys.tsunami.ethernet.totalTxIdle 5 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 4 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR drivesys.tsunami.ethernet.txBandwidth 31920 # Transmit Bandwidth (bits/s) drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted @@ -140,35 +139,34 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 36787265 # Simulator instruction rate (inst/s) -host_mem_usage 407784 # Number of bytes of host memory used -host_seconds 7.46 # Real time elapsed on the host -host_tick_rate 26810828297 # Simulator tick rate (ticks/s) +host_inst_rate 6618724 # Simulator instruction rate (inst/s) +host_seconds 41.30 # Real time elapsed on the host +host_tick_rate 4842704130 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 274411697 # Number of instructions simulated +sim_insts 273348482 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated sim_ticks 200000789468 # Number of ticks simulated testsys.cpu.dtb.accesses 335402 # DTB accesses testsys.cpu.dtb.acv 161 # DTB access violations -testsys.cpu.dtb.hits 1163325 # DTB hits +testsys.cpu.dtb.hits 1163322 # DTB hits testsys.cpu.dtb.misses 3815 # DTB misses testsys.cpu.dtb.read_accesses 225414 # DTB read accesses testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_hits 658458 # DTB read hits +testsys.cpu.dtb.read_hits 658456 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.write_accesses 109988 # DTB write accesses testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_hits 504867 # DTB write hits +testsys.cpu.dtb.write_hits 504866 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.idle_fraction 0.999999 # Percentage of idle cycles -testsys.cpu.itb.accesses 1249840 # ITB accesses +testsys.cpu.itb.accesses 1249851 # ITB accesses testsys.cpu.itb.acv 69 # ITB acv -testsys.cpu.itb.hits 1248343 # ITB hits +testsys.cpu.itb.hits 1248354 # ITB hits testsys.cpu.itb.misses 1497 # ITB misses -testsys.cpu.kern.callpal 13124 # number of callpals executed +testsys.cpu.kern.callpal 13125 # number of callpals executed testsys.cpu.kern.callpal_swpctx 438 3.34% 3.34% # number of callpals executed testsys.cpu.kern.callpal_tbi 20 0.15% 3.49% # number of callpals executed -testsys.cpu.kern.callpal_swpipl 11076 84.40% 87.88% # number of callpals executed +testsys.cpu.kern.callpal_swpipl 11077 84.40% 87.89% # number of callpals executed testsys.cpu.kern.callpal_rdps 359 2.74% 90.62% # number of callpals executed testsys.cpu.kern.callpal_wrusp 3 0.02% 90.64% # number of callpals executed testsys.cpu.kern.callpal_rdusp 3 0.02% 90.67% # number of callpals executed @@ -176,41 +174,40 @@ testsys.cpu.kern.callpal_rti 1041 7.93% 98.60% # nu testsys.cpu.kern.callpal_callsys 140 1.07% 99.66% # number of callpals executed testsys.cpu.kern.callpal_imb 44 0.34% 100.00% # number of callpals executed testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.hwrei 19055 # number of hwrei instructions executed -testsys.cpu.kern.inst.quiesce 377 # number of quiesce instructions executed -testsys.cpu.kern.ipl_count 12506 # number of times we switched to this ipl +testsys.cpu.kern.inst.hwrei 19056 # number of hwrei instructions executed +testsys.cpu.kern.inst.quiesce 376 # number of quiesce instructions executed +testsys.cpu.kern.ipl_count 12507 # number of times we switched to this ipl testsys.cpu.kern.ipl_count_0 5061 40.47% 40.47% # number of times we switched to this ipl testsys.cpu.kern.ipl_count_21 184 1.47% 41.94% # number of times we switched to this ipl testsys.cpu.kern.ipl_count_22 205 1.64% 43.58% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count_31 7056 56.42% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count_31 7057 56.42% 100.00% # number of times we switched to this ipl testsys.cpu.kern.ipl_good 10499 # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_0 5055 48.15% 48.15% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_21 184 1.75% 49.90% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_22 205 1.95% 51.85% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good_31 5055 48.15% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks 199569922466 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_0 199569307215 100.00% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks 199570420798 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks_0 199569805534 100.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_21 31026 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks_22 17630 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks_31 566595 0.00% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used 0.839517 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_ticks_31 566608 0.00% 100.00% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used_0 0.998814 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used_31 0.716412 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.mode_good_kernel 654 -testsys.cpu.kern.mode_good_user 649 +testsys.cpu.kern.ipl_used_31 0.716310 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.mode_good_kernel 655 +testsys.cpu.kern.mode_good_user 650 testsys.cpu.kern.mode_good_idle 5 -testsys.cpu.kern.mode_switch_kernel 1099 # number of protection mode switches -testsys.cpu.kern.mode_switch_user 649 # number of protection mode switches -testsys.cpu.kern.mode_switch_idle 381 # number of protection mode switches -testsys.cpu.kern.mode_switch_good 0.614373 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_kernel 0.595086 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_kernel 1100 # number of protection mode switches +testsys.cpu.kern.mode_switch_user 650 # number of protection mode switches +testsys.cpu.kern.mode_switch_idle 380 # number of protection mode switches +testsys.cpu.kern.mode_switch_good 1.608612 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good_kernel 0.595455 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good_idle 0.013123 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks_kernel 1821131 2.16% 2.16% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_user 1065606 1.26% 3.42% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks_idle 81402279 96.58% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_switch_good_idle 0.013158 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks_kernel 1822940 2.12% 2.12% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_user 1065616 1.24% 3.36% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks_idle 83000460 96.64% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.cpu.kern.syscall 83 # number of syscalls executed testsys.cpu.kern.syscall_2 3 3.61% 3.61% # number of syscalls executed @@ -235,9 +232,9 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 3566068 # number of cpu cycles simulated -testsys.cpu.num_insts 3564502 # Number of instructions executed -testsys.cpu.num_refs 1173608 # Number of memory references +testsys.cpu.numCycles 3566060 # number of cpu cycles simulated +testsys.cpu.num_insts 3564494 # Number of instructions executed +testsys.cpu.num_refs 1173605 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -259,9 +256,9 @@ testsys.tsunami.ethernet.coalescedTotal 1 # av testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -testsys.tsunami.ethernet.descDMAReads 8 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 6 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 192 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 144 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped testsys.tsunami.ethernet.postedInterrupts 10 # number of posts to CPU @@ -289,7 +286,7 @@ testsys.tsunami.ethernet.totalRxOk 0 # to testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -testsys.tsunami.ethernet.totalTxIdle 8 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 6 # total number of TxIdle written to ISR testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR testsys.tsunami.ethernet.txBandwidth 38400 # Transmit Bandwidth (bits/s) testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted @@ -383,12 +380,11 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 80923531996 # Simulator instruction rate (inst/s) -host_mem_usage 407784 # Number of bytes of host memory used +host_inst_rate 65191624612 # Simulator instruction rate (inst/s) host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 216582530 # Simulator tick rate (ticks/s) +host_tick_rate 183725573 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 274411697 # Number of instructions simulated +sim_insts 273348482 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated sim_ticks 785978 # Number of ticks simulated testsys.cpu.dtb.accesses 0 # DTB accesses diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout index 4fb87de69..08d7271d7 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 30 2007 13:38:38 -M5 started Mon Apr 30 14:01:42 2007 -M5 executing on zeep -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled Jun 10 2007 14:10:03 +M5 started Mon Jun 11 01:47:32 2007 +M5 executing on iceaxe +command line: /Users/nate/build/outgoing/build/ALPHA_FS/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_FS/tests/debug/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -Exiting @ tick 4300236342388 because checkpoint +Exiting @ tick 4300235844056 because checkpoint diff --git a/util/make_release.py b/util/make_release.py index 09629a78a..636391a96 100755 --- a/util/make_release.py +++ b/util/make_release.py @@ -120,10 +120,6 @@ when = int(time.time()) + 120 # make sure scons doesn't try to run flex unnecessarily touch(release_dir, 'src/encumbered/eio/exolex.cc', when=(when, when)) -# make sure libelf doesn't try to rebuild the de.msg file since it -# might fail on non linux machines -touch(release_dir, 'ext/libelf/po/de.msg', when=(when, when)) - # get rid of non-shipping code rmtree(release_dir, 'src/encumbered/dev') rmtree(release_dir, 'src/cpu/ozone') |