diff options
| -rw-r--r-- | arch/alpha/alpha_memory.cc | 6 | ||||
| -rw-r--r-- | arch/alpha/alpha_memory.hh | 6 | ||||
| -rw-r--r-- | cpu/exec_context.hh | 18 | ||||
| -rw-r--r-- | cpu/memtest/memtest.cc | 2 | ||||
| -rw-r--r-- | cpu/memtest/memtest.hh | 4 | ||||
| -rw-r--r-- | dev/alpha_console.cc | 4 | ||||
| -rw-r--r-- | dev/alpha_console.hh | 4 |
7 files changed, 22 insertions, 22 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index d934299b8..0f9ad2cfc 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -83,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const void -AlphaTlb::checkCacheability(MemReqPtr req) +AlphaTlb::checkCacheability(MemReqPtr &req) { // in Alpha, cacheability is controlled by upper-level bits of the // physical address @@ -260,7 +260,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const Fault -AlphaItb::translate(MemReqPtr req) const +AlphaItb::translate(MemReqPtr &req) const { InternalProcReg *ipr = req->xc->regs.ipr; @@ -425,7 +425,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const } Fault -AlphaDtb::translate(MemReqPtr req, bool write) const +AlphaDtb::translate(MemReqPtr &req, bool write) const { RegFile *regs = &req->xc->regs; Addr pc = regs->pc; diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh index bfcd313e2..482a13eee 100644 --- a/arch/alpha/alpha_memory.hh +++ b/arch/alpha/alpha_memory.hh @@ -70,7 +70,7 @@ class AlphaTlb : public SimObject return (unimplBits == 0) || (unimplBits == VA_UNIMPL_MASK); } - static void checkCacheability(MemReqPtr req); + static void checkCacheability(MemReqPtr &req); // Checkpointing virtual void serialize(std::ostream &os); @@ -92,7 +92,7 @@ class AlphaItb : public AlphaTlb AlphaItb(const std::string &name, int size); virtual void regStats(); - Fault translate(MemReqPtr req) const; + Fault translate(MemReqPtr &req) const; }; class AlphaDtb : public AlphaTlb @@ -118,7 +118,7 @@ class AlphaDtb : public AlphaTlb AlphaDtb(const std::string &name, int size); virtual void regStats(); - Fault translate(MemReqPtr req, bool write) const; + Fault translate(MemReqPtr &req, bool write) const; }; #endif // __ALPHA_MEMORY_HH__ diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index f3c4b8015..b49db9720 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -189,17 +189,17 @@ class ExecContext int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } - Fault translateInstReq(MemReqPtr req) + Fault translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault translateDataReadReq(MemReqPtr req) + Fault translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault translateDataWriteReq(MemReqPtr req) + Fault translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } @@ -214,7 +214,7 @@ class ExecContext int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault dummyTranslation(MemReqPtr req) + Fault dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -225,15 +225,15 @@ class ExecContext req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; return No_Fault; } - Fault translateInstReq(MemReqPtr req) + Fault translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataReadReq(MemReqPtr req) + Fault translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataWriteReq(MemReqPtr req) + Fault translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -241,7 +241,7 @@ class ExecContext #endif template <class T> - Fault read(MemReqPtr req, T& data) + Fault read(MemReqPtr &req, T& data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) if (req->flags & LOCKED) { @@ -254,7 +254,7 @@ class ExecContext } template <class T> - Fault write(MemReqPtr req, T& data) + Fault write(MemReqPtr &req, T& data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc index db24bb507..4ec5eed59 100644 --- a/cpu/memtest/memtest.cc +++ b/cpu/memtest/memtest.cc @@ -119,7 +119,7 @@ printData(ostream &os, uint8_t *data, int nbytes) } void -MemTest::completeRequest(MemReqPtr req, uint8_t *data) +MemTest::completeRequest(MemReqPtr &req, uint8_t *data) { switch (req->cmd) { case Read: diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh index 3e7dff968..09f22a177 100644 --- a/cpu/memtest/memtest.hh +++ b/cpu/memtest/memtest.hh @@ -108,7 +108,7 @@ class MemTest : public BaseCPU Statistics::Scalar<> numCopies; // called by MemCompleteEvent::process() - void completeRequest(MemReqPtr req, uint8_t *data); + void completeRequest(MemReqPtr &req, uint8_t *data); friend class MemCompleteEvent; }; @@ -122,7 +122,7 @@ class MemCompleteEvent : public Event public: - MemCompleteEvent(MemReqPtr _req, uint8_t *_data, MemTest *_tester) + MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester) : Event(&mainEventQueue), req(_req), data(_data), tester(_tester) { diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 8e59db932..e708be514 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -73,7 +73,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, } Fault -AlphaConsole::read(MemReqPtr req, uint8_t *data) +AlphaConsole::read(MemReqPtr &req, uint8_t *data) { memset(data, 0, req->size); uint64_t val; @@ -109,7 +109,7 @@ AlphaConsole::read(MemReqPtr req, uint8_t *data) } Fault -AlphaConsole::write(MemReqPtr req, const uint8_t *data) +AlphaConsole::write(MemReqPtr &req, const uint8_t *data) { uint64_t val; diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh index 9e774773e..c39b8e8d4 100644 --- a/dev/alpha_console.hh +++ b/dev/alpha_console.hh @@ -94,8 +94,8 @@ class AlphaConsole : public MmapDevice /** * memory mapped reads and writes */ - virtual Fault read(MemReqPtr req, uint8_t *data); - virtual Fault write(MemReqPtr req, const uint8_t *data); + virtual Fault read(MemReqPtr &req, uint8_t *data); + virtual Fault write(MemReqPtr &req, const uint8_t *data); /** * standard serialization routines for checkpointing |