summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/cpu/o3/O3CPU.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 042c5e637..3138aebbf 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -141,6 +141,7 @@ class DerivO3CPU(BaseCPU):
warnOnlyOnLoadError=True)
self.checker.itb = ArmTLB(size = self.itb.size)
self.checker.dtb = ArmTLB(size = self.dtb.size)
+ self.checker.cpu_id = self.cpu_id
else:
print "ERROR: Checker only supported under ARM ISA!"