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-rw-r--r--src/arch/alpha/isa/decoder.isa8
-rw-r--r--src/arch/arm/isa/templates/pred.isa4
-rw-r--r--src/arch/sparc/isa/decoder.isa2
-rw-r--r--src/arch/sparc/isa/includes.isa5
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa8
-rw-r--r--src/arch/x86/isa/includes.isa4
6 files changed, 1 insertions, 30 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 359c6b3b2..d0aa13d38 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -944,7 +944,6 @@ decode OPCODE default Unknown::unknown() {
format BasicOperate {
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
-#if FULL_SYSTEM
0x00: arm({{
PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
@@ -960,7 +959,6 @@ decode OPCODE default Unknown::unknown() {
0x04: quiesceTime({{
R0 = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
-#endif
0x07: rpns({{
R0 = PseudoInst::rpns(xc->tcBase());
}}, IsNonSpeculative, IsUnverifiable);
@@ -980,14 +978,12 @@ decode OPCODE default Unknown::unknown() {
0x21: m5exit({{
PseudoInst::m5exit(xc->tcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
-#if FULL_SYSTEM
0x31: loadsymbol({{
PseudoInst::loadsymbol(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x30: initparam({{
Ra = PseudoInst::initParam(xc->tcBase());
}});
-#endif
0x40: resetstats({{
PseudoInst::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
@@ -1000,22 +996,18 @@ decode OPCODE default Unknown::unknown() {
0x43: m5checkpoint({{
PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
-#if FULL_SYSTEM
0x50: m5readfile({{
R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
}}, IsNonSpeculative);
-#endif
0x51: m5break({{
PseudoInst::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
PseudoInst::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
-#if FULL_SYSTEM
0x53: m5addsymbol({{
PseudoInst::addsymbol(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
-#endif
0x54: m5panic({{
panic("M5 panic instruction called at pc = %#x.", PC);
}}, IsNonSpeculative);
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 8b7ff69e7..8d9d16492 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -196,9 +196,7 @@ def template QuiescePredOpExecute {{
}
} else {
xc->setPredicate(false);
-#if FULL_SYSTEM
PseudoInst::quiesceSkip(xc->tcBase());
-#endif
}
return fault;
@@ -224,9 +222,7 @@ def template QuiescePredOpExecuteWithFixup {{
} else {
xc->setPredicate(false);
%(pred_fixup)s;
-#if FULL_SYSTEM
PseudoInst::quiesceSkip(xc->tcBase());
-#endif
}
return fault;
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 82c712eb0..0e515ea2b 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -975,7 +975,6 @@ decode OP default Unknown::unknown()
}
// M5 special opcodes use the reserved IMPDEP2A opcode space
0x37: decode M5FUNC {
-#if FULL_SYSTEM
format BasicOperate {
// we have 7 bits of space here to play with...
0x21: m5exit({{
@@ -991,7 +990,6 @@ decode OP default Unknown::unknown()
panic("M5 panic instruction called at pc = %#x.", PC);
}}, No_OpClass, IsNonSpeculative);
}
-#endif
default: Trap::impdep2({{fault = new IllegalInstruction;}});
}
0x38: Branch::jmpl({{
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index db3677752..0c49cee16 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -63,10 +63,6 @@ using namespace SparcISA;
output exec {{
#include "base/fenv.hh"
-#if FULL_SYSTEM
-#include "sim/pseudo_inst.hh"
-#endif
-
#include <cmath>
#include <limits>
@@ -78,6 +74,7 @@ output exec {{
#include "debug/Sparc.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
using namespace SparcISA;
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index f856f2d37..e4df4ac66 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -136,7 +136,6 @@
//0x04: loadall_or_reset_or_hang();
0x4: decode IMMEDIATE {
format BasicOperate {
-#if FULL_SYSTEM
0x00: m5arm({{
PseudoInst::arm(xc->tcBase());
}}, IsNonSpeculative);
@@ -152,21 +151,18 @@
0x04: m5quiesceTime({{
Rax = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative);
-#endif
0x07: m5rpns({{
Rax = PseudoInst::rpns(xc->tcBase());
}}, IsNonSpeculative);
0x21: m5exit({{
PseudoInst::m5exit(xc->tcBase(), Rdi);
}}, IsNonSpeculative);
-#if FULL_SYSTEM
0x30: m5initparam({{
Rax = PseudoInst::initParam(xc->tcBase());
}}, IsNonSpeculative);
0x31: m5loadsymbol({{
PseudoInst::loadsymbol(xc->tcBase());
}}, IsNonSpeculative);
-#endif
0x40: m5resetstats({{
PseudoInst::resetstats(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
@@ -179,23 +175,19 @@
0x43: m5checkpoint({{
PseudoInst::m5checkpoint(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
-#if FULL_SYSTEM
0x50: m5readfile({{
Rax = PseudoInst::readfile(
xc->tcBase(), Rdi, Rsi, Rdx);
}}, IsNonSpeculative);
-#endif
0x51: m5debugbreak({{
PseudoInst::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
PseudoInst::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
-#if FULL_SYSTEM
0x53: m5addsymbol({{
PseudoInst::addsymbol(xc->tcBase(), Rdi, Rsi);
}}, IsNonSpeculative);
-#endif
0x54: m5panic({{
panic("M5 panic instruction called at pc = %#x.\n",
RIP);
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index dc8abbc66..237b29877 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -102,10 +102,6 @@ output exec {{
#include <ieeefp.h>
#endif
-#if FULL_SYSTEM
-#include "sim/pseudo_inst.hh"
-#endif
-
#include <cmath>
#include <limits>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 05:54:14 +0000