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-rw-r--r--src/arch/alpha/isa/decoder.isa2
-rw-r--r--src/arch/mips/SConscript3
-rw-r--r--src/arch/mips/isa/decoder.isa3
-rw-r--r--src/arch/mips/isa/includes.isa1
-rw-r--r--src/arch/mips/isa_traits.cc100
-rwxr-xr-xsrc/arch/mips/mt_constants.hh1
-rwxr-xr-xsrc/arch/mips/regfile/misc_regfile.cc8
-rw-r--r--src/arch/mips/regfile/misc_regfile.hh11
-rw-r--r--src/arch/mips/regfile/regfile.hh8
-rw-r--r--src/arch/mips/utility.hh2
-rw-r--r--src/arch/sparc/isa/decoder.isa4
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/decoder/x87.isa4
-rw-r--r--src/arch/x86/isa/microops/ldstop.isa2
-rw-r--r--src/arch/x86/process.cc5
-rw-r--r--src/cpu/base_dyn_inst.hh1
-rw-r--r--src/cpu/nativetrace.cc173
-rw-r--r--src/cpu/nativetrace.hh111
-rw-r--r--src/cpu/static_inst.hh4
-rw-r--r--src/sim/insttracer.hh1
-rw-r--r--tests/long/70.twolf/test.py2
21 files changed, 226 insertions, 222 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index af1a91a62..2177e8c4f 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -714,7 +714,7 @@ decode OPCODE default Unknown::unknown() {
}}, IsNonSpeculative);
0x83: callsys({{
xc->syscall(R0);
- }}, IsSerializeAfter, IsNonSpeculative);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
// Write uniq reg with value from ABI arg register (r16)
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index de209348a..658710389 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -34,8 +34,9 @@ Import('*')
if env['TARGET_ISA'] == 'mips':
Source('faults.cc')
- Source('isa_traits.cc')
+ Source('regfile/int_regfile.cc')
Source('regfile/misc_regfile.cc')
+ Source('regfile/regfile.cc')
Source('utility.cc')
Source('dsp.cc')
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index e55d2e070..40ea223f6 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -134,7 +134,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
0x4: syscall({{ xc->syscall(R2); }},
- IsSerializeAfter, IsNonSpeculative);
+ IsSerializeAfter, IsNonSpeculative,
+ IsSyscall);
0x7: sync({{ ; }}, IsMemBarrier);
}
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 0e0cf44eb..0ce807a24 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -72,6 +72,7 @@ output exec {{
#include "arch/mips/dsp.hh"
#include "arch/mips/pra_constants.hh"
#include "arch/mips/dt_constants.hh"
+#include "arch/mips/mt.hh"
#include "arch/mips/mt_constants.hh"
#include <math.h>
diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc
deleted file mode 100644
index 0c84ce2b2..000000000
--- a/src/arch/mips/isa_traits.cc
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- * Korey Sewell
- */
-
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/regfile/regfile.hh"
-#include "sim/serialize.hh"
-#include "base/bitfield.hh"
-
-using namespace MipsISA;
-using namespace std;
-
-void
-MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
- panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-void
-MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
-{
- panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-void
-IntRegFile::serialize(std::ostream &os)
-{
- SERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void
-IntRegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
- UNSERIALIZE_ARRAY(regs, NumIntRegs);
-}
-
-void
-RegFile::serialize(std::ostream &os)
-{
- intRegFile.serialize(os);
- //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
- //SERIALZE_ARRAY(miscRegFile);
- //SERIALIZE_SCALAR(miscRegs.fpcr);
- //SERIALIZE_SCALAR(miscRegs.lock_flag);
- //SERIALIZE_SCALAR(miscRegs.lock_addr);
- SERIALIZE_SCALAR(pc);
- SERIALIZE_SCALAR(npc);
- SERIALIZE_SCALAR(nnpc);
-}
-
-
-void
-RegFile::unserialize(Checkpoint *cp, const std::string &section)
-{
- intRegFile.unserialize(cp, section);
- //UNSERIALIZE_ARRAY(floatRegFile);
- //UNSERIALZE_ARRAY(miscRegFile);
- //UNSERIALIZE_SCALAR(miscRegs.fpcr);
- //UNSERIALIZE_SCALAR(miscRegs.lock_flag);
- //UNSERIALIZE_SCALAR(miscRegs.lock_addr);
- UNSERIALIZE_SCALAR(pc);
- UNSERIALIZE_SCALAR(npc);
- UNSERIALIZE_SCALAR(nnpc);
-
-}
-
-
diff --git a/src/arch/mips/mt_constants.hh b/src/arch/mips/mt_constants.hh
index 0f6978433..57306d237 100755
--- a/src/arch/mips/mt_constants.hh
+++ b/src/arch/mips/mt_constants.hh
@@ -31,7 +31,6 @@
#ifndef __ARCH_MIPS_MT_CONSTANTS_HH__
#define __ARCH_MIPS_MT_CONSTANTS_HH__
-#include "arch/mips/types.hh"
//#include "config/full_system.hh"
namespace MipsISA
diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index c97d93cf9..8f8899e92 100755
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -30,13 +30,13 @@
#include "base/bitfield.hh"
-#include "arch/mips/regfile/misc_regfile.hh"
-#include "arch/mips/mt_constants.hh"
#include "arch/mips/faults.hh"
+#include "arch/mips/mt.hh"
+#include "arch/mips/mt_constants.hh"
+#include "arch/mips/regfile/misc_regfile.hh"
-#include "cpu/thread_context.hh"
#include "cpu/base.hh"
-#include "cpu/exetrace.hh"
+#include "cpu/thread_context.hh"
//#include "cpu/mixie/cpu.hh"
using namespace std;
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 54b086a8b..0846378bb 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -33,14 +33,12 @@
#include "arch/mips/isa_traits.hh"
#include "arch/mips/types.hh"
-#include "arch/mips/mt.hh"
-#include "arch/mips/mt_constants.hh"
-#include "base/bitfield.hh"
-#include "cpu/base.hh"
+#include "sim/eventq.hh"
#include "sim/faults.hh"
#include <queue>
class ThreadContext;
+class BaseCPU;
namespace MipsISA
{
@@ -76,7 +74,10 @@ namespace MipsISA
void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
- void copyMiscRegs(ThreadContext *tc);
+ void copyMiscRegs(ThreadContext *tc)
+ {
+ panic("Copy Misc. Regs Not Implemented Yet\n");
+ }
inline unsigned getVPENum(unsigned tid);
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index f13653132..b83bb576b 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -32,8 +32,6 @@
#define __ARCH_MIPS_REGFILE_REGFILE_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/mt.hh"
#include "arch/mips/regfile/int_regfile.hh"
#include "arch/mips/regfile/float_regfile.hh"
#include "arch/mips/regfile/misc_regfile.hh"
@@ -189,9 +187,11 @@ namespace MipsISA
return reg;
}
- void copyRegs(ThreadContext *src, ThreadContext *dest);
+ void
+ copyRegs(ThreadContext *src, ThreadContext *dest);
- void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+ void
+ copyMiscRegs(ThreadContext *src, ThreadContext *dest);
} // namespace MipsISA
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 6195c4ceb..300761c93 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -74,8 +74,6 @@ namespace MipsISA {
void startupCPU(ThreadContext *tc, int cpuId);
- void copyRegs(ThreadContext *src, ThreadContext *dest);
-
// Instruction address compression hooks
static inline Addr realPCToFetchPC(const Addr &addr) {
return addr;
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 68b2183ad..14c652606 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1230,7 +1230,7 @@ decode OP default Unknown::unknown()
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
fault = new TrapInstruction(lTrapNum);
}
- }}, IsSerializeAfter, IsNonSpeculative);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
0x2: Trap::tccx({{
if(passesCondition(Ccr<7:4>, COND2))
{
@@ -1238,7 +1238,7 @@ decode OP default Unknown::unknown()
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
fault = new TrapInstruction(lTrapNum);
}
- }}, IsSerializeAfter, IsNonSpeculative);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
}
0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
MemWriteOp);
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index a8c4e7062..e8307c6e6 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -70,7 +70,7 @@
#if FULL_SYSTEM
0x05: syscall();
#else
- 0x05: SyscallInst::syscall('xc->syscall(rax)');
+ 0x05: SyscallInst::syscall('xc->syscall(rax)', IsSyscall);
#endif
0x06: clts();
//sandpile.org says (AMD) after sysret, so I might want to check
diff --git a/src/arch/x86/isa/decoder/x87.isa b/src/arch/x86/isa/decoder/x87.isa
index f16647fe5..bab687acd 100644
--- a/src/arch/x86/isa/decoder/x87.isa
+++ b/src/arch/x86/isa/decoder/x87.isa
@@ -103,7 +103,7 @@
0x5: fldln2();
0x6: fldz();
}
- default: fldcw();
+ default: fldcw_Mw();
}
0x6: decode MODRM_MOD {
0x3: decode MODRM_RM {
@@ -129,7 +129,7 @@
0x6: fsin();
0x7: fcos();
}
- default: fnstcw();
+ default: fnstcw_Mw();
}
}
//0x2: esc2();
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 18cbc6082..b8cddb09b 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -170,7 +170,7 @@ def template MicroLoadCompleteAcc {{
%(op_rd)s;
Mem = pkt->get<typeof(Mem)>();
- int offset = pkt->flags;
+ int offset = pkt->req->getFlags();
Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8);
%(code)s;
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 036805612..17904cb33 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -412,11 +412,6 @@ X86LiveProcess::argsInit(int intSize, int pageSize)
initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
- //Set up the thread context to start running the process
- //Because of the peculiarities of how syscall works, I believe
- //a process starts with r11 containing the value of eflags or maybe r11
- //from before the call to execve. Empirically this value is 0x200.
- threadContexts[0]->setIntReg(INTREG_R11, 0x200);
//Set the stack pointer register
threadContexts[0]->setIntReg(StackPointerReg, stack_min);
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index a55c1e3c0..362babeff 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -498,6 +498,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
bool isQuiesce() const { return staticInst->isQuiesce(); }
bool isIprAccess() const { return staticInst->isIprAccess(); }
bool isUnverifiable() const { return staticInst->isUnverifiable(); }
+ bool isSyscall() const { return staticInst->isSyscall(); }
bool isMacroop() const { return staticInst->isMacroop(); }
bool isMicroop() const { return staticInst->isMicroop(); }
bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc
index 90a0e1a62..fe524e245 100644
--- a/src/cpu/nativetrace.cc
+++ b/src/cpu/nativetrace.cc
@@ -60,119 +60,122 @@ NativeTrace::NativeTrace(const std::string & _name) : InstTracer(_name)
}
ccprintf(cerr, "Listening for native process on port %d\n", port);
fd = native_listener.accept();
+ checkRcx = true;
+ checkR11 = true;
}
bool
-NativeTraceRecord::checkIntReg(const char * regName, int index, int size)
+NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
{
- uint64_t regVal;
- int res = read(parent->fd, &regVal, size);
- if(res < 0)
- panic("Read call failed! %s\n", strerror(errno));
- regVal = TheISA::gtoh(regVal);
- uint64_t realRegVal = thread->readIntReg(index);
- if(regVal != realRegVal)
- {
- DPRINTFN("Register %s should be %#x but is %#x.\n",
- regName, regVal, realRegVal);
- return false;
- }
+ if(!checkRcx)
+ checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
+ if(checkRcx)
+ return checkReg(name, mVal, nVal);
return true;
}
-bool NativeTraceRecord::checkPC(const char * regName, int size)
+bool
+NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
{
- uint64_t regVal;
- int res = read(parent->fd, &regVal, size);
- if(res < 0)
- panic("Read call failed! %s\n", strerror(errno));
- regVal = TheISA::gtoh(regVal);
- uint64_t realRegVal = thread->readNextPC();
- if(regVal != realRegVal)
- {
- DPRINTFN("%s should be %#x but is %#x.\n",
- regName, regVal, realRegVal);
- return false;
- }
+ if(!checkR11)
+ checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
+ if(checkR11)
+ return checkReg(name, mVal, nVal);
return true;
}
void
Trace::NativeTraceRecord::dump()
{
-// ostream &outs = Trace::output();
-
//Don't print what happens for each micro-op, just print out
//once at the last op, and for regular instructions.
if(!staticInst->isMicroop() || staticInst->isLastMicroop())
+ parent->check(thread, staticInst->isSyscall());
+}
+
+void
+Trace::NativeTrace::check(ThreadContext * tc, bool isSyscall)
+{
+// ostream &outs = Trace::output();
+ nState.update(fd);
+ mState.update(tc);
+
+ if(isSyscall)
{
- checkIntReg("rax", INTREG_RAX, sizeof(uint64_t));
- checkIntReg("rcx", INTREG_RCX, sizeof(uint64_t));
- checkIntReg("rdx", INTREG_RDX, sizeof(uint64_t));
- checkIntReg("rbx", INTREG_RBX, sizeof(uint64_t));
- checkIntReg("rsp", INTREG_RSP, sizeof(uint64_t));
- checkIntReg("rbp", INTREG_RBP, sizeof(uint64_t));
- checkIntReg("rsi", INTREG_RSI, sizeof(uint64_t));
- checkIntReg("rdi", INTREG_RDI, sizeof(uint64_t));
- checkIntReg("r8", INTREG_R8, sizeof(uint64_t));
- checkIntReg("r9", INTREG_R9, sizeof(uint64_t));
- checkIntReg("r10", INTREG_R10, sizeof(uint64_t));
- checkIntReg("r11", INTREG_R11, sizeof(uint64_t));
- checkIntReg("r12", INTREG_R12, sizeof(uint64_t));
- checkIntReg("r13", INTREG_R13, sizeof(uint64_t));
- checkIntReg("r14", INTREG_R14, sizeof(uint64_t));
- checkIntReg("r15", INTREG_R15, sizeof(uint64_t));
- checkPC("rip", sizeof(uint64_t));
+ checkRcx = false;
+ checkR11 = false;
+ oldRcxVal = mState.rcx;
+ oldRealRcxVal = nState.rcx;
+ oldR11Val = mState.r11;
+ oldRealR11Val = nState.r11;
+ }
+
+ checkReg("rax", mState.rax, nState.rax);
+ checkRcxReg("rcx", mState.rcx, nState.rcx);
+ checkReg("rdx", mState.rdx, nState.rdx);
+ checkReg("rbx", mState.rbx, nState.rbx);
+ checkReg("rsp", mState.rsp, nState.rsp);
+ checkReg("rbp", mState.rbp, nState.rbp);
+ checkReg("rsi", mState.rsi, nState.rsi);
+ checkReg("rdi", mState.rdi, nState.rdi);
+ checkReg("r8", mState.r8, nState.r8);
+ checkReg("r9", mState.r9, nState.r9);
+ checkReg("r10", mState.r10, nState.r10);
+ checkR11Reg("r11", mState.r11, nState.r11);
+ checkReg("r12", mState.r12, nState.r12);
+ checkReg("r13", mState.r13, nState.r13);
+ checkReg("r14", mState.r14, nState.r14);
+ checkReg("r15", mState.r15, nState.r15);
+ checkReg("rip", mState.rip, nState.rip);
#if THE_ISA == SPARC_ISA
- /*for(int f = 0; f <= 62; f+=2)
- {
- uint64_t regVal;
- int res = read(fd, &regVal, sizeof(regVal));
- if(res < 0)
- panic("First read call failed! %s\n", strerror(errno));
- regVal = TheISA::gtoh(regVal);
- uint64_t realRegVal = thread->readFloatRegBits(f, 64);
- if(regVal != realRegVal)
- {
- DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal);
- }
- }*/
+ /*for(int f = 0; f <= 62; f+=2)
+ {
uint64_t regVal;
int res = read(fd, &regVal, sizeof(regVal));
if(res < 0)
panic("First read call failed! %s\n", strerror(errno));
regVal = TheISA::gtoh(regVal);
- uint64_t realRegVal = thread->readNextPC();
- if(regVal != realRegVal)
- {
- DPRINTF(ExecRegDelta,
- "Register pc should be %#x but is %#x.\n",
- regVal, realRegVal);
- }
- res = read(fd, &regVal, sizeof(regVal));
- if(res < 0)
- panic("First read call failed! %s\n", strerror(errno));
- regVal = TheISA::gtoh(regVal);
- realRegVal = thread->readNextNPC();
+ uint64_t realRegVal = thread->readFloatRegBits(f, 64);
if(regVal != realRegVal)
{
- DPRINTF(ExecRegDelta,
- "Register npc should be %#x but is %#x.\n",
- regVal, realRegVal);
- }
- res = read(fd, &regVal, sizeof(regVal));
- if(res < 0)
- panic("First read call failed! %s\n", strerror(errno));
- regVal = TheISA::gtoh(regVal);
- realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
- if((regVal & 0xF) != (realRegVal & 0xF))
- {
- DPRINTF(ExecRegDelta,
- "Register ccr should be %#x but is %#x.\n",
- regVal, realRegVal);
+ DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal);
}
-#endif
+ }*/
+ uint64_t regVal;
+ int res = read(fd, &regVal, sizeof(regVal));
+ if(res < 0)
+ panic("First read call failed! %s\n", strerror(errno));
+ regVal = TheISA::gtoh(regVal);
+ uint64_t realRegVal = thread->readNextPC();
+ if(regVal != realRegVal)
+ {
+ DPRINTF(ExecRegDelta,
+ "Register pc should be %#x but is %#x.\n",
+ regVal, realRegVal);
}
+ res = read(fd, &regVal, sizeof(regVal));
+ if(res < 0)
+ panic("First read call failed! %s\n", strerror(errno));
+ regVal = TheISA::gtoh(regVal);
+ realRegVal = thread->readNextNPC();
+ if(regVal != realRegVal)
+ {
+ DPRINTF(ExecRegDelta,
+ "Register npc should be %#x but is %#x.\n",
+ regVal, realRegVal);
+ }
+ res = read(fd, &regVal, sizeof(regVal));
+ if(res < 0)
+ panic("First read call failed! %s\n", strerror(errno));
+ regVal = TheISA::gtoh(regVal);
+ realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
+ if((regVal & 0xF) != (realRegVal & 0xF))
+ {
+ DPRINTF(ExecRegDelta,
+ "Register ccr should be %#x but is %#x.\n",
+ regVal, realRegVal);
+ }
+#endif
}
/* namespace Trace */ }
diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh
index 48395792d..126077581 100644
--- a/src/cpu/nativetrace.hh
+++ b/src/cpu/nativetrace.hh
@@ -36,6 +36,7 @@
#include "cpu/static_inst.hh"
#include "sim/host.hh"
#include "sim/insttracer.hh"
+#include "arch/x86/intregs.hh"
class ThreadContext;
@@ -49,12 +50,6 @@ class NativeTraceRecord : public InstRecord
protected:
NativeTrace * parent;
- bool
- checkIntReg(const char * regName, int index, int size);
-
- bool
- checkPC(const char * regName, int size);
-
public:
NativeTraceRecord(NativeTrace * _parent,
Tick _when, ThreadContext *_thread,
@@ -73,8 +68,109 @@ class NativeTrace : public InstTracer
ListenSocket native_listener;
+ bool checkRcx;
+ bool checkR11;
+ uint64_t oldRcxVal, oldR11Val;
+ uint64_t oldRealRcxVal, oldRealR11Val;
+
+ struct ThreadState {
+ uint64_t rax;
+ uint64_t rcx;
+ uint64_t rdx;
+ uint64_t rbx;
+ uint64_t rsp;
+ uint64_t rbp;
+ uint64_t rsi;
+ uint64_t rdi;
+ uint64_t r8;
+ uint64_t r9;
+ uint64_t r10;
+ uint64_t r11;
+ uint64_t r12;
+ uint64_t r13;
+ uint64_t r14;
+ uint64_t r15;
+ uint64_t rip;
+
+ void update(int fd)
+ {
+ int bytesLeft = sizeof(ThreadState);
+ int bytesRead = 0;
+ do
+ {
+ int res = read(fd, ((char *)this) + bytesRead, bytesLeft);
+ if(res < 0)
+ panic("Read call failed! %s\n", strerror(errno));
+ bytesLeft -= res;
+ bytesRead += res;
+ } while(bytesLeft);
+ rax = TheISA::gtoh(rax);
+ rcx = TheISA::gtoh(rcx);
+ rdx = TheISA::gtoh(rdx);
+ rbx = TheISA::gtoh(rbx);
+ rsp = TheISA::gtoh(rsp);
+ rbp = TheISA::gtoh(rbp);
+ rsi = TheISA::gtoh(rsi);
+ rdi = TheISA::gtoh(rdi);
+ r8 = TheISA::gtoh(r8);
+ r9 = TheISA::gtoh(r9);
+ r10 = TheISA::gtoh(r10);
+ r11 = TheISA::gtoh(r11);
+ r12 = TheISA::gtoh(r12);
+ r13 = TheISA::gtoh(r13);
+ r14 = TheISA::gtoh(r14);
+ r15 = TheISA::gtoh(r15);
+ rip = TheISA::gtoh(rip);
+ }
+
+ void update(ThreadContext * tc)
+ {
+ rax = tc->readIntReg(X86ISA::INTREG_RAX);
+ rcx = tc->readIntReg(X86ISA::INTREG_RCX);
+ rdx = tc->readIntReg(X86ISA::INTREG_RDX);
+ rbx = tc->readIntReg(X86ISA::INTREG_RBX);
+ rsp = tc->readIntReg(X86ISA::INTREG_RSP);
+ rbp = tc->readIntReg(X86ISA::INTREG_RBP);
+ rsi = tc->readIntReg(X86ISA::INTREG_RSI);
+ rdi = tc->readIntReg(X86ISA::INTREG_RDI);
+ r8 = tc->readIntReg(X86ISA::INTREG_R8);
+ r9 = tc->readIntReg(X86ISA::INTREG_R9);
+ r10 = tc->readIntReg(X86ISA::INTREG_R10);
+ r11 = tc->readIntReg(X86ISA::INTREG_R11);
+ r12 = tc->readIntReg(X86ISA::INTREG_R12);
+ r13 = tc->readIntReg(X86ISA::INTREG_R13);
+ r14 = tc->readIntReg(X86ISA::INTREG_R14);
+ r15 = tc->readIntReg(X86ISA::INTREG_R15);
+ rip = tc->readNextPC();
+ }
+
+ };
+
+ ThreadState nState;
+ ThreadState mState;
+
+
public:
+ template<class T>
+ bool
+ checkReg(const char * regName, T &val, T &realVal)
+ {
+ if(val != realVal)
+ {
+ DPRINTFN("Register %s should be %#x but is %#x.\n",
+ regName, realVal, val);
+ return false;
+ }
+ return true;
+ }
+
+ bool
+ checkRcxReg(const char * regName, uint64_t &, uint64_t &);
+
+ bool
+ checkR11Reg(const char * regName, uint64_t &, uint64_t &);
+
NativeTrace(const std::string & name);
NativeTraceRecord *
@@ -88,6 +184,9 @@ class NativeTrace : public InstTracer
staticInst, pc, tc->misspeculating());
}
+ void
+ check(ThreadContext *, bool syscall);
+
friend class NativeTraceRecord;
};
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index b0a19c151..f32b61ee5 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -143,6 +143,9 @@ class StaticInstBase : public RefCounted
IsIprAccess, ///< Accesses IPRs
IsUnverifiable, ///< Can't be verified by a checker
+ IsSyscall, ///< Causes a system call to be emulated in syscall
+ /// emulation mode.
+
//Flags for microcode
IsMacroop, ///< Is a macroop containing microops
IsMicroop, ///< Is a microop
@@ -243,6 +246,7 @@ class StaticInstBase : public RefCounted
bool isQuiesce() const { return flags[IsQuiesce]; }
bool isIprAccess() const { return flags[IsIprAccess]; }
bool isUnverifiable() const { return flags[IsUnverifiable]; }
+ bool isSyscall() const { return flags[IsSyscall]; }
bool isMacroop() const { return flags[IsMacroop]; }
bool isMicroop() const { return flags[IsMicroop]; }
bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index ebeae1fe9..82b86ca84 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -32,6 +32,7 @@
#ifndef __INSTRECORD_HH__
#define __INSTRECORD_HH__
+#include "base/bigint.hh"
#include "base/trace.hh"
#include "cpu/inst_seq.hh" // for InstSeqNum
#include "cpu/static_inst.hh"
diff --git a/tests/long/70.twolf/test.py b/tests/long/70.twolf/test.py
index b2a2dc0b6..85b106eb4 100644
--- a/tests/long/70.twolf/test.py
+++ b/tests/long/70.twolf/test.py
@@ -32,7 +32,7 @@ import os
workload = twolf(isa, opsys, 'smred')
root.system.cpu.workload = workload.makeLiveProcess()
-cwd = root.system.cpu.workload.cwd
+cwd = root.system.cpu.workload[0].cwd
#Remove two files who's presence or absence affects execution
sav_file = os.path.join(cwd, workload.input_set + '.sav')
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 08:52:20 +0000