diff options
| -rw-r--r-- | cpu/simple/atomic.cc | 12 | ||||
| -rw-r--r-- | cpu/simple/timing.cc | 13 | ||||
| -rw-r--r-- | dev/io_device.hh | 2 | ||||
| -rw-r--r-- | mem/physical.cc | 5 | ||||
| -rw-r--r-- | mem/request.hh | 2 |
5 files changed, 22 insertions, 12 deletions
diff --git a/cpu/simple/atomic.cc b/cpu/simple/atomic.cc index c09f16ada..e9422b9c0 100644 --- a/cpu/simple/atomic.cc +++ b/cpu/simple/atomic.cc @@ -349,20 +349,16 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) dcache_access = true; assert(data_write_pkt->result == Success); - } - if (res && (fault == NoFault)) - *res = data_write_pkt->result; + if (res && data_write_req->getFlags() & LOCKED) { + *res = data_write_req->getScResult(); + } + } // This will need a new way to tell if it's hooked up to a cache or not. if (data_write_req->getFlags() & UNCACHEABLE) recordEvent("Uncached Write"); - // @todo this is a hack and only works on uniprocessor systems - // some one else can implement LL/SC. - if (data_write_req->getFlags() & LOCKED) - *res = 1; - // If the write needs to have a fault on the access, consider calling // changeStatus() and changing it to "bad addr write" or something. return fault; diff --git a/cpu/simple/timing.cc b/cpu/simple/timing.cc index 80d3380a5..70b88c4b1 100644 --- a/cpu/simple/timing.cc +++ b/cpu/simple/timing.cc @@ -75,6 +75,9 @@ TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) void TimingSimpleCPU::CpuPort::recvStatusChange(Status status) { + if (status == RangeChange) + return; + panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); } @@ -342,6 +345,8 @@ TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) void TimingSimpleCPU::fetch() { + checkForInterrupts(); + Request *ifetch_req = new Request(true); ifetch_req->setSize(sizeof(MachInst)); @@ -380,7 +385,12 @@ TimingSimpleCPU::completeInst(Fault fault) advancePC(fault); - fetch(); + if (_status == Running) { + // kick off fetch of next instruction... callback from icache + // response will cause that instruction to be executed, + // keeping the CPU running. + fetch(); + } } @@ -397,6 +407,7 @@ TimingSimpleCPU::completeIfetch() Fault fault = curStaticInst->initiateAcc(this, traceData); assert(fault == NoFault); assert(_status == DcacheWaitResponse); + // instruction will complete in dcache response callback } else { // non-memory instruction: execute completely now Fault fault = curStaticInst->execute(this, traceData); diff --git a/dev/io_device.hh b/dev/io_device.hh index 8b23422dd..6efa9ef63 100644 --- a/dev/io_device.hh +++ b/dev/io_device.hh @@ -90,7 +90,7 @@ class PioPort : public Port Packet *packet; SendEvent(PioPort *p, Packet *pkt, Tick t) - : Event(&mainEventQueue), packet(pkt) + : Event(&mainEventQueue), port(p), packet(pkt) { schedule(curTick + t); } virtual void process(); diff --git a/mem/physical.cc b/mem/physical.cc index 8de9c3203..bc2500678 100644 --- a/mem/physical.cc +++ b/mem/physical.cc @@ -155,6 +155,11 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt) case Write: memcpy(pmem_addr + pkt->addr - base_addr, pkt->getPtr<uint8_t>(), pkt->size); + // temporary hack: will need to add real LL/SC implementation + // for cacheless systems later. + if (pkt->req->getFlags() & LOCKED) { + pkt->req->setScResult(1); + } break; default: panic("unimplemented"); diff --git a/mem/request.hh b/mem/request.hh index 903e7503c..2db7b7779 100644 --- a/mem/request.hh +++ b/mem/request.hh @@ -97,8 +97,6 @@ class Request /** Flag structure for the request. */ uint32_t flags; - /** Wether or not flags is valid (has been written yet). */ - bool validFlags; //Accsesors for non-cpu request fields public: |