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-rw-r--r--SConstruct55
-rw-r--r--src/SConscript1
-rwxr-xr-xsrc/arch/isa_parser.py25
-rw-r--r--src/arch/mips/isa/formats/fp.isa6
-rw-r--r--src/base/compression/base.hh71
-rw-r--r--src/base/compression/lzss_compression.hh4
-rw-r--r--src/base/compression/null_compression.hh28
-rw-r--r--src/cpu/base_dyn_inst.hh12
-rw-r--r--src/cpu/checker/cpu.hh25
-rw-r--r--src/cpu/exec_context.hh25
-rw-r--r--src/cpu/o3/alpha/dyn_inst.hh35
-rw-r--r--src/cpu/o3/commit_impl.hh6
-rw-r--r--src/cpu/o3/fetch_impl.hh60
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh3
-rwxr-xr-xsrc/cpu/o3/mips/dyn_inst.hh35
-rw-r--r--src/cpu/ozone/cpu.hh99
-rw-r--r--src/cpu/ozone/dyn_inst.hh25
-rw-r--r--src/cpu/ozone/inorder_back_end.hh74
-rw-r--r--src/cpu/simple/base.hh25
-rw-r--r--src/cpu/simple_thread.hh69
-rw-r--r--src/mem/cache/cache.cc66
-rw-r--r--src/mem/cache/cache.hh15
-rw-r--r--src/mem/cache/cache_builder.cc148
-rw-r--r--src/mem/cache/cache_impl.hh70
-rw-r--r--src/mem/cache/miss/blocking_buffer.cc41
-rw-r--r--src/mem/cache/miss/blocking_buffer.hh61
-rw-r--r--src/mem/cache/miss/miss_buffer.cc62
-rw-r--r--src/mem/cache/miss/miss_buffer.hh223
-rw-r--r--src/mem/cache/miss/miss_queue.cc36
-rw-r--r--src/mem/cache/miss/miss_queue.hh30
-rw-r--r--src/mem/cache/prefetch/ghb_prefetcher.cc8
-rw-r--r--src/mem/cache/prefetch/ghb_prefetcher.hh10
-rw-r--r--src/mem/cache/prefetch/stride_prefetcher.cc8
-rw-r--r--src/mem/cache/prefetch/stride_prefetcher.hh10
-rw-r--r--src/mem/cache/prefetch/tagged_prefetcher.hh8
-rw-r--r--src/mem/cache/prefetch/tagged_prefetcher_impl.hh10
-rw-r--r--src/python/m5/objects/Repl.py6
-rw-r--r--src/python/m5/params.py11
-rw-r--r--tests/long/20.parser/ref/alpha/linux/NOTE6
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini417
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/config.out403
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt1974
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/stderr3
-rw-r--r--tests/long/30.eon/ref/alpha/linux/o3-timing/stdout13
-rwxr-xr-xutil/regress19
45 files changed, 755 insertions, 3586 deletions
diff --git a/SConstruct b/SConstruct
index 50ca2d6e4..7e8c6c2f0 100644
--- a/SConstruct
+++ b/SConstruct
@@ -66,6 +66,7 @@
# Python library imports
import sys
import os
+from os.path import join as joinpath
# Check for recent-enough Python and SCons versions. If your system's
# default installation of Python is not recent enough, you can use a
@@ -89,11 +90,11 @@ except:
# The absolute path to the current directory (where this file lives).
ROOT = Dir('.').abspath
-# Paths to the M5 and external source trees.
-SRCDIR = os.path.join(ROOT, 'src')
+# Path to the M5 source tree.
+SRCDIR = joinpath(ROOT, 'src')
# tell python where to find m5 python code
-sys.path.append(os.path.join(ROOT, 'src/python'))
+sys.path.append(joinpath(ROOT, 'src/python'))
###################################################
#
@@ -105,13 +106,6 @@ sys.path.append(os.path.join(ROOT, 'src/python'))
# Find default configuration & binary.
Default(os.environ.get('M5_DEFAULT_BINARY', 'build/ALPHA_SE/m5.debug'))
-# Ask SCons which directory it was invoked from.
-launch_dir = GetLaunchDir()
-
-# Make targets relative to invocation directory
-abs_targets = map(lambda x: os.path.normpath(os.path.join(launch_dir, str(x))),
- BUILD_TARGETS)
-
# helper function: find last occurrence of element in list
def rfind(l, elt, offs = -1):
for i in range(len(l)+offs, 0, -1):
@@ -141,6 +135,19 @@ def compare_versions(v1, v2):
# recognize that ALPHA_SE specifies the configuration because it
# follow 'build' in the bulid path.
+# Generate absolute paths to targets so we can see where the build dir is
+if COMMAND_LINE_TARGETS:
+ # Ask SCons which directory it was invoked from
+ launch_dir = GetLaunchDir()
+ # Make targets relative to invocation directory
+ abs_targets = map(lambda x: os.path.normpath(joinpath(launch_dir, str(x))),
+ COMMAND_LINE_TARGETS)
+else:
+ # Default targets are relative to root of tree
+ abs_targets = map(lambda x: os.path.normpath(joinpath(ROOT, str(x))),
+ DEFAULT_TARGETS)
+
+
# Generate a list of the unique build roots and configs that the
# collected targets reference.
build_paths = []
@@ -152,7 +159,7 @@ for t in abs_targets:
except:
print "Error: no non-leaf 'build' dir found on target path", t
Exit(1)
- this_build_root = os.path.join('/',*path_dirs[:build_top+1])
+ this_build_root = joinpath('/',*path_dirs[:build_top+1])
if not build_root:
build_root = this_build_root
else:
@@ -160,7 +167,7 @@ for t in abs_targets:
print "Error: build targets not under same build root\n"\
" %s\n %s" % (build_root, this_build_root)
Exit(1)
- build_path = os.path.join('/',*path_dirs[:build_top+2])
+ build_path = joinpath('/',*path_dirs[:build_top+2])
if build_path not in build_paths:
build_paths.append(build_path)
@@ -183,7 +190,7 @@ if ARGUMENTS.get('CC', None):
if ARGUMENTS.get('CXX', None):
env['CXX'] = ARGUMENTS.get('CXX')
-env.SConsignFile(os.path.join(build_root,"sconsign"))
+env.SConsignFile(joinpath(build_root,"sconsign"))
# Default duplicate option is to use hard links, but this messes up
# when you use emacs to edit a file in the target dir, as emacs moves
@@ -243,8 +250,8 @@ env.Append(SCANNERS = swig_scanner)
# Platform-specific configuration. Note again that we assume that all
# builds under a given build root run on the same host platform.
conf = Configure(env,
- conf_dir = os.path.join(build_root, '.scons_config'),
- log_file = os.path.join(build_root, 'scons_config.log'))
+ conf_dir = joinpath(build_root, '.scons_config'),
+ log_file = joinpath(build_root, 'scons_config.log'))
# Find Python include and library directories for embedding the
# interpreter. For consistency, we will use the same Python
@@ -257,7 +264,7 @@ conf = Configure(env,
py_version_name = 'python' + sys.version[:3]
# include path, e.g. /usr/local/include/python2.4
-py_header_path = os.path.join(sys.exec_prefix, 'include', py_version_name)
+py_header_path = joinpath(sys.exec_prefix, 'include', py_version_name)
env.Append(CPPPATH = py_header_path)
# verify that it works
if not conf.CheckHeader('Python.h', '<>'):
@@ -267,7 +274,7 @@ if not conf.CheckHeader('Python.h', '<>'):
# add library path too if it's not in the default place
py_lib_path = None
if sys.exec_prefix != '/usr':
- py_lib_path = os.path.join(sys.exec_prefix, 'lib')
+ py_lib_path = joinpath(sys.exec_prefix, 'lib')
elif sys.platform == 'cygwin':
# cygwin puts the .dll in /bin for some reason
py_lib_path = '/bin'
@@ -330,7 +337,7 @@ env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips']
env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU',
'O3CPU', 'OzoneCPU']
-if os.path.isdir(os.path.join(SRCDIR, 'src/encumbered/cpu/full')):
+if os.path.isdir(joinpath(SRCDIR, 'encumbered/cpu/full')):
env['ALL_CPU_LIST'] += ['FullCPU']
# Sticky options get saved in the options file so they persist from
@@ -417,7 +424,7 @@ def config_emitter(target, source, env):
# extract option name from Builder arg
option = str(target[0])
# True target is config header file
- target = os.path.join('config', option.lower() + '.hh')
+ target = joinpath('config', option.lower() + '.hh')
val = env[option]
if isinstance(val, bool):
# Force value to 0/1
@@ -466,7 +473,7 @@ Usage: scons [scons options] [build options] [target(s)]
# libelf build is shared across all configs in the build root.
env.SConscript('ext/libelf/SConscript',
- build_dir = os.path.join(build_root, 'libelf'),
+ build_dir = joinpath(build_root, 'libelf'),
exports = 'env')
###################################################
@@ -531,7 +538,7 @@ for build_path in build_paths:
# Options for $BUILD_ROOT/$BUILD_DIR are stored in
# $BUILD_ROOT/options/$BUILD_DIR so you can nuke
# $BUILD_ROOT/$BUILD_DIR without losing your options settings.
- current_opts_file = os.path.join(build_root, 'options', build_dir)
+ current_opts_file = joinpath(build_root, 'options', build_dir)
if os.path.isfile(current_opts_file):
sticky_opts.files.append(current_opts_file)
print "Using saved options file %s" % current_opts_file
@@ -546,8 +553,8 @@ for build_path in build_paths:
# Get default build options from source tree. Options are
# normally determined by name of $BUILD_DIR, but can be
# overriden by 'default=' arg on command line.
- default_opts_file = os.path.join('build_opts',
- ARGUMENTS.get('default', build_dir))
+ default_opts_file = joinpath('build_opts',
+ ARGUMENTS.get('default', build_dir))
if os.path.isfile(default_opts_file):
sticky_opts.files.append(default_opts_file)
print "Options file %s not found,\n using defaults in %s" \
@@ -611,7 +618,7 @@ for build_path in build_paths:
# Set up the regression tests for each build.
for e in envList:
SConscript('tests/SConscript',
- build_dir = os.path.join(build_path, 'tests', e.Label),
+ build_dir = joinpath(build_path, 'tests', e.Label),
exports = { 'env' : e }, duplicate = False)
Help(help_text)
diff --git a/src/SConscript b/src/SConscript
index 429e1bee1..f54e1de0d 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -108,6 +108,7 @@ base_sources = Split('''
mem/cache/coherence/coherence_protocol.cc
mem/cache/coherence/uni_coherence.cc
mem/cache/miss/blocking_buffer.cc
+ mem/cache/miss/miss_buffer.cc
mem/cache/miss/miss_queue.cc
mem/cache/miss/mshr.cc
mem/cache/miss/mshr_queue.cc
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 6504c7b32..a96622d4a 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1180,15 +1180,16 @@ class IntRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read integer register as FP')
if (self.size == self.dflt_size):
- return '%s = xc->readIntReg(this, %d);\n' % \
+ return '%s = xc->readIntRegOperand(this, %d);\n' % \
(self.base_name, self.src_reg_idx)
elif (self.size > self.dflt_size):
- int_reg_val = 'xc->readIntReg(this, %d)' % (self.src_reg_idx)
+ int_reg_val = 'xc->readIntRegOperand(this, %d)' % \
+ (self.src_reg_idx)
if (self.is_signed):
int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val)
return '%s = %s;\n' % (self.base_name, int_reg_val)
else:
- return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \
+ return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \
(self.base_name, self.src_reg_idx, self.size-1)
def makeWrite(self):
@@ -1201,7 +1202,7 @@ class IntRegOperand(Operand):
wb = '''
{
%s final_val = %s;
- xc->setIntReg(this, %d, final_val);\n
+ xc->setIntRegOperand(this, %d, final_val);\n
if (traceData) { traceData->setData(final_val); }
}''' % (self.dflt_ctype, final_val, self.dest_reg_idx)
return wb
@@ -1227,13 +1228,13 @@ class FloatRegOperand(Operand):
bit_select = 0
width = 0;
if (self.ctype == 'float'):
- func = 'readFloatReg'
+ func = 'readFloatRegOperand'
width = 32;
elif (self.ctype == 'double'):
- func = 'readFloatReg'
+ func = 'readFloatRegOperand'
width = 64;
else:
- func = 'readFloatRegBits'
+ func = 'readFloatRegOperandBits'
if (self.ctype == 'uint32_t'):
width = 32;
elif (self.ctype == 'uint64_t'):
@@ -1259,18 +1260,18 @@ class FloatRegOperand(Operand):
width = 0
if (self.ctype == 'float'):
width = 32
- func = 'setFloatReg'
+ func = 'setFloatRegOperand'
elif (self.ctype == 'double'):
width = 64
- func = 'setFloatReg'
+ func = 'setFloatRegOperand'
elif (self.ctype == 'uint32_t'):
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
width = 32
elif (self.ctype == 'uint64_t'):
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
width = 64
else:
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
final_ctype = 'uint%d_t' % self.dflt_size
if (self.size != self.dflt_size and self.is_signed):
final_val = 'sext<%d>(%s)' % (self.size, self.base_name)
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index cdb892b3f..153f3f949 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -99,7 +99,7 @@ output exec {{
int size = sizeof(src_op) * 8;
for (int i = 0; i < inst->numSrcRegs(); i++) {
- uint64_t src_bits = xc->readFloatRegBits(inst, 0, size);
+ uint64_t src_bits = xc->readFloatRegOperandBits(inst, 0, size);
if (isNan(&src_bits, size) ) {
if (isSnan(&src_bits, size)) {
@@ -113,7 +113,7 @@ output exec {{
mips_nan = src_bits;
}
- xc->setFloatRegBits(inst, 0, mips_nan, size);
+ xc->setFloatRegOperandBits(inst, 0, mips_nan, size);
if (traceData) { traceData->setData(mips_nan); }
return true;
}
@@ -139,7 +139,7 @@ output exec {{
}
//Set value to QNAN
- cpu->setFloatRegBits(inst, 0, mips_nan, size);
+ cpu->setFloatRegOperandBits(inst, 0, mips_nan, size);
//Read FCSR from FloatRegFile
uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
diff --git a/src/base/compression/base.hh b/src/base/compression/base.hh
new file mode 100644
index 000000000..8d1f8d6b5
--- /dev/null
+++ b/src/base/compression/base.hh
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Erik Hallnor
+ * Nathan Binkert
+ */
+
+#ifndef __BASE_COMPRESSION_BASE_HH__
+#define __BASE_COMPRESSION_BASE_HH__
+
+/**
+ * @file
+ * This file defines a base (abstract virtual) compression algorithm object.
+ */
+
+#include <inttypes.h>
+
+/**
+ * Abstract virtual compression algorithm object.
+ */
+class CompressionAlgorithm
+{
+ public:
+ virtual ~CompressionAlgorithm() {}
+
+ /**
+ * Uncompress the data, causes a fatal since no data should be compressed.
+ * @param dest The output buffer.
+ * @param src The compressed data.
+ * @param size The number of bytes in src.
+ *
+ * @retval The size of the uncompressed data.
+ */
+ virtual int uncompress(uint8_t * dest, uint8_t *src, int size) = 0;
+
+ /**
+ * Compress the data, just returns the source data.
+ * @param dest The output buffer.
+ * @param src The data to be compressed.
+ * @param size The number of bytes in src.
+ *
+ * @retval The size of the compressed data.
+ */
+ virtual int compress(uint8_t *dest, uint8_t *src, int size) = 0;
+};
+
+#endif //__BASE_COMPRESSION_BASE_HH__
diff --git a/src/base/compression/lzss_compression.hh b/src/base/compression/lzss_compression.hh
index 35e4dcb3f..a23d07ffd 100644
--- a/src/base/compression/lzss_compression.hh
+++ b/src/base/compression/lzss_compression.hh
@@ -35,12 +35,12 @@
* LZSSCompression declarations.
*/
-#include "sim/host.hh" // for uint8_t
+#include "base/compression/base.hh"
/**
* Simple LZSS compression scheme.
*/
-class LZSSCompression
+class LZSSCompression : public CompressionAlgorithm
{
/**
* Finds the longest substring for the given offset.
diff --git a/src/base/compression/null_compression.hh b/src/base/compression/null_compression.hh
index 5a582d828..ff110807a 100644
--- a/src/base/compression/null_compression.hh
+++ b/src/base/compression/null_compression.hh
@@ -38,41 +38,23 @@
*/
#include "base/misc.hh" // for fatal()
-#include "sim/host.hh"
+#include "base/compression/base.hh"
/**
* A dummy compression class to use when no data compression is desired.
*/
-class NullCompression
+class NullCompression : public CompressionAlgorithm
{
public:
- /**
- * Uncompress the data, causes a fatal since no data should be compressed.
- * @param dest The output buffer.
- * @param src The compressed data.
- * @param size The number of bytes in src.
- *
- * @retval The size of the uncompressed data.
- */
- static int uncompress(uint8_t * dest, uint8_t *src, int size)
+ int uncompress(uint8_t * dest, uint8_t *src, int size)
{
fatal("Can't uncompress data");
}
- /**
- * Compress the data, just returns the source data.
- * @param dest The output buffer.
- * @param src The data to be compressed.
- * @param size The number of bytes in src.
- *
- * @retval The size of the compressed data.
- */
-
- static int compress(uint8_t *dest, uint8_t *src, int size)
+ int compress(uint8_t *dest, uint8_t *src, int size)
{
- memcpy(dest,src,size);
- return size;
+ fatal("Can't compress data");
}
};
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 0f7976631..17e121dbf 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -501,14 +501,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
double readDoubleResult() { return instResult.dbl; }
/** Records an integer register being set to a value. */
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
if (recordResult)
instResult.integer = val;
}
/** Records an fp register being set to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
if (recordResult) {
if (width == 32)
@@ -521,21 +522,22 @@ class BaseDynInst : public FastAlloc, public RefCounted
}
/** Records an fp register being set to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
if (recordResult)
instResult.dbl = (double)val;
}
/** Records an fp register being set to an integer value. */
- void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
+ int width)
{
if (recordResult)
instResult.integer = val;
}
/** Records an fp register being set to an integer value. */
- void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
{
if (recordResult)
instResult.integer = val;
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 9be54529f..3e08193ee 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -216,42 +216,44 @@ class CheckerCPU : public BaseCPU
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx, width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx, width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx);
}
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
thread->setIntReg(si->destRegIdx(idx), val);
result.integer = val;
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val, width);
@@ -265,22 +267,23 @@ class CheckerCPU : public BaseCPU
};
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val);
result.dbl = (double)val;
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
- int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val, width);
result.integer = val;
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val);
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 13f70fa79..edccd747f 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -48,39 +48,42 @@ class ExecContext {
// to do).
/** Reads an integer register. */
- uint64_t readIntReg(const StaticInst *si, int idx);
+ uint64_t readIntRegOperand(const StaticInst *si, int idx);
/** Reads a floating point register of a specific width. */
- FloatReg readFloatReg(const StaticInst *si, int idx, int width);
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
/** Reads a floating point register of single register width. */
- FloatReg readFloatReg(const StaticInst *si, int idx);
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx);
/** Reads a floating point register of a specific width in its
* binary format, instead of by value. */
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width);
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width);
/** Reads a floating point register in its binary format, instead
* of by value. */
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx);
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
/** Sets an integer register to a value. */
- void setIntReg(const StaticInst *si, int idx, uint64_t val);
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
/** Sets a floating point register of a specific width to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width);
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width);
/** Sets a floating point register of single width to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val);
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
/** Sets the bits of a floating point register of a specific width
* to a binary value. */
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width);
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width);
/** Sets the bits of a floating point register of single width
* to a binary value. */
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val);
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val);
/** Reads the PC. */
uint64_t readPC();
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 4e2ce63df..c340a806a 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -147,27 +147,28 @@ class AlphaDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
}
@@ -175,35 +176,37 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setIntReg(si, idx, val);
+ BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatReg(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
public:
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 1527efe1a..3178410a8 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1180,16 +1180,16 @@ DefaultCommit<Impl>::getInsts()
rename_idx < fromRename->size;
rename_idx++) {
DynInstPtr inst = fromRename->insts[rename_idx];
- int tid = inst->threadNumber;
if (!inst->isSquashed()) {
DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
- "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+ "skidBuffer.\n", inst->readPC(), inst->seqNum,
+ inst->threadNumber);
skidBuffer.push(inst);
} else {
DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
"squashed, skipping.\n",
- inst->readPC(), inst->seqNum, tid);
+ inst->readPC(), inst->seqNum, inst->threadNumber);
}
}
}
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index f9e90614a..6cff52429 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -151,36 +151,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
" RoundRobin,LSQcount,IQcount}\n");
}
- // Size of cache block.
- cacheBlkSize = 64;
-
- // Create mask to get rid of offset bits.
- cacheBlkMask = (cacheBlkSize - 1);
-
- for (int tid=0; tid < numThreads; tid++) {
-
- fetchStatus[tid] = Running;
-
- priorityList.push_back(tid);
-
- memReq[tid] = NULL;
-
- // Create space to store a cache line.
- cacheData[tid] = new uint8_t[cacheBlkSize];
- cacheDataPC[tid] = 0;
- cacheDataValid[tid] = false;
-
- delaySlotInfo[tid].branchSeqNum = -1;
- delaySlotInfo[tid].numInsts = 0;
- delaySlotInfo[tid].targetAddr = 0;
- delaySlotInfo[tid].targetReady = false;
-
- stalls[tid].decode = false;
- stalls[tid].rename = false;
- stalls[tid].iew = false;
- stalls[tid].commit = false;
- }
-
// Get the size of an instruction.
instSize = sizeof(TheISA::MachInst);
}
@@ -353,6 +323,36 @@ DefaultFetch<Impl>::initStage()
nextNPC[tid] = cpu->readNextNPC(tid);
#endif
}
+
+ // Size of cache block.
+ cacheBlkSize = icachePort->peerBlockSize();
+
+ // Create mask to get rid of offset bits.
+ cacheBlkMask = (cacheBlkSize - 1);
+
+ for (int tid=0; tid < numThreads; tid++) {
+
+ fetchStatus[tid] = Running;
+
+ priorityList.push_back(tid);
+
+ memReq[tid] = NULL;
+
+ // Create space to store a cache line.
+ cacheData[tid] = new uint8_t[cacheBlkSize];
+ cacheDataPC[tid] = 0;
+ cacheDataValid[tid] = false;
+
+ delaySlotInfo[tid].branchSeqNum = -1;
+ delaySlotInfo[tid].numInsts = 0;
+ delaySlotInfo[tid].targetAddr = 0;
+ delaySlotInfo[tid].targetReady = false;
+
+ stalls[tid].decode = false;
+ stalls[tid].rename = false;
+ stalls[tid].iew = false;
+ stalls[tid].commit = false;
+ }
}
template<class Impl>
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 379724166..7ce3dc9cb 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -418,7 +418,8 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
// realizes there is activity.
// Mark it as executed unless it is an uncached load that
// needs to hit the head of commit.
- if (!(inst->req->isUncacheable()) || inst->isAtCommit()) {
+ if (!(inst->req && inst->req->isUncacheable()) ||
+ inst->isAtCommit()) {
inst->setExecuted();
}
iewStage->instToCommit(inst);
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index bf82168ce..009a08012 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -136,27 +136,28 @@ class MipsDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx], width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
}
@@ -164,35 +165,37 @@ class MipsDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setIntReg(si, idx, val);
+ BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatReg(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
this->cpu->setFloatRegBits(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
public:
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index c1373944d..0da446c9c 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -448,30 +448,6 @@ class OzoneCPU : public BaseCPU
}
#endif
- /** Old CPU read from memory function. No longer used. */
- template <class T>
- Fault read(Request *req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
- if (req->isLocked()) {
- lockAddrList.insert(req->paddr);
- lockFlag = true;
- }
-#endif
- Fault error;
-
- error = this->mem->read(req, data);
- data = gtoh(data);
- return error;
- }
-
-
/** CPU read function, forwards read to LSQ. */
template <class T>
Fault read(Request *req, T &data, int load_idx)
@@ -479,81 +455,6 @@ class OzoneCPU : public BaseCPU
return backEnd->read(req, data, load_idx);
}
- /** Old CPU write to memory function. No longer used. */
- template <class T>
- Fault write(Request *req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < this->system->threadContexts.size(); i++){
- xc = this->system->threadContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
-
- if (req->isLocked()) {
- if (req->isUncacheable()) {
- req->result = 2;
- } else {
- if (this->lockFlag) {
- if (lockAddrList.find(req->paddr) !=
- lockAddrList.end()) {
- req->result = 1;
- } else {
- req->result = 0;
- return NoFault;
- }
- } else {
- req->result = 0;
- return NoFault;
- }
- }
- }
-#endif
-
- return this->mem->write(req, (T)htog(data));
- }
-
/** CPU write function, forwards write to LSQ. */
template <class T>
Fault write(Request *req, T &data, int store_idx)
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 9445a5309..88f96b14b 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -146,12 +146,12 @@ class OzoneDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return srcInsts[idx]->readIntResult();
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
switch(width) {
case 32:
@@ -164,17 +164,18 @@ class OzoneDynInst : public BaseDynInst<Impl>
}
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return srcInsts[idx]->readFloatResult();
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return srcInsts[idx]->readIntResult();
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return srcInsts[idx]->readIntResult();
}
@@ -182,28 +183,30 @@ class OzoneDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
BaseDynInst<Impl>::setIntReg(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
BaseDynInst<Impl>::setFloatReg(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
}
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index b2522bdc8..4fd8e02f8 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -236,25 +236,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
*/
return fault;
}
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
-
- Fault error;
- error = thread->mem->read(req, data);
- data = LittleEndianGuest::gtoh(data);
- return error;
-}
-#endif
template <class Impl>
template <class T>
@@ -296,61 +277,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
*/
return fault;
}
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < cpu->system->execContexts.size(); i++){
- xc = cpu->system->execContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
- return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
-}
-#endif
template <class Impl>
template <class T>
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index efb884325..c39bfa9cd 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -213,60 +213,63 @@ class BaseSimpleCPU : public BaseCPU
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx, width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx, width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx);
}
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
thread->setIntReg(si->destRegIdx(idx), val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val, width);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index acbefeb67..f2f79c070 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -234,75 +234,6 @@ class SimpleThread : public ThreadState
/// Set the status to Halted.
void halt();
-/*
- template <class T>
- Fault read(RequestPtr &req, T &data)
- {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
-
- Fault error;
- error = mem->prot_read(req->paddr, data, req->size);
- data = LittleEndianGuest::gtoh(data);
- return error;
- }
-
- template <class T>
- Fault write(RequestPtr &req, T &data)
- {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < system->execContexts.size(); i++){
- xc = system->execContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
- return mem->prot_write(req->paddr, (T)htog(data), req->size);
- }
-*/
virtual bool misspeculating();
Fault instRead(RequestPtr &req)
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index db66c096e..29ca09060 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -37,7 +37,6 @@
*/
#include "mem/config/cache.hh"
-#include "mem/config/compression.hh"
#include "mem/cache/tags/cache_tags.hh"
@@ -61,11 +60,6 @@
#include "mem/cache/tags/split_lifo.hh"
#endif
-#include "base/compression/null_compression.hh"
-#if defined(USE_LZSS_COMPRESSION)
-#include "base/compression/lzss_compression.hh"
-#endif
-
#include "mem/cache/miss/miss_queue.hh"
#include "mem/cache/miss/blocking_buffer.hh"
@@ -79,68 +73,28 @@
#if defined(USE_CACHE_FALRU)
-template class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<FALRU,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<FALRU,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<FALRU>, SimpleCoherence>;
+template class Cache<CacheTags<FALRU>, UniCoherence>;
#endif
#if defined(USE_CACHE_IIC)
-template class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<IIC,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<IIC,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<IIC,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<IIC>, SimpleCoherence>;
+template class Cache<CacheTags<IIC>, UniCoherence>;
#endif
#if defined(USE_CACHE_LRU)
-template class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<LRU,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<LRU,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<LRU,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<LRU>, SimpleCoherence>;
+template class Cache<CacheTags<LRU>, UniCoherence>;
#endif
#if defined(USE_CACHE_SPLIT)
-template class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<Split,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<Split,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<Split,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<Split,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<Split,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<Split>, SimpleCoherence>;
+template class Cache<CacheTags<Split>, UniCoherence>;
#endif
#if defined(USE_CACHE_SPLIT_LIFO)
-template class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, UniCoherence>;
-#if defined(USE_LZSS_COMPRESSION)
-template class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, SimpleCoherence>;
-template class Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, UniCoherence>;
-template class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, SimpleCoherence>;
-template class Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, UniCoherence>;
-#endif
+template class Cache<CacheTags<SplitLIFO>, SimpleCoherence>;
+template class Cache<CacheTags<SplitLIFO>, UniCoherence>;
#endif
#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 1f3b087bb..29502042c 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -42,6 +42,7 @@
#include "cpu/smt.hh" // SMT_MAX_THREADS
#include "mem/cache/base_cache.hh"
+#include "mem/cache/miss/miss_buffer.hh"
#include "mem/cache/prefetch/prefetcher.hh"
//Forward decleration
@@ -55,7 +56,7 @@ class MSHR;
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
-template <class TagStore, class Buffering, class Coherence>
+template <class TagStore, class Coherence>
class Cache : public BaseCache
{
public:
@@ -68,12 +69,12 @@ class Cache : public BaseCache
/** Tag and data Storage */
TagStore *tags;
/** Miss and Writeback handler */
- Buffering *missQueue;
+ MissBuffer *missQueue;
/** Coherence protocol. */
Coherence *coherence;
/** Prefetcher */
- Prefetcher<TagStore, Buffering> *prefetcher;
+ Prefetcher<TagStore> *prefetcher;
/**
* The clock ratio of the outgoing bus.
@@ -105,16 +106,16 @@ class Cache : public BaseCache
{
public:
TagStore *tags;
- Buffering *missQueue;
+ MissBuffer *missQueue;
Coherence *coherence;
BaseCache::Params baseParams;
- Prefetcher<TagStore, Buffering> *prefetcher;
+ Prefetcher<TagStore> *prefetcher;
bool prefetchAccess;
int hitLatency;
- Params(TagStore *_tags, Buffering *mq, Coherence *coh,
+ Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
BaseCache::Params params,
- Prefetcher<TagStore, Buffering> *_prefetcher,
+ Prefetcher<TagStore> *_prefetcher,
bool prefetch_access, int hit_latency)
: tags(_tags), missQueue(mq), coherence(coh),
baseParams(params),
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 03646ec2a..4b1b19718 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -37,7 +37,6 @@
// Must be included first to determine which caches we want
#include "mem/config/cache.hh"
-#include "mem/config/compression.hh"
#include "mem/config/prefetch.hh"
#include "mem/cache/base_cache.hh"
@@ -69,9 +68,7 @@
// Compression Templates
#include "base/compression/null_compression.hh"
-#if defined(USE_LZSS_COMPRESSION)
#include "base/compression/lzss_compression.hh"
-#endif
// CacheTags Templates
#include "mem/cache/tags/cache_tags.hh"
@@ -211,156 +208,127 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
END_INIT_SIM_OBJECT_PARAMS(BaseCache)
-#define BUILD_CACHE(t, comp, b, c) do { \
- Prefetcher<CacheTags<t, comp>, b> *pf; \
+#define BUILD_CACHE(t, c) do { \
+ Prefetcher<CacheTags<t> > *pf; \
if (pf_policy == "tagged") { \
- BUILD_TAGGED_PREFETCHER(t, comp, b); \
+ BUILD_TAGGED_PREFETCHER(t); \
} \
else if (pf_policy == "stride") { \
- BUILD_STRIDED_PREFETCHER(t, comp, b); \
+ BUILD_STRIDED_PREFETCHER(t); \
} \
else if (pf_policy == "ghb") { \
- BUILD_GHB_PREFETCHER(t, comp, b); \
+ BUILD_GHB_PREFETCHER(t); \
} \
else { \
- BUILD_NULL_PREFETCHER(t, comp, b); \
+ BUILD_NULL_PREFETCHER(t); \
} \
- Cache<CacheTags<t, comp>, b, c>::Params params(tagStore, mq, coh, \
+ Cache<CacheTags<t>, c>::Params params(tagStore, mq, coh, \
base_params, \
- /*in_bus, out_bus,*/ pf, \
+ pf, \
prefetch_access, hit_latency); \
- Cache<CacheTags<t, comp>, b, c> *retval = \
- new Cache<CacheTags<t, comp>, b, c>(getInstanceName(), /*hier,*/ \
- params); \
-/* if (in_bus == NULL) { \
- retval->setSlaveInterface(new MemoryInterface<Cache<CacheTags<t, comp>, b, c> >(getInstanceName(), hier, retval, mem_trace)); \
- } else { \
- retval->setSlaveInterface(new SlaveInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, in_bus, mem_trace)); \
- } \
- retval->setMasterInterface(new MasterInterface<Cache<CacheTags<t, comp>, b, c>, Bus>(getInstanceName(), hier, retval, out_bus)); \
- out_bus->rangeChange(); \
- return retval; \
-*/return retval; \
+ Cache<CacheTags<t>, c> *retval = \
+ new Cache<CacheTags<t>, c>(getInstanceName(), params); \
+return retval; \
} while (0)
#define BUILD_CACHE_PANIC(x) do { \
panic("%s not compiled into M5", x); \
} while (0)
-#if defined(USE_LZSS_COMPRESSION)
-#define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
- if (compressed_bus || store_compressed){ \
- CacheTags<TAGS, LZSSCompression> *tagStore = \
- new CacheTags<TAGS, LZSSCompression>(tags, \
- compression_latency, \
- true, store_compressed, \
- adaptive_compression, \
- prefetch_miss); \
- BUILD_CACHE(TAGS, LZSSCompression, b, c); \
- } else { \
- CacheTags<TAGS, NullCompression> *tagStore = \
- new CacheTags<TAGS, NullCompression>(tags, \
- compression_latency, \
- true, store_compressed, \
- adaptive_compression, \
- prefetch_miss); \
- BUILD_CACHE(TAGS, NullCompression, b, c); \
- } \
- } while (0)
-#else
-#define BUILD_COMPRESSED_CACHE(TAGS, tags, b, c) do { \
- if (compressed_bus || store_compressed){ \
- BUILD_CACHE_PANIC("compressed caches"); \
+#define BUILD_COMPRESSED_CACHE(TAGS, tags, c) \
+ do { \
+ CompressionAlgorithm *compAlg; \
+ if (compressed_bus || store_compressed) { \
+ compAlg = new LZSSCompression(); \
} else { \
- CacheTags<TAGS, NullCompression> *tagStore = \
- new CacheTags<TAGS, NullCompression>(tags, \
- compression_latency, \
- true, store_compressed, \
- adaptive_compression \
- prefetch_miss); \
- BUILD_CACHE(TAGS, NullCompression, b, c); \
+ compAlg = new NullCompression(); \
} \
+ CacheTags<TAGS> *tagStore = \
+ new CacheTags<TAGS>(tags, compression_latency, true, \
+ store_compressed, adaptive_compression, \
+ compressed_bus, \
+ compAlg, prefetch_miss); \
+ BUILD_CACHE(TAGS, c); \
} while (0)
-#endif
#if defined(USE_CACHE_FALRU)
-#define BUILD_FALRU_CACHE(b,c) do { \
+#define BUILD_FALRU_CACHE(c) do { \
FALRU *tags = new FALRU(block_size, size, latency); \
- BUILD_COMPRESSED_CACHE(FALRU, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(FALRU, tags, c); \
} while (0)
#else
-#define BUILD_FALRU_CACHE(b, c) BUILD_CACHE_PANIC("falru cache")
+#define BUILD_FALRU_CACHE(c) BUILD_CACHE_PANIC("falru cache")
#endif
#if defined(USE_CACHE_LRU)
-#define BUILD_LRU_CACHE(b, c) do { \
+#define BUILD_LRU_CACHE(c) do { \
LRU *tags = new LRU(numSets, block_size, assoc, latency); \
- BUILD_COMPRESSED_CACHE(LRU, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(LRU, tags, c); \
} while (0)
#else
-#define BUILD_LRU_CACHE(b, c) BUILD_CACHE_PANIC("lru cache")
+#define BUILD_LRU_CACHE(c) BUILD_CACHE_PANIC("lru cache")
#endif
#if defined(USE_CACHE_SPLIT)
-#define BUILD_SPLIT_CACHE(b, c) do { \
+#define BUILD_SPLIT_CACHE(c) do { \
Split *tags = new Split(numSets, block_size, assoc, split_size, lifo, \
two_queue, latency); \
- BUILD_COMPRESSED_CACHE(Split, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(Split, tags, c); \
} while (0)
#else
-#define BUILD_SPLIT_CACHE(b, c) BUILD_CACHE_PANIC("split cache")
+#define BUILD_SPLIT_CACHE(c) BUILD_CACHE_PANIC("split cache")
#endif
#if defined(USE_CACHE_SPLIT_LIFO)
-#define BUILD_SPLIT_LIFO_CACHE(b, c) do { \
+#define BUILD_SPLIT_LIFO_CACHE(c) do { \
SplitLIFO *tags = new SplitLIFO(block_size, size, assoc, \
latency, two_queue, -1); \
- BUILD_COMPRESSED_CACHE(SplitLIFO, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(SplitLIFO, tags, c); \
} while (0)
#else
-#define BUILD_SPLIT_LIFO_CACHE(b, c) BUILD_CACHE_PANIC("lifo cache")
+#define BUILD_SPLIT_LIFO_CACHE(c) BUILD_CACHE_PANIC("lifo cache")
#endif
#if defined(USE_CACHE_IIC)
-#define BUILD_IIC_CACHE(b ,c) do { \
+#define BUILD_IIC_CACHE(c) do { \
IIC *tags = new IIC(iic_params); \
- BUILD_COMPRESSED_CACHE(IIC, tags, b, c); \
+ BUILD_COMPRESSED_CACHE(IIC, tags, c); \
} while (0)
#else
-#define BUILD_IIC_CACHE(b, c) BUILD_CACHE_PANIC("iic")
+#define BUILD_IIC_CACHE(c) BUILD_CACHE_PANIC("iic")
#endif
-#define BUILD_CACHES(b, c) do { \
+#define BUILD_CACHES(c) do { \
if (repl == NULL) { \
if (numSets == 1) { \
- BUILD_FALRU_CACHE(b, c); \
+ BUILD_FALRU_CACHE(c); \
} else { \
if (split == true) { \
- BUILD_SPLIT_CACHE(b, c); \
+ BUILD_SPLIT_CACHE(c); \
} else if (lifo == true) { \
- BUILD_SPLIT_LIFO_CACHE(b, c); \
+ BUILD_SPLIT_LIFO_CACHE(c); \
} else { \
- BUILD_LRU_CACHE(b, c); \
+ BUILD_LRU_CACHE(c); \
} \
} \
} else { \
- BUILD_IIC_CACHE(b, c); \
+ BUILD_IIC_CACHE(c); \
} \
} while (0)
#define BUILD_COHERENCE(b) do { \
if (protocol == NULL) { \
UniCoherence *coh = new UniCoherence(); \
- BUILD_CACHES(b, UniCoherence); \
+ BUILD_CACHES(UniCoherence); \
} else { \
SimpleCoherence *coh = new SimpleCoherence(protocol); \
- BUILD_CACHES(b, SimpleCoherence); \
+ BUILD_CACHES(SimpleCoherence); \
} \
} while (0)
#if defined(USE_TAGGED)
-#define BUILD_TAGGED_PREFETCHER(t, comp, b) pf = new \
- TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
+#define BUILD_TAGGED_PREFETCHER(t) pf = new \
+ TaggedPrefetcher<CacheTags<t> >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
@@ -368,12 +336,12 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
prefetch_latency, \
prefetch_degree)
#else
-#define BUILD_TAGGED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Tagged Prefetcher")
+#define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
#endif
#if defined(USE_STRIDED)
-#define BUILD_STRIDED_PREFETCHER(t, comp, b) pf = new \
- StridePrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
+#define BUILD_STRIDED_PREFETCHER(t) pf = new \
+ StridePrefetcher<CacheTags<t> >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
@@ -382,12 +350,12 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
prefetch_degree, \
prefetch_use_cpu_id)
#else
-#define BUILD_STRIDED_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("Stride Prefetcher")
+#define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
#endif
#if defined(USE_GHB)
-#define BUILD_GHB_PREFETCHER(t, comp, b) pf = new \
- GHBPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
+#define BUILD_GHB_PREFETCHER(t) pf = new \
+ GHBPrefetcher<CacheTags<t> >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
@@ -396,12 +364,12 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
prefetch_degree, \
prefetch_use_cpu_id)
#else
-#define BUILD_GHB_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("GHB Prefetcher")
+#define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
#endif
#if defined(USE_TAGGED)
-#define BUILD_NULL_PREFETCHER(t, comp, b) pf = new \
- TaggedPrefetcher<CacheTags<t, comp>, b>(prefetcher_size, \
+#define BUILD_NULL_PREFETCHER(t) pf = new \
+ TaggedPrefetcher<CacheTags<t> >(prefetcher_size, \
!prefetch_past_page, \
prefetch_serial_squash, \
prefetch_cache_check_push, \
@@ -409,7 +377,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
prefetch_latency, \
prefetch_degree)
#else
-#define BUILD_NULL_PREFETCHER(t, comp, b) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
+#define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
#endif
CREATE_SIM_OBJECT(BaseCache)
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 3a681bc52..6742d5892 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -55,9 +55,9 @@
bool SIGNAL_NACK_HACK;
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
bool
-Cache<TagStore,Buffering,Coherence>::
+Cache<TagStore,Coherence>::
doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
{
if (isCpuSide)
@@ -81,9 +81,9 @@ doTimingAccess(PacketPtr pkt, CachePort *cachePort, bool isCpuSide)
return true;
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
Tick
-Cache<TagStore,Buffering,Coherence>::
+Cache<TagStore,Coherence>::
doAtomicAccess(PacketPtr pkt, bool isCpuSide)
{
if (isCpuSide)
@@ -103,9 +103,9 @@ doAtomicAccess(PacketPtr pkt, bool isCpuSide)
return hitLatency;
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::
+Cache<TagStore,Coherence>::
doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
{
if (isCpuSide)
@@ -123,19 +123,19 @@ doFunctionalAccess(PacketPtr pkt, bool isCpuSide)
}
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::
+Cache<TagStore,Coherence>::
recvStatusChange(Port::Status status, bool isCpuSide)
{
}
-template<class TagStore, class Buffering, class Coherence>
-Cache<TagStore,Buffering,Coherence>::
+template<class TagStore, class Coherence>
+Cache<TagStore,Coherence>::
Cache(const std::string &_name,
- Cache<TagStore,Buffering,Coherence>::Params &params)
+ Cache<TagStore,Coherence>::Params &params)
: BaseCache(_name, params.baseParams),
prefetchAccess(params.prefetchAccess),
tags(params.tags), missQueue(params.missQueue),
@@ -154,9 +154,9 @@ Cache(const std::string &_name,
invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::regStats()
+Cache<TagStore,Coherence>::regStats()
{
BaseCache::regStats();
tags->regStats(name());
@@ -165,9 +165,9 @@ Cache<TagStore,Buffering,Coherence>::regStats()
prefetcher->regStats(name());
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
bool
-Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
+Cache<TagStore,Coherence>::access(PacketPtr &pkt)
{
//@todo Add back in MemDebug Calls
// MemDebug::cacheAccess(pkt);
@@ -253,9 +253,9 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
PacketPtr
-Cache<TagStore,Buffering,Coherence>::getPacket()
+Cache<TagStore,Coherence>::getPacket()
{
assert(missQueue->havePending());
PacketPtr pkt = missQueue->getPacket();
@@ -276,9 +276,9 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
return pkt;
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
+Cache<TagStore,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
bool success)
{
if (success && !(SIGNAL_NACK_HACK)) {
@@ -319,9 +319,9 @@ Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, MSHR* mshr,
}
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
+Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt)
{
BlkType *blk = NULL;
if (pkt->senderState) {
@@ -363,16 +363,16 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(PacketPtr &pkt)
}
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
PacketPtr
-Cache<TagStore,Buffering,Coherence>::getCoherencePacket()
+Cache<TagStore,Coherence>::getCoherencePacket()
{
return coherence->getPacket();
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
+Cache<TagStore,Coherence>::sendCoherenceResult(PacketPtr &pkt,
MSHR *cshr,
bool success)
{
@@ -380,9 +380,9 @@ Cache<TagStore,Buffering,Coherence>::sendCoherenceResult(PacketPtr &pkt,
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
+Cache<TagStore,Coherence>::snoop(PacketPtr &pkt)
{
if (pkt->req->isUncacheable()) {
//Can't get a hit on an uncacheable address
@@ -514,9 +514,9 @@ Cache<TagStore,Buffering,Coherence>::snoop(PacketPtr &pkt)
tags->handleSnoop(blk, new_state);
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
+Cache<TagStore,Coherence>::snoopResponse(PacketPtr &pkt)
{
//Need to handle the response, if NACKED
if (pkt->flags & NACKED_LINE) {
@@ -533,9 +533,9 @@ Cache<TagStore,Buffering,Coherence>::snoopResponse(PacketPtr &pkt)
}
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
void
-Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
+Cache<TagStore,Coherence>::invalidateBlk(Addr addr)
{
tags->invalidateBlk(addr);
}
@@ -544,9 +544,9 @@ Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
/**
* @todo Fix to not assume write allocate
*/
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
Tick
-Cache<TagStore,Buffering,Coherence>::probe(PacketPtr &pkt, bool update,
+Cache<TagStore,Coherence>::probe(PacketPtr &pkt, bool update,
CachePort* otherSidePort)
{
// MemDebug::cacheProbe(pkt);
@@ -694,9 +694,9 @@ return 0;
return 0;
}
-template<class TagStore, class Buffering, class Coherence>
+template<class TagStore, class Coherence>
Tick
-Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
+Cache<TagStore,Coherence>::snoopProbe(PacketPtr &pkt)
{
//Send a atomic (false) invalidate up if the protocol calls for it
if (coherence->propogateInvalidate(pkt, false)) {
diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index bf741e547..4a431d82d 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -33,11 +33,9 @@
* Definitions of a simple buffer for a blocking cache.
*/
-#include "cpu/smt.hh" //for maxThreadsPerCPU
#include "mem/cache/base_cache.hh"
#include "mem/cache/miss/blocking_buffer.hh"
#include "mem/cache/prefetch/base_prefetcher.hh"
-#include "sim/eventq.hh" // for Event declaration.
#include "mem/request.hh"
/**
@@ -46,28 +44,11 @@
void
BlockingBuffer::regStats(const std::string &name)
{
- using namespace Stats;
- writebacks
- .init(maxThreadsPerCPU)
- .name(name + ".writebacks")
- .desc("number of writebacks")
- .flags(total)
- ;
+ MissBuffer::regStats(name);
}
-void
-BlockingBuffer::setCache(BaseCache *_cache)
-{
- cache = _cache;
- blkSize = cache->getBlockSize();
-}
void
-BlockingBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
-{
- prefetcher = _prefetcher;
-}
-void
BlockingBuffer::handleMiss(PacketPtr &pkt, int blk_size, Tick time)
{
Addr blk_addr = pkt->getAddr() & ~(Addr)(blk_size - 1);
@@ -241,3 +222,23 @@ BlockingBuffer::doWriteback(PacketPtr &pkt)
cache->setBlocked(Blocked_NoWBBuffers);
cache->setMasterRequest(Request_WB, curTick);
}
+
+
+MSHR *
+BlockingBuffer::findMSHR(Addr addr)
+{
+ if (miss.addr == addr && miss.pkt)
+ return &miss;
+ return NULL;
+}
+
+
+bool
+BlockingBuffer::findWrites(Addr addr, std::vector<MSHR*>& writes)
+{
+ if (wb.addr == addr && wb.pkt) {
+ writes.push_back(&wb);
+ return true;
+ }
+ return false;
+}
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index 934a843a6..205068a8c 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -38,16 +38,14 @@
#include <vector>
+#include "base/misc.hh" // for fatal()
+#include "mem/cache/miss/miss_buffer.hh"
#include "mem/cache/miss/mshr.hh"
-#include "base/statistics.hh"
-
-class BaseCache;
-class BasePrefetcher;
/**
* Miss and writeback storage for a blocking cache.
*/
-class BlockingBuffer
+class BlockingBuffer : public MissBuffer
{
protected:
/** Miss storage. */
@@ -55,38 +53,13 @@ protected:
/** WB storage. */
MSHR wb;
- //Params
-
- /** Allocate on write misses. */
- const bool writeAllocate;
-
- /** Pointer to the parent cache. */
- BaseCache* cache;
-
- BasePrefetcher* prefetcher;
-
- /** Block size of the parent cache. */
- int blkSize;
-
- // Statistics
- /**
- * @addtogroup CacheStatistics
- * @{
- */
- /** Number of blocks written back per thread. */
- Stats::Vector<> writebacks;
-
- /**
- * @}
- */
-
public:
/**
* Builds and initializes this buffer.
* @param write_allocate If true, treat write misses the same as reads.
*/
BlockingBuffer(bool write_allocate)
- : writeAllocate(write_allocate)
+ : MissBuffer(write_allocate)
{
}
@@ -97,14 +70,6 @@ public:
void regStats(const std::string &name);
/**
- * Called by the parent cache to set the back pointer.
- * @param _cache A pointer to the parent cache.
- */
- void setCache(BaseCache *_cache);
-
- void setPrefetcher(BasePrefetcher *_prefetcher);
-
- /**
* Handle a cache miss properly. Requests the bus and marks the cache as
* blocked.
* @param pkt The request that missed in the cache.
@@ -183,12 +148,7 @@ public:
* @param asid The address space id.
* @return A pointer to miss if it matches.
*/
- MSHR* findMSHR(Addr addr)
- {
- if (miss.addr == addr && miss.pkt)
- return &miss;
- return NULL;
- }
+ MSHR* findMSHR(Addr addr);
/**
* Searches for the supplied address in the write buffer.
@@ -197,16 +157,7 @@ public:
* @param writes List of pointers to the matching writes.
* @return True if there is a matching write.
*/
- bool findWrites(Addr addr, std::vector<MSHR*>& writes)
- {
- if (wb.addr == addr && wb.pkt) {
- writes.push_back(&wb);
- return true;
- }
- return false;
- }
-
-
+ bool findWrites(Addr addr, std::vector<MSHR*>& writes);
/**
* Perform a writeback of dirty data to the given address.
diff --git a/src/mem/cache/miss/miss_buffer.cc b/src/mem/cache/miss/miss_buffer.cc
new file mode 100644
index 000000000..4d9cd0958
--- /dev/null
+++ b/src/mem/cache/miss/miss_buffer.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Erik Hallnor
+ */
+
+#include "cpu/smt.hh" //for maxThreadsPerCPU
+#include "mem/cache/base_cache.hh"
+#include "mem/cache/miss/miss_buffer.hh"
+#include "mem/cache/prefetch/base_prefetcher.hh"
+
+/**
+ * @todo Move writebacks into shared BaseBuffer class.
+ */
+void
+MissBuffer::regStats(const std::string &name)
+{
+ using namespace Stats;
+ writebacks
+ .init(maxThreadsPerCPU)
+ .name(name + ".writebacks")
+ .desc("number of writebacks")
+ .flags(total)
+ ;
+}
+
+void
+MissBuffer::setCache(BaseCache *_cache)
+{
+ cache = _cache;
+ blkSize = cache->getBlockSize();
+}
+
+void
+MissBuffer::setPrefetcher(BasePrefetcher *_prefetcher)
+{
+ prefetcher = _prefetcher;
+}
diff --git a/src/mem/cache/miss/miss_buffer.hh b/src/mem/cache/miss/miss_buffer.hh
new file mode 100644
index 000000000..3e3080578
--- /dev/null
+++ b/src/mem/cache/miss/miss_buffer.hh
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+/**
+ * @file
+ * MissBuffer declaration.
+ */
+
+#ifndef __MISS_BUFFER_HH__
+#define __MISS_BUFFER_HH__
+
+class BaseCache;
+class BasePrefetcher;
+class MSHR;
+
+/**
+ * Abstract base class for cache miss buffering.
+ */
+class MissBuffer
+{
+ protected:
+ /** True if the cache should allocate on a write miss. */
+ const bool writeAllocate;
+
+ /** Pointer to the parent cache. */
+ BaseCache *cache;
+
+ /** The Prefetcher */
+ BasePrefetcher *prefetcher;
+
+ /** Block size of the parent cache. */
+ int blkSize;
+
+ // Statistics
+ /**
+ * @addtogroup CacheStatistics
+ * @{
+ */
+ /** Number of blocks written back per thread. */
+ Stats::Vector<> writebacks;
+
+ /**
+ * @}
+ */
+
+ public:
+ MissBuffer(bool write_allocate)
+ : writeAllocate(write_allocate)
+ {
+ }
+
+ virtual ~MissBuffer() {}
+
+ /**
+ * Called by the parent cache to set the back pointer.
+ * @param _cache A pointer to the parent cache.
+ */
+ void setCache(BaseCache *_cache);
+
+ void setPrefetcher(BasePrefetcher *_prefetcher);
+
+ /**
+ * Register statistics for this object.
+ * @param name The name of the parent cache.
+ */
+ virtual void regStats(const std::string &name);
+
+ /**
+ * Handle a cache miss properly. Either allocate an MSHR for the request,
+ * or forward it through the write buffer.
+ * @param pkt The request that missed in the cache.
+ * @param blk_size The block size of the cache.
+ * @param time The time the miss is detected.
+ */
+ virtual void handleMiss(PacketPtr &pkt, int blk_size, Tick time) = 0;
+
+ /**
+ * Fetch the block for the given address and buffer the given target.
+ * @param addr The address to fetch.
+ * @param asid The address space of the address.
+ * @param blk_size The block size of the cache.
+ * @param time The time the miss is detected.
+ * @param target The target for the fetch.
+ */
+ virtual MSHR *fetchBlock(Addr addr, int blk_size, Tick time,
+ PacketPtr &target) = 0;
+
+ /**
+ * Selects a outstanding request to service.
+ * @return The request to service, NULL if none found.
+ */
+ virtual PacketPtr getPacket() = 0;
+
+ /**
+ * Set the command to the given bus command.
+ * @param pkt The request to update.
+ * @param cmd The bus command to use.
+ */
+ virtual void setBusCmd(PacketPtr &pkt, Packet::Command cmd) = 0;
+
+ /**
+ * Restore the original command in case of a bus transmission error.
+ * @param pkt The request to reset.
+ */
+ virtual void restoreOrigCmd(PacketPtr &pkt) = 0;
+
+ /**
+ * Marks a request as in service (sent on the bus). This can have side
+ * effect since storage for no response commands is deallocated once they
+ * are successfully sent.
+ * @param pkt The request that was sent on the bus.
+ */
+ virtual void markInService(PacketPtr &pkt, MSHR* mshr) = 0;
+
+ /**
+ * Collect statistics and free resources of a satisfied request.
+ * @param pkt The request that has been satisfied.
+ * @param time The time when the request is satisfied.
+ */
+ virtual void handleResponse(PacketPtr &pkt, Tick time) = 0;
+
+ /**
+ * Removes all outstanding requests for a given thread number. If a request
+ * has been sent to the bus, this function removes all of its targets.
+ * @param threadNum The thread number of the requests to squash.
+ */
+ virtual void squash(int threadNum) = 0;
+
+ /**
+ * Return the current number of outstanding misses.
+ * @return the number of outstanding misses.
+ */
+ virtual int getMisses() = 0;
+
+ /**
+ * Searches for the supplied address in the miss queue.
+ * @param addr The address to look for.
+ * @param asid The address space id.
+ * @return The MSHR that contains the address, NULL if not found.
+ * @warning Currently only searches the miss queue. If non write allocate
+ * might need to search the write buffer for coherence.
+ */
+ virtual MSHR* findMSHR(Addr addr) = 0;
+
+ /**
+ * Searches for the supplied address in the write buffer.
+ * @param addr The address to look for.
+ * @param asid The address space id.
+ * @param writes The list of writes that match the address.
+ * @return True if any writes are found
+ */
+ virtual bool findWrites(Addr addr, std::vector<MSHR*>& writes) = 0;
+
+ /**
+ * Perform a writeback of dirty data to the given address.
+ * @param addr The address to write to.
+ * @param asid The address space id.
+ * @param xc The execution context of the address space.
+ * @param size The number of bytes to write.
+ * @param data The data to write, can be NULL.
+ * @param compressed True if the data is compressed.
+ */
+ virtual void doWriteback(Addr addr, int size, uint8_t *data,
+ bool compressed) = 0;
+
+ /**
+ * Perform the given writeback request.
+ * @param pkt The writeback request.
+ */
+ virtual void doWriteback(PacketPtr &pkt) = 0;
+
+ /**
+ * Returns true if there are outstanding requests.
+ * @return True if there are outstanding requests.
+ */
+ virtual bool havePending() = 0;
+
+ /**
+ * Add a target to the given MSHR. This assumes it is in the miss queue.
+ * @param mshr The mshr to add a target to.
+ * @param pkt The target to add.
+ */
+ virtual void addTarget(MSHR *mshr, PacketPtr &pkt) = 0;
+
+ /**
+ * Allocate a MSHR to hold a list of targets to a block involved in a copy.
+ * If the block is marked done then the MSHR already holds the data to
+ * fill the block. Otherwise the block needs to be fetched.
+ * @param addr The address to buffer.
+ * @param asid The address space ID.
+ * @return A pointer to the allocated MSHR.
+ */
+ virtual MSHR* allocateTargetList(Addr addr) = 0;
+};
+
+#endif //__MISS_BUFFER_HH__
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 3c4586272..1d3e22326 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -48,16 +48,25 @@ using namespace std;
*/
MissQueue::MissQueue(int numMSHRs, int numTargets, int write_buffers,
bool write_allocate, bool prefetch_miss)
- : mq(numMSHRs, 4), wb(write_buffers,numMSHRs+1000), numMSHR(numMSHRs),
+ : MissBuffer(write_allocate),
+ mq(numMSHRs, 4), wb(write_buffers,numMSHRs+1000), numMSHR(numMSHRs),
numTarget(numTargets), writeBuffers(write_buffers),
- writeAllocate(write_allocate), order(0), prefetchMiss(prefetch_miss)
+ order(0), prefetchMiss(prefetch_miss)
{
noTargetMSHR = NULL;
}
+
+MissQueue::~MissQueue()
+{
+}
+
+
void
MissQueue::regStats(const string &name)
{
+ MissBuffer::regStats(name);
+
Request temp_req((Addr) NULL, 4, 0);
Packet::Command temp_cmd = Packet::ReadReq;
Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary
@@ -65,13 +74,6 @@ MissQueue::regStats(const string &name)
using namespace Stats;
- writebacks
- .init(maxThreadsPerCPU)
- .name(name + ".writebacks")
- .desc("number of writebacks")
- .flags(total)
- ;
-
// MSHR hit statistics
for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
Packet::Command cmd = (Packet::Command)access_idx;
@@ -336,18 +338,6 @@ MissQueue::regStats(const string &name)
}
-void
-MissQueue::setCache(BaseCache *_cache)
-{
- cache = _cache;
- blkSize = cache->getBlockSize();
-}
-
-void
-MissQueue::setPrefetcher(BasePrefetcher *_prefetcher)
-{
- prefetcher = _prefetcher;
-}
MSHR*
MissQueue::allocateMiss(PacketPtr &pkt, int size, Tick time)
@@ -706,13 +696,13 @@ MissQueue::squash(int threadNum)
}
MSHR*
-MissQueue::findMSHR(Addr addr) const
+MissQueue::findMSHR(Addr addr)
{
return mq.findMatch(addr);
}
bool
-MissQueue::findWrites(Addr addr, vector<MSHR*> &writes) const
+MissQueue::findWrites(Addr addr, vector<MSHR*> &writes)
{
return wb.findMatches(addr,writes);
}
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index b67a896f4..1f9bb1e0c 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -38,19 +38,18 @@
#include <vector>
+#include "mem/cache/miss/miss_buffer.hh"
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/miss/mshr_queue.hh"
#include "base/statistics.hh"
-class BaseCache;
-class BasePrefetcher;
/**
* Manages cache misses and writebacks. Contains MSHRs to store miss data
* and the writebuffer for writes/writebacks.
* @todo need to handle data on writes better (encapsulate).
* @todo need to make replacements/writebacks happen in Cache::access
*/
-class MissQueue
+class MissQueue : public MissBuffer
{
protected:
/** The MSHRs. */
@@ -66,16 +65,6 @@ class MissQueue
const int numTarget;
/** The number of write buffers. */
const int writeBuffers;
- /** True if the cache should allocate on a write miss. */
- const bool writeAllocate;
- /** Pointer to the parent cache. */
- BaseCache* cache;
-
- /** The Prefetcher */
- BasePrefetcher *prefetcher;
-
- /** The block size of the parent cache. */
- int blkSize;
/** Increasing order number assigned to each incoming request. */
uint64_t order;
@@ -87,9 +76,6 @@ class MissQueue
* @addtogroup CacheStatistics
* @{
*/
- /** Number of blocks written back per thread. */
- Stats::Vector<> writebacks;
-
/** Number of misses that hit in the MSHRs per command and thread. */
Stats::Vector<> mshr_hits[NUM_MEM_CMDS];
/** Demand misses that hit in the MSHRs. */
@@ -204,14 +190,6 @@ class MissQueue
void regStats(const std::string &name);
/**
- * Called by the parent cache to set the back pointer.
- * @param _cache A pointer to the parent cache.
- */
- void setCache(BaseCache *_cache);
-
- void setPrefetcher(BasePrefetcher *_prefetcher);
-
- /**
* Handle a cache miss properly. Either allocate an MSHR for the request,
* or forward it through the write buffer.
* @param pkt The request that missed in the cache.
@@ -289,7 +267,7 @@ class MissQueue
* @warning Currently only searches the miss queue. If non write allocate
* might need to search the write buffer for coherence.
*/
- MSHR* findMSHR(Addr addr) const;
+ MSHR* findMSHR(Addr addr);
/**
* Searches for the supplied address in the write buffer.
@@ -298,7 +276,7 @@ class MissQueue
* @param writes The list of writes that match the address.
* @return True if any writes are found
*/
- bool findWrites(Addr addr, std::vector<MSHR*>& writes) const;
+ bool findWrites(Addr addr, std::vector<MSHR*>& writes);
/**
* Perform a writeback of dirty data to the given address.
diff --git a/src/mem/cache/prefetch/ghb_prefetcher.cc b/src/mem/cache/prefetch/ghb_prefetcher.cc
index 247ec6e8b..a6c419113 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.cc
+++ b/src/mem/cache/prefetch/ghb_prefetcher.cc
@@ -38,17 +38,11 @@
#include "mem/cache/tags/lru.hh"
-#include "base/compression/null_compression.hh"
-
-#include "mem/cache/miss/miss_queue.hh"
-#include "mem/cache/miss/blocking_buffer.hh"
-
#include "mem/cache/prefetch/ghb_prefetcher.hh"
// Template Instantiations
#ifndef DOXYGEN_SHOULD_SKIP_THIS
-template class GHBPrefetcher<CacheTags<LRU,NullCompression>, MissQueue>;
-template class GHBPrefetcher<CacheTags<LRU,NullCompression>, BlockingBuffer>;
+template class GHBPrefetcher<CacheTags<LRU> >;
#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb_prefetcher.hh
index 14f5747df..c558a3e64 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.hh
+++ b/src/mem/cache/prefetch/ghb_prefetcher.hh
@@ -43,16 +43,16 @@
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
+ * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
-template <class TagStore, class Buffering>
-class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
+template <class TagStore>
+class GHBPrefetcher : public Prefetcher<TagStore>
{
protected:
- Buffering* mq;
+ MissBuffer* mq;
TagStore* tags;
Addr second_last_miss_addr[64/*MAX_CPUS*/];
@@ -67,7 +67,7 @@ class GHBPrefetcher : public Prefetcher<TagStore, Buffering>
GHBPrefetcher(int size, bool pageStop, bool serialSquash,
bool cacheCheckPush, bool onlyData,
Tick latency, int degree, bool useCPUId)
- :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
+ :Prefetcher<TagStore>(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree), useCPUId(useCPUId)
{
diff --git a/src/mem/cache/prefetch/stride_prefetcher.cc b/src/mem/cache/prefetch/stride_prefetcher.cc
index 93a096468..2204871cc 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.cc
+++ b/src/mem/cache/prefetch/stride_prefetcher.cc
@@ -38,17 +38,11 @@
#include "mem/cache/tags/lru.hh"
-#include "base/compression/null_compression.hh"
-
-#include "mem/cache/miss/miss_queue.hh"
-#include "mem/cache/miss/blocking_buffer.hh"
-
#include "mem/cache/prefetch/stride_prefetcher.hh"
// Template Instantiations
#ifndef DOXYGEN_SHOULD_SKIP_THIS
-template class StridePrefetcher<CacheTags<LRU,NullCompression>, MissQueue>;
-template class StridePrefetcher<CacheTags<LRU,NullCompression>, BlockingBuffer>;
+template class StridePrefetcher<CacheTags<LRU> >;
#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/prefetch/stride_prefetcher.hh b/src/mem/cache/prefetch/stride_prefetcher.hh
index d6fb8ab66..57e430400 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.hh
+++ b/src/mem/cache/prefetch/stride_prefetcher.hh
@@ -43,16 +43,16 @@
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
+ * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
-template <class TagStore, class Buffering>
-class StridePrefetcher : public Prefetcher<TagStore, Buffering>
+template <class TagStore>
+class StridePrefetcher : public Prefetcher<TagStore>
{
protected:
- Buffering* mq;
+ MissBuffer* mq;
TagStore* tags;
class strideEntry
@@ -84,7 +84,7 @@ class StridePrefetcher : public Prefetcher<TagStore, Buffering>
StridePrefetcher(int size, bool pageStop, bool serialSquash,
bool cacheCheckPush, bool onlyData,
Tick latency, int degree, bool useCPUId)
- :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
+ :Prefetcher<TagStore>(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree), useCPUId(useCPUId)
{
diff --git a/src/mem/cache/prefetch/tagged_prefetcher.hh b/src/mem/cache/prefetch/tagged_prefetcher.hh
index b61e57dcc..dc2aaec50 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher.hh
+++ b/src/mem/cache/prefetch/tagged_prefetcher.hh
@@ -41,16 +41,16 @@
/**
* A template-policy based cache. The behavior of the cache can be altered by
* supplying different template policies. TagStore handles all tag and data
- * storage @sa TagStore. Buffering handles all misses and writes/writebacks
+ * storage @sa TagStore. MissBuffer handles all misses and writes/writebacks
* @sa MissQueue. Coherence handles all coherence policy details @sa
* UniCoherence, SimpleMultiCoherence.
*/
-template <class TagStore, class Buffering>
-class TaggedPrefetcher : public Prefetcher<TagStore, Buffering>
+template <class TagStore>
+class TaggedPrefetcher : public Prefetcher<TagStore>
{
protected:
- Buffering* mq;
+ MissBuffer* mq;
TagStore* tags;
Tick latency;
diff --git a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
index a18de4571..b3d4284c7 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
+++ b/src/mem/cache/prefetch/tagged_prefetcher_impl.hh
@@ -36,20 +36,20 @@
#include "arch/isa_traits.hh"
#include "mem/cache/prefetch/tagged_prefetcher.hh"
-template <class TagStore, class Buffering>
-TaggedPrefetcher<TagStore, Buffering>::
+template <class TagStore>
+TaggedPrefetcher<TagStore>::
TaggedPrefetcher(int size, bool pageStop, bool serialSquash,
bool cacheCheckPush, bool onlyData,
Tick latency, int degree)
- :Prefetcher<TagStore, Buffering>(size, pageStop, serialSquash,
+ :Prefetcher<TagStore>(size, pageStop, serialSquash,
cacheCheckPush, onlyData),
latency(latency), degree(degree)
{
}
-template <class TagStore, class Buffering>
+template <class TagStore>
void
-TaggedPrefetcher<TagStore, Buffering>::
+TaggedPrefetcher<TagStore>::
calculatePrefetch(PacketPtr &pkt, std::list<Addr> &addresses,
std::list<Tick> &delays)
{
diff --git a/src/python/m5/objects/Repl.py b/src/python/m5/objects/Repl.py
index 10892cf6f..b76aa1d6e 100644
--- a/src/python/m5/objects/Repl.py
+++ b/src/python/m5/objects/Repl.py
@@ -6,6 +6,6 @@ class Repl(SimObject):
class GenRepl(Repl):
type = 'GenRepl'
- fresh_res = Param.Int("associativity")
- num_pools = Param.Int("capacity in bytes")
- pool_res = Param.Int("block size in bytes")
+ fresh_res = Param.Int("Fresh pool residency time")
+ num_pools = Param.Int("Number of priority pools")
+ pool_res = Param.Int("Pool residency time")
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 9e5f985c3..d83d5f73f 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -237,6 +237,12 @@ class NumericParamValue(ParamValue):
def __float__(self):
return float(self.value)
+ def __long__(self):
+ return long(self.value)
+
+ def __int__(self):
+ return int(self.value)
+
# hook for bounds checking
def _check(self):
return
@@ -308,8 +314,11 @@ class CheckedInt(NumericParamValue):
def __init__(self, value):
if isinstance(value, str):
self.value = convert.toInteger(value)
- elif isinstance(value, (int, long, float)):
+ elif isinstance(value, (int, long, float, NumericParamValue)):
self.value = long(value)
+ else:
+ raise TypeError, "Can't convert object of type %s to CheckedInt" \
+ % type(value).__name__
self._check()
class Int(CheckedInt): cxx_type = 'int'; size = 32; unsigned = False
diff --git a/tests/long/20.parser/ref/alpha/linux/NOTE b/tests/long/20.parser/ref/alpha/linux/NOTE
new file mode 100644
index 000000000..5e7d8c358
--- /dev/null
+++ b/tests/long/20.parser/ref/alpha/linux/NOTE
@@ -0,0 +1,6 @@
+I removed the reference outputs for this program because it's taking
+way too long... over an hour for simple-atomic and over 19 hrs for
+o3-timing. We need to find a shorter input if we want to keep this
+in the regressions.
+
+Steve
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini
index c3a59fbce..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.ini
@@ -1,417 +0,0 @@
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[debug]
-break_cycles=
-
-[exetrace]
-intel_format=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=DerivO3CPU
-children=dcache fuPool icache l2cache toL2Bus workload
-BTBEntries=4096
-BTBTagSize=16
-LFSTSize=1024
-LQEntries=32
-RASSize=16
-SQEntries=32
-SSITSize=1024
-activity=0
-backComSize=5
-choiceCtrBits=2
-choicePredictorSize=8192
-clock=1
-commitToDecodeDelay=1
-commitToFetchDelay=1
-commitToIEWDelay=1
-commitToRenameDelay=1
-commitWidth=8
-decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-defer_registration=false
-dispatchWidth=8
-fetchToDecodeDelay=1
-fetchTrapLatency=1
-fetchWidth=8
-forwardComSize=5
-fuPool=system.cpu.fuPool
-function_trace=false
-function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-iewToCommitDelay=1
-iewToDecodeDelay=1
-iewToFetchDelay=1
-iewToRenameDelay=1
-instShiftAmt=2
-issueToExecuteDelay=1
-issueWidth=8
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-mem=system.cpu.dcache
-numIQEntries=64
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
-numRobs=1
-numThreads=1
-predType=tournament
-renameToDecodeDelay=1
-renameToFetchDelay=1
-renameToIEWDelay=2
-renameToROBDelay=1
-renameWidth=8
-squashWidth=8
-system=system
-trapLatency=13
-wbDepth=1
-wbWidth=8
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.fuPool]
-type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-children=opList0
-count=6
-opList=system.cpu.fuPool.FUList0.opList0
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntAlu
-opLat=1
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-children=opList0 opList1
-count=2
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-issueLat=1
-opClass=IntMult
-opLat=3
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-issueLat=19
-opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatAdd
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-issueLat=1
-opClass=FloatCmp
-opLat=2
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-issueLat=1
-opClass=FloatCvt
-opLat=2
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-children=opList0 opList1 opList2
-count=2
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList4.opList0
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-children=opList0
-count=0
-opList=system.cpu.fuPool.FUList5.opList0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList0 opList1
-count=4
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-issueLat=1
-opClass=MemRead
-opLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-issueLat=1
-opClass=MemWrite
-opLat=1
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0
-count=1
-opList=system.cpu.fuPool.FUList7.opList0
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-issueLat=3
-opClass=IprAccess
-opLat=3
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-do_copy=false
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-env=
-executable=tests/test-progs/hello/bin/alpha/linux/hello
-input=cin
-output=cout
-system=system
-
-[system.membus]
-type=Bus
-bus_id=0
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-port=system.membus.port[0]
-
-[trace]
-bufsize=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out
index f491a3081..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/config.out
@@ -1,403 +0,0 @@
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-executable=tests/test-progs/hello/bin/alpha/linux/hello
-input=cin
-output=cout
-env=
-system=system
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.fuPool.FUList0.opList0]
-type=OpDesc
-opClass=IntAlu
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList0]
-type=FUDesc
-opList=system.cpu.fuPool.FUList0.opList0
-count=6
-
-[system.cpu.fuPool.FUList1.opList0]
-type=OpDesc
-opClass=IntMult
-opLat=3
-issueLat=1
-
-[system.cpu.fuPool.FUList1.opList1]
-type=OpDesc
-opClass=IntDiv
-opLat=20
-issueLat=19
-
-[system.cpu.fuPool.FUList1]
-type=FUDesc
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
-count=2
-
-[system.cpu.fuPool.FUList2.opList0]
-type=OpDesc
-opClass=FloatAdd
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
-opClass=FloatCmp
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2.opList2]
-type=OpDesc
-opClass=FloatCvt
-opLat=2
-issueLat=1
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
-count=4
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-opClass=FloatMult
-opLat=4
-issueLat=1
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-opClass=FloatDiv
-opLat=12
-issueLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-opClass=FloatSqrt
-opLat=24
-issueLat=24
-
-[system.cpu.fuPool.FUList3]
-type=FUDesc
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-count=2
-
-[system.cpu.fuPool.FUList4.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
-opList=system.cpu.fuPool.FUList4.opList0
-count=0
-
-[system.cpu.fuPool.FUList5.opList0]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList5]
-type=FUDesc
-opList=system.cpu.fuPool.FUList5.opList0
-count=0
-
-[system.cpu.fuPool.FUList6.opList0]
-type=OpDesc
-opClass=MemRead
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6.opList1]
-type=OpDesc
-opClass=MemWrite
-opLat=1
-issueLat=1
-
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-count=4
-
-[system.cpu.fuPool.FUList7.opList0]
-type=OpDesc
-opClass=IprAccess
-opLat=3
-issueLat=3
-
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-opList=system.cpu.fuPool.FUList7.opList0
-count=1
-
-[system.cpu.fuPool]
-type=FUPool
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
-
-[system.cpu]
-type=DerivO3CPU
-clock=1
-numThreads=1
-activity=0
-workload=system.cpu.workload
-mem=system.cpu.dcache
-checker=null
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-cachePorts=200
-decodeToFetchDelay=1
-renameToFetchDelay=1
-iewToFetchDelay=1
-commitToFetchDelay=1
-fetchWidth=8
-renameToDecodeDelay=1
-iewToDecodeDelay=1
-commitToDecodeDelay=1
-fetchToDecodeDelay=1
-decodeWidth=8
-iewToRenameDelay=1
-commitToRenameDelay=1
-decodeToRenameDelay=1
-renameWidth=8
-commitToIEWDelay=1
-renameToIEWDelay=2
-issueToExecuteDelay=1
-dispatchWidth=8
-issueWidth=8
-wbWidth=8
-wbDepth=1
-fuPool=system.cpu.fuPool
-iewToCommitDelay=1
-renameToROBDelay=1
-commitWidth=8
-squashWidth=8
-trapLatency=13
-backComSize=5
-forwardComSize=5
-predType=tournament
-localPredictorSize=2048
-localCtrBits=2
-localHistoryTableSize=2048
-localHistoryBits=11
-globalPredictorSize=8192
-globalCtrBits=2
-globalHistoryBits=13
-choicePredictorSize=8192
-choiceCtrBits=2
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-LQEntries=32
-SQEntries=32
-LFSTSize=1024
-SSITSize=1024
-numPhysIntRegs=256
-numPhysFloatRegs=256
-numIQEntries=64
-numROBEntries=192
-smtNumFetchingThreads=1
-smtFetchPolicy=SingleThread
-smtLSQPolicy=Partitioned
-smtLSQThreshold=100
-smtIQPolicy=Partitioned
-smtIQThreshold=100
-smtROBPolicy=Partitioned
-smtROBThreshold=100
-smtCommitPolicy=RoundRobin
-instShiftAmt=2
-defer_registration=false
-function_trace=false
-function_trace_start=0
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-do_copy=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-
-[trace]
-flags=
-start=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-trace_system=client
-
-[debug]
-break_cycles=
-
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt
index 5d4f9235a..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/m5stats.txt
@@ -1,1974 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 542 # Number of BTB hits
-global.BPredUnit.BTBLookups 1938 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted
-global.BPredUnit.lookups 2256 # Number of BP lookups
-global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target.
-host_inst_rate 41797 # Simulator instruction rate (inst/s)
-host_mem_usage 160344 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 50948 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 259 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit.
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 5623 # Number of instructions simulated
-sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 6870 # Number of ticks simulated
-system.cpu.commit.COM:branches 862 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached
-system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 6116
-system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 3908 6389.80%
- 1 1064 1739.70%
- 2 389 636.04%
- 3 210 343.36%
- 4 153 250.16%
- 5 93 152.06%
- 6 76 124.26%
- 7 149 243.62%
- 8 74 120.99%
-system.cpu.commit.COM:committed_per_cycle.max_value 8
-system.cpu.commit.COM:committed_per_cycle.end_dist
-
-system.cpu.commit.COM:count 5640 # Number of instructions committed
-system.cpu.commit.COM:loads 979 # Number of loads committed
-system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 1791 # Number of memory references committed
-system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 5623 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5623 # Number of Instructions Simulated
-system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2048 # number of overall hits
-system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 311 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched
-system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6871
-system.cpu.fetch.rateDist.min_value 0
- 0 4549 6620.58%
- 1 174 253.24%
- 2 186 270.70%
- 3 157 228.50%
- 4 211 307.09%
- 5 153 222.68%
- 6 171 248.87%
- 7 105 152.82%
- 8 1165 1695.53%
-system.cpu.fetch.rateDist.max_value 8
-system.cpu.fetch.rateDist.end_dist
-
-system.cpu.icache.ReadReq_accesses 1582 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 2.960245 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.996885 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1255 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 968 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.206700 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 327 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1582 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1255 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 968 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.206700 # miss rate for demand accesses
-system.cpu.icache.demand_misses 327 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 641 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.202908 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 1582 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 2.960245 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 1.996885 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1255 # number of overall hits
-system.cpu.icache.overall_miss_latency 968 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.206700 # miss rate for overall accesses
-system.cpu.icache.overall_misses 327 # number of overall misses
-system.cpu.icache.overall_mshr_hits 6 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 641 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.202908 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use
-system.cpu.icache.total_refs 1255 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.iew.EXEC:branches 1206 # Number of branches executed
-system.cpu.iew.EXEC:insts 7969 # Number of executed instructions
-system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed
-system.cpu.iew.EXEC:nop 37 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate
-system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed
-system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute
-system.cpu.iew.EXEC:stores 989 # Number of stores executed
-system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5438 # num instructions consuming a value
-system.cpu.iew.WB:count 7722 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back
-system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4049 # num instructions producing a value
-system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle
-system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 55 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads
-system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:(null).samples 0
-system.cpu.iq.IQ:residence:(null).min_value 0
- 0 0
- 2 0
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-system.cpu.iq.IQ:residence:(null).max_value 0
-system.cpu.iq.IQ:residence:(null).end_dist
-
-system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntAlu.samples 0
-system.cpu.iq.IQ:residence:IntAlu.min_value 0
- 0 0
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-system.cpu.iq.IQ:residence:IntAlu.max_value 0
-system.cpu.iq.IQ:residence:IntAlu.end_dist
-
-system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntMult.samples 0
-system.cpu.iq.IQ:residence:IntMult.min_value 0
- 0 0
- 2 0
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- 98 0
-system.cpu.iq.IQ:residence:IntMult.max_value 0
-system.cpu.iq.IQ:residence:IntMult.end_dist
-
-system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IntDiv.samples 0
-system.cpu.iq.IQ:residence:IntDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:IntDiv.max_value 0
-system.cpu.iq.IQ:residence:IntDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatAdd.samples 0
-system.cpu.iq.IQ:residence:FloatAdd.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatAdd.max_value 0
-system.cpu.iq.IQ:residence:FloatAdd.end_dist
-
-system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCmp.samples 0
-system.cpu.iq.IQ:residence:FloatCmp.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatCmp.max_value 0
-system.cpu.iq.IQ:residence:FloatCmp.end_dist
-
-system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatCvt.samples 0
-system.cpu.iq.IQ:residence:FloatCvt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatCvt.max_value 0
-system.cpu.iq.IQ:residence:FloatCvt.end_dist
-
-system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatMult.samples 0
-system.cpu.iq.IQ:residence:FloatMult.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatMult.max_value 0
-system.cpu.iq.IQ:residence:FloatMult.end_dist
-
-system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatDiv.samples 0
-system.cpu.iq.IQ:residence:FloatDiv.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 92 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:FloatDiv.max_value 0
-system.cpu.iq.IQ:residence:FloatDiv.end_dist
-
-system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:FloatSqrt.samples 0
-system.cpu.iq.IQ:residence:FloatSqrt.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:FloatSqrt.max_value 0
-system.cpu.iq.IQ:residence:FloatSqrt.end_dist
-
-system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemRead.samples 0
-system.cpu.iq.IQ:residence:MemRead.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:MemRead.max_value 0
-system.cpu.iq.IQ:residence:MemRead.end_dist
-
-system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:MemWrite.samples 0
-system.cpu.iq.IQ:residence:MemWrite.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 98 0
-system.cpu.iq.IQ:residence:MemWrite.max_value 0
-system.cpu.iq.IQ:residence:MemWrite.end_dist
-
-system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:IprAccess.samples 0
-system.cpu.iq.IQ:residence:IprAccess.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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- 98 0
-system.cpu.iq.IQ:residence:IprAccess.max_value 0
-system.cpu.iq.IQ:residence:IprAccess.end_dist
-
-system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue
-system.cpu.iq.IQ:residence:InstPrefetch.samples 0
-system.cpu.iq.IQ:residence:InstPrefetch.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
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- 96 0
- 98 0
-system.cpu.iq.IQ:residence:InstPrefetch.max_value 0
-system.cpu.iq.IQ:residence:InstPrefetch.end_dist
-
-system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:(null)_delay.samples 0
-system.cpu.iq.ISSUE:(null)_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
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-system.cpu.iq.ISSUE:(null)_delay.max_value 0
-system.cpu.iq.ISSUE:(null)_delay.end_dist
-
-system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntAlu_delay.samples 0
-system.cpu.iq.ISSUE:IntAlu_delay.min_value 0
- 0 0
- 2 0
- 4 0
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- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntAlu_delay.max_value 0
-system.cpu.iq.ISSUE:IntAlu_delay.end_dist
-
-system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntMult_delay.samples 0
-system.cpu.iq.ISSUE:IntMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntMult_delay.max_value 0
-system.cpu.iq.ISSUE:IntMult_delay.end_dist
-
-system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IntDiv_delay.samples 0
-system.cpu.iq.ISSUE:IntDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IntDiv_delay.max_value 0
-system.cpu.iq.ISSUE:IntDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatAdd_delay.samples 0
-system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0
-system.cpu.iq.ISSUE:FloatAdd_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCmp_delay.samples 0
-system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCmp_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatCvt_delay.samples 0
-system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatCvt_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatMult_delay.samples 0
-system.cpu.iq.ISSUE:FloatMult_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatMult_delay.max_value 0
-system.cpu.iq.ISSUE:FloatMult_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatDiv_delay.samples 0
-system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0
-system.cpu.iq.ISSUE:FloatDiv_delay.end_dist
-
-system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0
-system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist
-
-system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemRead_delay.samples 0
-system.cpu.iq.ISSUE:MemRead_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemRead_delay.max_value 0
-system.cpu.iq.ISSUE:MemRead_delay.end_dist
-
-system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:MemWrite_delay.samples 0
-system.cpu.iq.ISSUE:MemWrite_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:MemWrite_delay.max_value 0
-system.cpu.iq.ISSUE:MemWrite_delay.end_dist
-
-system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:IprAccess_delay.samples 0
-system.cpu.iq.ISSUE:IprAccess_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:IprAccess_delay.max_value 0
-system.cpu.iq.ISSUE:IprAccess_delay.end_dist
-
-system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue
-system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0
- 0 0
- 2 0
- 4 0
- 6 0
- 8 0
- 10 0
- 12 0
- 14 0
- 16 0
- 18 0
- 20 0
- 22 0
- 24 0
- 26 0
- 28 0
- 30 0
- 32 0
- 34 0
- 36 0
- 38 0
- 40 0
- 42 0
- 44 0
- 46 0
- 48 0
- 50 0
- 52 0
- 54 0
- 56 0
- 58 0
- 60 0
- 62 0
- 64 0
- 66 0
- 68 0
- 70 0
- 72 0
- 74 0
- 76 0
- 78 0
- 80 0
- 82 0
- 84 0
- 86 0
- 88 0
- 90 0
- 92 0
- 94 0
- 96 0
- 98 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0
-system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist
-
-system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.start_dist
- (null) 2 0.02% # Type of FU issued
- IntAlu 5594 66.69% # Type of FU issued
- IntMult 1 0.01% # Type of FU issued
- IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2 0.02% # Type of FU issued
- FloatCmp 0 0.00% # Type of FU issued
- FloatCvt 0 0.00% # Type of FU issued
- FloatMult 0 0.00% # Type of FU issued
- FloatDiv 0 0.00% # Type of FU issued
- FloatSqrt 0 0.00% # Type of FU issued
- MemRead 1757 20.95% # Type of FU issued
- MemWrite 1032 12.30% # Type of FU issued
- IprAccess 0 0.00% # Type of FU issued
- InstPrefetch 0 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 1 0.87% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 0 0.00% # attempts to use FU when none available
- FloatCmp 0 0.00% # attempts to use FU when none available
- FloatCvt 0 0.00% # attempts to use FU when none available
- FloatMult 0 0.00% # attempts to use FU when none available
- FloatDiv 0 0.00% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 76 66.09% # attempts to use FU when none available
- MemWrite 38 33.04% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full.end_dist
-system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6871
-system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 3753 5462.09%
- 1 894 1301.12%
- 2 723 1052.25%
- 3 614 893.61%
- 4 451 656.38%
- 5 279 406.05%
- 6 104 151.36%
- 7 41 59.67%
- 8 12 17.46%
-system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
-system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-
-system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 497 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 6871 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 408 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
-system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-
----------- End Simulation Statistics ----------
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr b/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr
index 8893caac8..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/stderr
@@ -1,3 +0,0 @@
-warn: Entering event queue @ 0. Starting simulation...
-warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
-warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
diff --git a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout b/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout
index fbb329a2f..e69de29bb 100644
--- a/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout
+++ b/tests/long/30.eon/ref/alpha/linux/o3-timing/stdout
@@ -1,13 +0,0 @@
-Hello world!
-M5 Simulator System
-
-Copyright (c) 2001-2006
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Sep 5 2006 15:28:48
-M5 started Tue Sep 5 15:42:12 2006
-M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
-Exiting @ tick 6870 because target called exit()
diff --git a/util/regress b/util/regress
index 8e60b6fee..5d6f321f2 100755
--- a/util/regress
+++ b/util/regress
@@ -43,11 +43,13 @@ optparser.add_option('--builds', dest='builds',
help='comma-separated list of build targets to test '
" (default: '%default')" )
optparser.add_option('--variants', dest='variants',
- default='opt',
+ default='fast',
help='comma-separated list of build variants to test '
" (default: '%default')" )
optparser.add_option('--scons-opts', dest='scons_opts', default='',
help='scons options', metavar='OPTS')
+optparser.add_option('-j', '--jobs', type='int', default=1,
+ help='number of parallel jobs to use')
(options, tests) = optparser.parse_args()
@@ -75,10 +77,11 @@ def shellquote(s):
try:
if not tests:
- print "No tests specified."
- sys.exit(1)
-
- if 'all' in tests:
+ print "No tests specified, just building binaries."
+ targets = ['build/%s/m5.%s' % (build, variant)
+ for build in builds
+ for variant in variants]
+ elif 'all' in tests:
targets = ['build/%s/tests/%s' % (build, variant)
for build in builds
for variant in variants]
@@ -88,7 +91,11 @@ try:
for variant in variants
for test in tests]
- system('scons %s %s' % (options.scons_opts, ' '.join(targets)))
+ scons_opts = options.scons_opts
+ if options.jobs != 1:
+ scons_opts += ' -j %d' % options.jobs
+
+ system('scons %s %s' % (scons_opts, ' '.join(targets)))
sys.exit(0)