diff options
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 64 |
2 files changed, 67 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 5a28a9dba..2228a0f24 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -675,9 +675,11 @@ let {{ clrexIop = InstObjParams("clrex", "Clrex","PredOp", { "code": clrexCode, "predicate_test": predicateTest },[]) - header_output += BasicDeclare.subst(clrexIop) + header_output += ClrexDeclare.subst(clrexIop) decoder_output += BasicConstructor.subst(clrexIop) exec_output += PredOpExecute.subst(clrexIop) + exec_output += ClrexInitiateAcc.subst(clrexIop) + exec_output += ClrexCompleteAcc.subst(clrexIop) isbCode = ''' ''' diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 87c6e430c..d2224dc6d 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -336,3 +336,67 @@ def template RegImmRegShiftOpConstructor {{ %(constructor)s; } }}; + +def template ClrexDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + + /// Constructor. + %(class_name)s(ExtMachInst machInst); + + %(BasicExecDeclare)s + + %(InitiateAccDeclare)s + + %(CompleteAccDeclare)s + }; +}}; + +def template ClrexInitiateAcc {{ + Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + %(op_decl)s; + %(op_rd)s; + + if (%(predicate_test)s) + { + if (fault == NoFault) { + unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC; + fault = xc->read(0, (uint32_t&)Mem, memAccessFlags); + } + } else { + xc->setPredicate(false); + if (fault == NoFault && machInst.itstateMask != 0) { + xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); + } + } + + return fault; + } +}}; + +def template ClrexCompleteAcc {{ + Fault %(class_name)s::completeAcc(PacketPtr pkt, + %(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + + + if (fault == NoFault && machInst.itstateMask != 0) { + xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate); + } + + return fault; + } +}}; + |