diff options
| -rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 48 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/mem.isa | 21 |
2 files changed, 64 insertions, 5 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index 6b8c925b6..cb4c5c869 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -112,6 +112,42 @@ let {{ emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) + def buildRfeLoad(mnem, post, add, writeback): + name = mnem + Name = "RFE_" + loadImmClassName(post, add, writeback, 8) + + offset = 0 + if post != add: + offset += 4 + if not add: + offset -= 8 + + eaCode = "EA = Base + %d;" % offset + + wbDiff = -8 + if add: + wbDiff = 8 + accCode = ''' + NPC = bits(Mem.ud, 31, 0); + uint32_t newCpsr = cpsrWriteByInstr(Cpsr | CondCodes, + bits(Mem.ud, 63, 32), + 0xF, true); + Cpsr = ~CondCodesMask & newCpsr; + CondCodes = CondCodesMask & newCpsr; + ''' + if writeback: + accCode += "Base = Base + %s;\n" % wbDiff + + global header_output, decoder_output, exec_output + + (newHeader, + newDecoder, + newExec) = RfeBase(name, Name, eaCode, accCode, [], []) + + header_output += newHeader + decoder_output += newDecoder + exec_output += newExec + def buildRegLoad(mnem, post, add, writeback, \ size=4, sign=False, user=False, prefetch=False): name = mnem @@ -233,6 +269,16 @@ let {{ buildDoubleImmLoad(mnem, False, False, False) buildDoubleRegLoad(mnem, False, False, False) + def buildRfeLoads(mnem): + buildRfeLoad(mnem, True, True, True) + buildRfeLoad(mnem, True, True, False) + buildRfeLoad(mnem, True, False, True) + buildRfeLoad(mnem, True, False, False) + buildRfeLoad(mnem, False, True, True) + buildRfeLoad(mnem, False, True, False) + buildRfeLoad(mnem, False, False, True) + buildRfeLoad(mnem, False, False, False) + def buildPrefetches(mnem): buildRegLoad(mnem, False, False, False, size=1, prefetch=True) buildImmLoad(mnem, False, False, False, size=1, prefetch=True) @@ -252,6 +298,8 @@ let {{ buildDoubleLoads("ldrd") + buildRfeLoads("rfe") + buildPrefetches("pld") buildPrefetches("pldw") buildPrefetches("pli") diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index dc447cf8b..7f893bbed 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -38,7 +38,7 @@ // Authors: Gabe Black let {{ - def loadStoreBaseWork(name, Name, imm, swp, codeBlobs, memFlags, + def loadStoreBaseWork(name, Name, imm, swp, rfe, codeBlobs, memFlags, instFlags, double, base = 'Memory', execTemplateBase = ''): # Make sure flags are in lists (convert to lists if not). @@ -66,6 +66,9 @@ let {{ if swp: declareTemplate = SwapDeclare constructTemplate = SwapConstructor + elif rfe: + declareTemplate = RfeDeclare + constructTemplate = RfeConstructor elif imm: if double: declareTemplate = LoadStoreDImmDeclare @@ -94,8 +97,16 @@ let {{ codeBlobs = { "ea_code": eaCode, "memacc_code": accCode, "predicate_test": predicateTest } - return loadStoreBaseWork(name, Name, imm, False, codeBlobs, memFlags, - instFlags, double, base, execTemplateBase) + return loadStoreBaseWork(name, Name, imm, False, False, codeBlobs, + memFlags, instFlags, double, base, + execTemplateBase) + + def RfeBase(name, Name, eaCode, accCode, memFlags, instFlags): + codeBlobs = { "ea_code": eaCode, + "memacc_code": accCode, + "predicate_test": predicateTest } + return loadStoreBaseWork(name, Name, False, False, True, codeBlobs, + memFlags, instFlags, False, 'RfeOp', 'Load') def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags, instFlags): @@ -103,8 +114,8 @@ let {{ "preacc_code": preAccCode, "postacc_code": postAccCode, "predicate_test": predicateTest } - return loadStoreBaseWork(name, Name, False, True, codeBlobs, memFlags, - instFlags, False, 'Swap', 'Swap') + return loadStoreBaseWork(name, Name, False, True, False, codeBlobs, + memFlags, instFlags, False, 'Swap', 'Swap') def memClassName(base, post, add, writeback, \ size=4, sign=False, user=False): |