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-rw-r--r--src/cpu/memtest/memtest.cc10
-rw-r--r--src/cpu/memtest/memtest.hh4
-rw-r--r--src/cpu/o3/fetch.hh2
-rw-r--r--src/cpu/o3/fetch_impl.hh9
-rw-r--r--src/cpu/o3/lsq.hh2
-rw-r--r--src/cpu/o3/lsq_impl.hh10
-rw-r--r--src/cpu/simple/atomic.cc10
-rw-r--r--src/cpu/simple/atomic.hh2
-rw-r--r--src/cpu/simple/timing.cc11
-rw-r--r--src/cpu/simple/timing.hh4
10 files changed, 56 insertions, 8 deletions
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 91e073cf0..180f41541 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -81,8 +81,13 @@ MemTest::CpuPort::recvFunctional(PacketPtr pkt)
void
MemTest::CpuPort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
+ }
panic("MemTest doesn't expect recvStatusChange callback!");
}
@@ -145,6 +150,9 @@ MemTest::MemTest(const string &name,
// thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
curTick = 0;
+ cachePort.snoopRangeSent = false;
+ funcPort.snoopRangeSent = true;
+
// Needs to be masked off once we know the block size.
traceBlockAddr = _traceAddr;
baseAddr1 = 0x100000;
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 2694efd39..7bf34d827 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -100,6 +100,8 @@ class MemTest : public MemObject
: Port(_name, _memtest), memtest(_memtest)
{ }
+ bool snoopRangeSent;
+
protected:
virtual bool recvTiming(PacketPtr pkt);
@@ -120,6 +122,8 @@ class MemTest : public MemObject
CpuPort cachePort;
CpuPort funcPort;
+ bool snoopRangeSent;
+
class MemTestSenderState : public Packet::SenderState
{
public:
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index cc9a8abf5..04016347a 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -83,6 +83,8 @@ class DefaultFetch
: Port(_fetch->name() + "-iport"), fetch(_fetch)
{ }
+ bool snoopRangeSent;
+
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 25faa407e..63d22b293 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -70,8 +70,13 @@ template<class Impl>
void
DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
+ }
panic("DefaultFetch doesn't expect recvStatusChange callback!");
}
@@ -287,6 +292,8 @@ DefaultFetch<Impl>::setCPU(O3CPU *cpu_ptr)
// Name is finally available, so create the port.
icachePort = new IcachePort(this);
+ icachePort->snoopRangeSent = false;
+
#if USE_CHECKER
if (cpu->checker) {
cpu->checker->setIcachePort(icachePort);
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 6b12d75b4..7559a36d5 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -298,6 +298,8 @@ class LSQ {
: lsq(_lsq)
{ }
+ bool snoopRangeSent;
+
protected:
/** Atomic version of receive. Panics. */
virtual Tick recvAtomic(PacketPtr pkt);
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 5e7945c1c..6758e51c8 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -53,9 +53,13 @@ template <class Impl>
void
LSQ<Impl>::DcachePort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
-
+ }
panic("O3CPU doesn't expect recvStatusChange callback!");
}
@@ -97,6 +101,8 @@ LSQ<Impl>::LSQ(Params *params)
{
DPRINTF(LSQ, "Creating LSQ object.\n");
+ dcachePort.snoopRangeSent = false;
+
//**********************************************/
//************ Handle SMT Parameters ***********/
//**********************************************/
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 58dc1fe5f..9a1f831cd 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -107,8 +107,13 @@ AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
void
AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
+ }
panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
}
@@ -127,6 +132,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
{
_status = Idle;
+ icachePort.snoopRangeSent = false;
+ dcachePort.snoopRangeSent = false;
+
ifetch_req = new Request();
ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 166a18127..0df6fe079 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -90,6 +90,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
: Port(_name, _cpu), cpu(_cpu)
{ }
+ bool snoopRangeSent;
+
protected:
virtual bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index db2c940c0..1ea2df894 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -82,8 +82,13 @@ TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
void
TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
{
- if (status == RangeChange)
+ if (status == RangeChange) {
+ if (!snoopRangeSent) {
+ snoopRangeSent = true;
+ sendStatusChange(Port::RangeChange);
+ }
return;
+ }
panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
}
@@ -101,6 +106,10 @@ TimingSimpleCPU::TimingSimpleCPU(Params *p)
cpu_id(p->cpu_id)
{
_status = Idle;
+
+ icachePort.snoopRangeSent = false;
+ dcachePort.snoopRangeSent = false;
+
ifetch_pkt = dcache_pkt = NULL;
drainEvent = NULL;
fetchEvent = NULL;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 408fa315e..fe5d03666 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -82,6 +82,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
: Port(_name, _cpu), cpu(_cpu), lat(_lat)
{ }
+ bool snoopRangeSent;
+
protected:
virtual Tick recvAtomic(PacketPtr pkt);
@@ -166,8 +168,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
PacketPtr ifetch_pkt;
PacketPtr dcache_pkt;
-
-
int cpu_id;
Tick previousTick;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 23:40:05 +0000