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-rw-r--r--arch/alpha/isa/decoder.isa2
-rw-r--r--dev/ide_ctrl.cc53
-rw-r--r--dev/ide_disk.hh2
-rw-r--r--dev/sinic.cc299
-rw-r--r--dev/sinic.hh16
-rw-r--r--dev/sinicreg.hh62
-rw-r--r--python/m5/objects/Ethernet.py10
-rw-r--r--sim/serialize.cc12
-rw-r--r--sim/serialize.hh5
-rw-r--r--util/stats/barchart.py8
10 files changed, 359 insertions, 110 deletions
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index ac9f9fc4c..b79286162 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -814,7 +814,7 @@ decode OPCODE default Unknown::unknown() {
AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
- panic("M5 panic instruction called.");
+ panic("M5 panic instruction called at pc=%#x.", xc->readPC());
}}, IsNonSpeculative);
}
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 56682a224..05c756f04 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -280,12 +280,28 @@ IdeController::readConfig(int offset, int size, uint8_t *data)
panic("Invalid PCI configuration read size!\n");
}
- DPRINTF(IdeCtrl, "PCI read offset: %#x size: %#x data: %#x\n",
- offset, size, *(uint32_t*)data);
+
} else {
panic("Read of unimplemented PCI config. register: %x\n", offset);
}
+ switch (size) {
+ case sizeof(uint8_t):
+ DPRINTF(IdeCtrl, "PCI read offset: %#x size: %d data: %#x\n",
+ offset, size, (uint32_t)*data);
+ break;
+ case sizeof(uint16_t):
+ DPRINTF(IdeCtrl, "PCI read offset: %#x size: %d data: %#x\n",
+ offset, size, *(uint16_t*)data);
+ break;
+ case sizeof(uint32_t):
+ DPRINTF(IdeCtrl, "PCI read offset: %#x size: %d data: %#x\n",
+ offset, size, *(uint32_t*)data);
+ break;
+ default:
+ panic("Invalid PCI configuration read size!\n");
+ }
+
}
void
@@ -317,8 +333,22 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data)
panic("Write of unimplemented PCI config. register: %x\n", offset);
}
- DPRINTF(IdeCtrl, "PCI write offset: %#x size: %#x data: %#x\n",
- offset, size, data);
+ switch(size) {
+ case sizeof(uint8_t):
+ DPRINTF(IdeCtrl, "PCI write offset: %#x size: %d data: %#x\n",
+ offset, size, (uint32_t)*data);
+ break;
+ case sizeof(uint16_t):
+ DPRINTF(IdeCtrl, "PCI write offset: %#x size: %d data: %#x\n",
+ offset, size, *(uint16_t*)data);
+ break;
+ case sizeof(uint32_t):
+ DPRINTF(IdeCtrl, "PCI write offset: %#x size: %d data: %#x\n",
+ offset, size, *(uint32_t*)data);
+ break;
+ default:
+ panic("Invalid PCI configuration write size!\n");
+ }
// Catch the writes to specific PCI registers that have side affects
// (like updating the PIO ranges)
@@ -455,6 +485,13 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
panic("IDE controller read of unknown register block type!\n");
}
+ if (req->size == 1)
+ DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
+ offset, req->size, (uint32_t)*data);
+ else if (req->size == 2)
+ DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
+ offset, req->size, *(uint16_t*)data);
+ else
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
@@ -624,7 +661,13 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
default:
panic("IDE controller write of unknown register block type!\n");
}
-
+ if (req->size == 1)
+ DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
+ offset, req->size, (uint32_t)*data);
+ else if (req->size == 2)
+ DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
+ offset, req->size, *(uint16_t*)data);
+ else
DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh
index f743e7a45..402ae44ee 100644
--- a/dev/ide_disk.hh
+++ b/dev/ide_disk.hh
@@ -43,7 +43,7 @@
#define DMA_BACKOFF_PERIOD 200
-#define MAX_DMA_SIZE (65536) // 64K
+#define MAX_DMA_SIZE (131072) // 128K
#define MAX_MULTSECT (128)
#define PRD_BASE_MASK 0xfffffffe
diff --git a/dev/sinic.cc b/dev/sinic.cc
index 363994919..0853717ba 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -85,7 +85,8 @@ Base::Base(Params *p)
}
Device::Device(Params *p)
- : Base(p), plat(p->plat), physmem(p->physmem),
+ : Base(p), plat(p->plat), physmem(p->physmem), rxUnique(0), txUnique(0),
+ virtualRegs(p->virtual_count < 1 ? 1 : p->virtual_count),
rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
rxKickTick(0), txKickTick(0),
txEvent(this), rxDmaEvent(this), txDmaEvent(this),
@@ -315,12 +316,9 @@ void
Device::prepareIO(int cpu, int index)
{
int size = virtualRegs.size();
- if (index < size)
- return;
-
- virtualRegs.resize(index + 1);
- for (int i = size; i <= index; ++i)
- virtualRegs[i].rxPacket = rxFifo.end();
+ if (index > size)
+ panic("Trying to access a vnic that doesn't exist %d > %d\n",
+ index, size);
}
void
@@ -333,7 +331,10 @@ Device::prepareRead(int cpu, int index)
// update rx registers
uint64_t rxdone = vnic.RxDone;
- rxdone = set_RxDone_Packets(rxdone, rxFifo.packets());
+ rxdone = set_RxDone_Packets(rxdone, rxFifo.countPacketsAfter(rxFifoPtr));
+ rxdone = set_RxDone_Empty(rxdone, rxFifo.empty());
+ rxdone = set_RxDone_High(rxdone, rxFifo.size() > regs.RxFifoMark);
+ rxdone = set_RxDone_NotHigh(rxdone, rxLow);
regs.RxData = vnic.RxData;
regs.RxDone = rxdone;
regs.RxWait = rxdone;
@@ -363,7 +364,7 @@ Device::read(MemReqPtr &req, uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = readBar(req, data);
- if (fault->isMachineCheckFault()) {
+ if (fault && fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
@@ -381,17 +382,19 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
Addr raddr = daddr & Regs::VirtualMask;
if (!regValid(raddr))
- panic("invalid register: cpu=%d, da=%#x pa=%#x va=%#x size=%d",
- cpu, daddr, req->paddr, req->vaddr, req->size);
+ panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
+ cpu, index, daddr, req->paddr, req->vaddr, req->size);
const Regs::Info &info = regInfo(raddr);
if (!info.read)
- panic("reading %s (write only): cpu=%d da=%#x pa=%#x va=%#x size=%d",
- info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
+ panic("read %s (write only): "
+ "cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
+ info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size);
if (req->size != info.size)
- panic("invalid size for reg %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
- info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
+ panic("read %s (invalid size): "
+ "cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
+ info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size);
prepareRead(cpu, index);
@@ -409,8 +412,9 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
}
DPRINTF(EthernetPIO,
- "read %s cpu=%d da=%#x pa=%#x va=%#x size=%d val=%#x\n",
- info.name, cpu, daddr, req->paddr, req->vaddr, req->size, value);
+ "read %s: cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d val=%#x\n",
+ info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size,
+ value);
// reading the interrupt status register has the side effect of
// clearing it
@@ -459,7 +463,7 @@ Device::write(MemReqPtr &req, const uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = writeBar(req, data);
- if (fault->isMachineCheckFault()) {
+ if (fault && fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
@@ -482,21 +486,23 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
const Regs::Info &info = regInfo(raddr);
if (!info.write)
- panic("writing %s (read only): cpu=%d da=%#x",
- info.name, cpu, daddr);
+ panic("write %s (read only): "
+ "cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
+ info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size);
if (req->size != info.size)
- panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
- info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
+ panic("write %s (invalid size): "
+ "cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
+ info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size);
uint32_t reg32 = *(uint32_t *)data;
uint64_t reg64 = *(uint64_t *)data;
VirtualReg &vnic = virtualRegs[index];
DPRINTF(EthernetPIO,
- "write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
- info.name, cpu, info.size == 4 ? reg32 : reg64,
- daddr, req->paddr, req->vaddr, req->size);
+ "write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
+ info.name, index, cpu, info.size == 4 ? reg32 : reg64, daddr,
+ req->paddr, req->vaddr, req->size);
prepareWrite(cpu, index);
@@ -522,10 +528,32 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
panic("receive machine busy with another request! rxState=%s",
RxStateStrings[rxState]);
+ vnic.rxUnique = rxUnique++;
vnic.RxDone = Regs::RxDone_Busy;
vnic.RxData = reg64;
- rxList.push_back(index);
- if (rxEnable && rxState == rxIdle) {
+
+ if (Regs::get_RxData_Vaddr(reg64)) {
+ Addr vaddr = Regs::get_RxData_Addr(reg64);
+ Addr paddr = vtophys(req->xc, vaddr);
+ DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d): "
+ "vaddr=%#x, paddr=%#x\n",
+ index, vnic.rxUnique, vaddr, paddr);
+
+ vnic.RxData = Regs::set_RxData_Addr(vnic.RxData, paddr);
+ } else {
+ DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d)\n",
+ index, vnic.rxUnique);
+ }
+
+ if (vnic.rxPacket == rxFifo.end()) {
+ DPRINTF(EthernetPIO, "request new packet...appending to rxList\n");
+ rxList.push_back(index);
+ } else {
+ DPRINTF(EthernetPIO, "packet exists...appending to rxBusy\n");
+ rxBusy.push_back(index);
+ }
+
+ if (rxEnable && (rxState == rxIdle || rxState == rxFifoBlock)) {
rxState = rxFifoBlock;
rxKick();
}
@@ -536,8 +564,23 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
panic("transmit machine busy with another request! txState=%s",
TxStateStrings[txState]);
+ vnic.txUnique = txUnique++;
vnic.TxDone = Regs::TxDone_Busy;
vnic.TxData = reg64;
+
+ if (Regs::get_TxData_Vaddr(reg64)) {
+ Addr vaddr = Regs::get_TxData_Addr(reg64);
+ Addr paddr = vtophys(req->xc, vaddr);
+ DPRINTF(EthernetPIO, "write TxData vnic %d (rxunique %d): "
+ "vaddr=%#x, paddr=%#x\n",
+ index, vnic.txUnique, vaddr, paddr);
+
+ vnic.TxData = Regs::set_TxData_Addr(vnic.TxData, paddr);
+ } else {
+ DPRINTF(EthernetPIO, "write TxData vnic %d (rxunique %d)\n",
+ index, vnic.txUnique);
+ }
+
if (txList.empty() || txList.front() != index)
txList.push_back(index);
if (txEnable && txState == txIdle && txList.front() == index) {
@@ -763,10 +806,21 @@ Device::reset()
regs.Config |= Config_TxThread;
if (params()->rss)
regs.Config |= Config_RSS;
+ if (params()->zero_copy)
+ regs.Config |= Config_ZeroCopy;
+ if (params()->delay_copy)
+ regs.Config |= Config_DelayCopy;
+ if (params()->virtual_addr)
+ regs.Config |= Config_Vaddr;
+
+ if (params()->delay_copy && params()->zero_copy)
+ panic("Can't delay copy and zero copy");
+
regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow;
regs.RxMaxCopy = params()->rx_max_copy;
regs.TxMaxCopy = params()->tx_max_copy;
regs.RxMaxIntr = params()->rx_max_intr;
+ regs.VirtualCount = params()->virtual_count;
regs.RxFifoSize = params()->rx_fifo_size;
regs.TxFifoSize = params()->tx_fifo_size;
regs.RxFifoMark = params()->rx_fifo_threshold;
@@ -774,6 +828,8 @@ Device::reset()
regs.HwAddr = params()->eaddr;
rxList.clear();
+ rxBusy.clear();
+ rxActive = -1;
txList.clear();
rxState = rxIdle;
@@ -783,6 +839,7 @@ Device::reset()
rxFifoPtr = rxFifo.end();
txFifo.clear();
rxEmpty = false;
+ rxLow = true;
txFull = false;
int size = virtualRegs.size();
@@ -797,8 +854,10 @@ Device::rxDmaCopy()
{
assert(rxState == rxCopy);
rxState = rxCopyDone;
+ DPRINTF(EthernetDMA, "begin rx dma write paddr=%#x len=%d\n",
+ rxDmaAddr, rxDmaLen);
physmem->dma_write(rxDmaAddr, (uint8_t *)rxDmaData, rxDmaLen);
- DPRINTF(EthernetDMA, "rx dma write paddr=%#x len=%d\n",
+ DPRINTF(EthernetDMA, "end rx dma write paddr=%#x len=%d\n",
rxDmaAddr, rxDmaLen);
DDUMP(EthernetData, rxDmaData, rxDmaLen);
}
@@ -818,13 +877,13 @@ Device::rxDmaDone()
void
Device::rxKick()
{
- VirtualReg *vnic;
+ VirtualReg *vnic = NULL;
- DPRINTF(EthernetSM, "receive kick rxState=%s (rxFifo.size=%d)\n",
+ DPRINTF(EthernetSM, "rxKick: rxState=%s (rxFifo.size=%d)\n",
RxStateStrings[rxState], rxFifo.size());
if (rxKickTick > curTick) {
- DPRINTF(EthernetSM, "receive kick exiting, can't run till %d\n",
+ DPRINTF(EthernetSM, "rxKick: exiting, can't run till %d\n",
rxKickTick);
return;
}
@@ -833,16 +892,50 @@ Device::rxKick()
if (rxState == rxIdle)
goto exit;
- assert(!rxList.empty());
- vnic = &virtualRegs[rxList.front()];
+ if (rxActive == -1) {
+ if (rxState != rxFifoBlock)
+ panic("no active vnic while in state %s", RxStateStrings[rxState]);
- DPRINTF(EthernetSM, "processing rxState=%s for virtual nic %d\n",
- RxStateStrings[rxState], rxList.front());
+ DPRINTF(EthernetSM, "processing rxState=%s\n",
+ RxStateStrings[rxState]);
+ } else {
+ vnic = &virtualRegs[rxActive];
+ DPRINTF(EthernetSM,
+ "processing rxState=%s for vnic %d (rxunique %d)\n",
+ RxStateStrings[rxState], rxActive, vnic->rxUnique);
+ }
switch (rxState) {
case rxFifoBlock:
- if (vnic->rxPacket != rxFifo.end()) {
+ if (DTRACE(EthernetSM)) {
+ PacketFifo::iterator end = rxFifo.end();
+ int size = virtualRegs.size();
+ for (int i = 0; i < size; ++i) {
+ VirtualReg *vn = &virtualRegs[i];
+ if (vn->rxPacket != end &&
+ !Regs::get_RxDone_Busy(vn->RxDone)) {
+ DPRINTF(EthernetSM,
+ "vnic %d (rxunique %d), has outstanding packet %d\n",
+ i, vn->rxUnique,
+ rxFifo.countPacketsBefore(vn->rxPacket));
+ }
+ }
+ }
+
+ if (!rxBusy.empty()) {
+ rxActive = rxBusy.front();
+ rxBusy.pop_front();
+ vnic = &virtualRegs[rxActive];
+
+ if (vnic->rxPacket == rxFifo.end())
+ panic("continuing vnic without packet\n");
+
+ DPRINTF(EthernetSM,
+ "continue processing for vnic %d (rxunique %d)\n",
+ rxActive, vnic->rxUnique);
+
rxState = rxBeginCopy;
+
break;
}
@@ -851,8 +944,19 @@ Device::rxKick()
goto exit;
}
+ if (rxList.empty())
+ panic("Not idle, but nothing to do!");
+
assert(!rxFifo.empty());
+ rxActive = rxList.front();
+ rxList.pop_front();
+ vnic = &virtualRegs[rxActive];
+
+ DPRINTF(EthernetSM,
+ "processing new packet for vnic %d (rxunique %d)\n",
+ rxActive, vnic->rxUnique);
+
// Grab a new packet from the fifo.
vnic->rxPacket = rxFifoPtr++;
vnic->rxPacketOffset = 0;
@@ -863,6 +967,7 @@ Device::rxKick()
/* scope for variables */ {
IpPtr ip(*vnic->rxPacket);
if (ip) {
+ DPRINTF(Ethernet, "ID is %d\n", ip->id());
vnic->rxDoneData |= Regs::RxDone_IpPacket;
rxIpChecksums++;
if (cksum(ip) != 0) {
@@ -872,6 +977,10 @@ Device::rxKick()
TcpPtr tcp(ip);
UdpPtr udp(ip);
if (tcp) {
+ DPRINTF(Ethernet,
+ "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
+ tcp->sport(), tcp->dport(), tcp->seq(),
+ tcp->ack());
vnic->rxDoneData |= Regs::RxDone_TcpPacket;
rxTcpChecksums++;
if (cksum(tcp) != 0) {
@@ -901,6 +1010,11 @@ Device::rxKick()
rxDmaData = (*vnic->rxPacket)->data + vnic->rxPacketOffset;
rxState = rxCopy;
+ if (rxDmaAddr == 1LL) {
+ rxState = rxCopyDone;
+ break;
+ }
+
if (dmaInterface) {
dmaInterface->doDMA(WriteInvalidate, rxDmaAddr, rxDmaLen,
curTick, &rxDmaEvent, true);
@@ -922,31 +1036,44 @@ Device::rxKick()
goto exit;
case rxCopyDone:
- vnic->RxDone = vnic->rxDoneData | rxDmaLen;
+ vnic->RxDone = vnic->rxDoneData;
vnic->RxDone |= Regs::RxDone_Complete;
if (vnic->rxPacketBytes == rxDmaLen) {
- DPRINTF(EthernetSM, "rxKick: packet complete on vnic %d\n",
- rxList.front());
+ // Packet is complete. Indicate how many bytes were copied
+ vnic->RxDone = Regs::set_RxDone_CopyLen(vnic->RxDone, rxDmaLen);
+
+ DPRINTF(EthernetSM,
+ "rxKick: packet complete on vnic %d (rxunique %d)\n",
+ rxActive, vnic->rxUnique);
rxFifo.remove(vnic->rxPacket);
vnic->rxPacket = rxFifo.end();
} else {
- vnic->RxDone |= Regs::RxDone_More;
vnic->rxPacketBytes -= rxDmaLen;
vnic->rxPacketOffset += rxDmaLen;
+ vnic->RxDone |= Regs::RxDone_More;
+ vnic->RxDone = Regs::set_RxDone_CopyLen(vnic->RxDone,
+ vnic->rxPacketBytes);
DPRINTF(EthernetSM,
- "rxKick: packet not complete on vnic %d: %d bytes left\n",
- rxList.front(), vnic->rxPacketBytes);
+ "rxKick: packet not complete on vnic %d (rxunique %d): "
+ "%d bytes left\n",
+ rxActive, vnic->rxUnique, vnic->rxPacketBytes);
}
- rxList.pop_front();
- rxState = rxList.empty() ? rxIdle : rxFifoBlock;
+ rxActive = -1;
+ rxState = rxBusy.empty() && rxList.empty() ? rxIdle : rxFifoBlock;
if (rxFifo.empty()) {
devIntrPost(Regs::Intr_RxEmpty);
rxEmpty = true;
}
+ if (rxFifo.size() < params()->rx_fifo_low_mark)
+ rxLow = true;
+
+ if (rxFifo.size() > params()->rx_fifo_threshold)
+ rxLow = false;
+
devIntrPost(Regs::Intr_RxDMA);
break;
@@ -1014,8 +1141,10 @@ Device::transmit()
DPRINTF(Ethernet, "ID is %d\n", ip->id());
TcpPtr tcp(ip);
if (tcp) {
- DPRINTF(Ethernet, "Src Port=%d, Dest Port=%d\n",
- tcp->sport(), tcp->dport());
+ DPRINTF(Ethernet,
+ "Src Port=%d, Dest Port=%d, Seq=%d, Ack=%d\n",
+ tcp->sport(), tcp->dport(), tcp->seq(),
+ tcp->ack());
}
}
}
@@ -1044,11 +1173,11 @@ void
Device::txKick()
{
VirtualReg *vnic;
- DPRINTF(EthernetSM, "transmit kick txState=%s (txFifo.size=%d)\n",
+ DPRINTF(EthernetSM, "txKick: txState=%s (txFifo.size=%d)\n",
TxStateStrings[txState], txFifo.size());
if (txKickTick > curTick) {
- DPRINTF(EthernetSM, "transmit kick exiting, can't run till %d\n",
+ DPRINTF(EthernetSM, "txKick: exiting, can't run till %d\n",
txKickTick);
return;
}
@@ -1062,7 +1191,7 @@ Device::txKick()
switch (txState) {
case txFifoBlock:
- assert(Regs::get_TxDone_Busy(vnic->TxData));
+ assert(Regs::get_TxDone_Busy(vnic->TxDone));
if (!txPacket) {
// Grab a new packet from the fifo.
txPacket = new PacketData(16384);
@@ -1319,6 +1448,8 @@ Base::unserialize(Checkpoint *cp, const std::string &section)
void
Device::serialize(ostream &os)
{
+ int count;
+
// Serialize the PciDev base class
Base::serialize(os);
@@ -1339,6 +1470,7 @@ Device::serialize(ostream &os)
SERIALIZE_SCALAR(regs.RxMaxCopy);
SERIALIZE_SCALAR(regs.TxMaxCopy);
SERIALIZE_SCALAR(regs.RxMaxIntr);
+ SERIALIZE_SCALAR(regs.VirtualCount);
SERIALIZE_SCALAR(regs.RxData);
SERIALIZE_SCALAR(regs.RxDone);
SERIALIZE_SCALAR(regs.TxData);
@@ -1358,8 +1490,6 @@ Device::serialize(ostream &os)
paramOut(os, reg + ".TxData", vnic->TxData);
paramOut(os, reg + ".TxDone", vnic->TxDone);
- PacketFifo::iterator rxFifoPtr;
-
bool rxPacketExists = vnic->rxPacket != rxFifo.end();
paramOut(os, reg + ".rxPacketExists", rxPacketExists);
if (rxPacketExists) {
@@ -1378,18 +1508,26 @@ Device::serialize(ostream &os)
paramOut(os, reg + ".rxDoneData", vnic->rxDoneData);
}
- VirtualList::iterator i, end;
- int count;
+ int rxFifoPtr = rxFifo.countPacketsBefore(this->rxFifoPtr);
+ SERIALIZE_SCALAR(rxFifoPtr);
- int rxListSize = rxList.size();
- SERIALIZE_SCALAR(rxListSize);
+ SERIALIZE_SCALAR(rxActive);
+
+ VirtualList::iterator i, end;
for (count = 0, i = rxList.begin(), end = rxList.end(); i != end; ++i)
paramOut(os, csprintf("rxList%d", count++), *i);
+ int rxListSize = count;
+ SERIALIZE_SCALAR(rxListSize);
+
+ for (count = 0, i = rxBusy.begin(), end = rxBusy.end(); i != end; ++i)
+ paramOut(os, csprintf("rxBusy%d", count++), *i);
+ int rxBusySize = count;
+ SERIALIZE_SCALAR(rxBusySize);
- int txListSize = txList.size();
- SERIALIZE_SCALAR(txListSize);
for (count = 0, i = txList.begin(), end = txList.end(); i != end; ++i)
paramOut(os, csprintf("txList%d", count++), *i);
+ int txListSize = count;
+ SERIALIZE_SCALAR(txListSize);
/*
* Serialize rx state machine
@@ -1397,6 +1535,7 @@ Device::serialize(ostream &os)
int rxState = this->rxState;
SERIALIZE_SCALAR(rxState);
SERIALIZE_SCALAR(rxEmpty);
+ SERIALIZE_SCALAR(rxLow);
rxFifo.serialize("rxFifo", os);
/*
@@ -1437,11 +1576,14 @@ Device::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(regs.RxMaxCopy);
UNSERIALIZE_SCALAR(regs.TxMaxCopy);
UNSERIALIZE_SCALAR(regs.RxMaxIntr);
+ UNSERIALIZE_SCALAR(regs.VirtualCount);
UNSERIALIZE_SCALAR(regs.RxData);
UNSERIALIZE_SCALAR(regs.RxDone);
UNSERIALIZE_SCALAR(regs.TxData);
UNSERIALIZE_SCALAR(regs.TxDone);
+ UNSERIALIZE_SCALAR(rxActive);
+
int rxListSize;
UNSERIALIZE_SCALAR(rxListSize);
rxList.clear();
@@ -1451,6 +1593,15 @@ Device::unserialize(Checkpoint *cp, const std::string &section)
rxList.push_back(value);
}
+ int rxBusySize;
+ UNSERIALIZE_SCALAR(rxBusySize);
+ rxBusy.clear();
+ for (int i = 0; i < rxBusySize; ++i) {
+ int value;
+ paramIn(cp, section, csprintf("rxBusy%d", i), value);
+ rxBusy.push_back(value);
+ }
+
int txListSize;
UNSERIALIZE_SCALAR(txListSize);
txList.clear();
@@ -1466,9 +1617,16 @@ Device::unserialize(Checkpoint *cp, const std::string &section)
int rxState;
UNSERIALIZE_SCALAR(rxState);
UNSERIALIZE_SCALAR(rxEmpty);
+ UNSERIALIZE_SCALAR(rxLow);
this->rxState = (RxState) rxState;
rxFifo.unserialize("rxFifo", cp, section);
+ int rxFifoPtr;
+ UNSERIALIZE_SCALAR(rxFifoPtr);
+ this->rxFifoPtr = rxFifo.begin();
+ for (int i = 0; i < rxFifoPtr; ++i)
+ ++this->rxFifoPtr;
+
/*
* Unserialize tx state machine
*/
@@ -1506,6 +1664,9 @@ Device::unserialize(Checkpoint *cp, const std::string &section)
paramIn(cp, section, reg + ".TxData", vnic->TxData);
paramIn(cp, section, reg + ".TxDone", vnic->TxDone);
+ vnic->rxUnique = rxUnique++;
+ vnic->txUnique = txUnique++;
+
bool rxPacketExists;
paramIn(cp, section, reg + ".rxPacketExists", rxPacketExists);
if (rxPacketExists) {
@@ -1535,10 +1696,8 @@ Device::unserialize(Checkpoint *cp, const std::string &section)
/*
* re-add addrRanges to bus bridges
*/
- if (pioInterface) {
+ if (pioInterface)
pioInterface->addAddrRange(RangeSize(BARAddrs[0], BARSize[0]));
- pioInterface->addAddrRange(RangeSize(BARAddrs[1], BARSize[1]));
- }
}
Tick
@@ -1620,6 +1779,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<uint32_t> rx_fifo_size;
Param<uint32_t> tx_fifo_size;
Param<uint32_t> rx_fifo_threshold;
+ Param<uint32_t> rx_fifo_low_mark;
+ Param<uint32_t> tx_fifo_high_mark;
Param<uint32_t> tx_fifo_threshold;
Param<bool> rx_filter;
@@ -1627,6 +1788,10 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<bool> rx_thread;
Param<bool> tx_thread;
Param<bool> rss;
+ Param<uint32_t> virtual_count;
+ Param<bool> zero_copy;
+ Param<bool> delay_copy;
+ Param<bool> virtual_addr;
END_DECLARE_SIM_OBJECT_PARAMS(Device)
@@ -1664,13 +1829,19 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
+ INIT_PARAM(rx_fifo_low_mark, "max size in bytes of rxFifo"),
+ INIT_PARAM(tx_fifo_high_mark, "max size in bytes of txFifo"),
INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(rx_thread, ""),
INIT_PARAM(tx_thread, ""),
- INIT_PARAM(rss, "")
+ INIT_PARAM(rss, ""),
+ INIT_PARAM(virtual_count, ""),
+ INIT_PARAM(zero_copy, ""),
+ INIT_PARAM(delay_copy, ""),
+ INIT_PARAM(virtual_addr, "")
END_INIT_SIM_OBJECT_PARAMS(Device)
@@ -1712,6 +1883,8 @@ CREATE_SIM_OBJECT(Device)
params->rx_fifo_size = rx_fifo_size;
params->tx_fifo_size = tx_fifo_size;
params->rx_fifo_threshold = rx_fifo_threshold;
+ params->rx_fifo_low_mark = rx_fifo_low_mark;
+ params->tx_fifo_high_mark = tx_fifo_high_mark;
params->tx_fifo_threshold = tx_fifo_threshold;
params->rx_filter = rx_filter;
@@ -1719,6 +1892,10 @@ CREATE_SIM_OBJECT(Device)
params->rx_thread = rx_thread;
params->tx_thread = tx_thread;
params->rss = rss;
+ params->virtual_count = virtual_count;
+ params->zero_copy = zero_copy;
+ params->delay_copy = delay_copy;
+ params->virtual_addr = virtual_addr;
return new Device(params);
}
diff --git a/dev/sinic.hh b/dev/sinic.hh
index 25172fa45..892b3ab69 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -122,7 +122,7 @@ class Device : public Base
uint32_t RxMaxCopy; // 0x10
uint32_t TxMaxCopy; // 0x14
uint32_t RxMaxIntr; // 0x18
- uint32_t Reserved0; // 0x1c
+ uint32_t VirtualCount; // 0x1c
uint32_t RxFifoSize; // 0x20
uint32_t TxFifoSize; // 0x24
uint32_t RxFifoMark; // 0x28
@@ -147,6 +147,9 @@ class Device : public Base
int rxPacketBytes;
uint64_t rxDoneData;
+ Counter rxUnique;
+ Counter txUnique;
+
VirtualReg()
: RxData(0), RxDone(0), TxData(0), TxDone(0),
rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
@@ -154,8 +157,12 @@ class Device : public Base
};
typedef std::vector<VirtualReg> VirtualRegs;
typedef std::list<int> VirtualList;
+ Counter rxUnique;
+ Counter txUnique;
VirtualRegs virtualRegs;
VirtualList rxList;
+ VirtualList rxBusy;
+ int rxActive;
VirtualList txList;
uint8_t &regData8(Addr daddr) { return *((uint8_t *)&regs + daddr); }
@@ -171,6 +178,7 @@ class Device : public Base
PacketFifo rxFifo;
PacketFifo::iterator rxFifoPtr;
bool rxEmpty;
+ bool rxLow;
Addr rxDmaAddr;
uint8_t *rxDmaData;
int rxDmaLen;
@@ -347,6 +355,8 @@ class Device : public Base
uint32_t rx_fifo_size;
uint32_t tx_fifo_size;
uint32_t rx_fifo_threshold;
+ uint32_t rx_fifo_low_mark;
+ uint32_t tx_fifo_high_mark;
uint32_t tx_fifo_threshold;
Tick dma_read_delay;
Tick dma_read_factor;
@@ -356,6 +366,10 @@ class Device : public Base
bool rx_thread;
bool tx_thread;
bool rss;
+ uint32_t virtual_count;
+ bool zero_copy;
+ bool delay_copy;
+ bool virtual_addr;
};
protected:
diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh
index f90432398..d41eb5b16 100644
--- a/dev/sinicreg.hh
+++ b/dev/sinicreg.hh
@@ -55,38 +55,40 @@
namespace Sinic {
namespace Regs {
-static const int VirtualMask = 0xff;
static const int VirtualShift = 8;
+static const int VirtualMask = 0xff;
// Registers
-__SINIC_REG32(Config, 0x00); // 32: configuration register
-__SINIC_REG32(Command, 0x04); // 32: command register
-__SINIC_REG32(IntrStatus, 0x08); // 32: interrupt status
-__SINIC_REG32(IntrMask, 0x0c); // 32: interrupt mask
-__SINIC_REG32(RxMaxCopy, 0x10); // 32: max bytes per rx copy
-__SINIC_REG32(TxMaxCopy, 0x14); // 32: max bytes per tx copy
-__SINIC_REG32(RxMaxIntr, 0x18); // 32: max receives per interrupt
-__SINIC_REG32(Reserved0, 0x1c); // 32: reserved
-__SINIC_REG32(RxFifoSize, 0x20); // 32: rx fifo capacity in bytes
-__SINIC_REG32(TxFifoSize, 0x24); // 32: tx fifo capacity in bytes
-__SINIC_REG32(RxFifoMark, 0x28); // 32: rx fifo high watermark
-__SINIC_REG32(TxFifoMark, 0x2c); // 32: tx fifo low watermark
-__SINIC_REG32(RxData, 0x30); // 64: receive data
-__SINIC_REG32(RxDone, 0x38); // 64: receive done
-__SINIC_REG32(RxWait, 0x40); // 64: receive done (busy wait)
-__SINIC_REG32(TxData, 0x48); // 64: transmit data
-__SINIC_REG32(TxDone, 0x50); // 64: transmit done
-__SINIC_REG32(TxWait, 0x58); // 64: transmit done (busy wait)
-__SINIC_REG32(HwAddr, 0x60); // 64: mac address
-__SINIC_REG32(Size, 0x68); // register addres space size
+__SINIC_REG32(Config, 0x00); // 32: configuration register
+__SINIC_REG32(Command, 0x04); // 32: command register
+__SINIC_REG32(IntrStatus, 0x08); // 32: interrupt status
+__SINIC_REG32(IntrMask, 0x0c); // 32: interrupt mask
+__SINIC_REG32(RxMaxCopy, 0x10); // 32: max bytes per rx copy
+__SINIC_REG32(TxMaxCopy, 0x14); // 32: max bytes per tx copy
+__SINIC_REG32(RxMaxIntr, 0x18); // 32: max receives per interrupt
+__SINIC_REG32(VirtualCount, 0x1c); // 32: number of virutal NICs
+__SINIC_REG32(RxFifoSize, 0x20); // 32: rx fifo capacity in bytes
+__SINIC_REG32(TxFifoSize, 0x24); // 32: tx fifo capacity in bytes
+__SINIC_REG32(RxFifoMark, 0x28); // 32: rx fifo high watermark
+__SINIC_REG32(TxFifoMark, 0x2c); // 32: tx fifo low watermark
+__SINIC_REG32(RxData, 0x30); // 64: receive data
+__SINIC_REG32(RxDone, 0x38); // 64: receive done
+__SINIC_REG32(RxWait, 0x40); // 64: receive done (busy wait)
+__SINIC_REG32(TxData, 0x48); // 64: transmit data
+__SINIC_REG32(TxDone, 0x50); // 64: transmit done
+__SINIC_REG32(TxWait, 0x58); // 64: transmit done (busy wait)
+__SINIC_REG32(HwAddr, 0x60); // 64: mac address
+__SINIC_REG32(Size, 0x68); // register addres space size
// Config register bits
+__SINIC_VAL32(Config_ZeroCopy, 12, 1); // enable zero copy
+__SINIC_VAL32(Config_DelayCopy,11, 1); // enable delayed copy
__SINIC_VAL32(Config_RSS, 10, 1); // enable receive side scaling
__SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads
__SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread
__SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter
__SINIC_VAL32(Config_Vlan, 6, 1); // enable vlan tagging
-__SINIC_VAL32(Config_Virtual, 5, 1); // enable virtual addressing
+__SINIC_VAL32(Config_Vaddr, 5, 1); // enable virtual addressing
__SINIC_VAL32(Config_Desc, 4, 1); // enable tx/rx descriptors
__SINIC_VAL32(Config_Poll, 3, 1); // enable polling
__SINIC_VAL32(Config_IntEn, 2, 1); // enable interrupts
@@ -112,13 +114,15 @@ __SINIC_REG32(Intr_NoDelay, 0x01cc); // interrupts that aren't coalesced
__SINIC_REG32(Intr_Res, ~0x01ff); // reserved interrupt bits
// RX Data Description
-__SINIC_VAL64(RxData_Len, 40, 20); // 0 - 1M
-__SINIC_VAL64(RxData_Addr, 0, 40); // Address 1TB
+__SINIC_VAL64(RxData_Vaddr, 60, 1); // Addr is virtual
+__SINIC_VAL64(RxData_Len, 40, 20); // 0 - 256k
+__SINIC_VAL64(RxData_Addr, 0, 40); // Address 1TB
// TX Data Description
__SINIC_VAL64(TxData_More, 63, 1); // Packet not complete (will dma more)
__SINIC_VAL64(TxData_Checksum, 62, 1); // do checksum
-__SINIC_VAL64(TxData_Len, 40, 20); // 0 - 1M
+__SINIC_VAL64(TxData_Vaddr, 60, 1); // Addr is virtual
+__SINIC_VAL64(TxData_Len, 40, 20); // 0 - 256k
__SINIC_VAL64(TxData_Addr, 0, 40); // Address 1TB
// RX Done/Busy Information
@@ -126,9 +130,9 @@ __SINIC_VAL64(RxDone_Packets, 32, 16); // number of packets in rx fifo
__SINIC_VAL64(RxDone_Busy, 31, 1); // receive dma busy copying
__SINIC_VAL64(RxDone_Complete, 30, 1); // valid data (packet complete)
__SINIC_VAL64(RxDone_More, 29, 1); // Packet has more data (dma again)
-__SINIC_VAL64(RxDone_Res0, 28, 1); // reserved
-__SINIC_VAL64(RxDone_Res1, 27, 1); // reserved
-__SINIC_VAL64(RxDone_Res2, 26, 1); // reserved
+__SINIC_VAL64(RxDone_Empty, 28, 1); // rx fifo is empty
+__SINIC_VAL64(RxDone_High, 27, 1); // rx fifo is above the watermark
+__SINIC_VAL64(RxDone_NotHigh, 26, 1); // rxfifo never hit the high watermark
__SINIC_VAL64(RxDone_TcpError, 25, 1); // TCP packet error (bad checksum)
__SINIC_VAL64(RxDone_UdpError, 24, 1); // UDP packet error (bad checksum)
__SINIC_VAL64(RxDone_IpError, 23, 1); // IP packet error (bad checksum)
@@ -175,7 +179,7 @@ regInfo(Addr daddr)
{ 4, true, false, "RxMaxCopy" },
{ 4, true, false, "TxMaxCopy" },
{ 4, true, false, "RxMaxIntr" },
- invalid,
+ { 4, true, false, "VirtualCount" },
{ 4, true, false, "RxFifoSize" },
{ 4, true, false, "TxFifoSize" },
{ 4, true, false, "RxFifoMark" },
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index 6113e656f..68b21b404 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -105,8 +105,14 @@ class Sinic(EtherDevBase):
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
- rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
- tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")
+ rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
+ rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
+ tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
+ tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
+ virtual_count = Param.UInt32(1, "Virtualized SINIC")
+ zero_copy = Param.Bool(False, "Zero copy receive")
+ delay_copy = Param.Bool(False, "Delayed copy transmit")
+ virtual_addr = Param.Bool(False, "Virtual addressing")
class SinicInt(EtherInt):
type = 'SinicInt'
diff --git a/sim/serialize.cc b/sim/serialize.cc
index ec7241498..c4ef124bb 100644
--- a/sim/serialize.cc
+++ b/sim/serialize.cc
@@ -51,8 +51,9 @@
using namespace std;
-int Serializable::maxCount = 0;
-int Serializable::count = 0;
+int Serializable::ckptMaxCount = 0;
+int Serializable::ckptCount = 0;
+int Serializable::ckptPrevCount = -1;
void
Serializable::nameOut(ostream &os)
@@ -241,8 +242,11 @@ Serializable::serializeAll()
globals.serialize(outstream);
SimObject::serializeAll(outstream);
- if (maxCount && ++count >= maxCount)
+ assert(Serializable::ckptPrevCount + 1 == Serializable::ckptCount);
+ Serializable::ckptPrevCount++;
+ if (ckptMaxCount && ++ckptCount >= ckptMaxCount)
SimExit(curTick + 1, "Maximum number of checkpoints dropped");
+
}
@@ -352,7 +356,7 @@ SerializeParamContext::checkParams()
if (serialize_cycle > 0)
Checkpoint::setup(serialize_cycle, serialize_period);
- Serializable::maxCount = serialize_count;
+ Serializable::ckptMaxCount = serialize_count;
}
void
diff --git a/sim/serialize.hh b/sim/serialize.hh
index bc82bf9b8..d8f5f8fc5 100644
--- a/sim/serialize.hh
+++ b/sim/serialize.hh
@@ -119,8 +119,9 @@ class Serializable
static Serializable *create(Checkpoint *cp,
const std::string &section);
- static int count;
- static int maxCount;
+ static int ckptCount;
+ static int ckptMaxCount;
+ static int ckptPrevCount;
static void serializeAll();
static void unserializeGlobals(Checkpoint *cp);
};
diff --git a/util/stats/barchart.py b/util/stats/barchart.py
index 5d6dd0ab1..a477d1f3b 100644
--- a/util/stats/barchart.py
+++ b/util/stats/barchart.py
@@ -233,7 +233,7 @@ class BarChart(ChartOptions):
inner_axes.set_yticks(ticks)
inner_axes.set_yticklabels(self.yticks)
elif self.ylim is not None:
- self.inner_axes.set_ylim(self.ylim)
+ inner_axes.set_ylim(self.ylim)
if self.xticks is not None:
outer_axes.set_xticks(arange(cshape[2]) + .5)
@@ -242,9 +242,9 @@ class BarChart(ChartOptions):
if self.xsubticks is not None:
numticks = (cshape[0] + 1) * cshape[2]
inner_axes.set_xticks(arange(numticks) * width + 2 * center)
- self.xsubticks.append('')
- inner_axes.set_xticklabels(self.xsubticks * cshape[2], fontsize=7,
- rotation=90)
+ xsubticks = list(self.xsubticks) + [ '' ]
+ inner_axes.set_xticklabels(xsubticks * cshape[2], fontsize=7,
+ rotation=30)
if self.legend is not None:
if dim == 1:
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 00:58:29 +0000