diff options
| -rw-r--r-- | src/arch/riscv/isa/formats/mem.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index ef5f9527c..2cb2f18b4 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -254,7 +254,7 @@ def template StoreCompleteAcc {{ } }}; -def format Load(memacc_code, ea_code = {{EA = Rs1 + offset;}}, mem_flags=[], +def format Load(memacc_code, ea_code={{EA = Rs1 + offset;}}, mem_flags=[], inst_flags=[]) {{ offset_code = """ offset = IMM12; |