diff options
| -rw-r--r-- | src/arch/alpha/isa/decoder.isa | 6 | ||||
| -rw-r--r-- | src/sim/pseudo_inst.cc | 12 |
2 files changed, 0 insertions, 18 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index be6f574a9..7014d4c22 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -795,12 +795,6 @@ decode OPCODE default Unknown::unknown() { 0x04: quiesceTime({{ R0 = AlphaPseudo::quiesceTime(xc->tcBase()); }}, IsNonSpeculative, IsUnverifiable); - 0x10: ivlb({{ - AlphaPseudo::ivlb(xc->tcBase()); - }}, No_OpClass, IsNonSpeculative); - 0x11: ivle({{ - AlphaPseudo::ivle(xc->tcBase()); - }}, No_OpClass, IsNonSpeculative); 0x20: m5exit_old({{ AlphaPseudo::m5exit_old(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index d913e159b..548d0c167 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -134,18 +134,6 @@ namespace AlphaPseudo } void - ivlb(ThreadContext *tc) - { - if (tc->getKernelStats()) - tc->getKernelStats()->ivlb(); - } - - void - ivle(ThreadContext *tc) - { - } - - void m5exit_old(ThreadContext *tc) { exitSimLoop("m5_exit_old instruction encountered"); |