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-rw-r--r--base/mysql.cc13
-rw-r--r--base/mysql.hh10
-rw-r--r--base/statistics.cc3
-rw-r--r--base/stats/mysql.cc67
-rw-r--r--base/stats/mysql.hh5
-rw-r--r--base/stats/statdb.cc4
-rw-r--r--base/traceflags.py3
-rw-r--r--dev/etherdump.cc15
-rw-r--r--dev/etherdump.hh3
-rw-r--r--dev/etherlink.hh2
-rw-r--r--dev/ns_gige.cc304
-rw-r--r--dev/ns_gige.hh25
-rw-r--r--kern/linux/linux_system.cc12
-rw-r--r--sim/eventq.cc17
-rw-r--r--sim/stat_control.cc8
15 files changed, 304 insertions, 187 deletions
diff --git a/base/mysql.cc b/base/mysql.cc
index 8481e74e2..15e12fdeb 100644
--- a/base/mysql.cc
+++ b/base/mysql.cc
@@ -29,6 +29,7 @@
#include <iostream>
#include "base/mysql.hh"
+#include "base/trace.hh"
using namespace std;
@@ -94,4 +95,16 @@ Connection::close()
mysql_close(&mysql);
}
+bool
+Connection::query(const string &sql)
+{
+ DPRINTF(SQL, "Sending SQL query to server:\n%s", sql);
+ error.clear();
+ if (mysql_real_query(&mysql, sql.c_str(), sql.size()))
+ error.set(mysql_error(&mysql));
+
+ return error;
+}
+
+
/* namespace MySQL */ }
diff --git a/base/mysql.hh b/base/mysql.hh
index 89bec73d0..58a1bf7c2 100644
--- a/base/mysql.hh
+++ b/base/mysql.hh
@@ -177,15 +177,7 @@ class Connection
operator MYSQL *() { return &mysql; }
public:
- bool
- query(const std::string &sql)
- {
- error.clear();
- if (mysql_real_query(&mysql, sql.c_str(), sql.size()))
- error.set(mysql_error(&mysql));
-
- return error;
- }
+ bool query(const std::string &sql);
bool
query(const std::stringstream &sql)
diff --git a/base/statistics.cc b/base/statistics.cc
index 78012bff7..6e3dae1ef 100644
--- a/base/statistics.cc
+++ b/base/statistics.cc
@@ -273,7 +273,8 @@ check()
for (i = Database::stats().begin(); i != end; ++i) {
StatData *data = *i;
assert(data);
- data->check();
+ if (!data->check() || !data->baseCheck())
+ panic("stat check failed for %s\n", data->name);
}
int j = 0;
diff --git a/base/stats/mysql.cc b/base/stats/mysql.cc
index a749b573a..523494743 100644
--- a/base/stats/mysql.cc
+++ b/base/stats/mysql.cc
@@ -486,7 +486,7 @@ MySql::configure()
}
-void
+bool
MySql::configure(const StatData &data, string type)
{
stat.init();
@@ -500,19 +500,25 @@ MySql::configure(const StatData &data, string type)
stat.total = data.flags & total;
stat.pdf = data.flags & pdf;
stat.cdf = data.flags & cdf;
+
+ return stat.print;
}
void
MySql::configure(const ScalarData &data)
{
- configure(data, "SCALAR");
+ if (!configure(data, "SCALAR"))
+ return;
+
insert(data.id, stat.setup());
}
void
MySql::configure(const VectorData &data)
{
- configure(data, "VECTOR");
+ if (!configure(data, "VECTOR"))
+ return;
+
uint16_t statid = stat.setup();
if (!data.subnames.empty()) {
@@ -535,7 +541,9 @@ MySql::configure(const VectorData &data)
void
MySql::configure(const DistData &data)
{
- configure(data, "DIST");
+ if (!configure(data, "DIST"))
+ return;
+
if (!data.data.fancy) {
stat.size = data.data.size;
stat.min = data.data.min;
@@ -548,7 +556,8 @@ MySql::configure(const DistData &data)
void
MySql::configure(const VectorDistData &data)
{
- configure(data, "VECTORDIST");
+ if (!configure(data, "VECTORDIST"))
+ return;
if (!data.data[0].fancy) {
stat.size = data.data[0].size;
@@ -578,7 +587,9 @@ MySql::configure(const VectorDistData &data)
void
MySql::configure(const Vector2dData &data)
{
- configure(data, "VECTOR2D");
+ if (!configure(data, "VECTOR2D"))
+ return;
+
uint16_t statid = stat.setup();
if (!data.subnames.empty()) {
@@ -619,14 +630,21 @@ MySql::configure(const FormulaData &data)
}
void
-MySql::output(const string &bin)
+MySql::output(MainBin *bin)
{
- // set up new bin in database if there is a bin name
- newdata.bin = bin.empty() ? 0 : SetupBin(bin);
+ if (bin) {
+ bin->activate();
+ newdata.bin = SetupBin(bin->name());
+ } else {
+ newdata.bin = 0;
+ }
Database::stat_list_t::const_iterator i, end = Database::stats().end();
- for (i = Database::stats().begin(); i != end; ++i)
- (*i)->visit(*this);
+ for (i = Database::stats().begin(); i != end; ++i) {
+ StatData *stat = *i;
+ if (bin && stat->binned() || !bin && !stat->binned())
+ stat->visit(*this);
+ }
}
bool
@@ -647,15 +665,11 @@ MySql::output()
// store sample #
newdata.tick = curTick;
- if (bins().empty()) {
- output(string(""));
- } else {
+ output(NULL);
+ if (!bins().empty()) {
bin_list_t::iterator i, end = bins().end();
- for (i = bins().begin(); i != end; ++i) {
- MainBin *bin = *i;
- bin->activate();
- output(bin->name());
- }
+ for (i = bins().begin(); i != end; ++i)
+ output(*i);
}
newdata.flush();
@@ -664,6 +678,9 @@ MySql::output()
void
MySql::output(const ScalarData &data)
{
+ if (!(data.flags & print))
+ return;
+
newdata.stat = find(data.id);
newdata.x = 0;
newdata.y = 0;
@@ -675,6 +692,9 @@ MySql::output(const ScalarData &data)
void
MySql::output(const VectorData &data)
{
+ if (!(data.flags & print))
+ return;
+
newdata.stat = find(data.id);
newdata.y = 0;
@@ -740,6 +760,9 @@ MySql::output(const DistDataData &data)
void
MySql::output(const DistData &data)
{
+ if (!(data.flags & print))
+ return;
+
newdata.stat = find(data.id);
newdata.y = 0;
output(data.data);
@@ -748,6 +771,9 @@ MySql::output(const DistData &data)
void
MySql::output(const VectorDistData &data)
{
+ if (!(data.flags & print))
+ return;
+
newdata.stat = find(data.id);
int size = data.data.size();
@@ -760,6 +786,9 @@ MySql::output(const VectorDistData &data)
void
MySql::output(const Vector2dData &data)
{
+ if (!(data.flags & print))
+ return;
+
newdata.stat = find(data.id);
int index = 0;
diff --git a/base/stats/mysql.hh b/base/stats/mysql.hh
index fcbe8c5e0..5b6d8a138 100644
--- a/base/stats/mysql.hh
+++ b/base/stats/mysql.hh
@@ -37,6 +37,7 @@
namespace MySQL { class Connection; }
namespace Stats {
+class MainBin;
class DistDataData;
class MySqlRun;
bool MySqlConnected();
@@ -130,7 +131,7 @@ class MySql : public Output
protected:
// Output helper
- void output(const std::string &bin);
+ void output(MainBin *bin);
void output(const DistDataData &data);
void output(const ScalarData &data);
void output(const VectorData &data);
@@ -140,7 +141,7 @@ class MySql : public Output
void output(const FormulaData &data);
void configure();
- void configure(const StatData &data, std::string type);
+ bool configure(const StatData &data, std::string type);
void configure(const ScalarData &data);
void configure(const VectorData &data);
void configure(const DistData &data);
diff --git a/base/stats/statdb.cc b/base/stats/statdb.cc
index eed3d6296..66871b9f7 100644
--- a/base/stats/statdb.cc
+++ b/base/stats/statdb.cc
@@ -51,6 +51,10 @@ find(void *stat)
void
regBin(MainBin *bin, const std::string &_name)
{
+ bin_list_t::iterator i, end = bins().end();
+ for (i = bins().begin(); i != end; ++i)
+ if ((*i)->name() == _name)
+ panic("re-registering bin %s", _name);
bins().push_back(bin);
DPRINTF(Stats, "registering %s\n", _name);
}
diff --git a/base/traceflags.py b/base/traceflags.py
index e073f96c1..4be61d7ee 100644
--- a/base/traceflags.py
+++ b/base/traceflags.py
@@ -121,7 +121,8 @@ baseFlags = [
'IdeDisk',
'Tsunami',
'Uart',
- 'Split'
+ 'Split',
+ 'SQL'
]
#
diff --git a/dev/etherdump.cc b/dev/etherdump.cc
index 54e573be4..27817d456 100644
--- a/dev/etherdump.cc
+++ b/dev/etherdump.cc
@@ -32,6 +32,7 @@
#include <sys/time.h>
+#include <algorithm>
#include <string>
#include "base/misc.hh"
@@ -41,8 +42,8 @@
using std::string;
-EtherDump::EtherDump(const string &name, const string &file)
- : SimObject(name)
+EtherDump::EtherDump(const string &name, const string &file, int max)
+ : SimObject(name), maxlen(max)
{
if (!file.empty())
stream.open(file.c_str());
@@ -113,22 +114,24 @@ EtherDump::dumpPacket(PacketPtr &packet)
pcap_pkthdr pkthdr;
pkthdr.seconds = curtime + (curTick / s_freq);
pkthdr.microseconds = (curTick / us_freq) % ULL(1000000);
- pkthdr.caplen = packet->length;
+ pkthdr.caplen = std::min(packet->length, maxlen);
pkthdr.len = packet->length;
stream.write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));
- stream.write(reinterpret_cast<char *>(packet->data), packet->length);
+ stream.write(reinterpret_cast<char *>(packet->data), pkthdr.caplen);
stream.flush();
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
Param<string> file;
+ Param<int> maxlen;
END_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDump)
- INIT_PARAM(file, "file to dump packets to")
+ INIT_PARAM(file, "file to dump packets to"),
+ INIT_PARAM_DFLT(maxlen, "max portion of packet data to dump", 96)
END_INIT_SIM_OBJECT_PARAMS(EtherDump)
@@ -148,7 +151,7 @@ CREATE_SIM_OBJECT(EtherDump)
}
}
- return new EtherDump(getInstanceName(), filename);
+ return new EtherDump(getInstanceName(), filename, maxlen);
}
REGISTER_SIM_OBJECT("EtherDump", EtherDump)
diff --git a/dev/etherdump.hh b/dev/etherdump.hh
index ef4399e1a..62364359e 100644
--- a/dev/etherdump.hh
+++ b/dev/etherdump.hh
@@ -44,6 +44,7 @@ class EtherDump : public SimObject
{
private:
std::ofstream stream;
+ const int maxlen;
void dumpPacket(PacketPtr &packet);
void init();
@@ -52,7 +53,7 @@ class EtherDump : public SimObject
Tick us_freq;
public:
- EtherDump(const std::string &name, const std::string &file);
+ EtherDump(const std::string &name, const std::string &file, int max);
inline void dump(PacketPtr &pkt) { if (stream.is_open()) dumpPacket(pkt); }
};
diff --git a/dev/etherlink.hh b/dev/etherlink.hh
index 4f227fac5..204348c6d 100644
--- a/dev/etherlink.hh
+++ b/dev/etherlink.hh
@@ -105,7 +105,7 @@ class EtherLink : public SimObject
public:
Interface(const std::string &name, Link *txlink, Link *rxlink);
bool recvPacket(PacketPtr &packet) { return txlink->transmit(packet); }
- void sendDone() { }
+ void sendDone() { peer->sendDone(); }
};
Link *link1;
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 159a4442c..ab539c3c6 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -38,8 +38,10 @@
#include "cpu/exec_context.hh"
#include "cpu/intr_control.hh"
#include "dev/dma.hh"
-#include "dev/ns_gige.hh"
#include "dev/etherlink.hh"
+#include "dev/ns_gige.hh"
+#include "dev/pciconfigall.hh"
+#include "dev/tsunami_cchip.hh"
#include "mem/bus/bus.hh"
#include "mem/bus/dma_interface.hh"
#include "mem/bus/pio_interface.hh"
@@ -50,8 +52,6 @@
#include "sim/host.hh"
#include "sim/sim_stats.hh"
#include "targetarch/vtophys.hh"
-#include "dev/pciconfigall.hh"
-#include "dev/tsunami_cchip.hh"
const char *NsRxStateStrings[] =
{
@@ -86,8 +86,9 @@ const char *NsDmaState[] =
using namespace std;
-//helper function declarations
-//These functions reverse Endianness so we can evaluate network data correctly
+// helper function declarations
+// These functions reverse Endianness so we can evaluate network data
+// correctly
uint16_t reverseEnd16(uint16_t);
uint32_t reverseEnd32(uint32_t);
@@ -304,9 +305,9 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
// Need to catch writes to BARs to update the PIO interface
switch (offset) {
- //seems to work fine without all these PCI settings, but i put in the IO
- //to double check, an assertion will fail if we need to properly
- // implement it
+ // seems to work fine without all these PCI settings, but i
+ // put in the IO to double check, an assertion will fail if we
+ // need to properly implement it
case PCI_COMMAND:
if (config.data[offset] & PCI_CMD_IOSE)
ioEnable = true;
@@ -332,22 +333,20 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
case PCI0_BASE_ADDR0:
if (BARAddrs[0] != 0) {
-
if (pioInterface)
- pioInterface->addAddrRange(BARAddrs[0], BARAddrs[0] + BARSize[0] - 1);
+ pioInterface->addAddrRange(BARAddrs[0],
+ BARAddrs[0] + BARSize[0] - 1);
BARAddrs[0] &= PA_UNCACHED_MASK;
-
}
break;
case PCI0_BASE_ADDR1:
if (BARAddrs[1] != 0) {
-
if (pioInterface)
- pioInterface->addAddrRange(BARAddrs[1], BARAddrs[1] + BARSize[1] - 1);
+ pioInterface->addAddrRange(BARAddrs[1],
+ BARAddrs[1] + BARSize[1] - 1);
BARAddrs[1] &= PA_UNCACHED_MASK;
-
}
break;
}
@@ -368,8 +367,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
daddr, req->paddr, req->vaddr, req->size);
- //there are some reserved registers, you can see ns_gige_reg.h and
- //the spec sheet for details
+ // there are some reserved registers, you can see ns_gige_reg.h and
+ // the spec sheet for details
if (daddr > LAST && daddr <= RESERVED) {
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
@@ -466,10 +465,11 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
reg = regs.pcr;
break;
- //see the spec sheet for how RFCR and RFDR work
- //basically, you write to RFCR to tell the machine what you want to do next
- //then you act upon RFDR, and the device will be prepared b/c
- //of what you wrote to RFCR
+ // see the spec sheet for how RFCR and RFDR work
+ // basically, you write to RFCR to tell the machine
+ // what you want to do next, then you act upon RFDR,
+ // and the device will be prepared b/c of what you
+ // wrote to RFCR
case RFCR:
reg = regs.rfcr;
break;
@@ -490,8 +490,9 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
reg += rom.perfectMatch[4];
break;
default:
- panic("reading from RFDR for something for other than PMATCH!\n");
- //didn't implement other RFDR functionality b/c driver didn't use
+ panic("reading RFDR for something other than PMATCH!\n");
+ // didn't implement other RFDR functionality b/c
+ // driver didn't use it
}
break;
@@ -623,26 +624,34 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
break;
case CFG:
- if (reg & CFG_LNKSTS || reg & CFG_SPDSTS || reg & CFG_DUPSTS
- || reg & CFG_RESERVED || reg & CFG_T64ADDR
- || reg & CFG_PCI64_DET)
+ if (reg & CFG_LNKSTS ||
+ reg & CFG_SPDSTS ||
+ reg & CFG_DUPSTS ||
+ reg & CFG_RESERVED ||
+ reg & CFG_T64ADDR ||
+ reg & CFG_PCI64_DET)
panic("writing to read-only or reserved CFG bits!\n");
- regs.config |= reg & ~(CFG_LNKSTS | CFG_SPDSTS | CFG_DUPSTS | CFG_RESERVED |
- CFG_T64ADDR | CFG_PCI64_DET);
+ regs.config |= reg & ~(CFG_LNKSTS | CFG_SPDSTS | CFG_DUPSTS |
+ CFG_RESERVED | CFG_T64ADDR | CFG_PCI64_DET);
-// all these #if 0's are because i don't THINK the kernel needs to have these implemented
-// if there is a problem relating to one of these, you may need to add functionality in
+// all these #if 0's are because i don't THINK the kernel needs to
+// have these implemented. if there is a problem relating to one of
+// these, you may need to add functionality in.
#if 0
- if (reg & CFG_TBI_EN) ;
- if (reg & CFG_MODE_1000) ;
+ if (reg & CFG_TBI_EN) ;
+ if (reg & CFG_MODE_1000) ;
#endif
if (reg & CFG_AUTO_1000)
panic("CFG_AUTO_1000 not implemented!\n");
#if 0
- if (reg & CFG_PINT_DUPSTS || reg & CFG_PINT_LNKSTS || reg & CFG_PINT_SPDSTS) ;
+ if (reg & CFG_PINT_DUPSTS ||
+ reg & CFG_PINT_LNKSTS ||
+ reg & CFG_PINT_SPDSTS)
+ ;
+
if (reg & CFG_TMRTEST) ;
if (reg & CFG_MRM_DIS) ;
if (reg & CFG_MWI_DIS) ;
@@ -678,11 +687,12 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
case MEAR:
regs.mear = reg;
- /* since phy is completely faked, MEAR_MD* don't matter
- and since the driver never uses MEAR_EE*, they don't matter */
+ // since phy is completely faked, MEAR_MD* don't matter
+ // and since the driver never uses MEAR_EE*, they don't
+ // matter
#if 0
if (reg & MEAR_EEDI) ;
- if (reg & MEAR_EEDO) ; //this one is read only
+ if (reg & MEAR_EEDO) ; // this one is read only
if (reg & MEAR_EECLK) ;
if (reg & MEAR_EESEL) ;
if (reg & MEAR_MDIO) ;
@@ -693,8 +703,8 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
case PTSCR:
regs.ptscr = reg & ~(PTSCR_RBIST_RDONLY);
- /* these control BISTs for various parts of chip - we don't care or do
- just fake that the BIST is done */
+ // these control BISTs for various parts of chip - we
+ // don't care or do just fake that the BIST is done
if (reg & PTSCR_RBIST_EN)
regs.ptscr |= PTSCR_RBIST_DONE;
if (reg & PTSCR_EEBIST_EN)
@@ -737,20 +747,26 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
if (reg & TXCFG_HBI) ;
if (reg & TXCFG_MLB) ;
if (reg & TXCFG_ATP) ;
- if (reg & TXCFG_ECRETRY) ; /* this could easily be implemented, but
- considering the network is just a fake
- pipe, wouldn't make sense to do this */
+ if (reg & TXCFG_ECRETRY) {
+ /*
+ * this could easily be implemented, but considering
+ * the network is just a fake pipe, wouldn't make
+ * sense to do this
+ */
+ }
if (reg & TXCFG_BRST_DIS) ;
#endif
-
+#if 0
/* we handle our own DMA, ignore the kernel's exhortations */
- //if (reg & TXCFG_MXDMA) ;
+ if (reg & TXCFG_MXDMA) ;
+#endif
- //also, we currently don't care about fill/drain thresholds
- //though this may change in the future with more realistic
- //networks or a driver which changes it according to feedback
+ // also, we currently don't care about fill/drain
+ // thresholds though this may change in the future with
+ // more realistic networks or a driver which changes it
+ // according to feedback
break;
@@ -776,12 +792,10 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
if (reg & RXCFG_RX_RD) ;
if (reg & RXCFG_ALP) ;
if (reg & RXCFG_AIRL) ;
-#endif
/* we handle our own DMA, ignore what kernel says about it */
- //if (reg & RXCFG_MXDMA) ;
+ if (reg & RXCFG_MXDMA) ;
-#if 0
//also, we currently don't care about fill/drain thresholds
//though this may change in the future with more realistic
//networks or a driver which changes it according to feedback
@@ -814,8 +828,10 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
acceptPerfect = (reg & RFCR_APM) ? true : false;
acceptArp = (reg & RFCR_AARP) ? true : false;
- if (reg & RFCR_APAT) ;
-// panic("RFCR_APAT not implemented!\n");
+#if 0
+ if (reg & RFCR_APAT)
+ panic("RFCR_APAT not implemented!\n");
+#endif
if (reg & RFCR_MHEN || reg & RFCR_UHEN)
panic("hash filtering not implemented!\n");
@@ -896,11 +912,11 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
break;
default:
- panic("thought i covered all the register, what is this? addr=%#x",
- daddr);
+ panic("invalid register access daddr=%#x", daddr);
}
- } else
+ } else {
panic("Invalid Request Size");
+ }
return No_Fault;
}
@@ -973,7 +989,8 @@ NSGigE::devIntrPost(uint32_t interrupts)
cpuIntrPost(when);
}
- DPRINTF(EthernetIntr, "**interrupt written to ISR: intr=%#x isr=%#x imr=%#x\n",
+ DPRINTF(EthernetIntr,
+ "interrupt written to ISR: intr=%#x isr=%#x imr=%#x\n",
interrupts, regs.isr, regs.imr);
}
@@ -1035,7 +1052,8 @@ NSGigE::devIntrClear(uint32_t interrupts)
if (!(regs.isr & regs.imr))
cpuIntrClear();
- DPRINTF(EthernetIntr, "**interrupt cleared from ISR: intr=%x isr=%x imr=%x\n",
+ DPRINTF(EthernetIntr,
+ "interrupt cleared from ISR: intr=%x isr=%x imr=%x\n",
interrupts, regs.isr, regs.imr);
}
@@ -1053,11 +1071,11 @@ NSGigE::devIntrChangeMask()
void
NSGigE::cpuIntrPost(Tick when)
{
- //If the interrupt you want to post is later than an
- //interrupt already scheduled, just let it post in the coming one and
- //don't schedule another.
- //HOWEVER, must be sure that the scheduled intrTick is in the future
- //(this was formerly the source of a bug)
+ // If the interrupt you want to post is later than an interrupt
+ // already scheduled, just let it post in the coming one and don't
+ // schedule another.
+ // HOWEVER, must be sure that the scheduled intrTick is in the
+ // future (this was formerly the source of a bug)
assert((intrTick >= curTick) || (intrTick == 0));
if (when > intrTick && intrTick != 0)
return;
@@ -1072,7 +1090,8 @@ NSGigE::cpuIntrPost(Tick when)
if (when < curTick) {
cpuInterrupt();
} else {
- DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
+ DPRINTF(EthernetIntr,
+ "going to schedule an interrupt for intrTick=%d\n",
intrTick);
intrEvent = new IntrEvent(this, true);
intrEvent->schedule(intrTick);
@@ -1091,7 +1110,8 @@ NSGigE::cpuInterrupt()
}
// Don't send an interrupt if it's supposed to be delayed
if (intrTick > curTick) {
- DPRINTF(EthernetIntr, "an interrupt is scheduled for %d, wait til then\n",
+ DPRINTF(EthernetIntr,
+ "an interrupt is scheduled for %d, wait til then\n",
intrTick);
return;
}
@@ -1112,13 +1132,14 @@ NSGigE::cpuInterrupt()
void
NSGigE::cpuIntrClear()
{
- if (cpuPendingIntr) {
- cpuPendingIntr = false;
- /** @todo rework the intctrl to be tsunami ok */
- //intctrl->clear(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_ETHERNET);
- DPRINTF(EthernetIntr, "clearing all interrupts from cchip\n");
- tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
- }
+ if (!cpuPendingIntr)
+ return;
+
+ cpuPendingIntr = false;
+ /** @todo rework the intctrl to be tsunami ok */
+ //intctrl->clear(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_ETHERNET);
+ DPRINTF(EthernetIntr, "clearing all interrupts from cchip\n");
+ tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
}
bool
@@ -1311,11 +1332,12 @@ NSGigE::rxKick()
}
// see state machine from spec for details
- // the way this works is, if you finish work on one state and can go directly to
- // another, you do that through jumping to the label "next". however, if you have
- // intermediate work, like DMA so that you can't go to the next state yet, you go to
- // exit and exit the loop. however, when the DMA is done it will trigger an
- // event and come back to this loop.
+ // the way this works is, if you finish work on one state and can
+ // go directly to another, you do that through jumping to the
+ // label "next". however, if you have intermediate work, like DMA
+ // so that you can't go to the next state yet, you go to exit and
+ // exit the loop. however, when the DMA is done it will trigger
+ // an event and come back to this loop.
switch (rxState) {
case rxIdle:
if (!regs.command & CR_RXE) {
@@ -1364,8 +1386,12 @@ NSGigE::rxKick()
goto exit;
DPRINTF(EthernetDesc,
- "rxDescCache:\n\tlink=%08x\n\tbufptr=%08x\n\tcmdsts=%08x\n\textsts=%08x\n"
- ,rxDescCache.link, rxDescCache.bufptr, rxDescCache.cmdsts,
+ "rxDescCache:\n"
+ "\tlink=%08x\n"
+ "\tbufptr=%08x\n"
+ "\tcmdsts=%08x\n"
+ "\textsts=%08x\n",
+ rxDescCache.link, rxDescCache.bufptr, rxDescCache.cmdsts,
rxDescCache.extsts);
if (rxDescCache.cmdsts & CMDSTS_OWN) {
@@ -1420,10 +1446,12 @@ NSGigE::rxKick()
}
- // dont' need the && rxDescCnt > 0 if driver sanity check above holds
+ // dont' need the && rxDescCnt > 0 if driver sanity check
+ // above holds
if (rxPktBytes > 0) {
rxState = rxFragWrite;
- // don't need min<>(rxPktBytes,rxDescCnt) if above sanity check holds
+ // don't need min<>(rxPktBytes,rxDescCnt) if above sanity
+ // check holds
rxXferLen = rxPktBytes;
rxDmaAddr = rxFragPtr & 0x3fffffff;
@@ -1448,11 +1476,13 @@ NSGigE::rxKick()
rxDescCache.cmdsts += rxPacket->length; //i.e. set CMDSTS_SIZE
#if 0
- /* all the driver uses these are for its own stats keeping
- which we don't care about, aren't necessary for functionality
- and doing this would just slow us down. if they end up using
- this in a later version for functional purposes, just undef
- */
+ /*
+ * all the driver uses these are for its own stats keeping
+ * which we don't care about, aren't necessary for
+ * functionality and doing this would just slow us down.
+ * if they end up using this in a later version for
+ * functional purposes, just undef
+ */
if (rxFilterEnable) {
rxDescCache.cmdsts &= ~CMDSTS_DEST_MASK;
if (rxFifo.front()->IsUnicast())
@@ -1489,13 +1519,15 @@ NSGigE::rxKick()
}
rxPacket = 0;
- /* the driver seems to always receive into desc buffers
- of size 1514, so you never have a pkt that is split
- into multiple descriptors on the receive side, so
- i don't implement that case, hence the assert above.
- */
+ /*
+ * the driver seems to always receive into desc buffers
+ * of size 1514, so you never have a pkt that is split
+ * into multiple descriptors on the receive side, so
+ * i don't implement that case, hence the assert above.
+ */
- DPRINTF(EthernetDesc, "rxDesc writeback:\n\tcmdsts=%08x\n\textsts=%08x\n",
+ DPRINTF(EthernetDesc,
+ "rxDesc writeback:\n\tcmdsts=%08x\n\textsts=%08x\n",
rxDescCache.cmdsts, rxDescCache.extsts);
rxDmaAddr = (regs.rxdp + offsetof(ns_desc, cmdsts)) & 0x3fffffff;
@@ -1617,18 +1649,23 @@ NSGigE::transmit()
txFifoAvail += txFifo.front()->length;
- DPRINTF(Ethernet, "Successful Xmit! now txFifoAvail is %d\n", txFifoAvail);
+ DPRINTF(Ethernet, "Successful Xmit! now txFifoAvail is %d\n",
+ txFifoAvail);
txFifo.front() = NULL;
txFifo.pop_front();
- /* normally do a writeback of the descriptor here, and ONLY after that is
- done, send this interrupt. but since our stuff never actually fails,
- just do this interrupt here, otherwise the code has to stray from this
- nice format. besides, it's functionally the same.
- */
+ /*
+ * normally do a writeback of the descriptor here, and ONLY
+ * after that is done, send this interrupt. but since our
+ * stuff never actually fails, just do this interrupt here,
+ * otherwise the code has to stray from this nice format.
+ * besides, it's functionally the same.
+ */
devIntrPost(ISR_TXOK);
- } else
- DPRINTF(Ethernet, "May need to rethink always sending the descriptors back?\n");
+ } else {
+ DPRINTF(Ethernet,
+ "May need to rethink always sending the descriptors back?\n");
+ }
if (!txFifo.empty() && !txEvent.scheduled()) {
DPRINTF(Ethernet, "reschedule transmit\n");
@@ -1815,8 +1852,12 @@ NSGigE::txKick()
goto exit;
DPRINTF(EthernetDesc,
- "txDescCache data:\n\tlink=%08x\n\tbufptr=%08x\n\tcmdsts=%08x\n\textsts=%08x\n"
- ,txDescCache.link, txDescCache.bufptr, txDescCache.cmdsts,
+ "txDescCache data:\n"
+ "\tlink=%08x\n"
+ "\tbufptr=%08x\n"
+ "\tcmdsts=%08x\n"
+ "\textsts=%08x\n",
+ txDescCache.link, txDescCache.bufptr, txDescCache.cmdsts,
txDescCache.extsts);
if (txDescCache.cmdsts & CMDSTS_OWN) {
@@ -1844,7 +1885,8 @@ NSGigE::txKick()
txDescCache.cmdsts &= ~CMDSTS_OWN;
- txDmaAddr = (regs.txdp + offsetof(ns_desc, cmdsts)) & 0x3fffffff;
+ txDmaAddr = regs.txdp + offsetof(ns_desc, cmdsts);
+ txDmaAddr &= 0x3fffffff;
txDmaData = &(txDescCache.cmdsts);
txDmaLen = sizeof(txDescCache.cmdsts);
txDmaFree = dmaDescFree;
@@ -1869,19 +1911,22 @@ NSGigE::txKick()
}
txPacket->length = txPacketBufPtr - txPacket->data;
- /* this is just because the receive can't handle a packet bigger
- want to make sure */
+ // this is just because the receive can't handle a
+ // packet bigger want to make sure
assert(txPacket->length <= 1514);
txFifo.push_back(txPacket);
- /* this following section is not to spec, but functionally shouldn't
- be any different. normally, the chip will wait til the transmit has
- occurred before writing back the descriptor because it has to wait
- to see that it was successfully transmitted to decide whether to set
- CMDSTS_OK or not. however, in the simulator since it is always
- successfully transmitted, and writing it exactly to spec would
- complicate the code, we just do it here
- */
+ /*
+ * this following section is not tqo spec, but
+ * functionally shouldn't be any different. normally,
+ * the chip will wait til the transmit has occurred
+ * before writing back the descriptor because it has
+ * to wait to see that it was successfully transmitted
+ * to decide whether to set CMDSTS_OK or not.
+ * however, in the simulator since it is always
+ * successfully transmitted, and writing it exactly to
+ * spec would complicate the code, we just do it here
+ */
txDescCache.cmdsts &= ~CMDSTS_OWN;
txDescCache.cmdsts |= CMDSTS_OK;
@@ -1890,9 +1935,11 @@ NSGigE::txKick()
"txDesc writeback:\n\tcmdsts=%08x\n\textsts=%08x\n",
txDescCache.cmdsts, txDescCache.extsts);
- txDmaAddr = (regs.txdp + offsetof(ns_desc, cmdsts)) & 0x3fffffff;
+ txDmaAddr = regs.txdp + offsetof(ns_desc, cmdsts);
+ txDmaAddr &= 0x3fffffff;
txDmaData = &(txDescCache.cmdsts);
- txDmaLen = sizeof(txDescCache.cmdsts) + sizeof(txDescCache.extsts);
+ txDmaLen = sizeof(txDescCache.cmdsts) +
+ sizeof(txDescCache.extsts);
txDmaFree = dmaDescFree;
descDmaWrites++;
@@ -1916,10 +1963,12 @@ NSGigE::txKick()
if (txFifoAvail) {
txState = txFragRead;
- /* The number of bytes transferred is either whatever is left
- in the descriptor (txDescCnt), or if there is not enough
- room in the fifo, just whatever room is left in the fifo
- */
+ /*
+ * The number of bytes transferred is either whatever
+ * is left in the descriptor (txDescCnt), or if there
+ * is not enough room in the fifo, just whatever room
+ * is left in the fifo
+ */
txXferLen = min<uint32_t>(txDescCnt, txFifoAvail);
txDmaAddr = txFragPtr & 0x3fffffff;
@@ -2029,8 +2078,8 @@ NSGigE::rxFilter(PacketPtr packet)
drop = false;
// If we make a perfect match
- if ((acceptPerfect)
- && (memcmp(rom.perfectMatch, packet->data, sizeof(rom.perfectMatch)) == 0))
+ if (acceptPerfect &&
+ memcmp(rom.perfectMatch, packet->data, EADDR_LEN) == 0)
drop = false;
eth_header *eth = (eth_header *) packet->data;
@@ -2071,7 +2120,8 @@ NSGigE::recvPacket(PacketPtr packet)
rxBytes += packet->length;
rxPackets++;
- DPRINTF(Ethernet, "\n\nReceiving packet from wire, rxFifoAvail = %d\n", maxRxFifoSize - rxFifoCnt);
+ DPRINTF(Ethernet, "\n\nReceiving packet from wire, rxFifoAvail=%d\n",
+ maxRxFifoSize - rxFifoCnt);
if (rxState == rxIdle) {
DPRINTF(Ethernet, "receive disabled...packet dropped\n");
@@ -2101,8 +2151,9 @@ NSGigE::recvPacket(PacketPtr packet)
}
/**
- * does a udp checksum. if gen is true, then it generates it and puts it in the right place
- * else, it just checks what it calculates against the value in the header in packet
+ * does a udp checksum. if gen is true, then it generates it and puts
+ * it in the right place else, it just checks what it calculates
+ * against the value in the header in packet
*/
bool
NSGigE::udpChecksum(PacketPtr packet, bool gen)
@@ -2142,10 +2193,11 @@ NSGigE::tcpChecksum(PacketPtr packet, bool gen)
pseudo->src_ip_addr = ip->src_ip_addr;
pseudo->dest_ip_addr = ip->dest_ip_addr;
pseudo->protocol = reverseEnd16(ip->protocol);
- pseudo->len = reverseEnd16(reverseEnd16(ip->dgram_len) - (ip->vers_len & 0xf)*4);
+ pseudo->len = reverseEnd16(reverseEnd16(ip->dgram_len) -
+ (ip->vers_len & 0xf)*4);
cksum = checksumCalc((uint16_t *) pseudo, (uint16_t *) hdr,
- (uint32_t) reverseEnd16(pseudo->len));
+ (uint32_t) reverseEnd16(pseudo->len));
} else {
pseudo->src_ip_addr = 0;
pseudo->dest_ip_addr = 0;
@@ -2153,7 +2205,8 @@ NSGigE::tcpChecksum(PacketPtr packet, bool gen)
pseudo->len = 0;
hdr->chksum = 0;
cksum = checksumCalc((uint16_t *) pseudo, (uint16_t *) hdr,
- (uint32_t) (reverseEnd16(ip->dgram_len) - (ip->vers_len & 0xf)*4));
+ (uint32_t) (reverseEnd16(ip->dgram_len) -
+ (ip->vers_len & 0xf)*4));
}
delete pseudo;
@@ -2171,7 +2224,8 @@ NSGigE::ipChecksum(PacketPtr packet, bool gen)
{
ip_header *hdr = packet->getIpHdr();
- uint16_t cksum = checksumCalc(NULL, (uint16_t *) hdr, (hdr->vers_len & 0xf)*4);
+ uint16_t cksum = checksumCalc(NULL, (uint16_t *) hdr,
+ (hdr->vers_len & 0xf)*4);
if (gen) {
DPRINTF(EthernetCksum, "generated checksum: %#x\n", cksum);
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 79ae00e64..c326d0921 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -34,21 +34,15 @@
#ifndef __NS_GIGE_HH__
#define __NS_GIGE_HH__
-//#include "base/range.hh"
+#include "base/statistics.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
-#include "sim/eventq.hh"
+#include "dev/io_device.hh"
#include "dev/ns_gige_reg.h"
-#include "base/statistics.hh"
#include "dev/pcidev.hh"
#include "dev/tsunami.hh"
-#include "dev/io_device.hh"
#include "mem/bus/bus.hh"
-
-/** defined by the NS83820 data sheet */
-//these are now params for the device
-//#define MAX_TX_FIFO_SIZE 8192
-//#define MAX_RX_FIFO_SIZE 32768
+#include "sim/eventq.hh"
/** length of ethernet address in bytes */
#define EADDR_LEN 6
@@ -92,7 +86,10 @@ struct dp_regs {
};
struct dp_rom {
- /** for perfect match memory. the linux driver doesn't use any other ROM */
+ /**
+ * for perfect match memory.
+ * the linux driver doesn't use any other ROM
+ */
uint8_t perfectMatch[EADDR_LEN];
};
@@ -284,7 +281,13 @@ class NSGigE : public PciDev
* Retransmit event
*/
void transmit();
- typedef EventWrapper<NSGigE, &NSGigE::transmit> TxEvent;
+ void txEventTransmit()
+ {
+ transmit();
+ if (txState == txFifoBlock)
+ txKick();
+ }
+ typedef EventWrapper<NSGigE, &NSGigE::txEventTransmit> TxEvent;
friend class TxEvent;
TxEvent txEvent;
diff --git a/kern/linux/linux_system.cc b/kern/linux/linux_system.cc
index 70f5fb783..ab1355637 100644
--- a/kern/linux/linux_system.cc
+++ b/kern/linux/linux_system.cc
@@ -28,10 +28,10 @@
/**
* @file
- * linux_system.cc loads the linux kernel, console, pal and patches certain functions.
- * The symbol tables are loaded so that traces can show the executing function and we can
- * skip functions. Various delay loops are skipped and their final values manually computed to
- * speed up boot time.
+ * loads the linux kernel, console, pal and patches certain functions.
+ * The symbol tables are loaded so that traces can show the executing
+ * function and we can skip functions. Various delay loops are skipped
+ * and their final values manually computed to speed up boot time.
*/
#include "base/loader/aout_object.hh"
@@ -121,13 +121,13 @@ LinuxSystem::LinuxSystem(const string _name, const uint64_t _init_param,
#endif
skipIdeDelay50msEvent = new SkipFuncEvent(&pcEventQueue,
- "ide_delay_50ms");
+ "ide_delay_50ms");
skipDelayLoopEvent = new LinuxSkipDelayLoopEvent(&pcEventQueue,
"calibrate_delay");
skipCacheProbeEvent = new SkipFuncEvent(&pcEventQueue,
- "determine_cpu_caches");
+ "determine_cpu_caches");
Addr addr = 0;
diff --git a/sim/eventq.cc b/sim/eventq.cc
index 6b4ccc827..f975c5e97 100644
--- a/sim/eventq.cc
+++ b/sim/eventq.cc
@@ -208,6 +208,13 @@ EventQueue::dump()
cprintf("============================================================\n");
}
+extern "C"
+void
+dumpMainQueue()
+{
+ mainEventQueue.dump();
+}
+
const char *
Event::description()
@@ -235,16 +242,18 @@ Event::trace(const char *action)
void
Event::dump()
{
+ cprintf("Event (%s)\n", description());
+ cprintf("Flags: %#x\n", _flags);
#if TRACING_ON
- cprintf(" Created: %d\n", when_created);
+ cprintf("Created: %d\n", when_created);
#endif
if (scheduled()) {
#if TRACING_ON
- cprintf(" Scheduled at %d\n", when_scheduled);
+ cprintf("Scheduled at %d\n", when_scheduled);
#endif
- cprintf(" Scheduled for %d\n", when());
+ cprintf("Scheduled for %d, priority %d\n", when(), _priority);
}
else {
- cprintf(" Not Scheduled\n");
+ cprintf("Not Scheduled\n");
}
}
diff --git a/sim/stat_control.cc b/sim/stat_control.cc
index 9a4313a61..8a8eaa790 100644
--- a/sim/stat_control.cc
+++ b/sim/stat_control.cc
@@ -80,6 +80,12 @@ statElapsedTime()
return elapsed();
}
+Tick
+statElapsedTicks()
+{
+ return curTick - startTick;
+}
+
SimTicksReset simTicksReset;
void
@@ -105,7 +111,7 @@ InitSimStats()
;
simTicks
- .scalar(curTick)
+ .functor(statElapsedTicks)
.name("sim_ticks")
.desc("Number of ticks simulated")
;
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-11 10:01:09 +0000