diff options
| -rw-r--r-- | src/arch/sparc/insts/SConscript | 2 | ||||
| -rw-r--r-- | src/arch/sparc/insts/blockmem.cc | 88 | ||||
| -rw-r--r-- | src/arch/sparc/insts/blockmem.hh | 92 | ||||
| -rw-r--r-- | src/arch/sparc/insts/mem.cc | 94 | ||||
| -rw-r--r-- | src/arch/sparc/insts/mem.hh | 78 | ||||
| -rw-r--r-- | src/arch/sparc/isa/formats/mem/blockmem.isa | 113 | ||||
| -rw-r--r-- | src/arch/sparc/isa/formats/mem/util.isa | 100 | ||||
| -rw-r--r-- | src/arch/sparc/isa/includes.isa | 2 |
8 files changed, 356 insertions, 213 deletions
diff --git a/src/arch/sparc/insts/SConscript b/src/arch/sparc/insts/SConscript index 8848566a8..f6085541b 100644 --- a/src/arch/sparc/insts/SConscript +++ b/src/arch/sparc/insts/SConscript @@ -32,7 +32,9 @@ Import('*') if env['TARGET_ISA'] == 'sparc': + Source('blockmem.cc') Source('branch.cc') + Source('mem.cc') Source('micro.cc') Source('priv.cc') Source('static_inst.cc') diff --git a/src/arch/sparc/insts/blockmem.cc b/src/arch/sparc/insts/blockmem.cc new file mode 100644 index 000000000..e8e930151 --- /dev/null +++ b/src/arch/sparc/insts/blockmem.cc @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2006-2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Gabe Black + */ + +#include "arch/sparc/insts/blockmem.hh" + +namespace SparcISA +{ + +std::string +BlockMemMicro::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream response; + bool load = flags[IsLoad]; + bool save = flags[IsStore]; + + printMnemonic(response, mnemonic); + if (save) { + printReg(response, _srcRegIdx[0]); + ccprintf(response, ", "); + } + ccprintf(response, "[ "); + printReg(response, _srcRegIdx[!save ? 0 : 1]); + ccprintf(response, " + "); + printReg(response, _srcRegIdx[!save ? 1 : 2]); + ccprintf(response, " ]"); + if (load) { + ccprintf(response, ", "); + printReg(response, _destRegIdx[0]); + } + + return response.str(); +} + +std::string +BlockMemImmMicro::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream response; + bool load = flags[IsLoad]; + bool save = flags[IsStore]; + + printMnemonic(response, mnemonic); + if (save) { + printReg(response, _srcRegIdx[1]); + ccprintf(response, ", "); + } + ccprintf(response, "[ "); + printReg(response, _srcRegIdx[0]); + if (imm >= 0) + ccprintf(response, " + 0x%x ]", imm); + else + ccprintf(response, " + -0x%x ]", -imm); + if (load) { + ccprintf(response, ", "); + printReg(response, _destRegIdx[0]); + } + + return response.str(); +} + +} diff --git a/src/arch/sparc/insts/blockmem.hh b/src/arch/sparc/insts/blockmem.hh new file mode 100644 index 000000000..5216b2d32 --- /dev/null +++ b/src/arch/sparc/insts/blockmem.hh @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2006-2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Gabe Black + */ + +#ifndef __ARCH_SPARC_INSTS_BLOCKMEM_HH__ +#define __ARCH_SPARC_INSTS_BLOCKMEM_HH__ + +#include "arch/sparc/insts/micro.hh" + +namespace SparcISA +{ + +//////////////////////////////////////////////////////////////////// +// +// Block Memory instructions +// + +class BlockMem : public SparcMacroInst +{ + protected: + // We make the assumption that all block memory operations will take + // 8 instructions to execute. + BlockMem(const char *mnem, ExtMachInst _machInst) : + SparcMacroInst(mnem, _machInst, No_OpClass, 8) + {} +}; + +class BlockMemImm : public BlockMem +{ + protected: + using BlockMem::BlockMem; +}; + +class BlockMemMicro : public SparcMicroInst +{ + protected: + BlockMemMicro(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, int8_t _offset) : + SparcMicroInst(mnem, _machInst, __opClass), offset(_offset) + {} + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; + + const int8_t offset; +}; + +class BlockMemImmMicro : public BlockMemMicro +{ + protected: + BlockMemImmMicro(const char *mnem, ExtMachInst _machInst, + OpClass __opClass, int8_t _offset) : + BlockMemMicro(mnem, _machInst, __opClass, _offset), + imm(sext<13>(bits(_machInst, 12, 0))) + {} + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; + + const int32_t imm; +}; + +} + +#endif // __ARCH_SPARC_INSTS_BLOCKMEM_HH__ diff --git a/src/arch/sparc/insts/mem.cc b/src/arch/sparc/insts/mem.cc new file mode 100644 index 000000000..a78ea6697 --- /dev/null +++ b/src/arch/sparc/insts/mem.cc @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2006-2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Gabe Black + * Steve Reinhardt + */ + +#include "arch/sparc/insts/mem.hh" + +namespace SparcISA +{ + +std::string +Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream response; + bool load = flags[IsLoad]; + bool store = flags[IsStore]; + + printMnemonic(response, mnemonic); + if (store) { + printReg(response, _srcRegIdx[0]); + ccprintf(response, ", "); + } + ccprintf(response, "["); + if (_srcRegIdx[!store ? 0 : 1].index() != 0) { + printSrcReg(response, !store ? 0 : 1); + ccprintf(response, " + "); + } + printSrcReg(response, !store ? 1 : 2); + ccprintf(response, "]"); + if (load) { + ccprintf(response, ", "); + printReg(response, _destRegIdx[0]); + } + + return response.str(); +} + +std::string +MemImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream response; + bool load = flags[IsLoad]; + bool save = flags[IsStore]; + + printMnemonic(response, mnemonic); + if (save) { + printReg(response, _srcRegIdx[0]); + ccprintf(response, ", "); + } + ccprintf(response, "["); + if (_srcRegIdx[!save ? 0 : 1].index() != 0) { + printReg(response, _srcRegIdx[!save ? 0 : 1]); + ccprintf(response, " + "); + } + if (imm >= 0) + ccprintf(response, "%#x]", imm); + else + ccprintf(response, "-%#x]", -imm); + if (load) { + ccprintf(response, ", "); + printReg(response, _destRegIdx[0]); + } + + return response.str(); +} + +} diff --git a/src/arch/sparc/insts/mem.hh b/src/arch/sparc/insts/mem.hh new file mode 100644 index 000000000..8e21edff6 --- /dev/null +++ b/src/arch/sparc/insts/mem.hh @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2006-2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * Gabe Black + * Steve Reinhardt + */ + +#ifndef __ARCH_SPARC_INSTS_MEM_HH__ +#define __ARCH_SPARC_INSTS_MEM_HH__ + +#include "arch/sparc/insts/static_inst.hh" + +namespace SparcISA +{ + +//////////////////////////////////////////////////////////////////// +// +// Mem utility templates and functions +// + +/** + * Base class for memory operations. + */ +class Mem : public SparcStaticInst +{ + protected: + using SparcStaticInst::SparcStaticInst; + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; +}; + +/** + * Class for memory operations which use an immediate offset. + */ +class MemImm : public Mem +{ + protected: + + // Constructor + MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : + Mem(mnem, _machInst, __opClass), imm(sext<13>(bits(_machInst, 12, 0))) + {} + + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; + + const int32_t imm; +}; + +} + +#endif // __ARCH_SPARC_INSTS_MEM_HH__ diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 3e3aabfcb..05ddc63b3 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -32,119 +32,6 @@ // Block Memory instructions // -output header {{ - - class BlockMem : public SparcMacroInst - { - protected: - - // Constructor - // We make the assumption that all block memory operations - // Will take 8 instructions to execute - BlockMem(const char *mnem, ExtMachInst _machInst) : - SparcMacroInst(mnem, _machInst, No_OpClass, 8) - {} - }; - - class BlockMemImm : public BlockMem - { - protected: - - // Constructor - BlockMemImm(const char *mnem, ExtMachInst _machInst) : - BlockMem(mnem, _machInst) - {} - }; - - class BlockMemMicro : public SparcMicroInst - { - protected: - - // Constructor - BlockMemMicro(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, int8_t _offset) : - SparcMicroInst(mnem, _machInst, __opClass), - offset(_offset) - {} - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - const int8_t offset; - }; - - class BlockMemImmMicro : public BlockMemMicro - { - protected: - - // Constructor - BlockMemImmMicro(const char *mnem, ExtMachInst _machInst, - OpClass __opClass, int8_t _offset) : - BlockMemMicro(mnem, _machInst, __opClass, _offset), - imm(sext<13>(SIMM13)) - {} - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - const int32_t imm; - }; -}}; - -output decoder {{ - std::string BlockMemMicro::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - bool load = flags[IsLoad]; - bool save = flags[IsStore]; - - printMnemonic(response, mnemonic); - if (save) { - printReg(response, _srcRegIdx[0]); - ccprintf(response, ", "); - } - ccprintf(response, "[ "); - printReg(response, _srcRegIdx[!save ? 0 : 1]); - ccprintf(response, " + "); - printReg(response, _srcRegIdx[!save ? 1 : 2]); - ccprintf(response, " ]"); - if (load) { - ccprintf(response, ", "); - printReg(response, _destRegIdx[0]); - } - - return response.str(); - } - - std::string BlockMemImmMicro::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - bool load = flags[IsLoad]; - bool save = flags[IsStore]; - - printMnemonic(response, mnemonic); - if (save) { - printReg(response, _srcRegIdx[1]); - ccprintf(response, ", "); - } - ccprintf(response, "[ "); - printReg(response, _srcRegIdx[0]); - if (imm >= 0) - ccprintf(response, " + 0x%x ]", imm); - else - ccprintf(response, " + -0x%x ]", -imm); - if (load) { - ccprintf(response, ", "); - printReg(response, _destRegIdx[0]); - } - - return response.str(); - } - -}}; - def template BlockMemDeclare {{ /** * Static instruction class for a block memory operation diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 4d7fc0608..ad43a6810 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -33,101 +33,6 @@ // Mem utility templates and functions // -output header {{ - /** - * Base class for memory operations. - */ - class Mem : public SparcStaticInst - { - protected: - - // Constructor - Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - SparcStaticInst(mnem, _machInst, __opClass) - { - } - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - }; - - /** - * Class for memory operations which use an immediate offset. - */ - class MemImm : public Mem - { - protected: - - // Constructor - MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : - Mem(mnem, _machInst, __opClass), imm(sext<13>(SIMM13)) - {} - - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; - - const int32_t imm; - }; -}}; - -output decoder {{ - std::string Mem::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - bool load = flags[IsLoad]; - bool store = flags[IsStore]; - - printMnemonic(response, mnemonic); - if (store) { - printReg(response, _srcRegIdx[0]); - ccprintf(response, ", "); - } - ccprintf(response, "["); - if (_srcRegIdx[!store ? 0 : 1].index() != 0) { - printSrcReg(response, !store ? 0 : 1); - ccprintf(response, " + "); - } - printSrcReg(response, !store ? 1 : 2); - ccprintf(response, "]"); - if (load) { - ccprintf(response, ", "); - printReg(response, _destRegIdx[0]); - } - - return response.str(); - } - - std::string MemImm::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - bool load = flags[IsLoad]; - bool save = flags[IsStore]; - - printMnemonic(response, mnemonic); - if (save) { - printReg(response, _srcRegIdx[0]); - ccprintf(response, ", "); - } - ccprintf(response, "["); - if (_srcRegIdx[!save ? 0 : 1].index() != 0) { - printReg(response, _srcRegIdx[!save ? 0 : 1]); - ccprintf(response, " + "); - } - if (imm >= 0) - ccprintf(response, "0x%x]", imm); - else - ccprintf(response, "-0x%x]", -imm); - if (load) { - ccprintf(response, ", "); - printReg(response, _destRegIdx[0]); - } - - return response.str(); - } -}}; - // This template provides the execute functions for a load def template LoadExecute {{ Fault %(class_name)s::execute(ExecContext *xc, @@ -280,11 +185,6 @@ def template EACompExecute {{ } }}; -// This declares the completeAcc function in memory operations -def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; -}}; - // Here are some code snippets which check for various fault conditions let {{ LoadFuncs = [LoadExecute, LoadInitiateAcc, LoadCompleteAcc] diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index a33a44ed9..49edccb0b 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -39,7 +39,9 @@ output header {{ #include <sstream> #include "arch/sparc/faults.hh" +#include "arch/sparc/insts/blockmem.hh" #include "arch/sparc/insts/branch.hh" +#include "arch/sparc/insts/mem.hh" #include "arch/sparc/insts/micro.hh" #include "arch/sparc/insts/nop.hh" #include "arch/sparc/insts/priv.hh" |