diff options
| -rw-r--r-- | src/cpu/simple/timing.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 5bfc9799d..2d0ab330e 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -243,6 +243,12 @@ bool TimingSimpleCPU::handleReadPacket(PacketPtr pkt) { RequestPtr req = pkt->req; + + // We're about the issues a locked load, so tell the monitor + // to start caring about this address + if (pkt->isRead() && pkt->req->isLLSC()) { + TheISA::handleLockedRead(thread, pkt->req); + } if (req->isMmappedIpr()) { Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt); new IprEvent(pkt, this, clockEdge(delay)); @@ -792,12 +798,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) traceData = NULL; } - // the locked flag may be cleared on the response packet, so check - // pkt->req and not pkt to see if it was a load-locked - if (pkt->isRead() && pkt->req->isLLSC()) { - TheISA::handleLockedRead(thread, pkt->req); - } - delete pkt->req; delete pkt; |