summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/mem/protocol/MESI_Three_Level-L0cache.sm20
-rw-r--r--src/mem/protocol/MESI_Three_Level-L1cache.sm8
-rw-r--r--src/mem/protocol/MESI_Three_Level-msg.sm2
3 files changed, 15 insertions, 15 deletions
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
index c5802d776..8ab0a92cb 100644
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -257,7 +257,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
in_port(messgeBuffer_in, CoherenceMsg, bufferFromL1, rank = 1) {
if (messgeBuffer_in.isReady()) {
peek(messgeBuffer_in, CoherenceMsg, block_on="Addr") {
- assert(in_msg.Destination == machineID);
+ assert(in_msg.Dest == machineID);
Entry cache_entry := getCacheEntry(in_msg.Addr);
TBE tbe := TBEs[in_msg.Addr];
@@ -368,9 +368,9 @@ machine(L0Cache, "MESI Directory L0 Cache")
out_msg.Addr := address;
out_msg.Class := CoherenceClass:GETS;
out_msg.Sender := machineID;
- out_msg.Destination := createMachineID(MachineType:L1Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L1Cache, version);
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
+ address, out_msg.Dest);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
}
@@ -384,10 +384,10 @@ machine(L0Cache, "MESI Directory L0 Cache")
out_msg.Class := CoherenceClass:GETX;
out_msg.Sender := machineID;
DPRINTF(RubySlicc, "%s\n", machineID);
- out_msg.Destination := createMachineID(MachineType:L1Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L1Cache, version);
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
+ address, out_msg.Dest);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
}
@@ -400,10 +400,10 @@ machine(L0Cache, "MESI Directory L0 Cache")
out_msg.Addr := address;
out_msg.Class := CoherenceClass:UPGRADE;
out_msg.Sender := machineID;
- out_msg.Destination := createMachineID(MachineType:L1Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L1Cache, version);
DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
+ address, out_msg.Dest);
out_msg.MessageSize := MessageSizeType:Control;
out_msg.AccessMode := in_msg.AccessMode;
}
@@ -418,7 +418,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
out_msg.Sender := machineID;
- out_msg.Destination := createMachineID(MachineType:L1Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L1Cache, version);
out_msg.MessageSize := MessageSizeType:Writeback_Data;
}
}
@@ -429,7 +429,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
out_msg.Addr := address;
out_msg.Class := CoherenceClass:INV_ACK;
out_msg.Sender := machineID;
- out_msg.Destination := createMachineID(MachineType:L1Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L1Cache, version);
out_msg.MessageSize := MessageSizeType:Response_Control;
}
}
@@ -450,7 +450,7 @@ machine(L0Cache, "MESI Directory L0 Cache")
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
out_msg.Sender:= machineID;
- out_msg.Destination := createMachineID(MachineType:L1Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L1Cache, version);
if (cache_entry.Dirty) {
out_msg.MessageSize := MessageSizeType:Writeback_Data;
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm
index 024f8f6da..7db3daede 100644
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -551,7 +551,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Addr := address;
out_msg.Class := CoherenceClass:INV;
out_msg.Sender := machineID;
- out_msg.Destination := createMachineID(MachineType:L0Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L0Cache, version);
out_msg.MessageSize := MessageSizeType:Control;
}
}
@@ -606,7 +606,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Addr := address;
out_msg.Class := CoherenceClass:DATA;
out_msg.Sender := machineID;
- out_msg.Destination := createMachineID(MachineType:L0Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L0Cache, version);
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
@@ -620,7 +620,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Addr := address;
out_msg.Class := CoherenceClass:STALE_DATA;
out_msg.Sender := machineID;
- out_msg.Destination := createMachineID(MachineType:L0Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L0Cache, version);
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
@@ -634,7 +634,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
out_msg.Addr := address;
out_msg.Class := CoherenceClass:DATA_EXCLUSIVE;
out_msg.Sender := machineID;
- out_msg.Destination := createMachineID(MachineType:L0Cache, version);
+ out_msg.Dest := createMachineID(MachineType:L0Cache, version);
out_msg.DataBlk := cache_entry.DataBlk;
out_msg.Dirty := cache_entry.Dirty;
out_msg.MessageSize := MessageSizeType:Response_Data;
diff --git a/src/mem/protocol/MESI_Three_Level-msg.sm b/src/mem/protocol/MESI_Three_Level-msg.sm
index eb29975f9..968d26964 100644
--- a/src/mem/protocol/MESI_Three_Level-msg.sm
+++ b/src/mem/protocol/MESI_Three_Level-msg.sm
@@ -59,7 +59,7 @@ structure(CoherenceMsg, desc="...", interface="Message") {
CoherenceClass Class, desc="Type of message (GetS, GetX, PutX, etc)";
RubyAccessMode AccessMode, desc="user/supervisor access type";
MachineID Sender, desc="What component sent this message";
- MachineID Destination, desc="What machine receives this message";
+ MachineID Dest, desc="What machine receives this message";
MessageSizeType MessageSize, desc="size category of the message";
DataBlock DataBlk, desc="Data for the cache line (if PUTX)";
bool Dirty, default="false", desc="Dirty bit";
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 06:50:47 +0000