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-rw-r--r--dev/etherpkt.cc3
-rw-r--r--dev/sinic.cc26
-rw-r--r--dev/sinic.hh2
-rw-r--r--kern/linux/linux_system.cc5
-rw-r--r--python/m5/objects/Ethernet.mpy29
5 files changed, 49 insertions, 16 deletions
diff --git a/dev/etherpkt.cc b/dev/etherpkt.cc
index bf60bc150..475274326 100644
--- a/dev/etherpkt.cc
+++ b/dev/etherpkt.cc
@@ -46,5 +46,6 @@ PacketData::unserialize(const string &base, Checkpoint *cp,
const string &section)
{
paramIn(cp, section, base + ".length", length);
- arrayParamIn(cp, section, base + ".data", data, length);
+ if (length)
+ arrayParamIn(cp, section, base + ".data", data, length);
}
diff --git a/dev/sinic.cc b/dev/sinic.cc
index 4d6ecf668..1f7fceebe 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -94,20 +94,20 @@ Device::Device(Params *p)
{
reset();
- if (p->header_bus) {
- pioInterface = newPioInterface(p->name, p->hier, p->header_bus, this,
+ if (p->io_bus) {
+ pioInterface = newPioInterface(p->name, p->hier, p->io_bus, this,
&Device::cacheAccess);
- pioLatency = p->pio_latency * p->header_bus->clockRatio;
+ pioLatency = p->pio_latency * p->io_bus->clockRatio;
if (p->payload_bus)
- dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
- p->header_bus, p->payload_bus,
- 1, p->dma_no_allocate);
+ dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
+ p->payload_bus, 1,
+ p->dma_no_allocate);
else
- dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
- p->header_bus, p->header_bus,
- 1, p->dma_no_allocate);
+ dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
+ p->io_bus, 1,
+ p->dma_no_allocate);
} else if (p->payload_bus) {
pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this,
&Device::cacheAccess);
@@ -1361,6 +1361,7 @@ REGISTER_SIM_OBJECT("SinicInt", Interface)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
+ Param<Addr> addr;
Param<Tick> cycle_time;
Param<Tick> tx_delay;
Param<Tick> rx_delay;
@@ -1369,7 +1370,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
SimObjectParam<PhysicalMemory *> physmem;
Param<bool> rx_filter;
Param<string> hardware_address;
- SimObjectParam<Bus*> header_bus;
+ SimObjectParam<Bus*> io_bus;
SimObjectParam<Bus*> payload_bus;
SimObjectParam<HierParams *> hier;
Param<Tick> pio_latency;
@@ -1395,6 +1396,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(Device)
BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
+ INIT_PARAM(addr, "Device Address"),
INIT_PARAM(cycle_time, "State machine cycle time"),
INIT_PARAM_DFLT(tx_delay, "Transmit Delay", 1000),
INIT_PARAM_DFLT(rx_delay, "Receive Delay", 1000),
@@ -1404,7 +1406,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM_DFLT(rx_filter, "Enable Receive Filter", true),
INIT_PARAM_DFLT(hardware_address, "Ethernet Hardware Address",
"00:99:00:00:00:01"),
- INIT_PARAM_DFLT(header_bus, "The IO Bus to attach to for headers", NULL),
+ INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to for headers", NULL),
INIT_PARAM_DFLT(payload_bus, "The IO Bus to attach to for payload", NULL),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
@@ -1440,7 +1442,7 @@ CREATE_SIM_OBJECT(Device)
params->rx_delay = rx_delay;
params->mmu = mmu;
params->hier = hier;
- params->header_bus = header_bus;
+ params->io_bus = io_bus;
params->payload_bus = payload_bus;
params->pio_latency = pio_latency;
params->configSpace = configspace;
diff --git a/dev/sinic.hh b/dev/sinic.hh
index 062a5408b..c87a66928 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -299,7 +299,7 @@ class Device : public Base
Tick tx_delay;
Tick rx_delay;
HierParams *hier;
- Bus *header_bus;
+ Bus *io_bus;
Bus *payload_bus;
Tick pio_latency;
PhysicalMemory *physmem;
diff --git a/kern/linux/linux_system.cc b/kern/linux/linux_system.cc
index a9c92b54a..5fa72735c 100644
--- a/kern/linux/linux_system.cc
+++ b/kern/linux/linux_system.cc
@@ -132,8 +132,9 @@ LinuxSystem::LinuxSystem(Params *p)
skipDelayLoopEvent = new LinuxSkipDelayLoopEvent(&pcEventQueue,
"calibrate_delay");
- if (kernelSymtab->findAddress("calibrate_delay", addr))
- skipDelayLoopEvent->schedule(addr+sizeof(MachInst));
+ if (kernelSymtab->findAddress("calibrate_delay", addr)) {
+ skipDelayLoopEvent->schedule(addr + 3 * sizeof(MachInst));
+ }
skipCacheProbeEvent = new SkipFuncEvent(&pcEventQueue,
"determine_cpu_caches");
diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy
index 141d138da..0065a238f 100644
--- a/python/m5/objects/Ethernet.mpy
+++ b/python/m5/objects/Ethernet.mpy
@@ -89,4 +89,33 @@ simobj NSGigEInt(EtherInt):
type = 'NSGigEInt'
device = Param.NSGigE("Ethernet device of this interface")
+simobj Sinic(PciDevice):
+ type = 'Sinic'
+ hardware_address = Param.EthernetAddr(NextEthernetAddr,
+ "Ethernet Hardware Address")
+
+ cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+
+ dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+ dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+ dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+ dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
+
+ rx_filter = Param.Bool(True, "Enable Receive Filter")
+ rx_delay = Param.Latency('1us', "Receive Delay")
+ tx_delay = Param.Latency('1us', "Transmit Delay")
+
+ rx_max_copy = Param.MemorySize('16kB', "rx max copy")
+ tx_max_copy = Param.MemorySize('16kB', "tx max copy")
+ rx_fifo_size = Param.MemorySize('64kB', "max size of rx fifo")
+ tx_fifo_size = Param.MemorySize('64kB', "max size of tx fifo")
+ rx_fifo_threshold = Param.MemorySize('48kB', "rx fifo high threshold")
+ tx_fifo_threshold = Param.MemorySize('16kB', "tx fifo low threshold")
+
+ intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
+ payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
+ physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
+simobj SinicInt(EtherInt):
+ type = 'SinicInt'
+ device = Param.Sinic("Ethernet device of this interface")
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 12:30:22 +0000