diff options
| -rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 9 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 52 |
2 files changed, 56 insertions, 5 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index 717bd1857..06f540717 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -129,7 +129,7 @@ format DataOp { } } 0x1: decode OPCODE { - 0x9: BranchExchange::oldbx({{ }}); + 0x9: ArmBx::armBx(); 0xb: PredOp::clz({{ Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm))); }}); @@ -138,7 +138,7 @@ format DataOp { 0x9: WarnUnimpl::bxj(); } 0x3: decode OPCODE { - 0x9: BranchExchange::oldblx({{ }}, Link); + 0x9: ArmBlxReg::armBlxReg(); } 0x5: decode OPCODE { 0x8: WarnUnimpl::qadd(); @@ -264,9 +264,8 @@ format DataOp { } 0x4: ArmMacroMem::armMacroMem(); 0x5: decode OPCODE_24 { - // Branch (and Link) Instructions - 0: Branch::oldb({{ }}); - 1: Branch::oldbl({{ }}, Link); + 0: ArmBBlxImm::armBBlxImm(); + 1: ArmBlBlxImm::armBlBlxImm(); } 0x6: decode CPNUM { 0xb: decode LOADOP { diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index efe91f039..62a6e40c2 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -1,5 +1,17 @@ // -*- mode:c++ -*- +// Copyright (c) 2010 ARM Limited +// All rights reserved +// +// The license below extends only to copyright in the software and shall +// not be construed as granting a license to any other intellectual +// property including but not limited to intellectual property relating +// to a hardware implementation of the functionality of the software +// licensed hereunder. You may use the software subject to the license +// terms below provided that you ensure that this notice is replicated +// unmodified and in its entirety in all distributions of the software, +// modified or unmodified, in source code or in binary form. +// // Copyright (c) 2007-2008 The Florida State University // All rights reserved. // @@ -33,6 +45,46 @@ // Control transfer instructions // +def format ArmBBlxImm() {{ + decode_block = ''' + if (machInst.condCode == 0xF) { + int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | + (bits(machInst, 24) << 1); + return new BlxImm(machInst, imm); + } else { + return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2), + (ConditionCode)(uint32_t)machInst.condCode); + } + ''' +}}; + +def format ArmBlBlxImm() {{ + decode_block = ''' + if (machInst.condCode == 0xF) { + int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | + (bits(machInst, 24) << 1); + return new BlxImm(machInst, imm); + } else { + return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2), + (ConditionCode)(uint32_t)machInst.condCode); + } + ''' +}}; + +def format ArmBx() {{ + decode_block = ''' + return new BxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), + (ConditionCode)(uint32_t)machInst.condCode); + ''' +}}; + +def format ArmBlxReg() {{ + decode_block = ''' + return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), + (ConditionCode)(uint32_t)machInst.condCode); + ''' +}}; + def format Branch(code,*opt_flags) {{ #Build Instruction Flags |