diff options
233 files changed, 13740 insertions, 7925 deletions
@@ -1,4 +1,4 @@ -Copyright (c) 2000-2008 The Regents of The University of Michigan +Copyright (c) 2000-2011 The Regents of The University of Michigan All rights reserved. Redistribution and use in source and binary forms, with or without @@ -1,4 +1,4 @@ -This is release 2.0_beta6 of the M5 simulator. +This is the M5 simulator. For detailed information about building the simulator and getting started please refer to http://www.m5sim.org. @@ -9,13 +9,16 @@ http://www.m5sim.org/wiki/index.php/Running_M5 Short version: -1. If you don't have SCons version 0.96.91 or newer, get it from +1. If you don't have SCons version 0.98.1 or newer, get it from http://wwww.scons.org. -2. If you don't have SWIG version 1.3.28 or newer, get it from +2. If you don't have SWIG version 1.3.31 or newer, get it from http://wwww.swig.org. -3. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This +3. Make sure you also have gcc version 3.4.6 or newer, Python 2.4 or newer +(the dev version with header files), zlib, and the m4 preprocessor. + +4. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'. This will build the debug version of the m5 binary (m5.debug) for the Alpha syscall emulation target, and run the quick regression tests on it. @@ -25,18 +28,21 @@ WHAT'S INCLUDED (AND NOT) ------------------------- The basic source release includes these subdirectories: - - m5: + - m5: + - configs: simulation configuration scripts + - ext: less-common external packages needed to build m5 - src: source code of the m5 simulator + - system: source for some optional system software for simulated systems - tests: regression tests - - ext: less-common external packages needed to build m5 + - util: useful utility programs and files -To run full-system simulations, you will need compiled console, -PALcode, and kernel binaries and one or more disk images. These files -are collected in a separate archive, m5_system.tar.bz2. This file -can he downloaded separately. +To run full-system simulations, you will need compiled system firmware +(console and PALcode for Alpha), kernel binaries and one or more disk images. +These files for Alpha are collected in a separate archive, m5_system.tar.bz2. +This file can he downloaded separately. -M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP -Tru64 version of Unix. We are able to distribute Linux and FreeBSD -bootdisks, but we are unable to distribute bootable disk images of +Depending on the ISA used, M5 may support Linux 2.4/2.6, FreeBSD, and the +proprietary Compaq/HP Tru64 version of Unix. We are able to distribute Linux +and FreeBSD bootdisks, but we are unable to distribute bootable disk images of Tru64 Unix. If you have a Tru64 license and are interested in obtaining disk images, contact us at m5-users@m5sim.org diff --git a/RELEASE_NOTES b/RELEASE_NOTES deleted file mode 100644 index f10ffddae..000000000 --- a/RELEASE_NOTES +++ /dev/null @@ -1,149 +0,0 @@ -October 6, 2008: m5_2.0_beta6 --------------------- -New Features -1. Support for gcc 4.3 -2. Core m5 code in libm5 for integration with other simulators -3. Preliminary support for X86 SE mode -4. Additional system calls emulated -5. m5term updated to work on OS X -6. Ability to disable listen sockets -7. Event queue performance improvements and rewrite -8. Better errors for unconnected memory ports - -Bug fixes -1. ALPHA_SE O3 perlbmk benchmark -2. Translation bug where O3 could fetch from uncachable memory -3. Many minor bugs - -Outstanding issues for 2.0 release: --------------------- -1. Statistics cleanup -2. Improve regression system -3. Testing -4. Validation - -March 1, 2008: m5_2.0_beta5 --------------------- -New Features -1. Rick Strong's Simpoints config changes -2. Support for FSU ARM port -3. EXTRAS= option allow architectures to be specified - -Bug fixes -1. Bus timing more realistic -2. Cache writeback, LL/SC fixes -3. Minor IGbE NIC fixes -4. O3 op latency fix -5. SPARC TLB demap fixes -6. SPARC SE memory layout fixes -7. Variety of MIPS fixes - -Nov 4, 2007: m5_2.0_beta4 --------------------- -New Features -1. New cache model -2. Use of a I/O cache between devices and memory -3. Ability to include compiled code with EXTRAS= -4. Python creation of params structures for initialization -5. Ability to remotely debug in SE - -Bug fixes: -1. Fix SE serialization -2. SPARC_FS booting with TimingSimpleCPU -3. Rename cycles() to ticks() -4. Various SPARC ISA fixes -5. Draining code for checkpointing -6. Various performance improvements - -Possible Incompatibilities: -1. Real TLBs are now used in SE mode. This is more accurate however it could - cause some problems if you've modified the way page handling is done in - SE mode. -2. There have been many changes to the way the SCons files work. SimObjects, - sources files, and trace flags are all specified in the SConscript files. - To see how to add your sources take a look at one of them. -3. Python is now used to created the parameter structs that were created - manually before. The parameters listed in a py file are turned into - a header file with the same name (e.g. BadDevice.py -> BadDevice.hh). - With this change the structs can be populated automatically and the - ugly macros to define and create SimObjects at the bottem of source - files are gone. The parameter structs also automatically inherit - parameters from their parents. - -May 16, 2007: m5_2.0_beta3 --------------------- -New Features -1. Some support for SPARC full-system simulation -2. Reworking of trace facitities (parameter names changed, variadic macros - removed) -3. Scons script cleanups -4. Some support for compiling with Intel CC - -Bug fixes since beta 2: -1. Many SPARC linux syscall emulation support fixes -2. Multiprocessor linux boot using the detailed O3 CPU module -3. Workaround for DMA bug (final solution to be released with 2.0f) -4. Simulator performance and memory leak fixes -5. Fixed issue where console could stop printing in ALPHA_FS -6. Fix issues with remote debugging -7. Several compile fixes, including gcc 4.1 -8. Many other minor fixes and enhancements - -Nov. 28, 2006: m5_2.0_beta2 --------------------- -Bug fixes since beta 1: -1. Many cache issues resolved -2. Uni-coherence fixes in full-system -3. LL/SC Support -4. Draining/Switchover -5. Functional Accesses -6. Bus now has real timing -7. Single config file for all SpecCPU2000 benchmarks -8. Several other minor bug fixes and enhancements - -Aug. 25, 2006: m5_2.0_beta patch 1 --------------------- -Handful of minor bug fixes for m5_2.0_beta, -along with a few new regression tests. - -Aug. 15, 2006: m5_2.0_beta --------------------- -Major update to M5 including: -- New CPU model -- New memory system -- More extensive python integration -- Preliminary syscall emulation support for MIPS and SPARC -This is a *beta* release, meaning that some features are not complete, -and some features from M5 1.X aren't currently supported (e.g., MP -coherence). We are working to address these limitations and hope to -have a complete 2.0 release soon. - -Oct. 8, 2005: m5_1.1 --------------------- -Update release for IOSCA workshop mini-tutorial. New features include: -- Preliminary FreeBSD support -- Integration of regression tests into scons build framework -- Several bug fixes and better compatibility for Cygwin hosts -- Major cleanup of Alpha system code (console, PAL, etc.) to make - it easier for others to build/modify -- Fixes to enable compilation under g++ 4.0 -- Numerous minor bug fixes - -June 10, 2005: m5_1.0_web -------------------------- -The 1.0 release posted on Sourceforge after the ISCA tutorial contains -just a few very minor fixes relative to the CD. - -June 5, 2005: m5_1.0_tutorial ------------------------------ -First non-beta release. This release was on the CD distributed at the -ISCA tutorial. Major enhancements relative to beta releases include -Linux support and Python-based configuration language. - -June 17, 2004: m5_1.0_beta2 ---------------------------- -Stealth-mode beta bug-fix update, not widely advertised. - -Oct. 17, 2003: m5_1.0_beta1 ---------------------------- -Early beta release. diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 44ac104b5..f58fd3d2e 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -238,6 +238,7 @@ def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False, self.intrctrl = IntrControl() self.terminal = Terminal() + self.vncserver = VncServer() self.kernel = binary('vmlinux.arm') self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \ ' norandmaps slram=slram0,0x8000000,+0x8000000' + \ @@ -334,6 +335,9 @@ def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False # Create and connect the busses required by each memory system if Ruby: connectX86RubySystem(self) + # add the ide to the list of dma devices that later need to attach to + # dma controllers + self._dma_devices = [self.pc.south_bridge.ide] else: connectX86ClassicSystem(self) diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py index adc8e6147..2081a10c4 100644 --- a/configs/example/ruby_fs.py +++ b/configs/example/ruby_fs.py @@ -111,19 +111,17 @@ CPUClass.clock = options.clock if buildEnv['TARGET_ISA'] == "alpha": system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0]) - system.ruby = Ruby.create_system(options, - system, - system.piobus, - system.dma_devices) elif buildEnv['TARGET_ISA'] == "x86": system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True) setWorkCountOptions(system, options) - system.ruby = Ruby.create_system(options, - system, - system.piobus) else: fatal("incapable of building non-alpha or non-x86 full system!") +system.ruby = Ruby.create_system(options, + system, + system.piobus, + system._dma_devices) + system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)] for (i, cpu) in enumerate(system.cpu): diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py index e32e0c114..f58ebc1de 100644 --- a/configs/example/ruby_mem_test.py +++ b/configs/example/ruby_mem_test.py @@ -135,6 +135,12 @@ for (i, cpu) in enumerate(cpus): cpu.test = system.ruby.cpu_ruby_ports[i].port cpu.functional = system.funcmem.port + # + # Since the memtester is incredibly bursty, increase the deadlock + # threshold to 5 million cycles + # + system.ruby.cpu_ruby_ports[i].deadlock_threshold = 5000000 + for (i, dma) in enumerate(dmas): # # Tie the dma memtester ports to the correct functional port diff --git a/ext/x11keysym/keysym.h b/ext/x11keysym/keysym.h new file mode 100644 index 000000000..319ce4991 --- /dev/null +++ b/ext/x11keysym/keysym.h @@ -0,0 +1,76 @@ +/* $Xorg: keysym.h,v 1.4 2001/02/09 02:03:23 xorgcvs Exp $ */ + +/*********************************************************** + +Copyright 1987, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall not be +used in advertising or otherwise to promote the sale, use or other dealings +in this Software without prior written authorization from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: xc/include/keysym.h,v 1.3 2001/01/17 17:53:12 dawes Exp $ */ + +/* default keysyms */ +#define XK_MISCELLANY +#define XK_XKB_KEYS +#define XK_LATIN1 +#define XK_LATIN2 +#define XK_LATIN3 +#define XK_LATIN4 +#define XK_LATIN8 +#define XK_LATIN9 +#define XK_CAUCASUS +#define XK_GREEK +#define XK_KATAKANA +#define XK_ARABIC +#define XK_CYRILLIC +#define XK_HEBREW +#define XK_THAI +#define XK_KOREAN +#define XK_ARMENIAN +#define XK_GEORGIAN +#define XK_VIETNAMESE +#define XK_CURRENCY +#define XK_MATHEMATICAL +#define XK_BRAILLE + +#include "x11keysym/keysymdef.h" + diff --git a/ext/x11keysym/keysymdef.h b/ext/x11keysym/keysymdef.h new file mode 100644 index 000000000..b3ade4d9e --- /dev/null +++ b/ext/x11keysym/keysymdef.h @@ -0,0 +1,2358 @@ +/* $Xorg: keysymdef.h,v 1.4 2001/02/09 02:03:23 $ */ + +/*********************************************************** +Copyright 1987, 1994, 1998 The Open Group + +Permission to use, copy, modify, distribute, and sell this software and its +documentation for any purpose is hereby granted without fee, provided that +the above copyright notice appear in all copies and that both that +copyright notice and this permission notice appear in supporting +documentation. + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE OPEN GROUP BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of The Open Group shall +not be used in advertising or otherwise to promote the sale, use or +other dealings in this Software without prior written authorization +from The Open Group. + + +Copyright 1987 by Digital Equipment Corporation, Maynard, Massachusetts + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************/ +/* $XFree86: $ */ + +/* + * The "X11 Window System Protocol" standard defines in Appendix A the + * keysym codes. These 29-bit integer values identify characters or + * functions associated with each key (e.g., via the visible + * engraving) of a keyboard layout. This file assigns mnemonic macro + * names for these keysyms. + * + * This file is also compiled (by xc/lib/X11/util/makekeys.c) into + * hash tables that can be accessed with X11 library functions such as + * XStringToKeysym() and XKeysymToString(). + * + * Where a keysym corresponds one-to-one to an ISO 10646 / Unicode + * character, this is noted in a comment that provides both the U+xxxx + * Unicode position, as well as the official Unicode name of the + * character. + * + * Where the correspondence is either not one-to-one or semantically + * unclear, the Unicode position and name are enclosed in + * parentheses. Such legacy keysyms should be considered deprecated + * and are not recommended for use in future keyboard mappings. + * + * For any future extension of the keysyms with characters already + * found in ISO 10646 / Unicode, the following algorithm shall be + * used. The new keysym code position will simply be the character's + * Unicode number plus 0x01000000. The keysym values in the range + * 0x01000100 to 0x0110ffff are reserved to represent Unicode + * characters in the range U+0100 to U+10FFFF. + * + * While most newer Unicode-based X11 clients do already accept + * Unicode-mapped keysyms in the range 0x01000100 to 0x0110ffff, it + * will remain necessary for clients -- in the interest of + * compatibility with existing servers -- to also understand the + * existing legacy keysym values in the range 0x0100 to 0x20ff. + * + * Where several mnemonic names are defined for the same keysym in this + * file, all but the first one listed should be considered deprecated. + * + * Mnemonic names for keysyms are defined in this file with lines + * that match one of these Perl regular expressions: + * + * /^\#define XK_([a-zA-Z_0-9]+)\s+0x([0-9a-f]+)\s*\/\* U+([0-9A-F]{4,6}) (.*) \*\/\s*$/ + * /^\#define XK_([a-zA-Z_0-9]+)\s+0x([0-9a-f]+)\s*\/\*\(U+([0-9A-F]{4,6}) (.*)\)\*\/\s*$/ + * /^\#define XK_([a-zA-Z_0-9]+)\s+0x([0-9a-f]+)\s*(\/\*\s*(.*)\s*\*\/)?\s*$/ + * + * When adding new keysyms to this file, do not forget to also update the + * mappings in xc/lib/X11/KeyBind.c and the protocol specification in + * xc/doc/specs/XProtocol/X11.keysyms. + */ + +/* + * Now that the Xorg code base is managed in Git repositories, the KeyBind.c + * and X11.keysyms files mentioned in the last comment block are located at: + * + * src/KeyBind.c in the repo git://anongit.freedesktop.org/xorg/lib/libX11 + * specs/XProtocol/X11.keysyms in the repo git://anongit.freedesktop.org/xorg/doc/xorg-docs + */ + +#define XK_VoidSymbol 0xffffff /* Void symbol */ + +#ifdef XK_MISCELLANY +/* + * TTY function keys, cleverly chosen to map to ASCII, for convenience of + * programming, but could have been arbitrary (at the cost of lookup + * tables in client code). + */ + +#define XK_BackSpace 0xff08 /* Back space, back char */ +#define XK_Tab 0xff09 +#define XK_Linefeed 0xff0a /* Linefeed, LF */ +#define XK_Clear 0xff0b +#define XK_Return 0xff0d /* Return, enter */ +#define XK_Pause 0xff13 /* Pause, hold */ +#define XK_Scroll_Lock 0xff14 +#define XK_Sys_Req 0xff15 +#define XK_Escape 0xff1b +#define XK_Delete 0xffff /* Delete, rubout */ + + + +/* International & multi-key character composition */ + +#define XK_Multi_key 0xff20 /* Multi-key character compose */ +#define XK_Codeinput 0xff37 +#define XK_SingleCandidate 0xff3c +#define XK_MultipleCandidate 0xff3d +#define XK_PreviousCandidate 0xff3e + +/* Japanese keyboard support */ + +#define XK_Kanji 0xff21 /* Kanji, Kanji convert */ +#define XK_Muhenkan 0xff22 /* Cancel Conversion */ +#define XK_Henkan_Mode 0xff23 /* Start/Stop Conversion */ +#define XK_Henkan 0xff23 /* Alias for Henkan_Mode */ +#define XK_Romaji 0xff24 /* to Romaji */ +#define XK_Hiragana 0xff25 /* to Hiragana */ +#define XK_Katakana 0xff26 /* to Katakana */ +#define XK_Hiragana_Katakana 0xff27 /* Hiragana/Katakana toggle */ +#define XK_Zenkaku 0xff28 /* to Zenkaku */ +#define XK_Hankaku 0xff29 /* to Hankaku */ +#define XK_Zenkaku_Hankaku 0xff2a /* Zenkaku/Hankaku toggle */ +#define XK_Touroku 0xff2b /* Add to Dictionary */ +#define XK_Massyo 0xff2c /* Delete from Dictionary */ +#define XK_Kana_Lock 0xff2d /* Kana Lock */ +#define XK_Kana_Shift 0xff2e /* Kana Shift */ +#define XK_Eisu_Shift 0xff2f /* Alphanumeric Shift */ +#define XK_Eisu_toggle 0xff30 /* Alphanumeric toggle */ +#define XK_Kanji_Bangou 0xff37 /* Codeinput */ +#define XK_Zen_Koho 0xff3d /* Multiple/All Candidate(s) */ +#define XK_Mae_Koho 0xff3e /* Previous Candidate */ + +/* 0xff31 thru 0xff3f are under XK_KOREAN */ + +/* Cursor control & motion */ + +#define XK_Home 0xff50 +#define XK_Left 0xff51 /* Move left, left arrow */ +#define XK_Up 0xff52 /* Move up, up arrow */ +#define XK_Right 0xff53 /* Move right, right arrow */ +#define XK_Down 0xff54 /* Move down, down arrow */ +#define XK_Prior 0xff55 /* Prior, previous */ +#define XK_Page_Up 0xff55 +#define XK_Next 0xff56 /* Next */ +#define XK_Page_Down 0xff56 +#define XK_End 0xff57 /* EOL */ +#define XK_Begin 0xff58 /* BOL */ + + +/* Misc functions */ + +#define XK_Select 0xff60 /* Select, mark */ +#define XK_Print 0xff61 +#define XK_Execute 0xff62 /* Execute, run, do */ +#define XK_Insert 0xff63 /* Insert, insert here */ +#define XK_Undo 0xff65 +#define XK_Redo 0xff66 /* Redo, again */ +#define XK_Menu 0xff67 +#define XK_Find 0xff68 /* Find, search */ +#define XK_Cancel 0xff69 /* Cancel, stop, abort, exit */ +#define XK_Help 0xff6a /* Help */ +#define XK_Break 0xff6b +#define XK_Mode_switch 0xff7e /* Character set switch */ +#define XK_script_switch 0xff7e /* Alias for mode_switch */ +#define XK_Num_Lock 0xff7f + +/* Keypad functions, keypad numbers cleverly chosen to map to ASCII */ + +#define XK_KP_Space 0xff80 /* Space */ +#define XK_KP_Tab 0xff89 +#define XK_KP_Enter 0xff8d /* Enter */ +#define XK_KP_F1 0xff91 /* PF1, KP_A, ... */ +#define XK_KP_F2 0xff92 +#define XK_KP_F3 0xff93 +#define XK_KP_F4 0xff94 +#define XK_KP_Home 0xff95 +#define XK_KP_Left 0xff96 +#define XK_KP_Up 0xff97 +#define XK_KP_Right 0xff98 +#define XK_KP_Down 0xff99 +#define XK_KP_Prior 0xff9a +#define XK_KP_Page_Up 0xff9a +#define XK_KP_Next 0xff9b +#define XK_KP_Page_Down 0xff9b +#define XK_KP_End 0xff9c +#define XK_KP_Begin 0xff9d +#define XK_KP_Insert 0xff9e +#define XK_KP_Delete 0xff9f +#define XK_KP_Equal 0xffbd /* Equals */ +#define XK_KP_Multiply 0xffaa +#define XK_KP_Add 0xffab +#define XK_KP_Separator 0xffac /* Separator, often comma */ +#define XK_KP_Subtract 0xffad +#define XK_KP_Decimal 0xffae +#define XK_KP_Divide 0xffaf + +#define XK_KP_0 0xffb0 +#define XK_KP_1 0xffb1 +#define XK_KP_2 0xffb2 +#define XK_KP_3 0xffb3 +#define XK_KP_4 0xffb4 +#define XK_KP_5 0xffb5 +#define XK_KP_6 0xffb6 +#define XK_KP_7 0xffb7 +#define XK_KP_8 0xffb8 +#define XK_KP_9 0xffb9 + + + +/* + * Auxiliary functions; note the duplicate definitions for left and right + * function keys; Sun keyboards and a few other manufacturers have such + * function key groups on the left and/or right sides of the keyboard. + * We've not found a keyboard with more than 35 function keys total. + */ + +#define XK_F1 0xffbe +#define XK_F2 0xffbf +#define XK_F3 0xffc0 +#define XK_F4 0xffc1 +#define XK_F5 0xffc2 +#define XK_F6 0xffc3 +#define XK_F7 0xffc4 +#define XK_F8 0xffc5 +#define XK_F9 0xffc6 +#define XK_F10 0xffc7 +#define XK_F11 0xffc8 +#define XK_L1 0xffc8 +#define XK_F12 0xffc9 +#define XK_L2 0xffc9 +#define XK_F13 0xffca +#define XK_L3 0xffca +#define XK_F14 0xffcb +#define XK_L4 0xffcb +#define XK_F15 0xffcc +#define XK_L5 0xffcc +#define XK_F16 0xffcd +#define XK_L6 0xffcd +#define XK_F17 0xffce +#define XK_L7 0xffce +#define XK_F18 0xffcf +#define XK_L8 0xffcf +#define XK_F19 0xffd0 +#define XK_L9 0xffd0 +#define XK_F20 0xffd1 +#define XK_L10 0xffd1 +#define XK_F21 0xffd2 +#define XK_R1 0xffd2 +#define XK_F22 0xffd3 +#define XK_R2 0xffd3 +#define XK_F23 0xffd4 +#define XK_R3 0xffd4 +#define XK_F24 0xffd5 +#define XK_R4 0xffd5 +#define XK_F25 0xffd6 +#define XK_R5 0xffd6 +#define XK_F26 0xffd7 +#define XK_R6 0xffd7 +#define XK_F27 0xffd8 +#define XK_R7 0xffd8 +#define XK_F28 0xffd9 +#define XK_R8 0xffd9 +#define XK_F29 0xffda +#define XK_R9 0xffda +#define XK_F30 0xffdb +#define XK_R10 0xffdb +#define XK_F31 0xffdc +#define XK_R11 0xffdc +#define XK_F32 0xffdd +#define XK_R12 0xffdd +#define XK_F33 0xffde +#define XK_R13 0xffde +#define XK_F34 0xffdf +#define XK_R14 0xffdf +#define XK_F35 0xffe0 +#define XK_R15 0xffe0 + +/* Modifiers */ + +#define XK_Shift_L 0xffe1 /* Left shift */ +#define XK_Shift_R 0xffe2 /* Right shift */ +#define XK_Control_L 0xffe3 /* Left control */ +#define XK_Control_R 0xffe4 /* Right control */ +#define XK_Caps_Lock 0xffe5 /* Caps lock */ +#define XK_Shift_Lock 0xffe6 /* Shift lock */ + +#define XK_Meta_L 0xffe7 /* Left meta */ +#define XK_Meta_R 0xffe8 /* Right meta */ +#define XK_Alt_L 0xffe9 /* Left alt */ +#define XK_Alt_R 0xffea /* Right alt */ +#define XK_Super_L 0xffeb /* Left super */ +#define XK_Super_R 0xffec /* Right super */ +#define XK_Hyper_L 0xffed /* Left hyper */ +#define XK_Hyper_R 0xffee /* Right hyper */ +#endif /* XK_MISCELLANY */ + +/* + * Keyboard (XKB) Extension function and modifier keys + * (from Appendix C of "The X Keyboard Extension: Protocol Specification") + * Byte 3 = 0xfe + */ + +#ifdef XK_XKB_KEYS +#define XK_ISO_Lock 0xfe01 +#define XK_ISO_Level2_Latch 0xfe02 +#define XK_ISO_Level3_Shift 0xfe03 +#define XK_ISO_Level3_Latch 0xfe04 +#define XK_ISO_Level3_Lock 0xfe05 +#define XK_ISO_Level5_Shift 0xfe11 +#define XK_ISO_Level5_Latch 0xfe12 +#define XK_ISO_Level5_Lock 0xfe13 +#define XK_ISO_Group_Shift 0xff7e /* Alias for mode_switch */ +#define XK_ISO_Group_Latch 0xfe06 +#define XK_ISO_Group_Lock 0xfe07 +#define XK_ISO_Next_Group 0xfe08 +#define XK_ISO_Next_Group_Lock 0xfe09 +#define XK_ISO_Prev_Group 0xfe0a +#define XK_ISO_Prev_Group_Lock 0xfe0b +#define XK_ISO_First_Group 0xfe0c +#define XK_ISO_First_Group_Lock 0xfe0d +#define XK_ISO_Last_Group 0xfe0e +#define XK_ISO_Last_Group_Lock 0xfe0f + +#define XK_ISO_Left_Tab 0xfe20 +#define XK_ISO_Move_Line_Up 0xfe21 +#define XK_ISO_Move_Line_Down 0xfe22 +#define XK_ISO_Partial_Line_Up 0xfe23 +#define XK_ISO_Partial_Line_Down 0xfe24 +#define XK_ISO_Partial_Space_Left 0xfe25 +#define XK_ISO_Partial_Space_Right 0xfe26 +#define XK_ISO_Set_Margin_Left 0xfe27 +#define XK_ISO_Set_Margin_Right 0xfe28 +#define XK_ISO_Release_Margin_Left 0xfe29 +#define XK_ISO_Release_Margin_Right 0xfe2a +#define XK_ISO_Release_Both_Margins 0xfe2b +#define XK_ISO_Fast_Cursor_Left 0xfe2c +#define XK_ISO_Fast_Cursor_Right 0xfe2d +#define XK_ISO_Fast_Cursor_Up 0xfe2e +#define XK_ISO_Fast_Cursor_Down 0xfe2f +#define XK_ISO_Continuous_Underline 0xfe30 +#define XK_ISO_Discontinuous_Underline 0xfe31 +#define XK_ISO_Emphasize 0xfe32 +#define XK_ISO_Center_Object 0xfe33 +#define XK_ISO_Enter 0xfe34 + +#define XK_dead_grave 0xfe50 +#define XK_dead_acute 0xfe51 +#define XK_dead_circumflex 0xfe52 +#define XK_dead_tilde 0xfe53 +#define XK_dead_macron 0xfe54 +#define XK_dead_breve 0xfe55 +#define XK_dead_abovedot 0xfe56 +#define XK_dead_diaeresis 0xfe57 +#define XK_dead_abovering 0xfe58 +#define XK_dead_doubleacute 0xfe59 +#define XK_dead_caron 0xfe5a +#define XK_dead_cedilla 0xfe5b +#define XK_dead_ogonek 0xfe5c +#define XK_dead_iota 0xfe5d +#define XK_dead_voiced_sound 0xfe5e +#define XK_dead_semivoiced_sound 0xfe5f +#define XK_dead_belowdot 0xfe60 +#define XK_dead_hook 0xfe61 +#define XK_dead_horn 0xfe62 +#define XK_dead_stroke 0xfe63 +#define XK_dead_abovecomma 0xfe64 +#define XK_dead_psili 0xfe64 /* alias for dead_abovecomma */ +#define XK_dead_abovereversedcomma 0xfe65 +#define XK_dead_dasia 0xfe66 /* alias for dead_abovereversedcomma */ + +#define XK_First_Virtual_Screen 0xfed0 +#define XK_Prev_Virtual_Screen 0xfed1 +#define XK_Next_Virtual_Screen 0xfed2 +#define XK_Last_Virtual_Screen 0xfed4 +#define XK_Terminate_Server 0xfed5 + +#define XK_AccessX_Enable 0xfe70 +#define XK_AccessX_Feedback_Enable 0xfe71 +#define XK_RepeatKeys_Enable 0xfe72 +#define XK_SlowKeys_Enable 0xfe73 +#define XK_BounceKeys_Enable 0xfe74 +#define XK_StickyKeys_Enable 0xfe75 +#define XK_MouseKeys_Enable 0xfe76 +#define XK_MouseKeys_Accel_Enable 0xfe77 +#define XK_Overlay1_Enable 0xfe78 +#define XK_Overlay2_Enable 0xfe79 +#define XK_AudibleBell_Enable 0xfe7a + +#define XK_Pointer_Left 0xfee0 +#define XK_Pointer_Right 0xfee1 +#define XK_Pointer_Up 0xfee2 +#define XK_Pointer_Down 0xfee3 +#define XK_Pointer_UpLeft 0xfee4 +#define XK_Pointer_UpRight 0xfee5 +#define XK_Pointer_DownLeft 0xfee6 +#define XK_Pointer_DownRight 0xfee7 +#define XK_Pointer_Button_Dflt 0xfee8 +#define XK_Pointer_Button1 0xfee9 +#define XK_Pointer_Button2 0xfeea +#define XK_Pointer_Button3 0xfeeb +#define XK_Pointer_Button4 0xfeec +#define XK_Pointer_Button5 0xfeed +#define XK_Pointer_DblClick_Dflt 0xfeee +#define XK_Pointer_DblClick1 0xfeef +#define XK_Pointer_DblClick2 0xfef0 +#define XK_Pointer_DblClick3 0xfef1 +#define XK_Pointer_DblClick4 0xfef2 +#define XK_Pointer_DblClick5 0xfef3 +#define XK_Pointer_Drag_Dflt 0xfef4 +#define XK_Pointer_Drag1 0xfef5 +#define XK_Pointer_Drag2 0xfef6 +#define XK_Pointer_Drag3 0xfef7 +#define XK_Pointer_Drag4 0xfef8 +#define XK_Pointer_Drag5 0xfefd + +#define XK_Pointer_EnableKeys 0xfef9 +#define XK_Pointer_Accelerate 0xfefa +#define XK_Pointer_DfltBtnNext 0xfefb +#define XK_Pointer_DfltBtnPrev 0xfefc + +#endif /* XK_XKB_KEYS */ + +/* + * 3270 Terminal Keys + * Byte 3 = 0xfd + */ + +#ifdef XK_3270 +#define XK_3270_Duplicate 0xfd01 +#define XK_3270_FieldMark 0xfd02 +#define XK_3270_Right2 0xfd03 +#define XK_3270_Left2 0xfd04 +#define XK_3270_BackTab 0xfd05 +#define XK_3270_EraseEOF 0xfd06 +#define XK_3270_EraseInput 0xfd07 +#define XK_3270_Reset 0xfd08 +#define XK_3270_Quit 0xfd09 +#define XK_3270_PA1 0xfd0a +#define XK_3270_PA2 0xfd0b +#define XK_3270_PA3 0xfd0c +#define XK_3270_Test 0xfd0d +#define XK_3270_Attn 0xfd0e +#define XK_3270_CursorBlink 0xfd0f +#define XK_3270_AltCursor 0xfd10 +#define XK_3270_KeyClick 0xfd11 +#define XK_3270_Jump 0xfd12 +#define XK_3270_Ident 0xfd13 +#define XK_3270_Rule 0xfd14 +#define XK_3270_Copy 0xfd15 +#define XK_3270_Play 0xfd16 +#define XK_3270_Setup 0xfd17 +#define XK_3270_Record 0xfd18 +#define XK_3270_ChangeScreen 0xfd19 +#define XK_3270_DeleteWord 0xfd1a +#define XK_3270_ExSelect 0xfd1b +#define XK_3270_CursorSelect 0xfd1c +#define XK_3270_PrintScreen 0xfd1d +#define XK_3270_Enter 0xfd1e +#endif /* XK_3270 */ + +/* + * Latin 1 + * (ISO/IEC 8859-1 = Unicode U+0020..U+00FF) + * Byte 3 = 0 + */ +#ifdef XK_LATIN1 +#define XK_space 0x0020 /* U+0020 SPACE */ +#define XK_exclam 0x0021 /* U+0021 EXCLAMATION MARK */ +#define XK_quotedbl 0x0022 /* U+0022 QUOTATION MARK */ +#define XK_numbersign 0x0023 /* U+0023 NUMBER SIGN */ +#define XK_dollar 0x0024 /* U+0024 DOLLAR SIGN */ +#define XK_percent 0x0025 /* U+0025 PERCENT SIGN */ +#define XK_ampersand 0x0026 /* U+0026 AMPERSAND */ +#define XK_apostrophe 0x0027 /* U+0027 APOSTROPHE */ +#define XK_quoteright 0x0027 /* deprecated */ +#define XK_parenleft 0x0028 /* U+0028 LEFT PARENTHESIS */ +#define XK_parenright 0x0029 /* U+0029 RIGHT PARENTHESIS */ +#define XK_asterisk 0x002a /* U+002A ASTERISK */ +#define XK_plus 0x002b /* U+002B PLUS SIGN */ +#define XK_comma 0x002c /* U+002C COMMA */ +#define XK_minus 0x002d /* U+002D HYPHEN-MINUS */ +#define XK_period 0x002e /* U+002E FULL STOP */ +#define XK_slash 0x002f /* U+002F SOLIDUS */ +#define XK_0 0x0030 /* U+0030 DIGIT ZERO */ +#define XK_1 0x0031 /* U+0031 DIGIT ONE */ +#define XK_2 0x0032 /* U+0032 DIGIT TWO */ +#define XK_3 0x0033 /* U+0033 DIGIT THREE */ +#define XK_4 0x0034 /* U+0034 DIGIT FOUR */ +#define XK_5 0x0035 /* U+0035 DIGIT FIVE */ +#define XK_6 0x0036 /* U+0036 DIGIT SIX */ +#define XK_7 0x0037 /* U+0037 DIGIT SEVEN */ +#define XK_8 0x0038 /* U+0038 DIGIT EIGHT */ +#define XK_9 0x0039 /* U+0039 DIGIT NINE */ +#define XK_colon 0x003a /* U+003A COLON */ +#define XK_semicolon 0x003b /* U+003B SEMICOLON */ +#define XK_less 0x003c /* U+003C LESS-THAN SIGN */ +#define XK_equal 0x003d /* U+003D EQUALS SIGN */ +#define XK_greater 0x003e /* U+003E GREATER-THAN SIGN */ +#define XK_question 0x003f /* U+003F QUESTION MARK */ +#define XK_at 0x0040 /* U+0040 COMMERCIAL AT */ +#define XK_A 0x0041 /* U+0041 LATIN CAPITAL LETTER A */ +#define XK_B 0x0042 /* U+0042 LATIN CAPITAL LETTER B */ +#define XK_C 0x0043 /* U+0043 LATIN CAPITAL LETTER C */ +#define XK_D 0x0044 /* U+0044 LATIN CAPITAL LETTER D */ +#define XK_E 0x0045 /* U+0045 LATIN CAPITAL LETTER E */ +#define XK_F 0x0046 /* U+0046 LATIN CAPITAL LETTER F */ +#define XK_G 0x0047 /* U+0047 LATIN CAPITAL LETTER G */ +#define XK_H 0x0048 /* U+0048 LATIN CAPITAL LETTER H */ +#define XK_I 0x0049 /* U+0049 LATIN CAPITAL LETTER I */ +#define XK_J 0x004a /* U+004A LATIN CAPITAL LETTER J */ +#define XK_K 0x004b /* U+004B LATIN CAPITAL LETTER K */ +#define XK_L 0x004c /* U+004C LATIN CAPITAL LETTER L */ +#define XK_M 0x004d /* U+004D LATIN CAPITAL LETTER M */ +#define XK_N 0x004e /* U+004E LATIN CAPITAL LETTER N */ +#define XK_O 0x004f /* U+004F LATIN CAPITAL LETTER O */ +#define XK_P 0x0050 /* U+0050 LATIN CAPITAL LETTER P */ +#define XK_Q 0x0051 /* U+0051 LATIN CAPITAL LETTER Q */ +#define XK_R 0x0052 /* U+0052 LATIN CAPITAL LETTER R */ +#define XK_S 0x0053 /* U+0053 LATIN CAPITAL LETTER S */ +#define XK_T 0x0054 /* U+0054 LATIN CAPITAL LETTER T */ +#define XK_U 0x0055 /* U+0055 LATIN CAPITAL LETTER U */ +#define XK_V 0x0056 /* U+0056 LATIN CAPITAL LETTER V */ +#define XK_W 0x0057 /* U+0057 LATIN CAPITAL LETTER W */ +#define XK_X 0x0058 /* U+0058 LATIN CAPITAL LETTER X */ +#define XK_Y 0x0059 /* U+0059 LATIN CAPITAL LETTER Y */ +#define XK_Z 0x005a /* U+005A LATIN CAPITAL LETTER Z */ +#define XK_bracketleft 0x005b /* U+005B LEFT SQUARE BRACKET */ +#define XK_backslash 0x005c /* U+005C REVERSE SOLIDUS */ +#define XK_bracketright 0x005d /* U+005D RIGHT SQUARE BRACKET */ +#define XK_asciicircum 0x005e /* U+005E CIRCUMFLEX ACCENT */ +#define XK_underscore 0x005f /* U+005F LOW LINE */ +#define XK_grave 0x0060 /* U+0060 GRAVE ACCENT */ +#define XK_quoteleft 0x0060 /* deprecated */ +#define XK_a 0x0061 /* U+0061 LATIN SMALL LETTER A */ +#define XK_b 0x0062 /* U+0062 LATIN SMALL LETTER B */ +#define XK_c 0x0063 /* U+0063 LATIN SMALL LETTER C */ +#define XK_d 0x0064 /* U+0064 LATIN SMALL LETTER D */ +#define XK_e 0x0065 /* U+0065 LATIN SMALL LETTER E */ +#define XK_f 0x0066 /* U+0066 LATIN SMALL LETTER F */ +#define XK_g 0x0067 /* U+0067 LATIN SMALL LETTER G */ +#define XK_h 0x0068 /* U+0068 LATIN SMALL LETTER H */ +#define XK_i 0x0069 /* U+0069 LATIN SMALL LETTER I */ +#define XK_j 0x006a /* U+006A LATIN SMALL LETTER J */ +#define XK_k 0x006b /* U+006B LATIN SMALL LETTER K */ +#define XK_l 0x006c /* U+006C LATIN SMALL LETTER L */ +#define XK_m 0x006d /* U+006D LATIN SMALL LETTER M */ +#define XK_n 0x006e /* U+006E LATIN SMALL LETTER N */ +#define XK_o 0x006f /* U+006F LATIN SMALL LETTER O */ +#define XK_p 0x0070 /* U+0070 LATIN SMALL LETTER P */ +#define XK_q 0x0071 /* U+0071 LATIN SMALL LETTER Q */ +#define XK_r 0x0072 /* U+0072 LATIN SMALL LETTER R */ +#define XK_s 0x0073 /* U+0073 LATIN SMALL LETTER S */ +#define XK_t 0x0074 /* U+0074 LATIN SMALL LETTER T */ +#define XK_u 0x0075 /* U+0075 LATIN SMALL LETTER U */ +#define XK_v 0x0076 /* U+0076 LATIN SMALL LETTER V */ +#define XK_w 0x0077 /* U+0077 LATIN SMALL LETTER W */ +#define XK_x 0x0078 /* U+0078 LATIN SMALL LETTER X */ +#define XK_y 0x0079 /* U+0079 LATIN SMALL LETTER Y */ +#define XK_z 0x007a /* U+007A LATIN SMALL LETTER Z */ +#define XK_braceleft 0x007b /* U+007B LEFT CURLY BRACKET */ +#define XK_bar 0x007c /* U+007C VERTICAL LINE */ +#define XK_braceright 0x007d /* U+007D RIGHT CURLY BRACKET */ +#define XK_asciitilde 0x007e /* U+007E TILDE */ + +#define XK_nobreakspace 0x00a0 /* U+00A0 NO-BREAK SPACE */ +#define XK_exclamdown 0x00a1 /* U+00A1 INVERTED EXCLAMATION MARK */ +#define XK_cent 0x00a2 /* U+00A2 CENT SIGN */ +#define XK_sterling 0x00a3 /* U+00A3 POUND SIGN */ +#define XK_currency 0x00a4 /* U+00A4 CURRENCY SIGN */ +#define XK_yen 0x00a5 /* U+00A5 YEN SIGN */ +#define XK_brokenbar 0x00a6 /* U+00A6 BROKEN BAR */ +#define XK_section 0x00a7 /* U+00A7 SECTION SIGN */ +#define XK_diaeresis 0x00a8 /* U+00A8 DIAERESIS */ +#define XK_copyright 0x00a9 /* U+00A9 COPYRIGHT SIGN */ +#define XK_ordfeminine 0x00aa /* U+00AA FEMININE ORDINAL INDICATOR */ +#define XK_guillemotleft 0x00ab /* U+00AB LEFT-POINTING DOUBLE ANGLE QUOTATION MARK */ +#define XK_notsign 0x00ac /* U+00AC NOT SIGN */ +#define XK_hyphen 0x00ad /* U+00AD SOFT HYPHEN */ +#define XK_registered 0x00ae /* U+00AE REGISTERED SIGN */ +#define XK_macron 0x00af /* U+00AF MACRON */ +#define XK_degree 0x00b0 /* U+00B0 DEGREE SIGN */ +#define XK_plusminus 0x00b1 /* U+00B1 PLUS-MINUS SIGN */ +#define XK_twosuperior 0x00b2 /* U+00B2 SUPERSCRIPT TWO */ +#define XK_threesuperior 0x00b3 /* U+00B3 SUPERSCRIPT THREE */ +#define XK_acute 0x00b4 /* U+00B4 ACUTE ACCENT */ +#define XK_mu 0x00b5 /* U+00B5 MICRO SIGN */ +#define XK_paragraph 0x00b6 /* U+00B6 PILCROW SIGN */ +#define XK_periodcentered 0x00b7 /* U+00B7 MIDDLE DOT */ +#define XK_cedilla 0x00b8 /* U+00B8 CEDILLA */ +#define XK_onesuperior 0x00b9 /* U+00B9 SUPERSCRIPT ONE */ +#define XK_masculine 0x00ba /* U+00BA MASCULINE ORDINAL INDICATOR */ +#define XK_guillemotright 0x00bb /* U+00BB RIGHT-POINTING DOUBLE ANGLE QUOTATION MARK */ +#define XK_onequarter 0x00bc /* U+00BC VULGAR FRACTION ONE QUARTER */ +#define XK_onehalf 0x00bd /* U+00BD VULGAR FRACTION ONE HALF */ +#define XK_threequarters 0x00be /* U+00BE VULGAR FRACTION THREE QUARTERS */ +#define XK_questiondown 0x00bf /* U+00BF INVERTED QUESTION MARK */ +#define XK_Agrave 0x00c0 /* U+00C0 LATIN CAPITAL LETTER A WITH GRAVE */ +#define XK_Aacute 0x00c1 /* U+00C1 LATIN CAPITAL LETTER A WITH ACUTE */ +#define XK_Acircumflex 0x00c2 /* U+00C2 LATIN CAPITAL LETTER A WITH CIRCUMFLEX */ +#define XK_Atilde 0x00c3 /* U+00C3 LATIN CAPITAL LETTER A WITH TILDE */ +#define XK_Adiaeresis 0x00c4 /* U+00C4 LATIN CAPITAL LETTER A WITH DIAERESIS */ +#define XK_Aring 0x00c5 /* U+00C5 LATIN CAPITAL LETTER A WITH RING ABOVE */ +#define XK_AE 0x00c6 /* U+00C6 LATIN CAPITAL LETTER AE */ +#define XK_Ccedilla 0x00c7 /* U+00C7 LATIN CAPITAL LETTER C WITH CEDILLA */ +#define XK_Egrave 0x00c8 /* U+00C8 LATIN CAPITAL LETTER E WITH GRAVE */ +#define XK_Eacute 0x00c9 /* U+00C9 LATIN CAPITAL LETTER E WITH ACUTE */ +#define XK_Ecircumflex 0x00ca /* U+00CA LATIN CAPITAL LETTER E WITH CIRCUMFLEX */ +#define XK_Ediaeresis 0x00cb /* U+00CB LATIN CAPITAL LETTER E WITH DIAERESIS */ +#define XK_Igrave 0x00cc /* U+00CC LATIN CAPITAL LETTER I WITH GRAVE */ +#define XK_Iacute 0x00cd /* U+00CD LATIN CAPITAL LETTER I WITH ACUTE */ +#define XK_Icircumflex 0x00ce /* U+00CE LATIN CAPITAL LETTER I WITH CIRCUMFLEX */ +#define XK_Idiaeresis 0x00cf /* U+00CF LATIN CAPITAL LETTER I WITH DIAERESIS */ +#define XK_ETH 0x00d0 /* U+00D0 LATIN CAPITAL LETTER ETH */ +#define XK_Eth 0x00d0 /* deprecated */ +#define XK_Ntilde 0x00d1 /* U+00D1 LATIN CAPITAL LETTER N WITH TILDE */ +#define XK_Ograve 0x00d2 /* U+00D2 LATIN CAPITAL LETTER O WITH GRAVE */ +#define XK_Oacute 0x00d3 /* U+00D3 LATIN CAPITAL LETTER O WITH ACUTE */ +#define XK_Ocircumflex 0x00d4 /* U+00D4 LATIN CAPITAL LETTER O WITH CIRCUMFLEX */ +#define XK_Otilde 0x00d5 /* U+00D5 LATIN CAPITAL LETTER O WITH TILDE */ +#define XK_Odiaeresis 0x00d6 /* U+00D6 LATIN CAPITAL LETTER O WITH DIAERESIS */ +#define XK_multiply 0x00d7 /* U+00D7 MULTIPLICATION SIGN */ +#define XK_Oslash 0x00d8 /* U+00D8 LATIN CAPITAL LETTER O WITH STROKE */ +#define XK_Ooblique 0x00d8 /* U+00D8 LATIN CAPITAL LETTER O WITH STROKE */ +#define XK_Ugrave 0x00d9 /* U+00D9 LATIN CAPITAL LETTER U WITH GRAVE */ +#define XK_Uacute 0x00da /* U+00DA LATIN CAPITAL LETTER U WITH ACUTE */ +#define XK_Ucircumflex 0x00db /* U+00DB LATIN CAPITAL LETTER U WITH CIRCUMFLEX */ +#define XK_Udiaeresis 0x00dc /* U+00DC LATIN CAPITAL LETTER U WITH DIAERESIS */ +#define XK_Yacute 0x00dd /* U+00DD LATIN CAPITAL LETTER Y WITH ACUTE */ +#define XK_THORN 0x00de /* U+00DE LATIN CAPITAL LETTER THORN */ +#define XK_Thorn 0x00de /* deprecated */ +#define XK_ssharp 0x00df /* U+00DF LATIN SMALL LETTER SHARP S */ +#define XK_agrave 0x00e0 /* U+00E0 LATIN SMALL LETTER A WITH GRAVE */ +#define XK_aacute 0x00e1 /* U+00E1 LATIN SMALL LETTER A WITH ACUTE */ +#define XK_acircumflex 0x00e2 /* U+00E2 LATIN SMALL LETTER A WITH CIRCUMFLEX */ +#define XK_atilde 0x00e3 /* U+00E3 LATIN SMALL LETTER A WITH TILDE */ +#define XK_adiaeresis 0x00e4 /* U+00E4 LATIN SMALL LETTER A WITH DIAERESIS */ +#define XK_aring 0x00e5 /* U+00E5 LATIN SMALL LETTER A WITH RING ABOVE */ +#define XK_ae 0x00e6 /* U+00E6 LATIN SMALL LETTER AE */ +#define XK_ccedilla 0x00e7 /* U+00E7 LATIN SMALL LETTER C WITH CEDILLA */ +#define XK_egrave 0x00e8 /* U+00E8 LATIN SMALL LETTER E WITH GRAVE */ +#define XK_eacute 0x00e9 /* U+00E9 LATIN SMALL LETTER E WITH ACUTE */ +#define XK_ecircumflex 0x00ea /* U+00EA LATIN SMALL LETTER E WITH CIRCUMFLEX */ +#define XK_ediaeresis 0x00eb /* U+00EB LATIN SMALL LETTER E WITH DIAERESIS */ +#define XK_igrave 0x00ec /* U+00EC LATIN SMALL LETTER I WITH GRAVE */ +#define XK_iacute 0x00ed /* U+00ED LATIN SMALL LETTER I WITH ACUTE */ +#define XK_icircumflex 0x00ee /* U+00EE LATIN SMALL LETTER I WITH CIRCUMFLEX */ +#define XK_idiaeresis 0x00ef /* U+00EF LATIN SMALL LETTER I WITH DIAERESIS */ +#define XK_eth 0x00f0 /* U+00F0 LATIN SMALL LETTER ETH */ +#define XK_ntilde 0x00f1 /* U+00F1 LATIN SMALL LETTER N WITH TILDE */ +#define XK_ograve 0x00f2 /* U+00F2 LATIN SMALL LETTER O WITH GRAVE */ +#define XK_oacute 0x00f3 /* U+00F3 LATIN SMALL LETTER O WITH ACUTE */ +#define XK_ocircumflex 0x00f4 /* U+00F4 LATIN SMALL LETTER O WITH CIRCUMFLEX */ +#define XK_otilde 0x00f5 /* U+00F5 LATIN SMALL LETTER O WITH TILDE */ +#define XK_odiaeresis 0x00f6 /* U+00F6 LATIN SMALL LETTER O WITH DIAERESIS */ +#define XK_division 0x00f7 /* U+00F7 DIVISION SIGN */ +#define XK_oslash 0x00f8 /* U+00F8 LATIN SMALL LETTER O WITH STROKE */ +#define XK_ooblique 0x00f8 /* U+00F8 LATIN SMALL LETTER O WITH STROKE */ +#define XK_ugrave 0x00f9 /* U+00F9 LATIN SMALL LETTER U WITH GRAVE */ +#define XK_uacute 0x00fa /* U+00FA LATIN SMALL LETTER U WITH ACUTE */ +#define XK_ucircumflex 0x00fb /* U+00FB LATIN SMALL LETTER U WITH CIRCUMFLEX */ +#define XK_udiaeresis 0x00fc /* U+00FC LATIN SMALL LETTER U WITH DIAERESIS */ +#define XK_yacute 0x00fd /* U+00FD LATIN SMALL LETTER Y WITH ACUTE */ +#define XK_thorn 0x00fe /* U+00FE LATIN SMALL LETTER THORN */ +#define XK_ydiaeresis 0x00ff /* U+00FF LATIN SMALL LETTER Y WITH DIAERESIS */ +#endif /* XK_LATIN1 */ + +/* + * Latin 2 + * Byte 3 = 1 + */ + +#ifdef XK_LATIN2 +#define XK_Aogonek 0x01a1 /* U+0104 LATIN CAPITAL LETTER A WITH OGONEK */ +#define XK_breve 0x01a2 /* U+02D8 BREVE */ +#define XK_Lstroke 0x01a3 /* U+0141 LATIN CAPITAL LETTER L WITH STROKE */ +#define XK_Lcaron 0x01a5 /* U+013D LATIN CAPITAL LETTER L WITH CARON */ +#define XK_Sacute 0x01a6 /* U+015A LATIN CAPITAL LETTER S WITH ACUTE */ +#define XK_Scaron 0x01a9 /* U+0160 LATIN CAPITAL LETTER S WITH CARON */ +#define XK_Scedilla 0x01aa /* U+015E LATIN CAPITAL LETTER S WITH CEDILLA */ +#define XK_Tcaron 0x01ab /* U+0164 LATIN CAPITAL LETTER T WITH CARON */ +#define XK_Zacute 0x01ac /* U+0179 LATIN CAPITAL LETTER Z WITH ACUTE */ +#define XK_Zcaron 0x01ae /* U+017D LATIN CAPITAL LETTER Z WITH CARON */ +#define XK_Zabovedot 0x01af /* U+017B LATIN CAPITAL LETTER Z WITH DOT ABOVE */ +#define XK_aogonek 0x01b1 /* U+0105 LATIN SMALL LETTER A WITH OGONEK */ +#define XK_ogonek 0x01b2 /* U+02DB OGONEK */ +#define XK_lstroke 0x01b3 /* U+0142 LATIN SMALL LETTER L WITH STROKE */ +#define XK_lcaron 0x01b5 /* U+013E LATIN SMALL LETTER L WITH CARON */ +#define XK_sacute 0x01b6 /* U+015B LATIN SMALL LETTER S WITH ACUTE */ +#define XK_caron 0x01b7 /* U+02C7 CARON */ +#define XK_scaron 0x01b9 /* U+0161 LATIN SMALL LETTER S WITH CARON */ +#define XK_scedilla 0x01ba /* U+015F LATIN SMALL LETTER S WITH CEDILLA */ +#define XK_tcaron 0x01bb /* U+0165 LATIN SMALL LETTER T WITH CARON */ +#define XK_zacute 0x01bc /* U+017A LATIN SMALL LETTER Z WITH ACUTE */ +#define XK_doubleacute 0x01bd /* U+02DD DOUBLE ACUTE ACCENT */ +#define XK_zcaron 0x01be /* U+017E LATIN SMALL LETTER Z WITH CARON */ +#define XK_zabovedot 0x01bf /* U+017C LATIN SMALL LETTER Z WITH DOT ABOVE */ +#define XK_Racute 0x01c0 /* U+0154 LATIN CAPITAL LETTER R WITH ACUTE */ +#define XK_Abreve 0x01c3 /* U+0102 LATIN CAPITAL LETTER A WITH BREVE */ +#define XK_Lacute 0x01c5 /* U+0139 LATIN CAPITAL LETTER L WITH ACUTE */ +#define XK_Cacute 0x01c6 /* U+0106 LATIN CAPITAL LETTER C WITH ACUTE */ +#define XK_Ccaron 0x01c8 /* U+010C LATIN CAPITAL LETTER C WITH CARON */ +#define XK_Eogonek 0x01ca /* U+0118 LATIN CAPITAL LETTER E WITH OGONEK */ +#define XK_Ecaron 0x01cc /* U+011A LATIN CAPITAL LETTER E WITH CARON */ +#define XK_Dcaron 0x01cf /* U+010E LATIN CAPITAL LETTER D WITH CARON */ +#define XK_Dstroke 0x01d0 /* U+0110 LATIN CAPITAL LETTER D WITH STROKE */ +#define XK_Nacute 0x01d1 /* U+0143 LATIN CAPITAL LETTER N WITH ACUTE */ +#define XK_Ncaron 0x01d2 /* U+0147 LATIN CAPITAL LETTER N WITH CARON */ +#define XK_Odoubleacute 0x01d5 /* U+0150 LATIN CAPITAL LETTER O WITH DOUBLE ACUTE */ +#define XK_Rcaron 0x01d8 /* U+0158 LATIN CAPITAL LETTER R WITH CARON */ +#define XK_Uring 0x01d9 /* U+016E LATIN CAPITAL LETTER U WITH RING ABOVE */ +#define XK_Udoubleacute 0x01db /* U+0170 LATIN CAPITAL LETTER U WITH DOUBLE ACUTE */ +#define XK_Tcedilla 0x01de /* U+0162 LATIN CAPITAL LETTER T WITH CEDILLA */ +#define XK_racute 0x01e0 /* U+0155 LATIN SMALL LETTER R WITH ACUTE */ +#define XK_abreve 0x01e3 /* U+0103 LATIN SMALL LETTER A WITH BREVE */ +#define XK_lacute 0x01e5 /* U+013A LATIN SMALL LETTER L WITH ACUTE */ +#define XK_cacute 0x01e6 /* U+0107 LATIN SMALL LETTER C WITH ACUTE */ +#define XK_ccaron 0x01e8 /* U+010D LATIN SMALL LETTER C WITH CARON */ +#define XK_eogonek 0x01ea /* U+0119 LATIN SMALL LETTER E WITH OGONEK */ +#define XK_ecaron 0x01ec /* U+011B LATIN SMALL LETTER E WITH CARON */ +#define XK_dcaron 0x01ef /* U+010F LATIN SMALL LETTER D WITH CARON */ +#define XK_dstroke 0x01f0 /* U+0111 LATIN SMALL LETTER D WITH STROKE */ +#define XK_nacute 0x01f1 /* U+0144 LATIN SMALL LETTER N WITH ACUTE */ +#define XK_ncaron 0x01f2 /* U+0148 LATIN SMALL LETTER N WITH CARON */ +#define XK_odoubleacute 0x01f5 /* U+0151 LATIN SMALL LETTER O WITH DOUBLE ACUTE */ +#define XK_udoubleacute 0x01fb /* U+0171 LATIN SMALL LETTER U WITH DOUBLE ACUTE */ +#define XK_rcaron 0x01f8 /* U+0159 LATIN SMALL LETTER R WITH CARON */ +#define XK_uring 0x01f9 /* U+016F LATIN SMALL LETTER U WITH RING ABOVE */ +#define XK_tcedilla 0x01fe /* U+0163 LATIN SMALL LETTER T WITH CEDILLA */ +#define XK_abovedot 0x01ff /* U+02D9 DOT ABOVE */ +#endif /* XK_LATIN2 */ + +/* + * Latin 3 + * Byte 3 = 2 + */ + +#ifdef XK_LATIN3 +#define XK_Hstroke 0x02a1 /* U+0126 LATIN CAPITAL LETTER H WITH STROKE */ +#define XK_Hcircumflex 0x02a6 /* U+0124 LATIN CAPITAL LETTER H WITH CIRCUMFLEX */ +#define XK_Iabovedot 0x02a9 /* U+0130 LATIN CAPITAL LETTER I WITH DOT ABOVE */ +#define XK_Gbreve 0x02ab /* U+011E LATIN CAPITAL LETTER G WITH BREVE */ +#define XK_Jcircumflex 0x02ac /* U+0134 LATIN CAPITAL LETTER J WITH CIRCUMFLEX */ +#define XK_hstroke 0x02b1 /* U+0127 LATIN SMALL LETTER H WITH STROKE */ +#define XK_hcircumflex 0x02b6 /* U+0125 LATIN SMALL LETTER H WITH CIRCUMFLEX */ +#define XK_idotless 0x02b9 /* U+0131 LATIN SMALL LETTER DOTLESS I */ +#define XK_gbreve 0x02bb /* U+011F LATIN SMALL LETTER G WITH BREVE */ +#define XK_jcircumflex 0x02bc /* U+0135 LATIN SMALL LETTER J WITH CIRCUMFLEX */ +#define XK_Cabovedot 0x02c5 /* U+010A LATIN CAPITAL LETTER C WITH DOT ABOVE */ +#define XK_Ccircumflex 0x02c6 /* U+0108 LATIN CAPITAL LETTER C WITH CIRCUMFLEX */ +#define XK_Gabovedot 0x02d5 /* U+0120 LATIN CAPITAL LETTER G WITH DOT ABOVE */ +#define XK_Gcircumflex 0x02d8 /* U+011C LATIN CAPITAL LETTER G WITH CIRCUMFLEX */ +#define XK_Ubreve 0x02dd /* U+016C LATIN CAPITAL LETTER U WITH BREVE */ +#define XK_Scircumflex 0x02de /* U+015C LATIN CAPITAL LETTER S WITH CIRCUMFLEX */ +#define XK_cabovedot 0x02e5 /* U+010B LATIN SMALL LETTER C WITH DOT ABOVE */ +#define XK_ccircumflex 0x02e6 /* U+0109 LATIN SMALL LETTER C WITH CIRCUMFLEX */ +#define XK_gabovedot 0x02f5 /* U+0121 LATIN SMALL LETTER G WITH DOT ABOVE */ +#define XK_gcircumflex 0x02f8 /* U+011D LATIN SMALL LETTER G WITH CIRCUMFLEX */ +#define XK_ubreve 0x02fd /* U+016D LATIN SMALL LETTER U WITH BREVE */ +#define XK_scircumflex 0x02fe /* U+015D LATIN SMALL LETTER S WITH CIRCUMFLEX */ +#endif /* XK_LATIN3 */ + + +/* + * Latin 4 + * Byte 3 = 3 + */ + +#ifdef XK_LATIN4 +#define XK_kra 0x03a2 /* U+0138 LATIN SMALL LETTER KRA */ +#define XK_kappa 0x03a2 /* deprecated */ +#define XK_Rcedilla 0x03a3 /* U+0156 LATIN CAPITAL LETTER R WITH CEDILLA */ +#define XK_Itilde 0x03a5 /* U+0128 LATIN CAPITAL LETTER I WITH TILDE */ +#define XK_Lcedilla 0x03a6 /* U+013B LATIN CAPITAL LETTER L WITH CEDILLA */ +#define XK_Emacron 0x03aa /* U+0112 LATIN CAPITAL LETTER E WITH MACRON */ +#define XK_Gcedilla 0x03ab /* U+0122 LATIN CAPITAL LETTER G WITH CEDILLA */ +#define XK_Tslash 0x03ac /* U+0166 LATIN CAPITAL LETTER T WITH STROKE */ +#define XK_rcedilla 0x03b3 /* U+0157 LATIN SMALL LETTER R WITH CEDILLA */ +#define XK_itilde 0x03b5 /* U+0129 LATIN SMALL LETTER I WITH TILDE */ +#define XK_lcedilla 0x03b6 /* U+013C LATIN SMALL LETTER L WITH CEDILLA */ +#define XK_emacron 0x03ba /* U+0113 LATIN SMALL LETTER E WITH MACRON */ +#define XK_gcedilla 0x03bb /* U+0123 LATIN SMALL LETTER G WITH CEDILLA */ +#define XK_tslash 0x03bc /* U+0167 LATIN SMALL LETTER T WITH STROKE */ +#define XK_ENG 0x03bd /* U+014A LATIN CAPITAL LETTER ENG */ +#define XK_eng 0x03bf /* U+014B LATIN SMALL LETTER ENG */ +#define XK_Amacron 0x03c0 /* U+0100 LATIN CAPITAL LETTER A WITH MACRON */ +#define XK_Iogonek 0x03c7 /* U+012E LATIN CAPITAL LETTER I WITH OGONEK */ +#define XK_Eabovedot 0x03cc /* U+0116 LATIN CAPITAL LETTER E WITH DOT ABOVE */ +#define XK_Imacron 0x03cf /* U+012A LATIN CAPITAL LETTER I WITH MACRON */ +#define XK_Ncedilla 0x03d1 /* U+0145 LATIN CAPITAL LETTER N WITH CEDILLA */ +#define XK_Omacron 0x03d2 /* U+014C LATIN CAPITAL LETTER O WITH MACRON */ +#define XK_Kcedilla 0x03d3 /* U+0136 LATIN CAPITAL LETTER K WITH CEDILLA */ +#define XK_Uogonek 0x03d9 /* U+0172 LATIN CAPITAL LETTER U WITH OGONEK */ +#define XK_Utilde 0x03dd /* U+0168 LATIN CAPITAL LETTER U WITH TILDE */ +#define XK_Umacron 0x03de /* U+016A LATIN CAPITAL LETTER U WITH MACRON */ +#define XK_amacron 0x03e0 /* U+0101 LATIN SMALL LETTER A WITH MACRON */ +#define XK_iogonek 0x03e7 /* U+012F LATIN SMALL LETTER I WITH OGONEK */ +#define XK_eabovedot 0x03ec /* U+0117 LATIN SMALL LETTER E WITH DOT ABOVE */ +#define XK_imacron 0x03ef /* U+012B LATIN SMALL LETTER I WITH MACRON */ +#define XK_ncedilla 0x03f1 /* U+0146 LATIN SMALL LETTER N WITH CEDILLA */ +#define XK_omacron 0x03f2 /* U+014D LATIN SMALL LETTER O WITH MACRON */ +#define XK_kcedilla 0x03f3 /* U+0137 LATIN SMALL LETTER K WITH CEDILLA */ +#define XK_uogonek 0x03f9 /* U+0173 LATIN SMALL LETTER U WITH OGONEK */ +#define XK_utilde 0x03fd /* U+0169 LATIN SMALL LETTER U WITH TILDE */ +#define XK_umacron 0x03fe /* U+016B LATIN SMALL LETTER U WITH MACRON */ +#endif /* XK_LATIN4 */ + +/* + * Latin 8 + */ +#ifdef XK_LATIN8 +#define XK_Babovedot 0x1001e02 /* U+1E02 LATIN CAPITAL LETTER B WITH DOT ABOVE */ +#define XK_babovedot 0x1001e03 /* U+1E03 LATIN SMALL LETTER B WITH DOT ABOVE */ +#define XK_Dabovedot 0x1001e0a /* U+1E0A LATIN CAPITAL LETTER D WITH DOT ABOVE */ +#define XK_Wgrave 0x1001e80 /* U+1E80 LATIN CAPITAL LETTER W WITH GRAVE */ +#define XK_Wacute 0x1001e82 /* U+1E82 LATIN CAPITAL LETTER W WITH ACUTE */ +#define XK_dabovedot 0x1001e0b /* U+1E0B LATIN SMALL LETTER D WITH DOT ABOVE */ +#define XK_Ygrave 0x1001ef2 /* U+1EF2 LATIN CAPITAL LETTER Y WITH GRAVE */ +#define XK_Fabovedot 0x1001e1e /* U+1E1E LATIN CAPITAL LETTER F WITH DOT ABOVE */ +#define XK_fabovedot 0x1001e1f /* U+1E1F LATIN SMALL LETTER F WITH DOT ABOVE */ +#define XK_Mabovedot 0x1001e40 /* U+1E40 LATIN CAPITAL LETTER M WITH DOT ABOVE */ +#define XK_mabovedot 0x1001e41 /* U+1E41 LATIN SMALL LETTER M WITH DOT ABOVE */ +#define XK_Pabovedot 0x1001e56 /* U+1E56 LATIN CAPITAL LETTER P WITH DOT ABOVE */ +#define XK_wgrave 0x1001e81 /* U+1E81 LATIN SMALL LETTER W WITH GRAVE */ +#define XK_pabovedot 0x1001e57 /* U+1E57 LATIN SMALL LETTER P WITH DOT ABOVE */ +#define XK_wacute 0x1001e83 /* U+1E83 LATIN SMALL LETTER W WITH ACUTE */ +#define XK_Sabovedot 0x1001e60 /* U+1E60 LATIN CAPITAL LETTER S WITH DOT ABOVE */ +#define XK_ygrave 0x1001ef3 /* U+1EF3 LATIN SMALL LETTER Y WITH GRAVE */ +#define XK_Wdiaeresis 0x1001e84 /* U+1E84 LATIN CAPITAL LETTER W WITH DIAERESIS */ +#define XK_wdiaeresis 0x1001e85 /* U+1E85 LATIN SMALL LETTER W WITH DIAERESIS */ +#define XK_sabovedot 0x1001e61 /* U+1E61 LATIN SMALL LETTER S WITH DOT ABOVE */ +#define XK_Wcircumflex 0x1000174 /* U+0174 LATIN CAPITAL LETTER W WITH CIRCUMFLEX */ +#define XK_Tabovedot 0x1001e6a /* U+1E6A LATIN CAPITAL LETTER T WITH DOT ABOVE */ +#define XK_Ycircumflex 0x1000176 /* U+0176 LATIN CAPITAL LETTER Y WITH CIRCUMFLEX */ +#define XK_wcircumflex 0x1000175 /* U+0175 LATIN SMALL LETTER W WITH CIRCUMFLEX */ +#define XK_tabovedot 0x1001e6b /* U+1E6B LATIN SMALL LETTER T WITH DOT ABOVE */ +#define XK_ycircumflex 0x1000177 /* U+0177 LATIN SMALL LETTER Y WITH CIRCUMFLEX */ +#endif /* XK_LATIN8 */ + +/* + * Latin 9 + * Byte 3 = 0x13 + */ + +#ifdef XK_LATIN9 +#define XK_OE 0x13bc /* U+0152 LATIN CAPITAL LIGATURE OE */ +#define XK_oe 0x13bd /* U+0153 LATIN SMALL LIGATURE OE */ +#define XK_Ydiaeresis 0x13be /* U+0178 LATIN CAPITAL LETTER Y WITH DIAERESIS */ +#endif /* XK_LATIN9 */ + +/* + * Katakana + * Byte 3 = 4 + */ + +#ifdef XK_KATAKANA +#define XK_overline 0x047e /* U+203E OVERLINE */ +#define XK_kana_fullstop 0x04a1 /* U+3002 IDEOGRAPHIC FULL STOP */ +#define XK_kana_openingbracket 0x04a2 /* U+300C LEFT CORNER BRACKET */ +#define XK_kana_closingbracket 0x04a3 /* U+300D RIGHT CORNER BRACKET */ +#define XK_kana_comma 0x04a4 /* U+3001 IDEOGRAPHIC COMMA */ +#define XK_kana_conjunctive 0x04a5 /* U+30FB KATAKANA MIDDLE DOT */ +#define XK_kana_middledot 0x04a5 /* deprecated */ +#define XK_kana_WO 0x04a6 /* U+30F2 KATAKANA LETTER WO */ +#define XK_kana_a 0x04a7 /* U+30A1 KATAKANA LETTER SMALL A */ +#define XK_kana_i 0x04a8 /* U+30A3 KATAKANA LETTER SMALL I */ +#define XK_kana_u 0x04a9 /* U+30A5 KATAKANA LETTER SMALL U */ +#define XK_kana_e 0x04aa /* U+30A7 KATAKANA LETTER SMALL E */ +#define XK_kana_o 0x04ab /* U+30A9 KATAKANA LETTER SMALL O */ +#define XK_kana_ya 0x04ac /* U+30E3 KATAKANA LETTER SMALL YA */ +#define XK_kana_yu 0x04ad /* U+30E5 KATAKANA LETTER SMALL YU */ +#define XK_kana_yo 0x04ae /* U+30E7 KATAKANA LETTER SMALL YO */ +#define XK_kana_tsu 0x04af /* U+30C3 KATAKANA LETTER SMALL TU */ +#define XK_kana_tu 0x04af /* deprecated */ +#define XK_prolongedsound 0x04b0 /* U+30FC KATAKANA-HIRAGANA PROLONGED SOUND MARK */ +#define XK_kana_A 0x04b1 /* U+30A2 KATAKANA LETTER A */ +#define XK_kana_I 0x04b2 /* U+30A4 KATAKANA LETTER I */ +#define XK_kana_U 0x04b3 /* U+30A6 KATAKANA LETTER U */ +#define XK_kana_E 0x04b4 /* U+30A8 KATAKANA LETTER E */ +#define XK_kana_O 0x04b5 /* U+30AA KATAKANA LETTER O */ +#define XK_kana_KA 0x04b6 /* U+30AB KATAKANA LETTER KA */ +#define XK_kana_KI 0x04b7 /* U+30AD KATAKANA LETTER KI */ +#define XK_kana_KU 0x04b8 /* U+30AF KATAKANA LETTER KU */ +#define XK_kana_KE 0x04b9 /* U+30B1 KATAKANA LETTER KE */ +#define XK_kana_KO 0x04ba /* U+30B3 KATAKANA LETTER KO */ +#define XK_kana_SA 0x04bb /* U+30B5 KATAKANA LETTER SA */ +#define XK_kana_SHI 0x04bc /* U+30B7 KATAKANA LETTER SI */ +#define XK_kana_SU 0x04bd /* U+30B9 KATAKANA LETTER SU */ +#define XK_kana_SE 0x04be /* U+30BB KATAKANA LETTER SE */ +#define XK_kana_SO 0x04bf /* U+30BD KATAKANA LETTER SO */ +#define XK_kana_TA 0x04c0 /* U+30BF KATAKANA LETTER TA */ +#define XK_kana_CHI 0x04c1 /* U+30C1 KATAKANA LETTER TI */ +#define XK_kana_TI 0x04c1 /* deprecated */ +#define XK_kana_TSU 0x04c2 /* U+30C4 KATAKANA LETTER TU */ +#define XK_kana_TU 0x04c2 /* deprecated */ +#define XK_kana_TE 0x04c3 /* U+30C6 KATAKANA LETTER TE */ +#define XK_kana_TO 0x04c4 /* U+30C8 KATAKANA LETTER TO */ +#define XK_kana_NA 0x04c5 /* U+30CA KATAKANA LETTER NA */ +#define XK_kana_NI 0x04c6 /* U+30CB KATAKANA LETTER NI */ +#define XK_kana_NU 0x04c7 /* U+30CC KATAKANA LETTER NU */ +#define XK_kana_NE 0x04c8 /* U+30CD KATAKANA LETTER NE */ +#define XK_kana_NO 0x04c9 /* U+30CE KATAKANA LETTER NO */ +#define XK_kana_HA 0x04ca /* U+30CF KATAKANA LETTER HA */ +#define XK_kana_HI 0x04cb /* U+30D2 KATAKANA LETTER HI */ +#define XK_kana_FU 0x04cc /* U+30D5 KATAKANA LETTER HU */ +#define XK_kana_HU 0x04cc /* deprecated */ +#define XK_kana_HE 0x04cd /* U+30D8 KATAKANA LETTER HE */ +#define XK_kana_HO 0x04ce /* U+30DB KATAKANA LETTER HO */ +#define XK_kana_MA 0x04cf /* U+30DE KATAKANA LETTER MA */ +#define XK_kana_MI 0x04d0 /* U+30DF KATAKANA LETTER MI */ +#define XK_kana_MU 0x04d1 /* U+30E0 KATAKANA LETTER MU */ +#define XK_kana_ME 0x04d2 /* U+30E1 KATAKANA LETTER ME */ +#define XK_kana_MO 0x04d3 /* U+30E2 KATAKANA LETTER MO */ +#define XK_kana_YA 0x04d4 /* U+30E4 KATAKANA LETTER YA */ +#define XK_kana_YU 0x04d5 /* U+30E6 KATAKANA LETTER YU */ +#define XK_kana_YO 0x04d6 /* U+30E8 KATAKANA LETTER YO */ +#define XK_kana_RA 0x04d7 /* U+30E9 KATAKANA LETTER RA */ +#define XK_kana_RI 0x04d8 /* U+30EA KATAKANA LETTER RI */ +#define XK_kana_RU 0x04d9 /* U+30EB KATAKANA LETTER RU */ +#define XK_kana_RE 0x04da /* U+30EC KATAKANA LETTER RE */ +#define XK_kana_RO 0x04db /* U+30ED KATAKANA LETTER RO */ +#define XK_kana_WA 0x04dc /* U+30EF KATAKANA LETTER WA */ +#define XK_kana_N 0x04dd /* U+30F3 KATAKANA LETTER N */ +#define XK_voicedsound 0x04de /* U+309B KATAKANA-HIRAGANA VOICED SOUND MARK */ +#define XK_semivoicedsound 0x04df /* U+309C KATAKANA-HIRAGANA SEMI-VOICED SOUND MARK */ +#define XK_kana_switch 0xff7e /* Alias for mode_switch */ +#endif /* XK_KATAKANA */ + +/* + * Arabic + * Byte 3 = 5 + */ + +#ifdef XK_ARABIC +#define XK_Farsi_0 0x10006f0 /* U+06F0 EXTENDED ARABIC-INDIC DIGIT ZERO */ +#define XK_Farsi_1 0x10006f1 /* U+06F1 EXTENDED ARABIC-INDIC DIGIT ONE */ +#define XK_Farsi_2 0x10006f2 /* U+06F2 EXTENDED ARABIC-INDIC DIGIT TWO */ +#define XK_Farsi_3 0x10006f3 /* U+06F3 EXTENDED ARABIC-INDIC DIGIT THREE */ +#define XK_Farsi_4 0x10006f4 /* U+06F4 EXTENDED ARABIC-INDIC DIGIT FOUR */ +#define XK_Farsi_5 0x10006f5 /* U+06F5 EXTENDED ARABIC-INDIC DIGIT FIVE */ +#define XK_Farsi_6 0x10006f6 /* U+06F6 EXTENDED ARABIC-INDIC DIGIT SIX */ +#define XK_Farsi_7 0x10006f7 /* U+06F7 EXTENDED ARABIC-INDIC DIGIT SEVEN */ +#define XK_Farsi_8 0x10006f8 /* U+06F8 EXTENDED ARABIC-INDIC DIGIT EIGHT */ +#define XK_Farsi_9 0x10006f9 /* U+06F9 EXTENDED ARABIC-INDIC DIGIT NINE */ +#define XK_Arabic_percent 0x100066a /* U+066A ARABIC PERCENT SIGN */ +#define XK_Arabic_superscript_alef 0x1000670 /* U+0670 ARABIC LETTER SUPERSCRIPT ALEF */ +#define XK_Arabic_tteh 0x1000679 /* U+0679 ARABIC LETTER TTEH */ +#define XK_Arabic_peh 0x100067e /* U+067E ARABIC LETTER PEH */ +#define XK_Arabic_tcheh 0x1000686 /* U+0686 ARABIC LETTER TCHEH */ +#define XK_Arabic_ddal 0x1000688 /* U+0688 ARABIC LETTER DDAL */ +#define XK_Arabic_rreh 0x1000691 /* U+0691 ARABIC LETTER RREH */ +#define XK_Arabic_comma 0x05ac /* U+060C ARABIC COMMA */ +#define XK_Arabic_fullstop 0x10006d4 /* U+06D4 ARABIC FULL STOP */ +#define XK_Arabic_0 0x1000660 /* U+0660 ARABIC-INDIC DIGIT ZERO */ +#define XK_Arabic_1 0x1000661 /* U+0661 ARABIC-INDIC DIGIT ONE */ +#define XK_Arabic_2 0x1000662 /* U+0662 ARABIC-INDIC DIGIT TWO */ +#define XK_Arabic_3 0x1000663 /* U+0663 ARABIC-INDIC DIGIT THREE */ +#define XK_Arabic_4 0x1000664 /* U+0664 ARABIC-INDIC DIGIT FOUR */ +#define XK_Arabic_5 0x1000665 /* U+0665 ARABIC-INDIC DIGIT FIVE */ +#define XK_Arabic_6 0x1000666 /* U+0666 ARABIC-INDIC DIGIT SIX */ +#define XK_Arabic_7 0x1000667 /* U+0667 ARABIC-INDIC DIGIT SEVEN */ +#define XK_Arabic_8 0x1000668 /* U+0668 ARABIC-INDIC DIGIT EIGHT */ +#define XK_Arabic_9 0x1000669 /* U+0669 ARABIC-INDIC DIGIT NINE */ +#define XK_Arabic_semicolon 0x05bb /* U+061B ARABIC SEMICOLON */ +#define XK_Arabic_question_mark 0x05bf /* U+061F ARABIC QUESTION MARK */ +#define XK_Arabic_hamza 0x05c1 /* U+0621 ARABIC LETTER HAMZA */ +#define XK_Arabic_maddaonalef 0x05c2 /* U+0622 ARABIC LETTER ALEF WITH MADDA ABOVE */ +#define XK_Arabic_hamzaonalef 0x05c3 /* U+0623 ARABIC LETTER ALEF WITH HAMZA ABOVE */ +#define XK_Arabic_hamzaonwaw 0x05c4 /* U+0624 ARABIC LETTER WAW WITH HAMZA ABOVE */ +#define XK_Arabic_hamzaunderalef 0x05c5 /* U+0625 ARABIC LETTER ALEF WITH HAMZA BELOW */ +#define XK_Arabic_hamzaonyeh 0x05c6 /* U+0626 ARABIC LETTER YEH WITH HAMZA ABOVE */ +#define XK_Arabic_alef 0x05c7 /* U+0627 ARABIC LETTER ALEF */ +#define XK_Arabic_beh 0x05c8 /* U+0628 ARABIC LETTER BEH */ +#define XK_Arabic_tehmarbuta 0x05c9 /* U+0629 ARABIC LETTER TEH MARBUTA */ +#define XK_Arabic_teh 0x05ca /* U+062A ARABIC LETTER TEH */ +#define XK_Arabic_theh 0x05cb /* U+062B ARABIC LETTER THEH */ +#define XK_Arabic_jeem 0x05cc /* U+062C ARABIC LETTER JEEM */ +#define XK_Arabic_hah 0x05cd /* U+062D ARABIC LETTER HAH */ +#define XK_Arabic_khah 0x05ce /* U+062E ARABIC LETTER KHAH */ +#define XK_Arabic_dal 0x05cf /* U+062F ARABIC LETTER DAL */ +#define XK_Arabic_thal 0x05d0 /* U+0630 ARABIC LETTER THAL */ +#define XK_Arabic_ra 0x05d1 /* U+0631 ARABIC LETTER REH */ +#define XK_Arabic_zain 0x05d2 /* U+0632 ARABIC LETTER ZAIN */ +#define XK_Arabic_seen 0x05d3 /* U+0633 ARABIC LETTER SEEN */ +#define XK_Arabic_sheen 0x05d4 /* U+0634 ARABIC LETTER SHEEN */ +#define XK_Arabic_sad 0x05d5 /* U+0635 ARABIC LETTER SAD */ +#define XK_Arabic_dad 0x05d6 /* U+0636 ARABIC LETTER DAD */ +#define XK_Arabic_tah 0x05d7 /* U+0637 ARABIC LETTER TAH */ +#define XK_Arabic_zah 0x05d8 /* U+0638 ARABIC LETTER ZAH */ +#define XK_Arabic_ain 0x05d9 /* U+0639 ARABIC LETTER AIN */ +#define XK_Arabic_ghain 0x05da /* U+063A ARABIC LETTER GHAIN */ +#define XK_Arabic_tatweel 0x05e0 /* U+0640 ARABIC TATWEEL */ +#define XK_Arabic_feh 0x05e1 /* U+0641 ARABIC LETTER FEH */ +#define XK_Arabic_qaf 0x05e2 /* U+0642 ARABIC LETTER QAF */ +#define XK_Arabic_kaf 0x05e3 /* U+0643 ARABIC LETTER KAF */ +#define XK_Arabic_lam 0x05e4 /* U+0644 ARABIC LETTER LAM */ +#define XK_Arabic_meem 0x05e5 /* U+0645 ARABIC LETTER MEEM */ +#define XK_Arabic_noon 0x05e6 /* U+0646 ARABIC LETTER NOON */ +#define XK_Arabic_ha 0x05e7 /* U+0647 ARABIC LETTER HEH */ +#define XK_Arabic_heh 0x05e7 /* deprecated */ +#define XK_Arabic_waw 0x05e8 /* U+0648 ARABIC LETTER WAW */ +#define XK_Arabic_alefmaksura 0x05e9 /* U+0649 ARABIC LETTER ALEF MAKSURA */ +#define XK_Arabic_yeh 0x05ea /* U+064A ARABIC LETTER YEH */ +#define XK_Arabic_fathatan 0x05eb /* U+064B ARABIC FATHATAN */ +#define XK_Arabic_dammatan 0x05ec /* U+064C ARABIC DAMMATAN */ +#define XK_Arabic_kasratan 0x05ed /* U+064D ARABIC KASRATAN */ +#define XK_Arabic_fatha 0x05ee /* U+064E ARABIC FATHA */ +#define XK_Arabic_damma 0x05ef /* U+064F ARABIC DAMMA */ +#define XK_Arabic_kasra 0x05f0 /* U+0650 ARABIC KASRA */ +#define XK_Arabic_shadda 0x05f1 /* U+0651 ARABIC SHADDA */ +#define XK_Arabic_sukun 0x05f2 /* U+0652 ARABIC SUKUN */ +#define XK_Arabic_madda_above 0x1000653 /* U+0653 ARABIC MADDAH ABOVE */ +#define XK_Arabic_hamza_above 0x1000654 /* U+0654 ARABIC HAMZA ABOVE */ +#define XK_Arabic_hamza_below 0x1000655 /* U+0655 ARABIC HAMZA BELOW */ +#define XK_Arabic_jeh 0x1000698 /* U+0698 ARABIC LETTER JEH */ +#define XK_Arabic_veh 0x10006a4 /* U+06A4 ARABIC LETTER VEH */ +#define XK_Arabic_keheh 0x10006a9 /* U+06A9 ARABIC LETTER KEHEH */ +#define XK_Arabic_gaf 0x10006af /* U+06AF ARABIC LETTER GAF */ +#define XK_Arabic_noon_ghunna 0x10006ba /* U+06BA ARABIC LETTER NOON GHUNNA */ +#define XK_Arabic_heh_doachashmee 0x10006be /* U+06BE ARABIC LETTER HEH DOACHASHMEE */ +#define XK_Farsi_yeh 0x10006cc /* U+06CC ARABIC LETTER FARSI YEH */ +#define XK_Arabic_farsi_yeh 0x10006cc /* U+06CC ARABIC LETTER FARSI YEH */ +#define XK_Arabic_yeh_baree 0x10006d2 /* U+06D2 ARABIC LETTER YEH BARREE */ +#define XK_Arabic_heh_goal 0x10006c1 /* U+06C1 ARABIC LETTER HEH GOAL */ +#define XK_Arabic_switch 0xff7e /* Alias for mode_switch */ +#endif /* XK_ARABIC */ + +/* + * Cyrillic + * Byte 3 = 6 + */ +#ifdef XK_CYRILLIC +#define XK_Cyrillic_GHE_bar 0x1000492 /* U+0492 CYRILLIC CAPITAL LETTER GHE WITH STROKE */ +#define XK_Cyrillic_ghe_bar 0x1000493 /* U+0493 CYRILLIC SMALL LETTER GHE WITH STROKE */ +#define XK_Cyrillic_ZHE_descender 0x1000496 /* U+0496 CYRILLIC CAPITAL LETTER ZHE WITH DESCENDER */ +#define XK_Cyrillic_zhe_descender 0x1000497 /* U+0497 CYRILLIC SMALL LETTER ZHE WITH DESCENDER */ +#define XK_Cyrillic_KA_descender 0x100049a /* U+049A CYRILLIC CAPITAL LETTER KA WITH DESCENDER */ +#define XK_Cyrillic_ka_descender 0x100049b /* U+049B CYRILLIC SMALL LETTER KA WITH DESCENDER */ +#define XK_Cyrillic_KA_vertstroke 0x100049c /* U+049C CYRILLIC CAPITAL LETTER KA WITH VERTICAL STROKE */ +#define XK_Cyrillic_ka_vertstroke 0x100049d /* U+049D CYRILLIC SMALL LETTER KA WITH VERTICAL STROKE */ +#define XK_Cyrillic_EN_descender 0x10004a2 /* U+04A2 CYRILLIC CAPITAL LETTER EN WITH DESCENDER */ +#define XK_Cyrillic_en_descender 0x10004a3 /* U+04A3 CYRILLIC SMALL LETTER EN WITH DESCENDER */ +#define XK_Cyrillic_U_straight 0x10004ae /* U+04AE CYRILLIC CAPITAL LETTER STRAIGHT U */ +#define XK_Cyrillic_u_straight 0x10004af /* U+04AF CYRILLIC SMALL LETTER STRAIGHT U */ +#define XK_Cyrillic_U_straight_bar 0x10004b0 /* U+04B0 CYRILLIC CAPITAL LETTER STRAIGHT U WITH STROKE */ +#define XK_Cyrillic_u_straight_bar 0x10004b1 /* U+04B1 CYRILLIC SMALL LETTER STRAIGHT U WITH STROKE */ +#define XK_Cyrillic_HA_descender 0x10004b2 /* U+04B2 CYRILLIC CAPITAL LETTER HA WITH DESCENDER */ +#define XK_Cyrillic_ha_descender 0x10004b3 /* U+04B3 CYRILLIC SMALL LETTER HA WITH DESCENDER */ +#define XK_Cyrillic_CHE_descender 0x10004b6 /* U+04B6 CYRILLIC CAPITAL LETTER CHE WITH DESCENDER */ +#define XK_Cyrillic_che_descender 0x10004b7 /* U+04B7 CYRILLIC SMALL LETTER CHE WITH DESCENDER */ +#define XK_Cyrillic_CHE_vertstroke 0x10004b8 /* U+04B8 CYRILLIC CAPITAL LETTER CHE WITH VERTICAL STROKE */ +#define XK_Cyrillic_che_vertstroke 0x10004b9 /* U+04B9 CYRILLIC SMALL LETTER CHE WITH VERTICAL STROKE */ +#define XK_Cyrillic_SHHA 0x10004ba /* U+04BA CYRILLIC CAPITAL LETTER SHHA */ +#define XK_Cyrillic_shha 0x10004bb /* U+04BB CYRILLIC SMALL LETTER SHHA */ + +#define XK_Cyrillic_SCHWA 0x10004d8 /* U+04D8 CYRILLIC CAPITAL LETTER SCHWA */ +#define XK_Cyrillic_schwa 0x10004d9 /* U+04D9 CYRILLIC SMALL LETTER SCHWA */ +#define XK_Cyrillic_I_macron 0x10004e2 /* U+04E2 CYRILLIC CAPITAL LETTER I WITH MACRON */ +#define XK_Cyrillic_i_macron 0x10004e3 /* U+04E3 CYRILLIC SMALL LETTER I WITH MACRON */ +#define XK_Cyrillic_O_bar 0x10004e8 /* U+04E8 CYRILLIC CAPITAL LETTER BARRED O */ +#define XK_Cyrillic_o_bar 0x10004e9 /* U+04E9 CYRILLIC SMALL LETTER BARRED O */ +#define XK_Cyrillic_U_macron 0x10004ee /* U+04EE CYRILLIC CAPITAL LETTER U WITH MACRON */ +#define XK_Cyrillic_u_macron 0x10004ef /* U+04EF CYRILLIC SMALL LETTER U WITH MACRON */ + +#define XK_Serbian_dje 0x06a1 /* U+0452 CYRILLIC SMALL LETTER DJE */ +#define XK_Macedonia_gje 0x06a2 /* U+0453 CYRILLIC SMALL LETTER GJE */ +#define XK_Cyrillic_io 0x06a3 /* U+0451 CYRILLIC SMALL LETTER IO */ +#define XK_Ukrainian_ie 0x06a4 /* U+0454 CYRILLIC SMALL LETTER UKRAINIAN IE */ +#define XK_Ukranian_je 0x06a4 /* deprecated */ +#define XK_Macedonia_dse 0x06a5 /* U+0455 CYRILLIC SMALL LETTER DZE */ +#define XK_Ukrainian_i 0x06a6 /* U+0456 CYRILLIC SMALL LETTER BYELORUSSIAN-UKRAINIAN I */ +#define XK_Ukranian_i 0x06a6 /* deprecated */ +#define XK_Ukrainian_yi 0x06a7 /* U+0457 CYRILLIC SMALL LETTER YI */ +#define XK_Ukranian_yi 0x06a7 /* deprecated */ +#define XK_Cyrillic_je 0x06a8 /* U+0458 CYRILLIC SMALL LETTER JE */ +#define XK_Serbian_je 0x06a8 /* deprecated */ +#define XK_Cyrillic_lje 0x06a9 /* U+0459 CYRILLIC SMALL LETTER LJE */ +#define XK_Serbian_lje 0x06a9 /* deprecated */ +#define XK_Cyrillic_nje 0x06aa /* U+045A CYRILLIC SMALL LETTER NJE */ +#define XK_Serbian_nje 0x06aa /* deprecated */ +#define XK_Serbian_tshe 0x06ab /* U+045B CYRILLIC SMALL LETTER TSHE */ +#define XK_Macedonia_kje 0x06ac /* U+045C CYRILLIC SMALL LETTER KJE */ +#define XK_Ukrainian_ghe_with_upturn 0x06ad /* U+0491 CYRILLIC SMALL LETTER GHE WITH UPTURN */ +#define XK_Byelorussian_shortu 0x06ae /* U+045E CYRILLIC SMALL LETTER SHORT U */ +#define XK_Cyrillic_dzhe 0x06af /* U+045F CYRILLIC SMALL LETTER DZHE */ +#define XK_Serbian_dze 0x06af /* deprecated */ +#define XK_numerosign 0x06b0 /* U+2116 NUMERO SIGN */ +#define XK_Serbian_DJE 0x06b1 /* U+0402 CYRILLIC CAPITAL LETTER DJE */ +#define XK_Macedonia_GJE 0x06b2 /* U+0403 CYRILLIC CAPITAL LETTER GJE */ +#define XK_Cyrillic_IO 0x06b3 /* U+0401 CYRILLIC CAPITAL LETTER IO */ +#define XK_Ukrainian_IE 0x06b4 /* U+0404 CYRILLIC CAPITAL LETTER UKRAINIAN IE */ +#define XK_Ukranian_JE 0x06b4 /* deprecated */ +#define XK_Macedonia_DSE 0x06b5 /* U+0405 CYRILLIC CAPITAL LETTER DZE */ +#define XK_Ukrainian_I 0x06b6 /* U+0406 CYRILLIC CAPITAL LETTER BYELORUSSIAN-UKRAINIAN I */ +#define XK_Ukranian_I 0x06b6 /* deprecated */ +#define XK_Ukrainian_YI 0x06b7 /* U+0407 CYRILLIC CAPITAL LETTER YI */ +#define XK_Ukranian_YI 0x06b7 /* deprecated */ +#define XK_Cyrillic_JE 0x06b8 /* U+0408 CYRILLIC CAPITAL LETTER JE */ +#define XK_Serbian_JE 0x06b8 /* deprecated */ +#define XK_Cyrillic_LJE 0x06b9 /* U+0409 CYRILLIC CAPITAL LETTER LJE */ +#define XK_Serbian_LJE 0x06b9 /* deprecated */ +#define XK_Cyrillic_NJE 0x06ba /* U+040A CYRILLIC CAPITAL LETTER NJE */ +#define XK_Serbian_NJE 0x06ba /* deprecated */ +#define XK_Serbian_TSHE 0x06bb /* U+040B CYRILLIC CAPITAL LETTER TSHE */ +#define XK_Macedonia_KJE 0x06bc /* U+040C CYRILLIC CAPITAL LETTER KJE */ +#define XK_Ukrainian_GHE_WITH_UPTURN 0x06bd /* U+0490 CYRILLIC CAPITAL LETTER GHE WITH UPTURN */ +#define XK_Byelorussian_SHORTU 0x06be /* U+040E CYRILLIC CAPITAL LETTER SHORT U */ +#define XK_Cyrillic_DZHE 0x06bf /* U+040F CYRILLIC CAPITAL LETTER DZHE */ +#define XK_Serbian_DZE 0x06bf /* deprecated */ +#define XK_Cyrillic_yu 0x06c0 /* U+044E CYRILLIC SMALL LETTER YU */ +#define XK_Cyrillic_a 0x06c1 /* U+0430 CYRILLIC SMALL LETTER A */ +#define XK_Cyrillic_be 0x06c2 /* U+0431 CYRILLIC SMALL LETTER BE */ +#define XK_Cyrillic_tse 0x06c3 /* U+0446 CYRILLIC SMALL LETTER TSE */ +#define XK_Cyrillic_de 0x06c4 /* U+0434 CYRILLIC SMALL LETTER DE */ +#define XK_Cyrillic_ie 0x06c5 /* U+0435 CYRILLIC SMALL LETTER IE */ +#define XK_Cyrillic_ef 0x06c6 /* U+0444 CYRILLIC SMALL LETTER EF */ +#define XK_Cyrillic_ghe 0x06c7 /* U+0433 CYRILLIC SMALL LETTER GHE */ +#define XK_Cyrillic_ha 0x06c8 /* U+0445 CYRILLIC SMALL LETTER HA */ +#define XK_Cyrillic_i 0x06c9 /* U+0438 CYRILLIC SMALL LETTER I */ +#define XK_Cyrillic_shorti 0x06ca /* U+0439 CYRILLIC SMALL LETTER SHORT I */ +#define XK_Cyrillic_ka 0x06cb /* U+043A CYRILLIC SMALL LETTER KA */ +#define XK_Cyrillic_el 0x06cc /* U+043B CYRILLIC SMALL LETTER EL */ +#define XK_Cyrillic_em 0x06cd /* U+043C CYRILLIC SMALL LETTER EM */ +#define XK_Cyrillic_en 0x06ce /* U+043D CYRILLIC SMALL LETTER EN */ +#define XK_Cyrillic_o 0x06cf /* U+043E CYRILLIC SMALL LETTER O */ +#define XK_Cyrillic_pe 0x06d0 /* U+043F CYRILLIC SMALL LETTER PE */ +#define XK_Cyrillic_ya 0x06d1 /* U+044F CYRILLIC SMALL LETTER YA */ +#define XK_Cyrillic_er 0x06d2 /* U+0440 CYRILLIC SMALL LETTER ER */ +#define XK_Cyrillic_es 0x06d3 /* U+0441 CYRILLIC SMALL LETTER ES */ +#define XK_Cyrillic_te 0x06d4 /* U+0442 CYRILLIC SMALL LETTER TE */ +#define XK_Cyrillic_u 0x06d5 /* U+0443 CYRILLIC SMALL LETTER U */ +#define XK_Cyrillic_zhe 0x06d6 /* U+0436 CYRILLIC SMALL LETTER ZHE */ +#define XK_Cyrillic_ve 0x06d7 /* U+0432 CYRILLIC SMALL LETTER VE */ +#define XK_Cyrillic_softsign 0x06d8 /* U+044C CYRILLIC SMALL LETTER SOFT SIGN */ +#define XK_Cyrillic_yeru 0x06d9 /* U+044B CYRILLIC SMALL LETTER YERU */ +#define XK_Cyrillic_ze 0x06da /* U+0437 CYRILLIC SMALL LETTER ZE */ +#define XK_Cyrillic_sha 0x06db /* U+0448 CYRILLIC SMALL LETTER SHA */ +#define XK_Cyrillic_e 0x06dc /* U+044D CYRILLIC SMALL LETTER E */ +#define XK_Cyrillic_shcha 0x06dd /* U+0449 CYRILLIC SMALL LETTER SHCHA */ +#define XK_Cyrillic_che 0x06de /* U+0447 CYRILLIC SMALL LETTER CHE */ +#define XK_Cyrillic_hardsign 0x06df /* U+044A CYRILLIC SMALL LETTER HARD SIGN */ +#define XK_Cyrillic_YU 0x06e0 /* U+042E CYRILLIC CAPITAL LETTER YU */ +#define XK_Cyrillic_A 0x06e1 /* U+0410 CYRILLIC CAPITAL LETTER A */ +#define XK_Cyrillic_BE 0x06e2 /* U+0411 CYRILLIC CAPITAL LETTER BE */ +#define XK_Cyrillic_TSE 0x06e3 /* U+0426 CYRILLIC CAPITAL LETTER TSE */ +#define XK_Cyrillic_DE 0x06e4 /* U+0414 CYRILLIC CAPITAL LETTER DE */ +#define XK_Cyrillic_IE 0x06e5 /* U+0415 CYRILLIC CAPITAL LETTER IE */ +#define XK_Cyrillic_EF 0x06e6 /* U+0424 CYRILLIC CAPITAL LETTER EF */ +#define XK_Cyrillic_GHE 0x06e7 /* U+0413 CYRILLIC CAPITAL LETTER GHE */ +#define XK_Cyrillic_HA 0x06e8 /* U+0425 CYRILLIC CAPITAL LETTER HA */ +#define XK_Cyrillic_I 0x06e9 /* U+0418 CYRILLIC CAPITAL LETTER I */ +#define XK_Cyrillic_SHORTI 0x06ea /* U+0419 CYRILLIC CAPITAL LETTER SHORT I */ +#define XK_Cyrillic_KA 0x06eb /* U+041A CYRILLIC CAPITAL LETTER KA */ +#define XK_Cyrillic_EL 0x06ec /* U+041B CYRILLIC CAPITAL LETTER EL */ +#define XK_Cyrillic_EM 0x06ed /* U+041C CYRILLIC CAPITAL LETTER EM */ +#define XK_Cyrillic_EN 0x06ee /* U+041D CYRILLIC CAPITAL LETTER EN */ +#define XK_Cyrillic_O 0x06ef /* U+041E CYRILLIC CAPITAL LETTER O */ +#define XK_Cyrillic_PE 0x06f0 /* U+041F CYRILLIC CAPITAL LETTER PE */ +#define XK_Cyrillic_YA 0x06f1 /* U+042F CYRILLIC CAPITAL LETTER YA */ +#define XK_Cyrillic_ER 0x06f2 /* U+0420 CYRILLIC CAPITAL LETTER ER */ +#define XK_Cyrillic_ES 0x06f3 /* U+0421 CYRILLIC CAPITAL LETTER ES */ +#define XK_Cyrillic_TE 0x06f4 /* U+0422 CYRILLIC CAPITAL LETTER TE */ +#define XK_Cyrillic_U 0x06f5 /* U+0423 CYRILLIC CAPITAL LETTER U */ +#define XK_Cyrillic_ZHE 0x06f6 /* U+0416 CYRILLIC CAPITAL LETTER ZHE */ +#define XK_Cyrillic_VE 0x06f7 /* U+0412 CYRILLIC CAPITAL LETTER VE */ +#define XK_Cyrillic_SOFTSIGN 0x06f8 /* U+042C CYRILLIC CAPITAL LETTER SOFT SIGN */ +#define XK_Cyrillic_YERU 0x06f9 /* U+042B CYRILLIC CAPITAL LETTER YERU */ +#define XK_Cyrillic_ZE 0x06fa /* U+0417 CYRILLIC CAPITAL LETTER ZE */ +#define XK_Cyrillic_SHA 0x06fb /* U+0428 CYRILLIC CAPITAL LETTER SHA */ +#define XK_Cyrillic_E 0x06fc /* U+042D CYRILLIC CAPITAL LETTER E */ +#define XK_Cyrillic_SHCHA 0x06fd /* U+0429 CYRILLIC CAPITAL LETTER SHCHA */ +#define XK_Cyrillic_CHE 0x06fe /* U+0427 CYRILLIC CAPITAL LETTER CHE */ +#define XK_Cyrillic_HARDSIGN 0x06ff /* U+042A CYRILLIC CAPITAL LETTER HARD SIGN */ +#endif /* XK_CYRILLIC */ + +/* + * Greek + * (based on an early draft of, and not quite identical to, ISO/IEC 8859-7) + * Byte 3 = 7 + */ + +#ifdef XK_GREEK +#define XK_Greek_ALPHAaccent 0x07a1 /* U+0386 GREEK CAPITAL LETTER ALPHA WITH TONOS */ +#define XK_Greek_EPSILONaccent 0x07a2 /* U+0388 GREEK CAPITAL LETTER EPSILON WITH TONOS */ +#define XK_Greek_ETAaccent 0x07a3 /* U+0389 GREEK CAPITAL LETTER ETA WITH TONOS */ +#define XK_Greek_IOTAaccent 0x07a4 /* U+038A GREEK CAPITAL LETTER IOTA WITH TONOS */ +#define XK_Greek_IOTAdieresis 0x07a5 /* U+03AA GREEK CAPITAL LETTER IOTA WITH DIALYTIKA */ +#define XK_Greek_IOTAdiaeresis 0x07a5 /* old typo */ +#define XK_Greek_OMICRONaccent 0x07a7 /* U+038C GREEK CAPITAL LETTER OMICRON WITH TONOS */ +#define XK_Greek_UPSILONaccent 0x07a8 /* U+038E GREEK CAPITAL LETTER UPSILON WITH TONOS */ +#define XK_Greek_UPSILONdieresis 0x07a9 /* U+03AB GREEK CAPITAL LETTER UPSILON WITH DIALYTIKA */ +#define XK_Greek_OMEGAaccent 0x07ab /* U+038F GREEK CAPITAL LETTER OMEGA WITH TONOS */ +#define XK_Greek_accentdieresis 0x07ae /* U+0385 GREEK DIALYTIKA TONOS */ +#define XK_Greek_horizbar 0x07af /* U+2015 HORIZONTAL BAR */ +#define XK_Greek_alphaaccent 0x07b1 /* U+03AC GREEK SMALL LETTER ALPHA WITH TONOS */ +#define XK_Greek_epsilonaccent 0x07b2 /* U+03AD GREEK SMALL LETTER EPSILON WITH TONOS */ +#define XK_Greek_etaaccent 0x07b3 /* U+03AE GREEK SMALL LETTER ETA WITH TONOS */ +#define XK_Greek_iotaaccent 0x07b4 /* U+03AF GREEK SMALL LETTER IOTA WITH TONOS */ +#define XK_Greek_iotadieresis 0x07b5 /* U+03CA GREEK SMALL LETTER IOTA WITH DIALYTIKA */ +#define XK_Greek_iotaaccentdieresis 0x07b6 /* U+0390 GREEK SMALL LETTER IOTA WITH DIALYTIKA AND TONOS */ +#define XK_Greek_omicronaccent 0x07b7 /* U+03CC GREEK SMALL LETTER OMICRON WITH TONOS */ +#define XK_Greek_upsilonaccent 0x07b8 /* U+03CD GREEK SMALL LETTER UPSILON WITH TONOS */ +#define XK_Greek_upsilondieresis 0x07b9 /* U+03CB GREEK SMALL LETTER UPSILON WITH DIALYTIKA */ +#define XK_Greek_upsilonaccentdieresis 0x07ba /* U+03B0 GREEK SMALL LETTER UPSILON WITH DIALYTIKA AND TONOS */ +#define XK_Greek_omegaaccent 0x07bb /* U+03CE GREEK SMALL LETTER OMEGA WITH TONOS */ +#define XK_Greek_ALPHA 0x07c1 /* U+0391 GREEK CAPITAL LETTER ALPHA */ +#define XK_Greek_BETA 0x07c2 /* U+0392 GREEK CAPITAL LETTER BETA */ +#define XK_Greek_GAMMA 0x07c3 /* U+0393 GREEK CAPITAL LETTER GAMMA */ +#define XK_Greek_DELTA 0x07c4 /* U+0394 GREEK CAPITAL LETTER DELTA */ +#define XK_Greek_EPSILON 0x07c5 /* U+0395 GREEK CAPITAL LETTER EPSILON */ +#define XK_Greek_ZETA 0x07c6 /* U+0396 GREEK CAPITAL LETTER ZETA */ +#define XK_Greek_ETA 0x07c7 /* U+0397 GREEK CAPITAL LETTER ETA */ +#define XK_Greek_THETA 0x07c8 /* U+0398 GREEK CAPITAL LETTER THETA */ +#define XK_Greek_IOTA 0x07c9 /* U+0399 GREEK CAPITAL LETTER IOTA */ +#define XK_Greek_KAPPA 0x07ca /* U+039A GREEK CAPITAL LETTER KAPPA */ +#define XK_Greek_LAMDA 0x07cb /* U+039B GREEK CAPITAL LETTER LAMDA */ +#define XK_Greek_LAMBDA 0x07cb /* U+039B GREEK CAPITAL LETTER LAMDA */ +#define XK_Greek_MU 0x07cc /* U+039C GREEK CAPITAL LETTER MU */ +#define XK_Greek_NU 0x07cd /* U+039D GREEK CAPITAL LETTER NU */ +#define XK_Greek_XI 0x07ce /* U+039E GREEK CAPITAL LETTER XI */ +#define XK_Greek_OMICRON 0x07cf /* U+039F GREEK CAPITAL LETTER OMICRON */ +#define XK_Greek_PI 0x07d0 /* U+03A0 GREEK CAPITAL LETTER PI */ +#define XK_Greek_RHO 0x07d1 /* U+03A1 GREEK CAPITAL LETTER RHO */ +#define XK_Greek_SIGMA 0x07d2 /* U+03A3 GREEK CAPITAL LETTER SIGMA */ +#define XK_Greek_TAU 0x07d4 /* U+03A4 GREEK CAPITAL LETTER TAU */ +#define XK_Greek_UPSILON 0x07d5 /* U+03A5 GREEK CAPITAL LETTER UPSILON */ +#define XK_Greek_PHI 0x07d6 /* U+03A6 GREEK CAPITAL LETTER PHI */ +#define XK_Greek_CHI 0x07d7 /* U+03A7 GREEK CAPITAL LETTER CHI */ +#define XK_Greek_PSI 0x07d8 /* U+03A8 GREEK CAPITAL LETTER PSI */ +#define XK_Greek_OMEGA 0x07d9 /* U+03A9 GREEK CAPITAL LETTER OMEGA */ +#define XK_Greek_alpha 0x07e1 /* U+03B1 GREEK SMALL LETTER ALPHA */ +#define XK_Greek_beta 0x07e2 /* U+03B2 GREEK SMALL LETTER BETA */ +#define XK_Greek_gamma 0x07e3 /* U+03B3 GREEK SMALL LETTER GAMMA */ +#define XK_Greek_delta 0x07e4 /* U+03B4 GREEK SMALL LETTER DELTA */ +#define XK_Greek_epsilon 0x07e5 /* U+03B5 GREEK SMALL LETTER EPSILON */ +#define XK_Greek_zeta 0x07e6 /* U+03B6 GREEK SMALL LETTER ZETA */ +#define XK_Greek_eta 0x07e7 /* U+03B7 GREEK SMALL LETTER ETA */ +#define XK_Greek_theta 0x07e8 /* U+03B8 GREEK SMALL LETTER THETA */ +#define XK_Greek_iota 0x07e9 /* U+03B9 GREEK SMALL LETTER IOTA */ +#define XK_Greek_kappa 0x07ea /* U+03BA GREEK SMALL LETTER KAPPA */ +#define XK_Greek_lamda 0x07eb /* U+03BB GREEK SMALL LETTER LAMDA */ +#define XK_Greek_lambda 0x07eb /* U+03BB GREEK SMALL LETTER LAMDA */ +#define XK_Greek_mu 0x07ec /* U+03BC GREEK SMALL LETTER MU */ +#define XK_Greek_nu 0x07ed /* U+03BD GREEK SMALL LETTER NU */ +#define XK_Greek_xi 0x07ee /* U+03BE GREEK SMALL LETTER XI */ +#define XK_Greek_omicron 0x07ef /* U+03BF GREEK SMALL LETTER OMICRON */ +#define XK_Greek_pi 0x07f0 /* U+03C0 GREEK SMALL LETTER PI */ +#define XK_Greek_rho 0x07f1 /* U+03C1 GREEK SMALL LETTER RHO */ +#define XK_Greek_sigma 0x07f2 /* U+03C3 GREEK SMALL LETTER SIGMA */ +#define XK_Greek_finalsmallsigma 0x07f3 /* U+03C2 GREEK SMALL LETTER FINAL SIGMA */ +#define XK_Greek_tau 0x07f4 /* U+03C4 GREEK SMALL LETTER TAU */ +#define XK_Greek_upsilon 0x07f5 /* U+03C5 GREEK SMALL LETTER UPSILON */ +#define XK_Greek_phi 0x07f6 /* U+03C6 GREEK SMALL LETTER PHI */ +#define XK_Greek_chi 0x07f7 /* U+03C7 GREEK SMALL LETTER CHI */ +#define XK_Greek_psi 0x07f8 /* U+03C8 GREEK SMALL LETTER PSI */ +#define XK_Greek_omega 0x07f9 /* U+03C9 GREEK SMALL LETTER OMEGA */ +#define XK_Greek_switch 0xff7e /* Alias for mode_switch */ +#endif /* XK_GREEK */ + +/* + * Technical + * (from the DEC VT330/VT420 Technical Character Set, http://vt100.net/charsets/technical.html) + * Byte 3 = 8 + */ + +#ifdef XK_TECHNICAL +#define XK_leftradical 0x08a1 /* U+23B7 RADICAL SYMBOL BOTTOM */ +#define XK_topleftradical 0x08a2 /*(U+250C BOX DRAWINGS LIGHT DOWN AND RIGHT)*/ +#define XK_horizconnector 0x08a3 /*(U+2500 BOX DRAWINGS LIGHT HORIZONTAL)*/ +#define XK_topintegral 0x08a4 /* U+2320 TOP HALF INTEGRAL */ +#define XK_botintegral 0x08a5 /* U+2321 BOTTOM HALF INTEGRAL */ +#define XK_vertconnector 0x08a6 /*(U+2502 BOX DRAWINGS LIGHT VERTICAL)*/ +#define XK_topleftsqbracket 0x08a7 /* U+23A1 LEFT SQUARE BRACKET UPPER CORNER */ +#define XK_botleftsqbracket 0x08a8 /* U+23A3 LEFT SQUARE BRACKET LOWER CORNER */ +#define XK_toprightsqbracket 0x08a9 /* U+23A4 RIGHT SQUARE BRACKET UPPER CORNER */ +#define XK_botrightsqbracket 0x08aa /* U+23A6 RIGHT SQUARE BRACKET LOWER CORNER */ +#define XK_topleftparens 0x08ab /* U+239B LEFT PARENTHESIS UPPER HOOK */ +#define XK_botleftparens 0x08ac /* U+239D LEFT PARENTHESIS LOWER HOOK */ +#define XK_toprightparens 0x08ad /* U+239E RIGHT PARENTHESIS UPPER HOOK */ +#define XK_botrightparens 0x08ae /* U+23A0 RIGHT PARENTHESIS LOWER HOOK */ +#define XK_leftmiddlecurlybrace 0x08af /* U+23A8 LEFT CURLY BRACKET MIDDLE PIECE */ +#define XK_rightmiddlecurlybrace 0x08b0 /* U+23AC RIGHT CURLY BRACKET MIDDLE PIECE */ +#define XK_topleftsummation 0x08b1 +#define XK_botleftsummation 0x08b2 +#define XK_topvertsummationconnector 0x08b3 +#define XK_botvertsummationconnector 0x08b4 +#define XK_toprightsummation 0x08b5 +#define XK_botrightsummation 0x08b6 +#define XK_rightmiddlesummation 0x08b7 +#define XK_lessthanequal 0x08bc /* U+2264 LESS-THAN OR EQUAL TO */ +#define XK_notequal 0x08bd /* U+2260 NOT EQUAL TO */ +#define XK_greaterthanequal 0x08be /* U+2265 GREATER-THAN OR EQUAL TO */ +#define XK_integral 0x08bf /* U+222B INTEGRAL */ +#define XK_therefore 0x08c0 /* U+2234 THEREFORE */ +#define XK_variation 0x08c1 /* U+221D PROPORTIONAL TO */ +#define XK_infinity 0x08c2 /* U+221E INFINITY */ +#define XK_nabla 0x08c5 /* U+2207 NABLA */ +#define XK_approximate 0x08c8 /* U+223C TILDE OPERATOR */ +#define XK_similarequal 0x08c9 /* U+2243 ASYMPTOTICALLY EQUAL TO */ +#define XK_ifonlyif 0x08cd /* U+21D4 LEFT RIGHT DOUBLE ARROW */ +#define XK_implies 0x08ce /* U+21D2 RIGHTWARDS DOUBLE ARROW */ +#define XK_identical 0x08cf /* U+2261 IDENTICAL TO */ +#define XK_radical 0x08d6 /* U+221A SQUARE ROOT */ +#define XK_includedin 0x08da /* U+2282 SUBSET OF */ +#define XK_includes 0x08db /* U+2283 SUPERSET OF */ +#define XK_intersection 0x08dc /* U+2229 INTERSECTION */ +#define XK_union 0x08dd /* U+222A UNION */ +#define XK_logicaland 0x08de /* U+2227 LOGICAL AND */ +#define XK_logicalor 0x08df /* U+2228 LOGICAL OR */ +#define XK_partialderivative 0x08ef /* U+2202 PARTIAL DIFFERENTIAL */ +#define XK_function 0x08f6 /* U+0192 LATIN SMALL LETTER F WITH HOOK */ +#define XK_leftarrow 0x08fb /* U+2190 LEFTWARDS ARROW */ +#define XK_uparrow 0x08fc /* U+2191 UPWARDS ARROW */ +#define XK_rightarrow 0x08fd /* U+2192 RIGHTWARDS ARROW */ +#define XK_downarrow 0x08fe /* U+2193 DOWNWARDS ARROW */ +#endif /* XK_TECHNICAL */ + +/* + * Special + * (from the DEC VT100 Special Graphics Character Set) + * Byte 3 = 9 + */ + +#ifdef XK_SPECIAL +#define XK_blank 0x09df +#define XK_soliddiamond 0x09e0 /* U+25C6 BLACK DIAMOND */ +#define XK_checkerboard 0x09e1 /* U+2592 MEDIUM SHADE */ +#define XK_ht 0x09e2 /* U+2409 SYMBOL FOR HORIZONTAL TABULATION */ +#define XK_ff 0x09e3 /* U+240C SYMBOL FOR FORM FEED */ +#define XK_cr 0x09e4 /* U+240D SYMBOL FOR CARRIAGE RETURN */ +#define XK_lf 0x09e5 /* U+240A SYMBOL FOR LINE FEED */ +#define XK_nl 0x09e8 /* U+2424 SYMBOL FOR NEWLINE */ +#define XK_vt 0x09e9 /* U+240B SYMBOL FOR VERTICAL TABULATION */ +#define XK_lowrightcorner 0x09ea /* U+2518 BOX DRAWINGS LIGHT UP AND LEFT */ +#define XK_uprightcorner 0x09eb /* U+2510 BOX DRAWINGS LIGHT DOWN AND LEFT */ +#define XK_upleftcorner 0x09ec /* U+250C BOX DRAWINGS LIGHT DOWN AND RIGHT */ +#define XK_lowleftcorner 0x09ed /* U+2514 BOX DRAWINGS LIGHT UP AND RIGHT */ +#define XK_crossinglines 0x09ee /* U+253C BOX DRAWINGS LIGHT VERTICAL AND HORIZONTAL */ +#define XK_horizlinescan1 0x09ef /* U+23BA HORIZONTAL SCAN LINE-1 */ +#define XK_horizlinescan3 0x09f0 /* U+23BB HORIZONTAL SCAN LINE-3 */ +#define XK_horizlinescan5 0x09f1 /* U+2500 BOX DRAWINGS LIGHT HORIZONTAL */ +#define XK_horizlinescan7 0x09f2 /* U+23BC HORIZONTAL SCAN LINE-7 */ +#define XK_horizlinescan9 0x09f3 /* U+23BD HORIZONTAL SCAN LINE-9 */ +#define XK_leftt 0x09f4 /* U+251C BOX DRAWINGS LIGHT VERTICAL AND RIGHT */ +#define XK_rightt 0x09f5 /* U+2524 BOX DRAWINGS LIGHT VERTICAL AND LEFT */ +#define XK_bott 0x09f6 /* U+2534 BOX DRAWINGS LIGHT UP AND HORIZONTAL */ +#define XK_topt 0x09f7 /* U+252C BOX DRAWINGS LIGHT DOWN AND HORIZONTAL */ +#define XK_vertbar 0x09f8 /* U+2502 BOX DRAWINGS LIGHT VERTICAL */ +#endif /* XK_SPECIAL */ + +/* + * Publishing + * (these are probably from a long forgotten DEC Publishing + * font that once shipped with DECwrite) + * Byte 3 = 0x0a + */ + +#ifdef XK_PUBLISHING +#define XK_emspace 0x0aa1 /* U+2003 EM SPACE */ +#define XK_enspace 0x0aa2 /* U+2002 EN SPACE */ +#define XK_em3space 0x0aa3 /* U+2004 THREE-PER-EM SPACE */ +#define XK_em4space 0x0aa4 /* U+2005 FOUR-PER-EM SPACE */ +#define XK_digitspace 0x0aa5 /* U+2007 FIGURE SPACE */ +#define XK_punctspace 0x0aa6 /* U+2008 PUNCTUATION SPACE */ +#define XK_thinspace 0x0aa7 /* U+2009 THIN SPACE */ +#define XK_hairspace 0x0aa8 /* U+200A HAIR SPACE */ +#define XK_emdash 0x0aa9 /* U+2014 EM DASH */ +#define XK_endash 0x0aaa /* U+2013 EN DASH */ +#define XK_signifblank 0x0aac /*(U+2423 OPEN BOX)*/ +#define XK_ellipsis 0x0aae /* U+2026 HORIZONTAL ELLIPSIS */ +#define XK_doubbaselinedot 0x0aaf /* U+2025 TWO DOT LEADER */ +#define XK_onethird 0x0ab0 /* U+2153 VULGAR FRACTION ONE THIRD */ +#define XK_twothirds 0x0ab1 /* U+2154 VULGAR FRACTION TWO THIRDS */ +#define XK_onefifth 0x0ab2 /* U+2155 VULGAR FRACTION ONE FIFTH */ +#define XK_twofifths 0x0ab3 /* U+2156 VULGAR FRACTION TWO FIFTHS */ +#define XK_threefifths 0x0ab4 /* U+2157 VULGAR FRACTION THREE FIFTHS */ +#define XK_fourfifths 0x0ab5 /* U+2158 VULGAR FRACTION FOUR FIFTHS */ +#define XK_onesixth 0x0ab6 /* U+2159 VULGAR FRACTION ONE SIXTH */ +#define XK_fivesixths 0x0ab7 /* U+215A VULGAR FRACTION FIVE SIXTHS */ +#define XK_careof 0x0ab8 /* U+2105 CARE OF */ +#define XK_figdash 0x0abb /* U+2012 FIGURE DASH */ +#define XK_leftanglebracket 0x0abc /*(U+27E8 MATHEMATICAL LEFT ANGLE BRACKET)*/ +#define XK_decimalpoint 0x0abd /*(U+002E FULL STOP)*/ +#define XK_rightanglebracket 0x0abe /*(U+27E9 MATHEMATICAL RIGHT ANGLE BRACKET)*/ +#define XK_marker 0x0abf +#define XK_oneeighth 0x0ac3 /* U+215B VULGAR FRACTION ONE EIGHTH */ +#define XK_threeeighths 0x0ac4 /* U+215C VULGAR FRACTION THREE EIGHTHS */ +#define XK_fiveeighths 0x0ac5 /* U+215D VULGAR FRACTION FIVE EIGHTHS */ +#define XK_seveneighths 0x0ac6 /* U+215E VULGAR FRACTION SEVEN EIGHTHS */ +#define XK_trademark 0x0ac9 /* U+2122 TRADE MARK SIGN */ +#define XK_signaturemark 0x0aca /*(U+2613 SALTIRE)*/ +#define XK_trademarkincircle 0x0acb +#define XK_leftopentriangle 0x0acc /*(U+25C1 WHITE LEFT-POINTING TRIANGLE)*/ +#define XK_rightopentriangle 0x0acd /*(U+25B7 WHITE RIGHT-POINTING TRIANGLE)*/ +#define XK_emopencircle 0x0ace /*(U+25CB WHITE CIRCLE)*/ +#define XK_emopenrectangle 0x0acf /*(U+25AF WHITE VERTICAL RECTANGLE)*/ +#define XK_leftsinglequotemark 0x0ad0 /* U+2018 LEFT SINGLE QUOTATION MARK */ +#define XK_rightsinglequotemark 0x0ad1 /* U+2019 RIGHT SINGLE QUOTATION MARK */ +#define XK_leftdoublequotemark 0x0ad2 /* U+201C LEFT DOUBLE QUOTATION MARK */ +#define XK_rightdoublequotemark 0x0ad3 /* U+201D RIGHT DOUBLE QUOTATION MARK */ +#define XK_prescription 0x0ad4 /* U+211E PRESCRIPTION TAKE */ +#define XK_minutes 0x0ad6 /* U+2032 PRIME */ +#define XK_seconds 0x0ad7 /* U+2033 DOUBLE PRIME */ +#define XK_latincross 0x0ad9 /* U+271D LATIN CROSS */ +#define XK_hexagram 0x0ada +#define XK_filledrectbullet 0x0adb /*(U+25AC BLACK RECTANGLE)*/ +#define XK_filledlefttribullet 0x0adc /*(U+25C0 BLACK LEFT-POINTING TRIANGLE)*/ +#define XK_filledrighttribullet 0x0add /*(U+25B6 BLACK RIGHT-POINTING TRIANGLE)*/ +#define XK_emfilledcircle 0x0ade /*(U+25CF BLACK CIRCLE)*/ +#define XK_emfilledrect 0x0adf /*(U+25AE BLACK VERTICAL RECTANGLE)*/ +#define XK_enopencircbullet 0x0ae0 /*(U+25E6 WHITE BULLET)*/ +#define XK_enopensquarebullet 0x0ae1 /*(U+25AB WHITE SMALL SQUARE)*/ +#define XK_openrectbullet 0x0ae2 /*(U+25AD WHITE RECTANGLE)*/ +#define XK_opentribulletup 0x0ae3 /*(U+25B3 WHITE UP-POINTING TRIANGLE)*/ +#define XK_opentribulletdown 0x0ae4 /*(U+25BD WHITE DOWN-POINTING TRIANGLE)*/ +#define XK_openstar 0x0ae5 /*(U+2606 WHITE STAR)*/ +#define XK_enfilledcircbullet 0x0ae6 /*(U+2022 BULLET)*/ +#define XK_enfilledsqbullet 0x0ae7 /*(U+25AA BLACK SMALL SQUARE)*/ +#define XK_filledtribulletup 0x0ae8 /*(U+25B2 BLACK UP-POINTING TRIANGLE)*/ +#define XK_filledtribulletdown 0x0ae9 /*(U+25BC BLACK DOWN-POINTING TRIANGLE)*/ +#define XK_leftpointer 0x0aea /*(U+261C WHITE LEFT POINTING INDEX)*/ +#define XK_rightpointer 0x0aeb /*(U+261E WHITE RIGHT POINTING INDEX)*/ +#define XK_club 0x0aec /* U+2663 BLACK CLUB SUIT */ +#define XK_diamond 0x0aed /* U+2666 BLACK DIAMOND SUIT */ +#define XK_heart 0x0aee /* U+2665 BLACK HEART SUIT */ +#define XK_maltesecross 0x0af0 /* U+2720 MALTESE CROSS */ +#define XK_dagger 0x0af1 /* U+2020 DAGGER */ +#define XK_doubledagger 0x0af2 /* U+2021 DOUBLE DAGGER */ +#define XK_checkmark 0x0af3 /* U+2713 CHECK MARK */ +#define XK_ballotcross 0x0af4 /* U+2717 BALLOT X */ +#define XK_musicalsharp 0x0af5 /* U+266F MUSIC SHARP SIGN */ +#define XK_musicalflat 0x0af6 /* U+266D MUSIC FLAT SIGN */ +#define XK_malesymbol 0x0af7 /* U+2642 MALE SIGN */ +#define XK_femalesymbol 0x0af8 /* U+2640 FEMALE SIGN */ +#define XK_telephone 0x0af9 /* U+260E BLACK TELEPHONE */ +#define XK_telephonerecorder 0x0afa /* U+2315 TELEPHONE RECORDER */ +#define XK_phonographcopyright 0x0afb /* U+2117 SOUND RECORDING COPYRIGHT */ +#define XK_caret 0x0afc /* U+2038 CARET */ +#define XK_singlelowquotemark 0x0afd /* U+201A SINGLE LOW-9 QUOTATION MARK */ +#define XK_doublelowquotemark 0x0afe /* U+201E DOUBLE LOW-9 QUOTATION MARK */ +#define XK_cursor 0x0aff +#endif /* XK_PUBLISHING */ + +/* + * APL + * Byte 3 = 0x0b + */ + +#ifdef XK_APL +#define XK_leftcaret 0x0ba3 /*(U+003C LESS-THAN SIGN)*/ +#define XK_rightcaret 0x0ba6 /*(U+003E GREATER-THAN SIGN)*/ +#define XK_downcaret 0x0ba8 /*(U+2228 LOGICAL OR)*/ +#define XK_upcaret 0x0ba9 /*(U+2227 LOGICAL AND)*/ +#define XK_overbar 0x0bc0 /*(U+00AF MACRON)*/ +#define XK_downtack 0x0bc2 /* U+22A5 UP TACK */ +#define XK_upshoe 0x0bc3 /*(U+2229 INTERSECTION)*/ +#define XK_downstile 0x0bc4 /* U+230A LEFT FLOOR */ +#define XK_underbar 0x0bc6 /*(U+005F LOW LINE)*/ +#define XK_jot 0x0bca /* U+2218 RING OPERATOR */ +#define XK_quad 0x0bcc /* U+2395 APL FUNCTIONAL SYMBOL QUAD */ +#define XK_uptack 0x0bce /* U+22A4 DOWN TACK */ +#define XK_circle 0x0bcf /* U+25CB WHITE CIRCLE */ +#define XK_upstile 0x0bd3 /* U+2308 LEFT CEILING */ +#define XK_downshoe 0x0bd6 /*(U+222A UNION)*/ +#define XK_rightshoe 0x0bd8 /*(U+2283 SUPERSET OF)*/ +#define XK_leftshoe 0x0bda /*(U+2282 SUBSET OF)*/ +#define XK_lefttack 0x0bdc /* U+22A2 RIGHT TACK */ +#define XK_righttack 0x0bfc /* U+22A3 LEFT TACK */ +#endif /* XK_APL */ + +/* + * Hebrew + * Byte 3 = 0x0c + */ + +#ifdef XK_HEBREW +#define XK_hebrew_doublelowline 0x0cdf /* U+2017 DOUBLE LOW LINE */ +#define XK_hebrew_aleph 0x0ce0 /* U+05D0 HEBREW LETTER ALEF */ +#define XK_hebrew_bet 0x0ce1 /* U+05D1 HEBREW LETTER BET */ +#define XK_hebrew_beth 0x0ce1 /* deprecated */ +#define XK_hebrew_gimel 0x0ce2 /* U+05D2 HEBREW LETTER GIMEL */ +#define XK_hebrew_gimmel 0x0ce2 /* deprecated */ +#define XK_hebrew_dalet 0x0ce3 /* U+05D3 HEBREW LETTER DALET */ +#define XK_hebrew_daleth 0x0ce3 /* deprecated */ +#define XK_hebrew_he 0x0ce4 /* U+05D4 HEBREW LETTER HE */ +#define XK_hebrew_waw 0x0ce5 /* U+05D5 HEBREW LETTER VAV */ +#define XK_hebrew_zain 0x0ce6 /* U+05D6 HEBREW LETTER ZAYIN */ +#define XK_hebrew_zayin 0x0ce6 /* deprecated */ +#define XK_hebrew_chet 0x0ce7 /* U+05D7 HEBREW LETTER HET */ +#define XK_hebrew_het 0x0ce7 /* deprecated */ +#define XK_hebrew_tet 0x0ce8 /* U+05D8 HEBREW LETTER TET */ +#define XK_hebrew_teth 0x0ce8 /* deprecated */ +#define XK_hebrew_yod 0x0ce9 /* U+05D9 HEBREW LETTER YOD */ +#define XK_hebrew_finalkaph 0x0cea /* U+05DA HEBREW LETTER FINAL KAF */ +#define XK_hebrew_kaph 0x0ceb /* U+05DB HEBREW LETTER KAF */ +#define XK_hebrew_lamed 0x0cec /* U+05DC HEBREW LETTER LAMED */ +#define XK_hebrew_finalmem 0x0ced /* U+05DD HEBREW LETTER FINAL MEM */ +#define XK_hebrew_mem 0x0cee /* U+05DE HEBREW LETTER MEM */ +#define XK_hebrew_finalnun 0x0cef /* U+05DF HEBREW LETTER FINAL NUN */ +#define XK_hebrew_nun 0x0cf0 /* U+05E0 HEBREW LETTER NUN */ +#define XK_hebrew_samech 0x0cf1 /* U+05E1 HEBREW LETTER SAMEKH */ +#define XK_hebrew_samekh 0x0cf1 /* deprecated */ +#define XK_hebrew_ayin 0x0cf2 /* U+05E2 HEBREW LETTER AYIN */ +#define XK_hebrew_finalpe 0x0cf3 /* U+05E3 HEBREW LETTER FINAL PE */ +#define XK_hebrew_pe 0x0cf4 /* U+05E4 HEBREW LETTER PE */ +#define XK_hebrew_finalzade 0x0cf5 /* U+05E5 HEBREW LETTER FINAL TSADI */ +#define XK_hebrew_finalzadi 0x0cf5 /* deprecated */ +#define XK_hebrew_zade 0x0cf6 /* U+05E6 HEBREW LETTER TSADI */ +#define XK_hebrew_zadi 0x0cf6 /* deprecated */ +#define XK_hebrew_qoph 0x0cf7 /* U+05E7 HEBREW LETTER QOF */ +#define XK_hebrew_kuf 0x0cf7 /* deprecated */ +#define XK_hebrew_resh 0x0cf8 /* U+05E8 HEBREW LETTER RESH */ +#define XK_hebrew_shin 0x0cf9 /* U+05E9 HEBREW LETTER SHIN */ +#define XK_hebrew_taw 0x0cfa /* U+05EA HEBREW LETTER TAV */ +#define XK_hebrew_taf 0x0cfa /* deprecated */ +#define XK_Hebrew_switch 0xff7e /* Alias for mode_switch */ +#endif /* XK_HEBREW */ + +/* + * Thai + * Byte 3 = 0x0d + */ + +#ifdef XK_THAI +#define XK_Thai_kokai 0x0da1 /* U+0E01 THAI CHARACTER KO KAI */ +#define XK_Thai_khokhai 0x0da2 /* U+0E02 THAI CHARACTER KHO KHAI */ +#define XK_Thai_khokhuat 0x0da3 /* U+0E03 THAI CHARACTER KHO KHUAT */ +#define XK_Thai_khokhwai 0x0da4 /* U+0E04 THAI CHARACTER KHO KHWAI */ +#define XK_Thai_khokhon 0x0da5 /* U+0E05 THAI CHARACTER KHO KHON */ +#define XK_Thai_khorakhang 0x0da6 /* U+0E06 THAI CHARACTER KHO RAKHANG */ +#define XK_Thai_ngongu 0x0da7 /* U+0E07 THAI CHARACTER NGO NGU */ +#define XK_Thai_chochan 0x0da8 /* U+0E08 THAI CHARACTER CHO CHAN */ +#define XK_Thai_choching 0x0da9 /* U+0E09 THAI CHARACTER CHO CHING */ +#define XK_Thai_chochang 0x0daa /* U+0E0A THAI CHARACTER CHO CHANG */ +#define XK_Thai_soso 0x0dab /* U+0E0B THAI CHARACTER SO SO */ +#define XK_Thai_chochoe 0x0dac /* U+0E0C THAI CHARACTER CHO CHOE */ +#define XK_Thai_yoying 0x0dad /* U+0E0D THAI CHARACTER YO YING */ +#define XK_Thai_dochada 0x0dae /* U+0E0E THAI CHARACTER DO CHADA */ +#define XK_Thai_topatak 0x0daf /* U+0E0F THAI CHARACTER TO PATAK */ +#define XK_Thai_thothan 0x0db0 /* U+0E10 THAI CHARACTER THO THAN */ +#define XK_Thai_thonangmontho 0x0db1 /* U+0E11 THAI CHARACTER THO NANGMONTHO */ +#define XK_Thai_thophuthao 0x0db2 /* U+0E12 THAI CHARACTER THO PHUTHAO */ +#define XK_Thai_nonen 0x0db3 /* U+0E13 THAI CHARACTER NO NEN */ +#define XK_Thai_dodek 0x0db4 /* U+0E14 THAI CHARACTER DO DEK */ +#define XK_Thai_totao 0x0db5 /* U+0E15 THAI CHARACTER TO TAO */ +#define XK_Thai_thothung 0x0db6 /* U+0E16 THAI CHARACTER THO THUNG */ +#define XK_Thai_thothahan 0x0db7 /* U+0E17 THAI CHARACTER THO THAHAN */ +#define XK_Thai_thothong 0x0db8 /* U+0E18 THAI CHARACTER THO THONG */ +#define XK_Thai_nonu 0x0db9 /* U+0E19 THAI CHARACTER NO NU */ +#define XK_Thai_bobaimai 0x0dba /* U+0E1A THAI CHARACTER BO BAIMAI */ +#define XK_Thai_popla 0x0dbb /* U+0E1B THAI CHARACTER PO PLA */ +#define XK_Thai_phophung 0x0dbc /* U+0E1C THAI CHARACTER PHO PHUNG */ +#define XK_Thai_fofa 0x0dbd /* U+0E1D THAI CHARACTER FO FA */ +#define XK_Thai_phophan 0x0dbe /* U+0E1E THAI CHARACTER PHO PHAN */ +#define XK_Thai_fofan 0x0dbf /* U+0E1F THAI CHARACTER FO FAN */ +#define XK_Thai_phosamphao 0x0dc0 /* U+0E20 THAI CHARACTER PHO SAMPHAO */ +#define XK_Thai_moma 0x0dc1 /* U+0E21 THAI CHARACTER MO MA */ +#define XK_Thai_yoyak 0x0dc2 /* U+0E22 THAI CHARACTER YO YAK */ +#define XK_Thai_rorua 0x0dc3 /* U+0E23 THAI CHARACTER RO RUA */ +#define XK_Thai_ru 0x0dc4 /* U+0E24 THAI CHARACTER RU */ +#define XK_Thai_loling 0x0dc5 /* U+0E25 THAI CHARACTER LO LING */ +#define XK_Thai_lu 0x0dc6 /* U+0E26 THAI CHARACTER LU */ +#define XK_Thai_wowaen 0x0dc7 /* U+0E27 THAI CHARACTER WO WAEN */ +#define XK_Thai_sosala 0x0dc8 /* U+0E28 THAI CHARACTER SO SALA */ +#define XK_Thai_sorusi 0x0dc9 /* U+0E29 THAI CHARACTER SO RUSI */ +#define XK_Thai_sosua 0x0dca /* U+0E2A THAI CHARACTER SO SUA */ +#define XK_Thai_hohip 0x0dcb /* U+0E2B THAI CHARACTER HO HIP */ +#define XK_Thai_lochula 0x0dcc /* U+0E2C THAI CHARACTER LO CHULA */ +#define XK_Thai_oang 0x0dcd /* U+0E2D THAI CHARACTER O ANG */ +#define XK_Thai_honokhuk 0x0dce /* U+0E2E THAI CHARACTER HO NOKHUK */ +#define XK_Thai_paiyannoi 0x0dcf /* U+0E2F THAI CHARACTER PAIYANNOI */ +#define XK_Thai_saraa 0x0dd0 /* U+0E30 THAI CHARACTER SARA A */ +#define XK_Thai_maihanakat 0x0dd1 /* U+0E31 THAI CHARACTER MAI HAN-AKAT */ +#define XK_Thai_saraaa 0x0dd2 /* U+0E32 THAI CHARACTER SARA AA */ +#define XK_Thai_saraam 0x0dd3 /* U+0E33 THAI CHARACTER SARA AM */ +#define XK_Thai_sarai 0x0dd4 /* U+0E34 THAI CHARACTER SARA I */ +#define XK_Thai_saraii 0x0dd5 /* U+0E35 THAI CHARACTER SARA II */ +#define XK_Thai_saraue 0x0dd6 /* U+0E36 THAI CHARACTER SARA UE */ +#define XK_Thai_sarauee 0x0dd7 /* U+0E37 THAI CHARACTER SARA UEE */ +#define XK_Thai_sarau 0x0dd8 /* U+0E38 THAI CHARACTER SARA U */ +#define XK_Thai_sarauu 0x0dd9 /* U+0E39 THAI CHARACTER SARA UU */ +#define XK_Thai_phinthu 0x0dda /* U+0E3A THAI CHARACTER PHINTHU */ +#define XK_Thai_maihanakat_maitho 0x0dde +#define XK_Thai_baht 0x0ddf /* U+0E3F THAI CURRENCY SYMBOL BAHT */ +#define XK_Thai_sarae 0x0de0 /* U+0E40 THAI CHARACTER SARA E */ +#define XK_Thai_saraae 0x0de1 /* U+0E41 THAI CHARACTER SARA AE */ +#define XK_Thai_sarao 0x0de2 /* U+0E42 THAI CHARACTER SARA O */ +#define XK_Thai_saraaimaimuan 0x0de3 /* U+0E43 THAI CHARACTER SARA AI MAIMUAN */ +#define XK_Thai_saraaimaimalai 0x0de4 /* U+0E44 THAI CHARACTER SARA AI MAIMALAI */ +#define XK_Thai_lakkhangyao 0x0de5 /* U+0E45 THAI CHARACTER LAKKHANGYAO */ +#define XK_Thai_maiyamok 0x0de6 /* U+0E46 THAI CHARACTER MAIYAMOK */ +#define XK_Thai_maitaikhu 0x0de7 /* U+0E47 THAI CHARACTER MAITAIKHU */ +#define XK_Thai_maiek 0x0de8 /* U+0E48 THAI CHARACTER MAI EK */ +#define XK_Thai_maitho 0x0de9 /* U+0E49 THAI CHARACTER MAI THO */ +#define XK_Thai_maitri 0x0dea /* U+0E4A THAI CHARACTER MAI TRI */ +#define XK_Thai_maichattawa 0x0deb /* U+0E4B THAI CHARACTER MAI CHATTAWA */ +#define XK_Thai_thanthakhat 0x0dec /* U+0E4C THAI CHARACTER THANTHAKHAT */ +#define XK_Thai_nikhahit 0x0ded /* U+0E4D THAI CHARACTER NIKHAHIT */ +#define XK_Thai_leksun 0x0df0 /* U+0E50 THAI DIGIT ZERO */ +#define XK_Thai_leknung 0x0df1 /* U+0E51 THAI DIGIT ONE */ +#define XK_Thai_leksong 0x0df2 /* U+0E52 THAI DIGIT TWO */ +#define XK_Thai_leksam 0x0df3 /* U+0E53 THAI DIGIT THREE */ +#define XK_Thai_leksi 0x0df4 /* U+0E54 THAI DIGIT FOUR */ +#define XK_Thai_lekha 0x0df5 /* U+0E55 THAI DIGIT FIVE */ +#define XK_Thai_lekhok 0x0df6 /* U+0E56 THAI DIGIT SIX */ +#define XK_Thai_lekchet 0x0df7 /* U+0E57 THAI DIGIT SEVEN */ +#define XK_Thai_lekpaet 0x0df8 /* U+0E58 THAI DIGIT EIGHT */ +#define XK_Thai_lekkao 0x0df9 /* U+0E59 THAI DIGIT NINE */ +#endif /* XK_THAI */ + +/* + * Korean + * Byte 3 = 0x0e + */ + +#ifdef XK_KOREAN + +#define XK_Hangul 0xff31 /* Hangul start/stop(toggle) */ +#define XK_Hangul_Start 0xff32 /* Hangul start */ +#define XK_Hangul_End 0xff33 /* Hangul end, English start */ +#define XK_Hangul_Hanja 0xff34 /* Start Hangul->Hanja Conversion */ +#define XK_Hangul_Jamo 0xff35 /* Hangul Jamo mode */ +#define XK_Hangul_Romaja 0xff36 /* Hangul Romaja mode */ +#define XK_Hangul_Codeinput 0xff37 /* Hangul code input mode */ +#define XK_Hangul_Jeonja 0xff38 /* Jeonja mode */ +#define XK_Hangul_Banja 0xff39 /* Banja mode */ +#define XK_Hangul_PreHanja 0xff3a /* Pre Hanja conversion */ +#define XK_Hangul_PostHanja 0xff3b /* Post Hanja conversion */ +#define XK_Hangul_SingleCandidate 0xff3c /* Single candidate */ +#define XK_Hangul_MultipleCandidate 0xff3d /* Multiple candidate */ +#define XK_Hangul_PreviousCandidate 0xff3e /* Previous candidate */ +#define XK_Hangul_Special 0xff3f /* Special symbols */ +#define XK_Hangul_switch 0xff7e /* Alias for mode_switch */ + +/* Hangul Consonant Characters */ +#define XK_Hangul_Kiyeog 0x0ea1 +#define XK_Hangul_SsangKiyeog 0x0ea2 +#define XK_Hangul_KiyeogSios 0x0ea3 +#define XK_Hangul_Nieun 0x0ea4 +#define XK_Hangul_NieunJieuj 0x0ea5 +#define XK_Hangul_NieunHieuh 0x0ea6 +#define XK_Hangul_Dikeud 0x0ea7 +#define XK_Hangul_SsangDikeud 0x0ea8 +#define XK_Hangul_Rieul 0x0ea9 +#define XK_Hangul_RieulKiyeog 0x0eaa +#define XK_Hangul_RieulMieum 0x0eab +#define XK_Hangul_RieulPieub 0x0eac +#define XK_Hangul_RieulSios 0x0ead +#define XK_Hangul_RieulTieut 0x0eae +#define XK_Hangul_RieulPhieuf 0x0eaf +#define XK_Hangul_RieulHieuh 0x0eb0 +#define XK_Hangul_Mieum 0x0eb1 +#define XK_Hangul_Pieub 0x0eb2 +#define XK_Hangul_SsangPieub 0x0eb3 +#define XK_Hangul_PieubSios 0x0eb4 +#define XK_Hangul_Sios 0x0eb5 +#define XK_Hangul_SsangSios 0x0eb6 +#define XK_Hangul_Ieung 0x0eb7 +#define XK_Hangul_Jieuj 0x0eb8 +#define XK_Hangul_SsangJieuj 0x0eb9 +#define XK_Hangul_Cieuc 0x0eba +#define XK_Hangul_Khieuq 0x0ebb +#define XK_Hangul_Tieut 0x0ebc +#define XK_Hangul_Phieuf 0x0ebd +#define XK_Hangul_Hieuh 0x0ebe + +/* Hangul Vowel Characters */ +#define XK_Hangul_A 0x0ebf +#define XK_Hangul_AE 0x0ec0 +#define XK_Hangul_YA 0x0ec1 +#define XK_Hangul_YAE 0x0ec2 +#define XK_Hangul_EO 0x0ec3 +#define XK_Hangul_E 0x0ec4 +#define XK_Hangul_YEO 0x0ec5 +#define XK_Hangul_YE 0x0ec6 +#define XK_Hangul_O 0x0ec7 +#define XK_Hangul_WA 0x0ec8 +#define XK_Hangul_WAE 0x0ec9 +#define XK_Hangul_OE 0x0eca +#define XK_Hangul_YO 0x0ecb +#define XK_Hangul_U 0x0ecc +#define XK_Hangul_WEO 0x0ecd +#define XK_Hangul_WE 0x0ece +#define XK_Hangul_WI 0x0ecf +#define XK_Hangul_YU 0x0ed0 +#define XK_Hangul_EU 0x0ed1 +#define XK_Hangul_YI 0x0ed2 +#define XK_Hangul_I 0x0ed3 + +/* Hangul syllable-final (JongSeong) Characters */ +#define XK_Hangul_J_Kiyeog 0x0ed4 +#define XK_Hangul_J_SsangKiyeog 0x0ed5 +#define XK_Hangul_J_KiyeogSios 0x0ed6 +#define XK_Hangul_J_Nieun 0x0ed7 +#define XK_Hangul_J_NieunJieuj 0x0ed8 +#define XK_Hangul_J_NieunHieuh 0x0ed9 +#define XK_Hangul_J_Dikeud 0x0eda +#define XK_Hangul_J_Rieul 0x0edb +#define XK_Hangul_J_RieulKiyeog 0x0edc +#define XK_Hangul_J_RieulMieum 0x0edd +#define XK_Hangul_J_RieulPieub 0x0ede +#define XK_Hangul_J_RieulSios 0x0edf +#define XK_Hangul_J_RieulTieut 0x0ee0 +#define XK_Hangul_J_RieulPhieuf 0x0ee1 +#define XK_Hangul_J_RieulHieuh 0x0ee2 +#define XK_Hangul_J_Mieum 0x0ee3 +#define XK_Hangul_J_Pieub 0x0ee4 +#define XK_Hangul_J_PieubSios 0x0ee5 +#define XK_Hangul_J_Sios 0x0ee6 +#define XK_Hangul_J_SsangSios 0x0ee7 +#define XK_Hangul_J_Ieung 0x0ee8 +#define XK_Hangul_J_Jieuj 0x0ee9 +#define XK_Hangul_J_Cieuc 0x0eea +#define XK_Hangul_J_Khieuq 0x0eeb +#define XK_Hangul_J_Tieut 0x0eec +#define XK_Hangul_J_Phieuf 0x0eed +#define XK_Hangul_J_Hieuh 0x0eee + +/* Ancient Hangul Consonant Characters */ +#define XK_Hangul_RieulYeorinHieuh 0x0eef +#define XK_Hangul_SunkyeongeumMieum 0x0ef0 +#define XK_Hangul_SunkyeongeumPieub 0x0ef1 +#define XK_Hangul_PanSios 0x0ef2 +#define XK_Hangul_KkogjiDalrinIeung 0x0ef3 +#define XK_Hangul_SunkyeongeumPhieuf 0x0ef4 +#define XK_Hangul_YeorinHieuh 0x0ef5 + +/* Ancient Hangul Vowel Characters */ +#define XK_Hangul_AraeA 0x0ef6 +#define XK_Hangul_AraeAE 0x0ef7 + +/* Ancient Hangul syllable-final (JongSeong) Characters */ +#define XK_Hangul_J_PanSios 0x0ef8 +#define XK_Hangul_J_KkogjiDalrinIeung 0x0ef9 +#define XK_Hangul_J_YeorinHieuh 0x0efa + +/* Korean currency symbol */ +#define XK_Korean_Won 0x0eff /*(U+20A9 WON SIGN)*/ + +#endif /* XK_KOREAN */ + +/* + * Armenian + */ + +#ifdef XK_ARMENIAN +#define XK_Armenian_ligature_ew 0x1000587 /* U+0587 ARMENIAN SMALL LIGATURE ECH YIWN */ +#define XK_Armenian_full_stop 0x1000589 /* U+0589 ARMENIAN FULL STOP */ +#define XK_Armenian_verjaket 0x1000589 /* U+0589 ARMENIAN FULL STOP */ +#define XK_Armenian_separation_mark 0x100055d /* U+055D ARMENIAN COMMA */ +#define XK_Armenian_but 0x100055d /* U+055D ARMENIAN COMMA */ +#define XK_Armenian_hyphen 0x100058a /* U+058A ARMENIAN HYPHEN */ +#define XK_Armenian_yentamna 0x100058a /* U+058A ARMENIAN HYPHEN */ +#define XK_Armenian_exclam 0x100055c /* U+055C ARMENIAN EXCLAMATION MARK */ +#define XK_Armenian_amanak 0x100055c /* U+055C ARMENIAN EXCLAMATION MARK */ +#define XK_Armenian_accent 0x100055b /* U+055B ARMENIAN EMPHASIS MARK */ +#define XK_Armenian_shesht 0x100055b /* U+055B ARMENIAN EMPHASIS MARK */ +#define XK_Armenian_question 0x100055e /* U+055E ARMENIAN QUESTION MARK */ +#define XK_Armenian_paruyk 0x100055e /* U+055E ARMENIAN QUESTION MARK */ +#define XK_Armenian_AYB 0x1000531 /* U+0531 ARMENIAN CAPITAL LETTER AYB */ +#define XK_Armenian_ayb 0x1000561 /* U+0561 ARMENIAN SMALL LETTER AYB */ +#define XK_Armenian_BEN 0x1000532 /* U+0532 ARMENIAN CAPITAL LETTER BEN */ +#define XK_Armenian_ben 0x1000562 /* U+0562 ARMENIAN SMALL LETTER BEN */ +#define XK_Armenian_GIM 0x1000533 /* U+0533 ARMENIAN CAPITAL LETTER GIM */ +#define XK_Armenian_gim 0x1000563 /* U+0563 ARMENIAN SMALL LETTER GIM */ +#define XK_Armenian_DA 0x1000534 /* U+0534 ARMENIAN CAPITAL LETTER DA */ +#define XK_Armenian_da 0x1000564 /* U+0564 ARMENIAN SMALL LETTER DA */ +#define XK_Armenian_YECH 0x1000535 /* U+0535 ARMENIAN CAPITAL LETTER ECH */ +#define XK_Armenian_yech 0x1000565 /* U+0565 ARMENIAN SMALL LETTER ECH */ +#define XK_Armenian_ZA 0x1000536 /* U+0536 ARMENIAN CAPITAL LETTER ZA */ +#define XK_Armenian_za 0x1000566 /* U+0566 ARMENIAN SMALL LETTER ZA */ +#define XK_Armenian_E 0x1000537 /* U+0537 ARMENIAN CAPITAL LETTER EH */ +#define XK_Armenian_e 0x1000567 /* U+0567 ARMENIAN SMALL LETTER EH */ +#define XK_Armenian_AT 0x1000538 /* U+0538 ARMENIAN CAPITAL LETTER ET */ +#define XK_Armenian_at 0x1000568 /* U+0568 ARMENIAN SMALL LETTER ET */ +#define XK_Armenian_TO 0x1000539 /* U+0539 ARMENIAN CAPITAL LETTER TO */ +#define XK_Armenian_to 0x1000569 /* U+0569 ARMENIAN SMALL LETTER TO */ +#define XK_Armenian_ZHE 0x100053a /* U+053A ARMENIAN CAPITAL LETTER ZHE */ +#define XK_Armenian_zhe 0x100056a /* U+056A ARMENIAN SMALL LETTER ZHE */ +#define XK_Armenian_INI 0x100053b /* U+053B ARMENIAN CAPITAL LETTER INI */ +#define XK_Armenian_ini 0x100056b /* U+056B ARMENIAN SMALL LETTER INI */ +#define XK_Armenian_LYUN 0x100053c /* U+053C ARMENIAN CAPITAL LETTER LIWN */ +#define XK_Armenian_lyun 0x100056c /* U+056C ARMENIAN SMALL LETTER LIWN */ +#define XK_Armenian_KHE 0x100053d /* U+053D ARMENIAN CAPITAL LETTER XEH */ +#define XK_Armenian_khe 0x100056d /* U+056D ARMENIAN SMALL LETTER XEH */ +#define XK_Armenian_TSA 0x100053e /* U+053E ARMENIAN CAPITAL LETTER CA */ +#define XK_Armenian_tsa 0x100056e /* U+056E ARMENIAN SMALL LETTER CA */ +#define XK_Armenian_KEN 0x100053f /* U+053F ARMENIAN CAPITAL LETTER KEN */ +#define XK_Armenian_ken 0x100056f /* U+056F ARMENIAN SMALL LETTER KEN */ +#define XK_Armenian_HO 0x1000540 /* U+0540 ARMENIAN CAPITAL LETTER HO */ +#define XK_Armenian_ho 0x1000570 /* U+0570 ARMENIAN SMALL LETTER HO */ +#define XK_Armenian_DZA 0x1000541 /* U+0541 ARMENIAN CAPITAL LETTER JA */ +#define XK_Armenian_dza 0x1000571 /* U+0571 ARMENIAN SMALL LETTER JA */ +#define XK_Armenian_GHAT 0x1000542 /* U+0542 ARMENIAN CAPITAL LETTER GHAD */ +#define XK_Armenian_ghat 0x1000572 /* U+0572 ARMENIAN SMALL LETTER GHAD */ +#define XK_Armenian_TCHE 0x1000543 /* U+0543 ARMENIAN CAPITAL LETTER CHEH */ +#define XK_Armenian_tche 0x1000573 /* U+0573 ARMENIAN SMALL LETTER CHEH */ +#define XK_Armenian_MEN 0x1000544 /* U+0544 ARMENIAN CAPITAL LETTER MEN */ +#define XK_Armenian_men 0x1000574 /* U+0574 ARMENIAN SMALL LETTER MEN */ +#define XK_Armenian_HI 0x1000545 /* U+0545 ARMENIAN CAPITAL LETTER YI */ +#define XK_Armenian_hi 0x1000575 /* U+0575 ARMENIAN SMALL LETTER YI */ +#define XK_Armenian_NU 0x1000546 /* U+0546 ARMENIAN CAPITAL LETTER NOW */ +#define XK_Armenian_nu 0x1000576 /* U+0576 ARMENIAN SMALL LETTER NOW */ +#define XK_Armenian_SHA 0x1000547 /* U+0547 ARMENIAN CAPITAL LETTER SHA */ +#define XK_Armenian_sha 0x1000577 /* U+0577 ARMENIAN SMALL LETTER SHA */ +#define XK_Armenian_VO 0x1000548 /* U+0548 ARMENIAN CAPITAL LETTER VO */ +#define XK_Armenian_vo 0x1000578 /* U+0578 ARMENIAN SMALL LETTER VO */ +#define XK_Armenian_CHA 0x1000549 /* U+0549 ARMENIAN CAPITAL LETTER CHA */ +#define XK_Armenian_cha 0x1000579 /* U+0579 ARMENIAN SMALL LETTER CHA */ +#define XK_Armenian_PE 0x100054a /* U+054A ARMENIAN CAPITAL LETTER PEH */ +#define XK_Armenian_pe 0x100057a /* U+057A ARMENIAN SMALL LETTER PEH */ +#define XK_Armenian_JE 0x100054b /* U+054B ARMENIAN CAPITAL LETTER JHEH */ +#define XK_Armenian_je 0x100057b /* U+057B ARMENIAN SMALL LETTER JHEH */ +#define XK_Armenian_RA 0x100054c /* U+054C ARMENIAN CAPITAL LETTER RA */ +#define XK_Armenian_ra 0x100057c /* U+057C ARMENIAN SMALL LETTER RA */ +#define XK_Armenian_SE 0x100054d /* U+054D ARMENIAN CAPITAL LETTER SEH */ +#define XK_Armenian_se 0x100057d /* U+057D ARMENIAN SMALL LETTER SEH */ +#define XK_Armenian_VEV 0x100054e /* U+054E ARMENIAN CAPITAL LETTER VEW */ +#define XK_Armenian_vev 0x100057e /* U+057E ARMENIAN SMALL LETTER VEW */ +#define XK_Armenian_TYUN 0x100054f /* U+054F ARMENIAN CAPITAL LETTER TIWN */ +#define XK_Armenian_tyun 0x100057f /* U+057F ARMENIAN SMALL LETTER TIWN */ +#define XK_Armenian_RE 0x1000550 /* U+0550 ARMENIAN CAPITAL LETTER REH */ +#define XK_Armenian_re 0x1000580 /* U+0580 ARMENIAN SMALL LETTER REH */ +#define XK_Armenian_TSO 0x1000551 /* U+0551 ARMENIAN CAPITAL LETTER CO */ +#define XK_Armenian_tso 0x1000581 /* U+0581 ARMENIAN SMALL LETTER CO */ +#define XK_Armenian_VYUN 0x1000552 /* U+0552 ARMENIAN CAPITAL LETTER YIWN */ +#define XK_Armenian_vyun 0x1000582 /* U+0582 ARMENIAN SMALL LETTER YIWN */ +#define XK_Armenian_PYUR 0x1000553 /* U+0553 ARMENIAN CAPITAL LETTER PIWR */ +#define XK_Armenian_pyur 0x1000583 /* U+0583 ARMENIAN SMALL LETTER PIWR */ +#define XK_Armenian_KE 0x1000554 /* U+0554 ARMENIAN CAPITAL LETTER KEH */ +#define XK_Armenian_ke 0x1000584 /* U+0584 ARMENIAN SMALL LETTER KEH */ +#define XK_Armenian_O 0x1000555 /* U+0555 ARMENIAN CAPITAL LETTER OH */ +#define XK_Armenian_o 0x1000585 /* U+0585 ARMENIAN SMALL LETTER OH */ +#define XK_Armenian_FE 0x1000556 /* U+0556 ARMENIAN CAPITAL LETTER FEH */ +#define XK_Armenian_fe 0x1000586 /* U+0586 ARMENIAN SMALL LETTER FEH */ +#define XK_Armenian_apostrophe 0x100055a /* U+055A ARMENIAN APOSTROPHE */ +#endif /* XK_ARMENIAN */ + +/* + * Georgian + */ + +#ifdef XK_GEORGIAN +#define XK_Georgian_an 0x10010d0 /* U+10D0 GEORGIAN LETTER AN */ +#define XK_Georgian_ban 0x10010d1 /* U+10D1 GEORGIAN LETTER BAN */ +#define XK_Georgian_gan 0x10010d2 /* U+10D2 GEORGIAN LETTER GAN */ +#define XK_Georgian_don 0x10010d3 /* U+10D3 GEORGIAN LETTER DON */ +#define XK_Georgian_en 0x10010d4 /* U+10D4 GEORGIAN LETTER EN */ +#define XK_Georgian_vin 0x10010d5 /* U+10D5 GEORGIAN LETTER VIN */ +#define XK_Georgian_zen 0x10010d6 /* U+10D6 GEORGIAN LETTER ZEN */ +#define XK_Georgian_tan 0x10010d7 /* U+10D7 GEORGIAN LETTER TAN */ +#define XK_Georgian_in 0x10010d8 /* U+10D8 GEORGIAN LETTER IN */ +#define XK_Georgian_kan 0x10010d9 /* U+10D9 GEORGIAN LETTER KAN */ +#define XK_Georgian_las 0x10010da /* U+10DA GEORGIAN LETTER LAS */ +#define XK_Georgian_man 0x10010db /* U+10DB GEORGIAN LETTER MAN */ +#define XK_Georgian_nar 0x10010dc /* U+10DC GEORGIAN LETTER NAR */ +#define XK_Georgian_on 0x10010dd /* U+10DD GEORGIAN LETTER ON */ +#define XK_Georgian_par 0x10010de /* U+10DE GEORGIAN LETTER PAR */ +#define XK_Georgian_zhar 0x10010df /* U+10DF GEORGIAN LETTER ZHAR */ +#define XK_Georgian_rae 0x10010e0 /* U+10E0 GEORGIAN LETTER RAE */ +#define XK_Georgian_san 0x10010e1 /* U+10E1 GEORGIAN LETTER SAN */ +#define XK_Georgian_tar 0x10010e2 /* U+10E2 GEORGIAN LETTER TAR */ +#define XK_Georgian_un 0x10010e3 /* U+10E3 GEORGIAN LETTER UN */ +#define XK_Georgian_phar 0x10010e4 /* U+10E4 GEORGIAN LETTER PHAR */ +#define XK_Georgian_khar 0x10010e5 /* U+10E5 GEORGIAN LETTER KHAR */ +#define XK_Georgian_ghan 0x10010e6 /* U+10E6 GEORGIAN LETTER GHAN */ +#define XK_Georgian_qar 0x10010e7 /* U+10E7 GEORGIAN LETTER QAR */ +#define XK_Georgian_shin 0x10010e8 /* U+10E8 GEORGIAN LETTER SHIN */ +#define XK_Georgian_chin 0x10010e9 /* U+10E9 GEORGIAN LETTER CHIN */ +#define XK_Georgian_can 0x10010ea /* U+10EA GEORGIAN LETTER CAN */ +#define XK_Georgian_jil 0x10010eb /* U+10EB GEORGIAN LETTER JIL */ +#define XK_Georgian_cil 0x10010ec /* U+10EC GEORGIAN LETTER CIL */ +#define XK_Georgian_char 0x10010ed /* U+10ED GEORGIAN LETTER CHAR */ +#define XK_Georgian_xan 0x10010ee /* U+10EE GEORGIAN LETTER XAN */ +#define XK_Georgian_jhan 0x10010ef /* U+10EF GEORGIAN LETTER JHAN */ +#define XK_Georgian_hae 0x10010f0 /* U+10F0 GEORGIAN LETTER HAE */ +#define XK_Georgian_he 0x10010f1 /* U+10F1 GEORGIAN LETTER HE */ +#define XK_Georgian_hie 0x10010f2 /* U+10F2 GEORGIAN LETTER HIE */ +#define XK_Georgian_we 0x10010f3 /* U+10F3 GEORGIAN LETTER WE */ +#define XK_Georgian_har 0x10010f4 /* U+10F4 GEORGIAN LETTER HAR */ +#define XK_Georgian_hoe 0x10010f5 /* U+10F5 GEORGIAN LETTER HOE */ +#define XK_Georgian_fi 0x10010f6 /* U+10F6 GEORGIAN LETTER FI */ +#endif /* XK_GEORGIAN */ + +/* + * Azeri (and other Turkic or Caucasian languages) + */ + +#ifdef XK_CAUCASUS +/* latin */ +#define XK_Xabovedot 0x1001e8a /* U+1E8A LATIN CAPITAL LETTER X WITH DOT ABOVE */ +#define XK_Ibreve 0x100012c /* U+012C LATIN CAPITAL LETTER I WITH BREVE */ +#define XK_Zstroke 0x10001b5 /* U+01B5 LATIN CAPITAL LETTER Z WITH STROKE */ +#define XK_Gcaron 0x10001e6 /* U+01E6 LATIN CAPITAL LETTER G WITH CARON */ +#define XK_Ocaron 0x10001d1 /* U+01D2 LATIN CAPITAL LETTER O WITH CARON */ +#define XK_Obarred 0x100019f /* U+019F LATIN CAPITAL LETTER O WITH MIDDLE TILDE */ +#define XK_xabovedot 0x1001e8b /* U+1E8B LATIN SMALL LETTER X WITH DOT ABOVE */ +#define XK_ibreve 0x100012d /* U+012D LATIN SMALL LETTER I WITH BREVE */ +#define XK_zstroke 0x10001b6 /* U+01B6 LATIN SMALL LETTER Z WITH STROKE */ +#define XK_gcaron 0x10001e7 /* U+01E7 LATIN SMALL LETTER G WITH CARON */ +#define XK_ocaron 0x10001d2 /* U+01D2 LATIN SMALL LETTER O WITH CARON */ +#define XK_obarred 0x1000275 /* U+0275 LATIN SMALL LETTER BARRED O */ +#define XK_SCHWA 0x100018f /* U+018F LATIN CAPITAL LETTER SCHWA */ +#define XK_schwa 0x1000259 /* U+0259 LATIN SMALL LETTER SCHWA */ +/* those are not really Caucasus */ +/* For Inupiak */ +#define XK_Lbelowdot 0x1001e36 /* U+1E36 LATIN CAPITAL LETTER L WITH DOT BELOW */ +#define XK_lbelowdot 0x1001e37 /* U+1E37 LATIN SMALL LETTER L WITH DOT BELOW */ +#endif /* XK_CAUCASUS */ + +/* + * Vietnamese + */ + +#ifdef XK_VIETNAMESE +#define XK_Abelowdot 0x1001ea0 /* U+1EA0 LATIN CAPITAL LETTER A WITH DOT BELOW */ +#define XK_abelowdot 0x1001ea1 /* U+1EA1 LATIN SMALL LETTER A WITH DOT BELOW */ +#define XK_Ahook 0x1001ea2 /* U+1EA2 LATIN CAPITAL LETTER A WITH HOOK ABOVE */ +#define XK_ahook 0x1001ea3 /* U+1EA3 LATIN SMALL LETTER A WITH HOOK ABOVE */ +#define XK_Acircumflexacute 0x1001ea4 /* U+1EA4 LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND ACUTE */ +#define XK_acircumflexacute 0x1001ea5 /* U+1EA5 LATIN SMALL LETTER A WITH CIRCUMFLEX AND ACUTE */ +#define XK_Acircumflexgrave 0x1001ea6 /* U+1EA6 LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND GRAVE */ +#define XK_acircumflexgrave 0x1001ea7 /* U+1EA7 LATIN SMALL LETTER A WITH CIRCUMFLEX AND GRAVE */ +#define XK_Acircumflexhook 0x1001ea8 /* U+1EA8 LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND HOOK ABOVE */ +#define XK_acircumflexhook 0x1001ea9 /* U+1EA9 LATIN SMALL LETTER A WITH CIRCUMFLEX AND HOOK ABOVE */ +#define XK_Acircumflextilde 0x1001eaa /* U+1EAA LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND TILDE */ +#define XK_acircumflextilde 0x1001eab /* U+1EAB LATIN SMALL LETTER A WITH CIRCUMFLEX AND TILDE */ +#define XK_Acircumflexbelowdot 0x1001eac /* U+1EAC LATIN CAPITAL LETTER A WITH CIRCUMFLEX AND DOT BELOW */ +#define XK_acircumflexbelowdot 0x1001ead /* U+1EAD LATIN SMALL LETTER A WITH CIRCUMFLEX AND DOT BELOW */ +#define XK_Abreveacute 0x1001eae /* U+1EAE LATIN CAPITAL LETTER A WITH BREVE AND ACUTE */ +#define XK_abreveacute 0x1001eaf /* U+1EAF LATIN SMALL LETTER A WITH BREVE AND ACUTE */ +#define XK_Abrevegrave 0x1001eb0 /* U+1EB0 LATIN CAPITAL LETTER A WITH BREVE AND GRAVE */ +#define XK_abrevegrave 0x1001eb1 /* U+1EB1 LATIN SMALL LETTER A WITH BREVE AND GRAVE */ +#define XK_Abrevehook 0x1001eb2 /* U+1EB2 LATIN CAPITAL LETTER A WITH BREVE AND HOOK ABOVE */ +#define XK_abrevehook 0x1001eb3 /* U+1EB3 LATIN SMALL LETTER A WITH BREVE AND HOOK ABOVE */ +#define XK_Abrevetilde 0x1001eb4 /* U+1EB4 LATIN CAPITAL LETTER A WITH BREVE AND TILDE */ +#define XK_abrevetilde 0x1001eb5 /* U+1EB5 LATIN SMALL LETTER A WITH BREVE AND TILDE */ +#define XK_Abrevebelowdot 0x1001eb6 /* U+1EB6 LATIN CAPITAL LETTER A WITH BREVE AND DOT BELOW */ +#define XK_abrevebelowdot 0x1001eb7 /* U+1EB7 LATIN SMALL LETTER A WITH BREVE AND DOT BELOW */ +#define XK_Ebelowdot 0x1001eb8 /* U+1EB8 LATIN CAPITAL LETTER E WITH DOT BELOW */ +#define XK_ebelowdot 0x1001eb9 /* U+1EB9 LATIN SMALL LETTER E WITH DOT BELOW */ +#define XK_Ehook 0x1001eba /* U+1EBA LATIN CAPITAL LETTER E WITH HOOK ABOVE */ +#define XK_ehook 0x1001ebb /* U+1EBB LATIN SMALL LETTER E WITH HOOK ABOVE */ +#define XK_Etilde 0x1001ebc /* U+1EBC LATIN CAPITAL LETTER E WITH TILDE */ +#define XK_etilde 0x1001ebd /* U+1EBD LATIN SMALL LETTER E WITH TILDE */ +#define XK_Ecircumflexacute 0x1001ebe /* U+1EBE LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND ACUTE */ +#define XK_ecircumflexacute 0x1001ebf /* U+1EBF LATIN SMALL LETTER E WITH CIRCUMFLEX AND ACUTE */ +#define XK_Ecircumflexgrave 0x1001ec0 /* U+1EC0 LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND GRAVE */ +#define XK_ecircumflexgrave 0x1001ec1 /* U+1EC1 LATIN SMALL LETTER E WITH CIRCUMFLEX AND GRAVE */ +#define XK_Ecircumflexhook 0x1001ec2 /* U+1EC2 LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND HOOK ABOVE */ +#define XK_ecircumflexhook 0x1001ec3 /* U+1EC3 LATIN SMALL LETTER E WITH CIRCUMFLEX AND HOOK ABOVE */ +#define XK_Ecircumflextilde 0x1001ec4 /* U+1EC4 LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND TILDE */ +#define XK_ecircumflextilde 0x1001ec5 /* U+1EC5 LATIN SMALL LETTER E WITH CIRCUMFLEX AND TILDE */ +#define XK_Ecircumflexbelowdot 0x1001ec6 /* U+1EC6 LATIN CAPITAL LETTER E WITH CIRCUMFLEX AND DOT BELOW */ +#define XK_ecircumflexbelowdot 0x1001ec7 /* U+1EC7 LATIN SMALL LETTER E WITH CIRCUMFLEX AND DOT BELOW */ +#define XK_Ihook 0x1001ec8 /* U+1EC8 LATIN CAPITAL LETTER I WITH HOOK ABOVE */ +#define XK_ihook 0x1001ec9 /* U+1EC9 LATIN SMALL LETTER I WITH HOOK ABOVE */ +#define XK_Ibelowdot 0x1001eca /* U+1ECA LATIN CAPITAL LETTER I WITH DOT BELOW */ +#define XK_ibelowdot 0x1001ecb /* U+1ECB LATIN SMALL LETTER I WITH DOT BELOW */ +#define XK_Obelowdot 0x1001ecc /* U+1ECC LATIN CAPITAL LETTER O WITH DOT BELOW */ +#define XK_obelowdot 0x1001ecd /* U+1ECD LATIN SMALL LETTER O WITH DOT BELOW */ +#define XK_Ohook 0x1001ece /* U+1ECE LATIN CAPITAL LETTER O WITH HOOK ABOVE */ +#define XK_ohook 0x1001ecf /* U+1ECF LATIN SMALL LETTER O WITH HOOK ABOVE */ +#define XK_Ocircumflexacute 0x1001ed0 /* U+1ED0 LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND ACUTE */ +#define XK_ocircumflexacute 0x1001ed1 /* U+1ED1 LATIN SMALL LETTER O WITH CIRCUMFLEX AND ACUTE */ +#define XK_Ocircumflexgrave 0x1001ed2 /* U+1ED2 LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND GRAVE */ +#define XK_ocircumflexgrave 0x1001ed3 /* U+1ED3 LATIN SMALL LETTER O WITH CIRCUMFLEX AND GRAVE */ +#define XK_Ocircumflexhook 0x1001ed4 /* U+1ED4 LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND HOOK ABOVE */ +#define XK_ocircumflexhook 0x1001ed5 /* U+1ED5 LATIN SMALL LETTER O WITH CIRCUMFLEX AND HOOK ABOVE */ +#define XK_Ocircumflextilde 0x1001ed6 /* U+1ED6 LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND TILDE */ +#define XK_ocircumflextilde 0x1001ed7 /* U+1ED7 LATIN SMALL LETTER O WITH CIRCUMFLEX AND TILDE */ +#define XK_Ocircumflexbelowdot 0x1001ed8 /* U+1ED8 LATIN CAPITAL LETTER O WITH CIRCUMFLEX AND DOT BELOW */ +#define XK_ocircumflexbelowdot 0x1001ed9 /* U+1ED9 LATIN SMALL LETTER O WITH CIRCUMFLEX AND DOT BELOW */ +#define XK_Ohornacute 0x1001eda /* U+1EDA LATIN CAPITAL LETTER O WITH HORN AND ACUTE */ +#define XK_ohornacute 0x1001edb /* U+1EDB LATIN SMALL LETTER O WITH HORN AND ACUTE */ +#define XK_Ohorngrave 0x1001edc /* U+1EDC LATIN CAPITAL LETTER O WITH HORN AND GRAVE */ +#define XK_ohorngrave 0x1001edd /* U+1EDD LATIN SMALL LETTER O WITH HORN AND GRAVE */ +#define XK_Ohornhook 0x1001ede /* U+1EDE LATIN CAPITAL LETTER O WITH HORN AND HOOK ABOVE */ +#define XK_ohornhook 0x1001edf /* U+1EDF LATIN SMALL LETTER O WITH HORN AND HOOK ABOVE */ +#define XK_Ohorntilde 0x1001ee0 /* U+1EE0 LATIN CAPITAL LETTER O WITH HORN AND TILDE */ +#define XK_ohorntilde 0x1001ee1 /* U+1EE1 LATIN SMALL LETTER O WITH HORN AND TILDE */ +#define XK_Ohornbelowdot 0x1001ee2 /* U+1EE2 LATIN CAPITAL LETTER O WITH HORN AND DOT BELOW */ +#define XK_ohornbelowdot 0x1001ee3 /* U+1EE3 LATIN SMALL LETTER O WITH HORN AND DOT BELOW */ +#define XK_Ubelowdot 0x1001ee4 /* U+1EE4 LATIN CAPITAL LETTER U WITH DOT BELOW */ +#define XK_ubelowdot 0x1001ee5 /* U+1EE5 LATIN SMALL LETTER U WITH DOT BELOW */ +#define XK_Uhook 0x1001ee6 /* U+1EE6 LATIN CAPITAL LETTER U WITH HOOK ABOVE */ +#define XK_uhook 0x1001ee7 /* U+1EE7 LATIN SMALL LETTER U WITH HOOK ABOVE */ +#define XK_Uhornacute 0x1001ee8 /* U+1EE8 LATIN CAPITAL LETTER U WITH HORN AND ACUTE */ +#define XK_uhornacute 0x1001ee9 /* U+1EE9 LATIN SMALL LETTER U WITH HORN AND ACUTE */ +#define XK_Uhorngrave 0x1001eea /* U+1EEA LATIN CAPITAL LETTER U WITH HORN AND GRAVE */ +#define XK_uhorngrave 0x1001eeb /* U+1EEB LATIN SMALL LETTER U WITH HORN AND GRAVE */ +#define XK_Uhornhook 0x1001eec /* U+1EEC LATIN CAPITAL LETTER U WITH HORN AND HOOK ABOVE */ +#define XK_uhornhook 0x1001eed /* U+1EED LATIN SMALL LETTER U WITH HORN AND HOOK ABOVE */ +#define XK_Uhorntilde 0x1001eee /* U+1EEE LATIN CAPITAL LETTER U WITH HORN AND TILDE */ +#define XK_uhorntilde 0x1001eef /* U+1EEF LATIN SMALL LETTER U WITH HORN AND TILDE */ +#define XK_Uhornbelowdot 0x1001ef0 /* U+1EF0 LATIN CAPITAL LETTER U WITH HORN AND DOT BELOW */ +#define XK_uhornbelowdot 0x1001ef1 /* U+1EF1 LATIN SMALL LETTER U WITH HORN AND DOT BELOW */ +#define XK_Ybelowdot 0x1001ef4 /* U+1EF4 LATIN CAPITAL LETTER Y WITH DOT BELOW */ +#define XK_ybelowdot 0x1001ef5 /* U+1EF5 LATIN SMALL LETTER Y WITH DOT BELOW */ +#define XK_Yhook 0x1001ef6 /* U+1EF6 LATIN CAPITAL LETTER Y WITH HOOK ABOVE */ +#define XK_yhook 0x1001ef7 /* U+1EF7 LATIN SMALL LETTER Y WITH HOOK ABOVE */ +#define XK_Ytilde 0x1001ef8 /* U+1EF8 LATIN CAPITAL LETTER Y WITH TILDE */ +#define XK_ytilde 0x1001ef9 /* U+1EF9 LATIN SMALL LETTER Y WITH TILDE */ +#define XK_Ohorn 0x10001a0 /* U+01A0 LATIN CAPITAL LETTER O WITH HORN */ +#define XK_ohorn 0x10001a1 /* U+01A1 LATIN SMALL LETTER O WITH HORN */ +#define XK_Uhorn 0x10001af /* U+01AF LATIN CAPITAL LETTER U WITH HORN */ +#define XK_uhorn 0x10001b0 /* U+01B0 LATIN SMALL LETTER U WITH HORN */ + +#endif /* XK_VIETNAMESE */ + +#ifdef XK_CURRENCY +#define XK_EcuSign 0x10020a0 /* U+20A0 EURO-CURRENCY SIGN */ +#define XK_ColonSign 0x10020a1 /* U+20A1 COLON SIGN */ +#define XK_CruzeiroSign 0x10020a2 /* U+20A2 CRUZEIRO SIGN */ +#define XK_FFrancSign 0x10020a3 /* U+20A3 FRENCH FRANC SIGN */ +#define XK_LiraSign 0x10020a4 /* U+20A4 LIRA SIGN */ +#define XK_MillSign 0x10020a5 /* U+20A5 MILL SIGN */ +#define XK_NairaSign 0x10020a6 /* U+20A6 NAIRA SIGN */ +#define XK_PesetaSign 0x10020a7 /* U+20A7 PESETA SIGN */ +#define XK_RupeeSign 0x10020a8 /* U+20A8 RUPEE SIGN */ +#define XK_WonSign 0x10020a9 /* U+20A9 WON SIGN */ +#define XK_NewSheqelSign 0x10020aa /* U+20AA NEW SHEQEL SIGN */ +#define XK_DongSign 0x10020ab /* U+20AB DONG SIGN */ +#define XK_EuroSign 0x20ac /* U+20AC EURO SIGN */ +#endif /* XK_CURRENCY */ + +#ifdef XK_MATHEMATICAL +/* one, two and three are defined above. */ +#define XK_zerosuperior 0x1002070 /* U+2070 SUPERSCRIPT ZERO */ +#define XK_foursuperior 0x1002074 /* U+2074 SUPERSCRIPT FOUR */ +#define XK_fivesuperior 0x1002075 /* U+2075 SUPERSCRIPT FIVE */ +#define XK_sixsuperior 0x1002076 /* U+2076 SUPERSCRIPT SIX */ +#define XK_sevensuperior 0x1002077 /* U+2077 SUPERSCRIPT SEVEN */ +#define XK_eightsuperior 0x1002078 /* U+2078 SUPERSCRIPT EIGHT */ +#define XK_ninesuperior 0x1002079 /* U+2079 SUPERSCRIPT NINE */ +#define XK_zerosubscript 0x1002080 /* U+2080 SUBSCRIPT ZERO */ +#define XK_onesubscript 0x1002081 /* U+2081 SUBSCRIPT ONE */ +#define XK_twosubscript 0x1002082 /* U+2082 SUBSCRIPT TWO */ +#define XK_threesubscript 0x1002083 /* U+2083 SUBSCRIPT THREE */ +#define XK_foursubscript 0x1002084 /* U+2084 SUBSCRIPT FOUR */ +#define XK_fivesubscript 0x1002085 /* U+2085 SUBSCRIPT FIVE */ +#define XK_sixsubscript 0x1002086 /* U+2086 SUBSCRIPT SIX */ +#define XK_sevensubscript 0x1002087 /* U+2087 SUBSCRIPT SEVEN */ +#define XK_eightsubscript 0x1002088 /* U+2088 SUBSCRIPT EIGHT */ +#define XK_ninesubscript 0x1002089 /* U+2089 SUBSCRIPT NINE */ +#define XK_partdifferential 0x1002202 /* U+2202 PARTIAL DIFFERENTIAL */ +#define XK_emptyset 0x1002205 /* U+2205 NULL SET */ +#define XK_elementof 0x1002208 /* U+2208 ELEMENT OF */ +#define XK_notelementof 0x1002209 /* U+2209 NOT AN ELEMENT OF */ +#define XK_containsas 0x100220B /* U+220B CONTAINS AS MEMBER */ +#define XK_squareroot 0x100221A /* U+221A SQUARE ROOT */ +#define XK_cuberoot 0x100221B /* U+221B CUBE ROOT */ +#define XK_fourthroot 0x100221C /* U+221C FOURTH ROOT */ +#define XK_dintegral 0x100222C /* U+222C DOUBLE INTEGRAL */ +#define XK_tintegral 0x100222D /* U+222D TRIPLE INTEGRAL */ +#define XK_because 0x1002235 /* U+2235 BECAUSE */ +#define XK_approxeq 0x1002248 /* U+2245 ALMOST EQUAL TO */ +#define XK_notapproxeq 0x1002247 /* U+2247 NOT ALMOST EQUAL TO */ +#define XK_notidentical 0x1002262 /* U+2262 NOT IDENTICAL TO */ +#define XK_stricteq 0x1002263 /* U+2263 STRICTLY EQUIVALENT TO */ +#endif /* XK_MATHEMATICAL */ + +#ifdef XK_BRAILLE +#define XK_braille_dot_1 0xfff1 +#define XK_braille_dot_2 0xfff2 +#define XK_braille_dot_3 0xfff3 +#define XK_braille_dot_4 0xfff4 +#define XK_braille_dot_5 0xfff5 +#define XK_braille_dot_6 0xfff6 +#define XK_braille_dot_7 0xfff7 +#define XK_braille_dot_8 0xfff8 +#define XK_braille_dot_9 0xfff9 +#define XK_braille_dot_10 0xfffa +#define XK_braille_blank 0x1002800 /* U+2800 BRAILLE PATTERN BLANK */ +#define XK_braille_dots_1 0x1002801 /* U+2801 BRAILLE PATTERN DOTS-1 */ +#define XK_braille_dots_2 0x1002802 /* U+2802 BRAILLE PATTERN DOTS-2 */ +#define XK_braille_dots_12 0x1002803 /* U+2803 BRAILLE PATTERN DOTS-12 */ +#define XK_braille_dots_3 0x1002804 /* U+2804 BRAILLE PATTERN DOTS-3 */ +#define XK_braille_dots_13 0x1002805 /* U+2805 BRAILLE PATTERN DOTS-13 */ +#define XK_braille_dots_23 0x1002806 /* U+2806 BRAILLE PATTERN DOTS-23 */ +#define XK_braille_dots_123 0x1002807 /* U+2807 BRAILLE PATTERN DOTS-123 */ +#define XK_braille_dots_4 0x1002808 /* U+2808 BRAILLE PATTERN DOTS-4 */ +#define XK_braille_dots_14 0x1002809 /* U+2809 BRAILLE PATTERN DOTS-14 */ +#define XK_braille_dots_24 0x100280a /* U+280a BRAILLE PATTERN DOTS-24 */ +#define XK_braille_dots_124 0x100280b /* U+280b BRAILLE PATTERN DOTS-124 */ +#define XK_braille_dots_34 0x100280c /* U+280c BRAILLE PATTERN DOTS-34 */ +#define XK_braille_dots_134 0x100280d /* U+280d BRAILLE PATTERN DOTS-134 */ +#define XK_braille_dots_234 0x100280e /* U+280e BRAILLE PATTERN DOTS-234 */ +#define XK_braille_dots_1234 0x100280f /* U+280f BRAILLE PATTERN DOTS-1234 */ +#define XK_braille_dots_5 0x1002810 /* U+2810 BRAILLE PATTERN DOTS-5 */ +#define XK_braille_dots_15 0x1002811 /* U+2811 BRAILLE PATTERN DOTS-15 */ +#define XK_braille_dots_25 0x1002812 /* U+2812 BRAILLE PATTERN DOTS-25 */ +#define XK_braille_dots_125 0x1002813 /* U+2813 BRAILLE PATTERN DOTS-125 */ +#define XK_braille_dots_35 0x1002814 /* U+2814 BRAILLE PATTERN DOTS-35 */ +#define XK_braille_dots_135 0x1002815 /* U+2815 BRAILLE PATTERN DOTS-135 */ +#define XK_braille_dots_235 0x1002816 /* U+2816 BRAILLE PATTERN DOTS-235 */ +#define XK_braille_dots_1235 0x1002817 /* U+2817 BRAILLE PATTERN DOTS-1235 */ +#define XK_braille_dots_45 0x1002818 /* U+2818 BRAILLE PATTERN DOTS-45 */ +#define XK_braille_dots_145 0x1002819 /* U+2819 BRAILLE PATTERN DOTS-145 */ +#define XK_braille_dots_245 0x100281a /* U+281a BRAILLE PATTERN DOTS-245 */ +#define XK_braille_dots_1245 0x100281b /* U+281b BRAILLE PATTERN DOTS-1245 */ +#define XK_braille_dots_345 0x100281c /* U+281c BRAILLE PATTERN DOTS-345 */ +#define XK_braille_dots_1345 0x100281d /* U+281d BRAILLE PATTERN DOTS-1345 */ +#define XK_braille_dots_2345 0x100281e /* U+281e BRAILLE PATTERN DOTS-2345 */ +#define XK_braille_dots_12345 0x100281f /* U+281f BRAILLE PATTERN DOTS-12345 */ +#define XK_braille_dots_6 0x1002820 /* U+2820 BRAILLE PATTERN DOTS-6 */ +#define XK_braille_dots_16 0x1002821 /* U+2821 BRAILLE PATTERN DOTS-16 */ +#define XK_braille_dots_26 0x1002822 /* U+2822 BRAILLE PATTERN DOTS-26 */ +#define XK_braille_dots_126 0x1002823 /* U+2823 BRAILLE PATTERN DOTS-126 */ +#define XK_braille_dots_36 0x1002824 /* U+2824 BRAILLE PATTERN DOTS-36 */ +#define XK_braille_dots_136 0x1002825 /* U+2825 BRAILLE PATTERN DOTS-136 */ +#define XK_braille_dots_236 0x1002826 /* U+2826 BRAILLE PATTERN DOTS-236 */ +#define XK_braille_dots_1236 0x1002827 /* U+2827 BRAILLE PATTERN DOTS-1236 */ +#define XK_braille_dots_46 0x1002828 /* U+2828 BRAILLE PATTERN DOTS-46 */ +#define XK_braille_dots_146 0x1002829 /* U+2829 BRAILLE PATTERN DOTS-146 */ +#define XK_braille_dots_246 0x100282a /* U+282a BRAILLE PATTERN DOTS-246 */ +#define XK_braille_dots_1246 0x100282b /* U+282b BRAILLE PATTERN DOTS-1246 */ +#define XK_braille_dots_346 0x100282c /* U+282c BRAILLE PATTERN DOTS-346 */ +#define XK_braille_dots_1346 0x100282d /* U+282d BRAILLE PATTERN DOTS-1346 */ +#define XK_braille_dots_2346 0x100282e /* U+282e BRAILLE PATTERN DOTS-2346 */ +#define XK_braille_dots_12346 0x100282f /* U+282f BRAILLE PATTERN DOTS-12346 */ +#define XK_braille_dots_56 0x1002830 /* U+2830 BRAILLE PATTERN DOTS-56 */ +#define XK_braille_dots_156 0x1002831 /* U+2831 BRAILLE PATTERN DOTS-156 */ +#define XK_braille_dots_256 0x1002832 /* U+2832 BRAILLE PATTERN DOTS-256 */ +#define XK_braille_dots_1256 0x1002833 /* U+2833 BRAILLE PATTERN DOTS-1256 */ +#define XK_braille_dots_356 0x1002834 /* U+2834 BRAILLE PATTERN DOTS-356 */ +#define XK_braille_dots_1356 0x1002835 /* U+2835 BRAILLE PATTERN DOTS-1356 */ +#define XK_braille_dots_2356 0x1002836 /* U+2836 BRAILLE PATTERN DOTS-2356 */ +#define XK_braille_dots_12356 0x1002837 /* U+2837 BRAILLE PATTERN DOTS-12356 */ +#define XK_braille_dots_456 0x1002838 /* U+2838 BRAILLE PATTERN DOTS-456 */ +#define XK_braille_dots_1456 0x1002839 /* U+2839 BRAILLE PATTERN DOTS-1456 */ +#define XK_braille_dots_2456 0x100283a /* U+283a BRAILLE PATTERN DOTS-2456 */ +#define XK_braille_dots_12456 0x100283b /* U+283b BRAILLE PATTERN DOTS-12456 */ +#define XK_braille_dots_3456 0x100283c /* U+283c BRAILLE PATTERN DOTS-3456 */ +#define XK_braille_dots_13456 0x100283d /* U+283d BRAILLE PATTERN DOTS-13456 */ +#define XK_braille_dots_23456 0x100283e /* U+283e BRAILLE PATTERN DOTS-23456 */ +#define XK_braille_dots_123456 0x100283f /* U+283f BRAILLE PATTERN DOTS-123456 */ +#define XK_braille_dots_7 0x1002840 /* U+2840 BRAILLE PATTERN DOTS-7 */ +#define XK_braille_dots_17 0x1002841 /* U+2841 BRAILLE PATTERN DOTS-17 */ +#define XK_braille_dots_27 0x1002842 /* U+2842 BRAILLE PATTERN DOTS-27 */ +#define XK_braille_dots_127 0x1002843 /* U+2843 BRAILLE PATTERN DOTS-127 */ +#define XK_braille_dots_37 0x1002844 /* U+2844 BRAILLE PATTERN DOTS-37 */ +#define XK_braille_dots_137 0x1002845 /* U+2845 BRAILLE PATTERN DOTS-137 */ +#define XK_braille_dots_237 0x1002846 /* U+2846 BRAILLE PATTERN DOTS-237 */ +#define XK_braille_dots_1237 0x1002847 /* U+2847 BRAILLE PATTERN DOTS-1237 */ +#define XK_braille_dots_47 0x1002848 /* U+2848 BRAILLE PATTERN DOTS-47 */ +#define XK_braille_dots_147 0x1002849 /* U+2849 BRAILLE PATTERN DOTS-147 */ +#define XK_braille_dots_247 0x100284a /* U+284a BRAILLE PATTERN DOTS-247 */ +#define XK_braille_dots_1247 0x100284b /* U+284b BRAILLE PATTERN DOTS-1247 */ +#define XK_braille_dots_347 0x100284c /* U+284c BRAILLE PATTERN DOTS-347 */ +#define XK_braille_dots_1347 0x100284d /* U+284d BRAILLE PATTERN DOTS-1347 */ +#define XK_braille_dots_2347 0x100284e /* U+284e BRAILLE PATTERN DOTS-2347 */ +#define XK_braille_dots_12347 0x100284f /* U+284f BRAILLE PATTERN DOTS-12347 */ +#define XK_braille_dots_57 0x1002850 /* U+2850 BRAILLE PATTERN DOTS-57 */ +#define XK_braille_dots_157 0x1002851 /* U+2851 BRAILLE PATTERN DOTS-157 */ +#define XK_braille_dots_257 0x1002852 /* U+2852 BRAILLE PATTERN DOTS-257 */ +#define XK_braille_dots_1257 0x1002853 /* U+2853 BRAILLE PATTERN DOTS-1257 */ +#define XK_braille_dots_357 0x1002854 /* U+2854 BRAILLE PATTERN DOTS-357 */ +#define XK_braille_dots_1357 0x1002855 /* U+2855 BRAILLE PATTERN DOTS-1357 */ +#define XK_braille_dots_2357 0x1002856 /* U+2856 BRAILLE PATTERN DOTS-2357 */ +#define XK_braille_dots_12357 0x1002857 /* U+2857 BRAILLE PATTERN DOTS-12357 */ +#define XK_braille_dots_457 0x1002858 /* U+2858 BRAILLE PATTERN DOTS-457 */ +#define XK_braille_dots_1457 0x1002859 /* U+2859 BRAILLE PATTERN DOTS-1457 */ +#define XK_braille_dots_2457 0x100285a /* U+285a BRAILLE PATTERN DOTS-2457 */ +#define XK_braille_dots_12457 0x100285b /* U+285b BRAILLE PATTERN DOTS-12457 */ +#define XK_braille_dots_3457 0x100285c /* U+285c BRAILLE PATTERN DOTS-3457 */ +#define XK_braille_dots_13457 0x100285d /* U+285d BRAILLE PATTERN DOTS-13457 */ +#define XK_braille_dots_23457 0x100285e /* U+285e BRAILLE PATTERN DOTS-23457 */ +#define XK_braille_dots_123457 0x100285f /* U+285f BRAILLE PATTERN DOTS-123457 */ +#define XK_braille_dots_67 0x1002860 /* U+2860 BRAILLE PATTERN DOTS-67 */ +#define XK_braille_dots_167 0x1002861 /* U+2861 BRAILLE PATTERN DOTS-167 */ +#define XK_braille_dots_267 0x1002862 /* U+2862 BRAILLE PATTERN DOTS-267 */ +#define XK_braille_dots_1267 0x1002863 /* U+2863 BRAILLE PATTERN DOTS-1267 */ +#define XK_braille_dots_367 0x1002864 /* U+2864 BRAILLE PATTERN DOTS-367 */ +#define XK_braille_dots_1367 0x1002865 /* U+2865 BRAILLE PATTERN DOTS-1367 */ +#define XK_braille_dots_2367 0x1002866 /* U+2866 BRAILLE PATTERN DOTS-2367 */ +#define XK_braille_dots_12367 0x1002867 /* U+2867 BRAILLE PATTERN DOTS-12367 */ +#define XK_braille_dots_467 0x1002868 /* U+2868 BRAILLE PATTERN DOTS-467 */ +#define XK_braille_dots_1467 0x1002869 /* U+2869 BRAILLE PATTERN DOTS-1467 */ +#define XK_braille_dots_2467 0x100286a /* U+286a BRAILLE PATTERN DOTS-2467 */ +#define XK_braille_dots_12467 0x100286b /* U+286b BRAILLE PATTERN DOTS-12467 */ +#define XK_braille_dots_3467 0x100286c /* U+286c BRAILLE PATTERN DOTS-3467 */ +#define XK_braille_dots_13467 0x100286d /* U+286d BRAILLE PATTERN DOTS-13467 */ +#define XK_braille_dots_23467 0x100286e /* U+286e BRAILLE PATTERN DOTS-23467 */ +#define XK_braille_dots_123467 0x100286f /* U+286f BRAILLE PATTERN DOTS-123467 */ +#define XK_braille_dots_567 0x1002870 /* U+2870 BRAILLE PATTERN DOTS-567 */ +#define XK_braille_dots_1567 0x1002871 /* U+2871 BRAILLE PATTERN DOTS-1567 */ +#define XK_braille_dots_2567 0x1002872 /* U+2872 BRAILLE PATTERN DOTS-2567 */ +#define XK_braille_dots_12567 0x1002873 /* U+2873 BRAILLE PATTERN DOTS-12567 */ +#define XK_braille_dots_3567 0x1002874 /* U+2874 BRAILLE PATTERN DOTS-3567 */ +#define XK_braille_dots_13567 0x1002875 /* U+2875 BRAILLE PATTERN DOTS-13567 */ +#define XK_braille_dots_23567 0x1002876 /* U+2876 BRAILLE PATTERN DOTS-23567 */ +#define XK_braille_dots_123567 0x1002877 /* U+2877 BRAILLE PATTERN DOTS-123567 */ +#define XK_braille_dots_4567 0x1002878 /* U+2878 BRAILLE PATTERN DOTS-4567 */ +#define XK_braille_dots_14567 0x1002879 /* U+2879 BRAILLE PATTERN DOTS-14567 */ +#define XK_braille_dots_24567 0x100287a /* U+287a BRAILLE PATTERN DOTS-24567 */ +#define XK_braille_dots_124567 0x100287b /* U+287b BRAILLE PATTERN DOTS-124567 */ +#define XK_braille_dots_34567 0x100287c /* U+287c BRAILLE PATTERN DOTS-34567 */ +#define XK_braille_dots_134567 0x100287d /* U+287d BRAILLE PATTERN DOTS-134567 */ +#define XK_braille_dots_234567 0x100287e /* U+287e BRAILLE PATTERN DOTS-234567 */ +#define XK_braille_dots_1234567 0x100287f /* U+287f BRAILLE PATTERN DOTS-1234567 */ +#define XK_braille_dots_8 0x1002880 /* U+2880 BRAILLE PATTERN DOTS-8 */ +#define XK_braille_dots_18 0x1002881 /* U+2881 BRAILLE PATTERN DOTS-18 */ +#define XK_braille_dots_28 0x1002882 /* U+2882 BRAILLE PATTERN DOTS-28 */ +#define XK_braille_dots_128 0x1002883 /* U+2883 BRAILLE PATTERN DOTS-128 */ +#define XK_braille_dots_38 0x1002884 /* U+2884 BRAILLE PATTERN DOTS-38 */ +#define XK_braille_dots_138 0x1002885 /* U+2885 BRAILLE PATTERN DOTS-138 */ +#define XK_braille_dots_238 0x1002886 /* U+2886 BRAILLE PATTERN DOTS-238 */ +#define XK_braille_dots_1238 0x1002887 /* U+2887 BRAILLE PATTERN DOTS-1238 */ +#define XK_braille_dots_48 0x1002888 /* U+2888 BRAILLE PATTERN DOTS-48 */ +#define XK_braille_dots_148 0x1002889 /* U+2889 BRAILLE PATTERN DOTS-148 */ +#define XK_braille_dots_248 0x100288a /* U+288a BRAILLE PATTERN DOTS-248 */ +#define XK_braille_dots_1248 0x100288b /* U+288b BRAILLE PATTERN DOTS-1248 */ +#define XK_braille_dots_348 0x100288c /* U+288c BRAILLE PATTERN DOTS-348 */ +#define XK_braille_dots_1348 0x100288d /* U+288d BRAILLE PATTERN DOTS-1348 */ +#define XK_braille_dots_2348 0x100288e /* U+288e BRAILLE PATTERN DOTS-2348 */ +#define XK_braille_dots_12348 0x100288f /* U+288f BRAILLE PATTERN DOTS-12348 */ +#define XK_braille_dots_58 0x1002890 /* U+2890 BRAILLE PATTERN DOTS-58 */ +#define XK_braille_dots_158 0x1002891 /* U+2891 BRAILLE PATTERN DOTS-158 */ +#define XK_braille_dots_258 0x1002892 /* U+2892 BRAILLE PATTERN DOTS-258 */ +#define XK_braille_dots_1258 0x1002893 /* U+2893 BRAILLE PATTERN DOTS-1258 */ +#define XK_braille_dots_358 0x1002894 /* U+2894 BRAILLE PATTERN DOTS-358 */ +#define XK_braille_dots_1358 0x1002895 /* U+2895 BRAILLE PATTERN DOTS-1358 */ +#define XK_braille_dots_2358 0x1002896 /* U+2896 BRAILLE PATTERN DOTS-2358 */ +#define XK_braille_dots_12358 0x1002897 /* U+2897 BRAILLE PATTERN DOTS-12358 */ +#define XK_braille_dots_458 0x1002898 /* U+2898 BRAILLE PATTERN DOTS-458 */ +#define XK_braille_dots_1458 0x1002899 /* U+2899 BRAILLE PATTERN DOTS-1458 */ +#define XK_braille_dots_2458 0x100289a /* U+289a BRAILLE PATTERN DOTS-2458 */ +#define XK_braille_dots_12458 0x100289b /* U+289b BRAILLE PATTERN DOTS-12458 */ +#define XK_braille_dots_3458 0x100289c /* U+289c BRAILLE PATTERN DOTS-3458 */ +#define XK_braille_dots_13458 0x100289d /* U+289d BRAILLE PATTERN DOTS-13458 */ +#define XK_braille_dots_23458 0x100289e /* U+289e BRAILLE PATTERN DOTS-23458 */ +#define XK_braille_dots_123458 0x100289f /* U+289f BRAILLE PATTERN DOTS-123458 */ +#define XK_braille_dots_68 0x10028a0 /* U+28a0 BRAILLE PATTERN DOTS-68 */ +#define XK_braille_dots_168 0x10028a1 /* U+28a1 BRAILLE PATTERN DOTS-168 */ +#define XK_braille_dots_268 0x10028a2 /* U+28a2 BRAILLE PATTERN DOTS-268 */ +#define XK_braille_dots_1268 0x10028a3 /* U+28a3 BRAILLE PATTERN DOTS-1268 */ +#define XK_braille_dots_368 0x10028a4 /* U+28a4 BRAILLE PATTERN DOTS-368 */ +#define XK_braille_dots_1368 0x10028a5 /* U+28a5 BRAILLE PATTERN DOTS-1368 */ +#define XK_braille_dots_2368 0x10028a6 /* U+28a6 BRAILLE PATTERN DOTS-2368 */ +#define XK_braille_dots_12368 0x10028a7 /* U+28a7 BRAILLE PATTERN DOTS-12368 */ +#define XK_braille_dots_468 0x10028a8 /* U+28a8 BRAILLE PATTERN DOTS-468 */ +#define XK_braille_dots_1468 0x10028a9 /* U+28a9 BRAILLE PATTERN DOTS-1468 */ +#define XK_braille_dots_2468 0x10028aa /* U+28aa BRAILLE PATTERN DOTS-2468 */ +#define XK_braille_dots_12468 0x10028ab /* U+28ab BRAILLE PATTERN DOTS-12468 */ +#define XK_braille_dots_3468 0x10028ac /* U+28ac BRAILLE PATTERN DOTS-3468 */ +#define XK_braille_dots_13468 0x10028ad /* U+28ad BRAILLE PATTERN DOTS-13468 */ +#define XK_braille_dots_23468 0x10028ae /* U+28ae BRAILLE PATTERN DOTS-23468 */ +#define XK_braille_dots_123468 0x10028af /* U+28af BRAILLE PATTERN DOTS-123468 */ +#define XK_braille_dots_568 0x10028b0 /* U+28b0 BRAILLE PATTERN DOTS-568 */ +#define XK_braille_dots_1568 0x10028b1 /* U+28b1 BRAILLE PATTERN DOTS-1568 */ +#define XK_braille_dots_2568 0x10028b2 /* U+28b2 BRAILLE PATTERN DOTS-2568 */ +#define XK_braille_dots_12568 0x10028b3 /* U+28b3 BRAILLE PATTERN DOTS-12568 */ +#define XK_braille_dots_3568 0x10028b4 /* U+28b4 BRAILLE PATTERN DOTS-3568 */ +#define XK_braille_dots_13568 0x10028b5 /* U+28b5 BRAILLE PATTERN DOTS-13568 */ +#define XK_braille_dots_23568 0x10028b6 /* U+28b6 BRAILLE PATTERN DOTS-23568 */ +#define XK_braille_dots_123568 0x10028b7 /* U+28b7 BRAILLE PATTERN DOTS-123568 */ +#define XK_braille_dots_4568 0x10028b8 /* U+28b8 BRAILLE PATTERN DOTS-4568 */ +#define XK_braille_dots_14568 0x10028b9 /* U+28b9 BRAILLE PATTERN DOTS-14568 */ +#define XK_braille_dots_24568 0x10028ba /* U+28ba BRAILLE PATTERN DOTS-24568 */ +#define XK_braille_dots_124568 0x10028bb /* U+28bb BRAILLE PATTERN DOTS-124568 */ +#define XK_braille_dots_34568 0x10028bc /* U+28bc BRAILLE PATTERN DOTS-34568 */ +#define XK_braille_dots_134568 0x10028bd /* U+28bd BRAILLE PATTERN DOTS-134568 */ +#define XK_braille_dots_234568 0x10028be /* U+28be BRAILLE PATTERN DOTS-234568 */ +#define XK_braille_dots_1234568 0x10028bf /* U+28bf BRAILLE PATTERN DOTS-1234568 */ +#define XK_braille_dots_78 0x10028c0 /* U+28c0 BRAILLE PATTERN DOTS-78 */ +#define XK_braille_dots_178 0x10028c1 /* U+28c1 BRAILLE PATTERN DOTS-178 */ +#define XK_braille_dots_278 0x10028c2 /* U+28c2 BRAILLE PATTERN DOTS-278 */ +#define XK_braille_dots_1278 0x10028c3 /* U+28c3 BRAILLE PATTERN DOTS-1278 */ +#define XK_braille_dots_378 0x10028c4 /* U+28c4 BRAILLE PATTERN DOTS-378 */ +#define XK_braille_dots_1378 0x10028c5 /* U+28c5 BRAILLE PATTERN DOTS-1378 */ +#define XK_braille_dots_2378 0x10028c6 /* U+28c6 BRAILLE PATTERN DOTS-2378 */ +#define XK_braille_dots_12378 0x10028c7 /* U+28c7 BRAILLE PATTERN DOTS-12378 */ +#define XK_braille_dots_478 0x10028c8 /* U+28c8 BRAILLE PATTERN DOTS-478 */ +#define XK_braille_dots_1478 0x10028c9 /* U+28c9 BRAILLE PATTERN DOTS-1478 */ +#define XK_braille_dots_2478 0x10028ca /* U+28ca BRAILLE PATTERN DOTS-2478 */ +#define XK_braille_dots_12478 0x10028cb /* U+28cb BRAILLE PATTERN DOTS-12478 */ +#define XK_braille_dots_3478 0x10028cc /* U+28cc BRAILLE PATTERN DOTS-3478 */ +#define XK_braille_dots_13478 0x10028cd /* U+28cd BRAILLE PATTERN DOTS-13478 */ +#define XK_braille_dots_23478 0x10028ce /* U+28ce BRAILLE PATTERN DOTS-23478 */ +#define XK_braille_dots_123478 0x10028cf /* U+28cf BRAILLE PATTERN DOTS-123478 */ +#define XK_braille_dots_578 0x10028d0 /* U+28d0 BRAILLE PATTERN DOTS-578 */ +#define XK_braille_dots_1578 0x10028d1 /* U+28d1 BRAILLE PATTERN DOTS-1578 */ +#define XK_braille_dots_2578 0x10028d2 /* U+28d2 BRAILLE PATTERN DOTS-2578 */ +#define XK_braille_dots_12578 0x10028d3 /* U+28d3 BRAILLE PATTERN DOTS-12578 */ +#define XK_braille_dots_3578 0x10028d4 /* U+28d4 BRAILLE PATTERN DOTS-3578 */ +#define XK_braille_dots_13578 0x10028d5 /* U+28d5 BRAILLE PATTERN DOTS-13578 */ +#define XK_braille_dots_23578 0x10028d6 /* U+28d6 BRAILLE PATTERN DOTS-23578 */ +#define XK_braille_dots_123578 0x10028d7 /* U+28d7 BRAILLE PATTERN DOTS-123578 */ +#define XK_braille_dots_4578 0x10028d8 /* U+28d8 BRAILLE PATTERN DOTS-4578 */ +#define XK_braille_dots_14578 0x10028d9 /* U+28d9 BRAILLE PATTERN DOTS-14578 */ +#define XK_braille_dots_24578 0x10028da /* U+28da BRAILLE PATTERN DOTS-24578 */ +#define XK_braille_dots_124578 0x10028db /* U+28db BRAILLE PATTERN DOTS-124578 */ +#define XK_braille_dots_34578 0x10028dc /* U+28dc BRAILLE PATTERN DOTS-34578 */ +#define XK_braille_dots_134578 0x10028dd /* U+28dd BRAILLE PATTERN DOTS-134578 */ +#define XK_braille_dots_234578 0x10028de /* U+28de BRAILLE PATTERN DOTS-234578 */ +#define XK_braille_dots_1234578 0x10028df /* U+28df BRAILLE PATTERN DOTS-1234578 */ +#define XK_braille_dots_678 0x10028e0 /* U+28e0 BRAILLE PATTERN DOTS-678 */ +#define XK_braille_dots_1678 0x10028e1 /* U+28e1 BRAILLE PATTERN DOTS-1678 */ +#define XK_braille_dots_2678 0x10028e2 /* U+28e2 BRAILLE PATTERN DOTS-2678 */ +#define XK_braille_dots_12678 0x10028e3 /* U+28e3 BRAILLE PATTERN DOTS-12678 */ +#define XK_braille_dots_3678 0x10028e4 /* U+28e4 BRAILLE PATTERN DOTS-3678 */ +#define XK_braille_dots_13678 0x10028e5 /* U+28e5 BRAILLE PATTERN DOTS-13678 */ +#define XK_braille_dots_23678 0x10028e6 /* U+28e6 BRAILLE PATTERN DOTS-23678 */ +#define XK_braille_dots_123678 0x10028e7 /* U+28e7 BRAILLE PATTERN DOTS-123678 */ +#define XK_braille_dots_4678 0x10028e8 /* U+28e8 BRAILLE PATTERN DOTS-4678 */ +#define XK_braille_dots_14678 0x10028e9 /* U+28e9 BRAILLE PATTERN DOTS-14678 */ +#define XK_braille_dots_24678 0x10028ea /* U+28ea BRAILLE PATTERN DOTS-24678 */ +#define XK_braille_dots_124678 0x10028eb /* U+28eb BRAILLE PATTERN DOTS-124678 */ +#define XK_braille_dots_34678 0x10028ec /* U+28ec BRAILLE PATTERN DOTS-34678 */ +#define XK_braille_dots_134678 0x10028ed /* U+28ed BRAILLE PATTERN DOTS-134678 */ +#define XK_braille_dots_234678 0x10028ee /* U+28ee BRAILLE PATTERN DOTS-234678 */ +#define XK_braille_dots_1234678 0x10028ef /* U+28ef BRAILLE PATTERN DOTS-1234678 */ +#define XK_braille_dots_5678 0x10028f0 /* U+28f0 BRAILLE PATTERN DOTS-5678 */ +#define XK_braille_dots_15678 0x10028f1 /* U+28f1 BRAILLE PATTERN DOTS-15678 */ +#define XK_braille_dots_25678 0x10028f2 /* U+28f2 BRAILLE PATTERN DOTS-25678 */ +#define XK_braille_dots_125678 0x10028f3 /* U+28f3 BRAILLE PATTERN DOTS-125678 */ +#define XK_braille_dots_35678 0x10028f4 /* U+28f4 BRAILLE PATTERN DOTS-35678 */ +#define XK_braille_dots_135678 0x10028f5 /* U+28f5 BRAILLE PATTERN DOTS-135678 */ +#define XK_braille_dots_235678 0x10028f6 /* U+28f6 BRAILLE PATTERN DOTS-235678 */ +#define XK_braille_dots_1235678 0x10028f7 /* U+28f7 BRAILLE PATTERN DOTS-1235678 */ +#define XK_braille_dots_45678 0x10028f8 /* U+28f8 BRAILLE PATTERN DOTS-45678 */ +#define XK_braille_dots_145678 0x10028f9 /* U+28f9 BRAILLE PATTERN DOTS-145678 */ +#define XK_braille_dots_245678 0x10028fa /* U+28fa BRAILLE PATTERN DOTS-245678 */ +#define XK_braille_dots_1245678 0x10028fb /* U+28fb BRAILLE PATTERN DOTS-1245678 */ +#define XK_braille_dots_345678 0x10028fc /* U+28fc BRAILLE PATTERN DOTS-345678 */ +#define XK_braille_dots_1345678 0x10028fd /* U+28fd BRAILLE PATTERN DOTS-1345678 */ +#define XK_braille_dots_2345678 0x10028fe /* U+28fe BRAILLE PATTERN DOTS-2345678 */ +#define XK_braille_dots_12345678 0x10028ff /* U+28ff BRAILLE PATTERN DOTS-12345678 */ +#endif /* XK_BRAILLE */ diff --git a/src/SConscript b/src/SConscript index cad0736c5..0ee144747 100755 --- a/src/SConscript +++ b/src/SConscript @@ -446,7 +446,7 @@ def makeInfoPyFile(target, source, env): # Generate a file that wraps the basic top level files env.Command('python/m5/info.py', - [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ], + [ '#/AUTHORS', '#/LICENSE', '#/README', ], MakeAction(makeInfoPyFile, Transform("INFO"))) PySource('m5', 'python/m5/info.py') diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 6b2113639..e6dd728dd 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -208,19 +208,20 @@ TableWalker::processWalk() return f; } + Request::Flags flag = 0; + if (currState->sctlr.c == 0) { + flag = Request::UNCACHEABLE; + } + if (currState->timing) { port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), &doL1DescEvent, (uint8_t*)&currState->l1Desc.data, - currState->tc->getCpuPtr()->ticks(1)); + currState->tc->getCpuPtr()->ticks(1), flag); DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n", stateQueueL1.size()); stateQueueL1.push_back(currState); currState = NULL; } else { - Request::Flags flag = 0; - if (currState->sctlr.c == 0){ - flag = Request::UNCACHEABLE; - } port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t), NULL, (uint8_t*)&currState->l1Desc.data, currState->tc->getCpuPtr()->ticks(1), flag); @@ -472,7 +473,7 @@ TableWalker::doL1Descriptor() switch (currState->l1Desc.type()) { case L1Descriptor::Ignore: case L1Descriptor::Reserved: - if (!currState->delayed) { + if (!currState->timing) { currState->tc = NULL; currState->req = NULL; } @@ -577,7 +578,7 @@ TableWalker::doL2Descriptor() if (currState->l2Desc.invalid()) { DPRINTF(TLB, "L2 descriptor invalid, causing fault\n"); - if (!currState->delayed) { + if (!currState->timing) { currState->tc = NULL; currState->req = NULL; } @@ -622,7 +623,7 @@ TableWalker::doL2Descriptor() memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(), currState->l2Desc.shareable()); - if (!currState->delayed) { + if (!currState->timing) { currState->tc = NULL; currState->req = NULL; } diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 267a7ad26..96a39cc61 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -93,14 +93,14 @@ class TableWalker : public MemObject { if (supersection()) panic("Super sections not implemented\n"); - return mbits(data, 31,20); + return mbits(data, 31, 20); } /** Return the physcal address of the entry, bits in position*/ Addr paddr(Addr va) const { if (supersection()) panic("Super sections not implemented\n"); - return mbits(data, 31,20) | mbits(va, 20, 0); + return mbits(data, 31, 20) | mbits(va, 19, 0); } @@ -109,7 +109,7 @@ class TableWalker : public MemObject { if (supersection()) panic("Super sections not implemented\n"); - return bits(data, 31,20); + return bits(data, 31, 20); } /** Is the translation global (no asid used)? */ @@ -127,19 +127,19 @@ class TableWalker : public MemObject /** Three bit access protection flags */ uint8_t ap() const { - return (bits(data, 15) << 2) | bits(data,11,10); + return (bits(data, 15) << 2) | bits(data, 11, 10); } /** Domain Client/Manager: ARM DDI 0406B: B3-31 */ uint8_t domain() const { - return bits(data,8,5); + return bits(data, 8, 5); } /** Address of L2 descriptor if it exists */ Addr l2Addr() const { - return mbits(data, 31,10); + return mbits(data, 31, 10); } /** Memory region attributes: ARM DDI 0406B: B3-32. @@ -149,7 +149,7 @@ class TableWalker : public MemObject */ uint8_t texcb() const { - return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2; + return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2; } /** If the section is shareable. See texcb() comment. */ @@ -187,7 +187,7 @@ class TableWalker : public MemObject /** Is the entry invalid */ bool invalid() const { - return bits(data, 1,0) == 0;; + return bits(data, 1, 0) == 0; } /** What is the size of the mapping? */ @@ -218,8 +218,8 @@ class TableWalker : public MemObject uint8_t texcb() const { return large() ? - (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) : - (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2)); + (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) : + (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2)); } /** Return the physical frame, bits shifted right */ diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index e5f5b36f6..230c56200 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -696,6 +696,8 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, #endif if (!delay) translation->finish(fault, req, tc, mode); + else + translation->markDelayed(); return fault; } diff --git a/src/arch/generic/debugfaults.hh b/src/arch/generic/debugfaults.hh new file mode 100644 index 000000000..acffadc34 --- /dev/null +++ b/src/arch/generic/debugfaults.hh @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2010 Advanced Micro Devices + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_GENERIC_DEBUGFAULTS_HH__ +#define __ARCH_GENERIC_DEBUGFAULTS_HH__ + +#include "base/misc.hh" +#include "sim/faults.hh" + +#include <string> + +namespace GenericISA +{ +class M5DebugFault : public FaultBase +{ + public: + enum DebugFunc + { + PanicFunc, + FatalFunc, + WarnFunc, + WarnOnceFunc + }; + + protected: + std::string message; + DebugFunc func; + + public: + M5DebugFault(DebugFunc _func, std::string _message) : + message(_message), func(_func) + {} + + FaultName + name() const + { + switch (func) { + case PanicFunc: + return "panic fault"; + case FatalFunc: + return "fatal fault"; + case WarnFunc: + return "warn fault"; + case WarnOnceFunc: + return "warn_once fault"; + default: + panic("unrecognized debug function number\n"); + } + } + + void + invoke(ThreadContext *tc, + StaticInstPtr inst = StaticInst::nullStaticInstPtr) + { + switch (func) { + case PanicFunc: + panic(message); + break; + case FatalFunc: + fatal(message); + break; + case WarnFunc: + warn(message); + break; + case WarnOnceFunc: + warn_once(message); + break; + default: + panic("unrecognized debug function number\n"); + } + } +}; +} // namespace GenericISA + +#endif // __ARCH_GENERIC_DEBUGFAULTS_HH__ diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 173fa89df..d97a141de 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -367,21 +367,7 @@ decode OPCODE_HI default Unknown::unknown() { }}); 0x1: addiu({{ Rt.sw = Rs.sw + imm; }}); 0x2: slti({{ Rt.sw = (Rs.sw < imm) ? 1 : 0 }}); - - //Edited to include MIPS AVP Pass/Fail instructions and - //default to the sltiu instruction - 0x3: decode RS_RT_INTIMM { - 0xabc1: BasicOp::fail({{ - exitSimLoop("AVP/SRVP Test Failed"); - }}); - 0xabc2: BasicOp::pass({{ - exitSimLoop("AVP/SRVP Test Passed"); - }}); - default: sltiu({{ - Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0; - }}); - } - + 0x3: sltiu({{ Rt.uw = (Rs.uw < (uint32_t)sextImm) ? 1 : 0;}}); 0x4: andi({{ Rt.sw = Rs.sw & zextImm; }}); 0x5: ori({{ Rt.sw = Rs.sw | zextImm; }}); 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm; }}); diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 27de9da11..9cb774647 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -46,6 +46,7 @@ if env['TARGET_ISA'] == 'x86': Source('cpuid.cc') Source('emulenv.cc') Source('faults.cc') + Source('insts/badmicroop.cc') Source('insts/microfpop.cc') Source('insts/microldstop.cc') Source('insts/micromediaop.cc') diff --git a/src/arch/x86/insts/badmicroop.cc b/src/arch/x86/insts/badmicroop.cc new file mode 100644 index 000000000..ef493f250 --- /dev/null +++ b/src/arch/x86/insts/badmicroop.cc @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2011 Advanced Micro Devices + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/insts/badmicroop.hh" +#include "arch/x86/isa_traits.hh" +#include "arch/x86/decoder.hh" + +namespace X86ISA +{ + +// This microop needs to be allocated on the heap even though it could +// theoretically be statically allocated. The reference counted pointer would +// try to delete the static memory when it was destructed. +const StaticInstPtr badMicroop = + new X86ISAInst::MicroPanic(NoopMachInst, "BAD", + StaticInst::IsMicroop | StaticInst::IsLastMicroop, + "Invalid microop!", 0); + +} // namespace X86ISA diff --git a/src/arch/x86/insts/badmicroop.hh b/src/arch/x86/insts/badmicroop.hh new file mode 100644 index 000000000..57fe242c4 --- /dev/null +++ b/src/arch/x86/insts/badmicroop.hh @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2011 Advanced Micro Devices + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_INSTS_BADMICROOP_HH__ +#define __ARCH_X86_INSTS_BADMICROOP_HH__ + +class StaticInstPtr; + +namespace X86ISA +{ + +extern const StaticInstPtr badMicroop; + +} // namespace X86ISA + +#endif //__ARCH_X86_INSTS_BADMICROOP_HH__ diff --git a/src/arch/x86/insts/macroop.hh b/src/arch/x86/insts/macroop.hh index fcf051a37..4f4176b77 100644 --- a/src/arch/x86/insts/macroop.hh +++ b/src/arch/x86/insts/macroop.hh @@ -41,6 +41,7 @@ #define __ARCH_X86_INSTS_MACROOP_HH__ #include "arch/x86/emulenv.hh" +#include "arch/x86/insts/badmicroop.hh" #include "arch/x86/types.hh" #include "arch/x86/insts/static_inst.hh" @@ -76,8 +77,10 @@ class MacroopBase : public X86StaticInst StaticInstPtr fetchMicroop(MicroPC microPC) const { - assert(microPC < numMicroops); - return microops[microPC]; + if (microPC >= numMicroops) + return badMicroop; + else + return microops[microPC]; } std::string diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc index 6aee87449..dedea0f3d 100644 --- a/src/arch/x86/insts/microregop.cc +++ b/src/arch/x86/insts/microregop.cc @@ -50,9 +50,6 @@ namespace X86ISA bool subtract) const { DPRINTF(X86, "flagMask = %#x\n", flagMask); - if (_destRegIdx[0] & IntFoldBit) { - _dest >>= 8; - } uint64_t flags = oldFlags & ~flagMask; if(flagMask & (ECFBit | CFBit)) { diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 58b1fbc62..674e69e98 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -53,6 +53,7 @@ output header {{ #include <sstream> #include <iostream> +#include "arch/generic/debugfaults.hh" #include "arch/x86/emulenv.hh" #include "arch/x86/insts/macroop.hh" #include "arch/x86/insts/microfpop.hh" @@ -113,6 +114,7 @@ output exec {{ #include "arch/x86/regs/misc.hh" #include "arch/x86/tlb.hh" #include "base/bigint.hh" +#include "base/compiler.hh" #include "base/condcodes.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa index 4b2ecdd5a..220c1af97 100644 --- a/src/arch/x86/isa/microops/debug.isa +++ b/src/arch/x86/isa/microops/debug.isa @@ -45,16 +45,29 @@ output header {{ class MicroDebugBase : public X86ISA::X86MicroopBase { protected: + typedef GenericISA::M5DebugFault::DebugFunc DebugFunc; + DebugFunc func; std::string message; uint8_t cc; public: - MicroDebugBase(ExtMachInst _machInst, const char * mnem, + MicroDebugBase(ExtMachInst machInst, const char * mnem, const char * instMnem, uint64_t setFlags, - std::string _message, uint8_t _cc); + DebugFunc _func, std::string _message, uint8_t _cc) : + X86MicroopBase(machInst, mnem, instMnem, setFlags, No_OpClass), + func(_func), message(_message), cc(_cc) + {} - std::string generateDisassembly(Addr pc, - const SymbolTable *symtab) const; + std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + response << "\"" << message << "\""; + + return response.str(); + } }; }}; @@ -70,53 +83,31 @@ def template MicroDebugDeclare {{ }}; def template MicroDebugExecute {{ - Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Fault + %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { %(op_decl)s %(op_rd)s if (%(cond_test)s) { - %(func)s("%s\n", message); + return new GenericISA::M5DebugFault(func, message); + } else { + return NoFault; } - return NoFault; } }}; -output decoder {{ - inline MicroDebugBase::MicroDebugBase( - ExtMachInst machInst, const char * mnem, const char * instMnem, - uint64_t setFlags, std::string _message, uint8_t _cc) : - X86MicroopBase(machInst, mnem, instMnem, - setFlags, No_OpClass), - message(_message), cc(_cc) - { - } -}}; - def template MicroDebugConstructor {{ - inline %(class_name)s::%(class_name)s( + %(class_name)s::%(class_name)s( ExtMachInst machInst, const char * instMnem, uint64_t setFlags, std::string _message, uint8_t _cc) : %(base_class)s(machInst, "%(func)s", instMnem, - setFlags, _message, _cc) + setFlags, %(func_num)s, _message, _cc) { %(constructor)s; } }}; -output decoder {{ - std::string MicroDebugBase::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream response; - - printMnemonic(response, instMnem, mnemonic); - response << "\"" << message << "\""; - - return response.str(); - } -}}; - let {{ class MicroDebug(X86Microop): def __init__(self, message, flags=None): @@ -142,13 +133,14 @@ let {{ header_output = "" decoder_output = "" - def buildDebugMicro(func): + def buildDebugMicro(func, func_num): global exec_output, header_output, decoder_output iop = InstObjParams(func, "Micro%sFlags" % func.capitalize(), "MicroDebugBase", {"code": "", "func": func, + "func_num": "GenericISA::M5DebugFault::%s" % func_num, "cond_test": "checkCondition(ccFlagBits, cc)"}) exec_output += MicroDebugExecute.subst(iop) header_output += MicroDebugDeclare.subst(iop) @@ -158,6 +150,7 @@ let {{ "MicroDebugBase", {"code": "", "func": func, + "func_num": "GenericISA::M5DebugFault::%s" % func_num, "cond_test": "true"}) exec_output += MicroDebugExecute.subst(iop) header_output += MicroDebugDeclare.subst(iop) @@ -169,8 +162,8 @@ let {{ global microopClasses microopClasses[func] = MicroDebugChild - buildDebugMicro("panic") - buildDebugMicro("fatal") - buildDebugMicro("warn") - buildDebugMicro("warn_once") + buildDebugMicro("panic", "PanicFunc") + buildDebugMicro("fatal", "FatalFunc") + buildDebugMicro("warn", "WarnFunc") + buildDebugMicro("warn_once", "WarnOnceFunc") }}; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 216a74c6c..cd649d644 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -301,6 +301,46 @@ let {{ "dataSize" : self.dataSize, "addressSize" : self.addressSize, "memFlags" : self.memFlags} return allocator + + class BigLdStOp(X86Microop): + def __init__(self, data, segment, addr, disp, + dataSize, addressSize, baseFlags, atCPL0, prefetch): + self.data = data + [self.scale, self.index, self.base] = addr + self.disp = disp + self.segment = segment + self.dataSize = dataSize + self.addressSize = addressSize + self.memFlags = baseFlags + if atCPL0: + self.memFlags += " | (CPL0FlagBit << FlagShift)" + if prefetch: + self.memFlags += " | Request::PREFETCH" + self.memFlags += " | (machInst.legacy.addr ? " + \ + "(AddrSizeFlagBit << FlagShift) : 0)" + + def getAllocator(self, microFlags): + allocString = ''' + (%(dataSize)s >= 4) ? + (StaticInstPtr)(new %(class_name)sBig(machInst, + macrocodeBlock, %(flags)s, %(scale)s, %(index)s, + %(base)s, %(disp)s, %(segment)s, %(data)s, + %(dataSize)s, %(addressSize)s, %(memFlags)s)) : + (StaticInstPtr)(new %(class_name)s(machInst, + macrocodeBlock, %(flags)s, %(scale)s, %(index)s, + %(base)s, %(disp)s, %(segment)s, %(data)s, + %(dataSize)s, %(addressSize)s, %(memFlags)s)) + ''' + allocator = allocString % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "scale" : self.scale, "index" : self.index, + "base" : self.base, + "disp" : self.disp, + "segment" : self.segment, "data" : self.data, + "dataSize" : self.dataSize, "addressSize" : self.addressSize, + "memFlags" : self.memFlags} + return allocator }}; let {{ @@ -315,7 +355,8 @@ let {{ EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0); ''' - def defineMicroLoadOp(mnemonic, code, mem_flags="0"): + def defineMicroLoadOp(mnemonic, code, bigCode='', + mem_flags="0", big=True): global header_output global decoder_output global exec_output @@ -324,16 +365,22 @@ let {{ name = mnemonic.lower() # Build up the all register version of this micro op - iop = InstObjParams(name, Name, 'X86ISA::LdStOp', - {"code": code, - "ea_code": calculateEA}) - header_output += MicroLdStOpDeclare.subst(iop) - decoder_output += MicroLdStOpConstructor.subst(iop) - exec_output += MicroLoadExecute.subst(iop) - exec_output += MicroLoadInitiateAcc.subst(iop) - exec_output += MicroLoadCompleteAcc.subst(iop) - - class LoadOp(LdStOp): + iops = [InstObjParams(name, Name, 'X86ISA::LdStOp', + {"code": code, "ea_code": calculateEA})] + if big: + iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp', + {"code": bigCode, "ea_code": calculateEA})] + for iop in iops: + header_output += MicroLdStOpDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroLoadExecute.subst(iop) + exec_output += MicroLoadInitiateAcc.subst(iop) + exec_output += MicroLoadCompleteAcc.subst(iop) + + base = LdStOp + if big: + base = BigLdStOp + class LoadOp(base): def __init__(self, data, segment, addr, disp = 0, dataSize="env.dataSize", addressSize="env.addressSize", @@ -346,12 +393,15 @@ let {{ microopClasses[name] = LoadOp - defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') + defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);', + 'Data = Mem & mask(dataSize * 8);') defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', - '(StoreCheck << FlagShift)') + 'Data = Mem & mask(dataSize * 8);', + '(StoreCheck << FlagShift)') defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', - '(StoreCheck << FlagShift) | Request::LOCKED') - defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;') + 'Data = Mem & mask(dataSize * 8);', + '(StoreCheck << FlagShift) | Request::LOCKED') + defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;', big = False) def defineMicroStoreOp(mnemonic, code, \ postCode="", completeCode="", mem_flags="0"): diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index 2871d5a89..ac78b090d 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -114,8 +114,16 @@ let {{ self.dataSize = dataSize def getAllocator(self, microFlags): - allocator = '''new %(class_name)s(machInst, macrocodeBlock, - %(flags)s, %(dest)s, %(imm)s, %(dataSize)s)''' % { + allocString = ''' + (%(dataSize)s >= 4) ? + (StaticInstPtr)(new %(class_name)sBig(machInst, + macrocodeBlock, %(flags)s, %(dest)s, %(imm)s, + %(dataSize)s)) : + (StaticInstPtr)(new %(class_name)s(machInst, + macrocodeBlock, %(flags)s, %(dest)s, %(imm)s, + %(dataSize)s)) + ''' + allocator = allocString % { "class_name" : self.className, "mnemonic" : self.mnemonic, "flags" : self.microFlagsText(microFlags), @@ -152,12 +160,15 @@ let {{ let {{ # Build up the all register version of this micro op - iop = InstObjParams("limm", "Limm", 'X86MicroopBase', - {"code" : "DestReg = merge(DestReg, imm, dataSize);"}) - header_output += MicroLimmOpDeclare.subst(iop) - decoder_output += MicroLimmOpConstructor.subst(iop) - decoder_output += MicroLimmOpDisassembly.subst(iop) - exec_output += MicroLimmOpExecute.subst(iop) + iops = [InstObjParams("limm", "Limm", 'X86MicroopBase', + {"code" : "DestReg = merge(DestReg, imm, dataSize);"}), + InstObjParams("limm", "LimmBig", 'X86MicroopBase', + {"code" : "DestReg = imm & mask(dataSize * 8);"})] + for iop in iops: + header_output += MicroLimmOpDeclare.subst(iop) + decoder_output += MicroLimmOpConstructor.subst(iop) + decoder_output += MicroLimmOpDisassembly.subst(iop) + exec_output += MicroLimmOpExecute.subst(iop) iop = InstObjParams("lfpimm", "Lfpimm", 'X86MicroopBase', {"code" : "FpDestReg.uqw = imm"}) diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index ccfcb3a69..e2a51c127 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -51,6 +51,8 @@ def template MicroRegOpExecute {{ %(op_decl)s; %(op_rd)s; + IntReg result M5_VAR_USED; + if(%(cond_check)s) { %(code)s; @@ -79,6 +81,8 @@ def template MicroRegOpImmExecute {{ %(op_decl)s; %(op_rd)s; + IntReg result M5_VAR_USED; + if(%(cond_check)s) { %(code)s; @@ -224,8 +228,8 @@ let {{ MicroRegOpExecute) class RegOpMeta(type): - def buildCppClasses(self, name, Name, suffix, \ - code, flag_code, cond_check, else_code, cond_control_flag_init): + def buildCppClasses(self, name, Name, suffix, code, big_code, \ + flag_code, cond_check, else_code, cond_control_flag_init): # Globals to stick the output in global header_output @@ -235,11 +239,13 @@ let {{ # Stick all the code together so it can be searched at once allCode = "|".join((code, flag_code, cond_check, else_code, cond_control_flag_init)) + allBigCode = "|".join((big_code, flag_code, cond_check, else_code, + cond_control_flag_init)) # If op2 is used anywhere, make register and immediate versions # of this code. matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") - match = matcher.search(allCode) + match = matcher.search(allCode + allBigCode) if match: typeQual = "" if match.group("typeQual"): @@ -247,6 +253,7 @@ let {{ src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) self.buildCppClasses(name, Name, suffix, matcher.sub(src2_name, code), + matcher.sub(src2_name, big_code), matcher.sub(src2_name, flag_code), matcher.sub(src2_name, cond_check), matcher.sub(src2_name, else_code), @@ -254,6 +261,7 @@ let {{ imm_name = "%simm8" % match.group("prefix") self.buildCppClasses(name + "i", Name, suffix + "Imm", matcher.sub(imm_name, code), + matcher.sub(imm_name, big_code), matcher.sub(imm_name, flag_code), matcher.sub(imm_name, cond_check), matcher.sub(imm_name, else_code), @@ -264,27 +272,32 @@ let {{ # a version without it and fix up this version to use it. if flag_code != "" or cond_check != "true": self.buildCppClasses(name, Name, suffix, - code, "", "true", else_code, "") + code, big_code, "", "true", else_code, "") suffix = "Flags" + suffix # If psrc1 or psrc2 is used, we need to actually insert code to # compute it. - matcher = re.compile("(?<!\w)psrc1(?!\w)") - if matcher.search(allCode): - code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code - matcher = re.compile("(?<!\w)psrc2(?!\w)") - if matcher.search(allCode): - code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code - # Also make available versions which do sign extension - matcher = re.compile("(?<!\w)spsrc1(?!\w)") - if matcher.search(allCode): - code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code - matcher = re.compile("(?<!\w)spsrc2(?!\w)") - if matcher.search(allCode): - code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code - matcher = re.compile("(?<!\w)simm8(?!\w)") - if matcher.search(allCode): - code = "int8_t simm8 = imm8;" + code + for (big, all) in ((False, allCode), (True, allBigCode)): + prefix = "" + for (rex, decl) in ( + ("(?<!\w)psrc1(?!\w)", + "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"), + ("(?<!\w)psrc2(?!\w)", + "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"), + ("(?<!\w)spsrc1(?!\w)", + "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"), + ("(?<!\w)spsrc2(?!\w)", + "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"), + ("(?<!\w)simm8(?!\w)", + "int8_t simm8 = imm8;")): + matcher = re.compile(rex) + if matcher.search(all): + prefix += decl + "\n" + if big: + if big_code != "": + big_code = prefix + big_code + else: + code = prefix + code base = "X86ISA::RegOp" @@ -297,17 +310,26 @@ let {{ templates = immTemplates # Get everything ready for the substitution - iop = InstObjParams(name, Name + suffix, base, + iops = [InstObjParams(name, Name + suffix, base, {"code" : code, "flag_code" : flag_code, "cond_check" : cond_check, "else_code" : else_code, - "cond_control_flag_init": cond_control_flag_init}) + "cond_control_flag_init" : cond_control_flag_init})] + if big_code != "": + iops += [InstObjParams(name, Name + suffix + "Big", base, + {"code" : big_code, + "flag_code" : flag_code, + "cond_check" : cond_check, + "else_code" : else_code, + "cond_control_flag_init" : + cond_control_flag_init})] # Generate the actual code (finally!) - header_output += templates[0].subst(iop) - decoder_output += templates[1].subst(iop) - exec_output += templates[2].subst(iop) + for iop in iops: + header_output += templates[0].subst(iop) + decoder_output += templates[1].subst(iop) + exec_output += templates[2].subst(iop) def __new__(mcls, Name, bases, dict): @@ -322,14 +344,16 @@ let {{ cls.className = Name cls.base_mnemonic = name code = cls.code + big_code = cls.big_code flag_code = cls.flag_code cond_check = cls.cond_check else_code = cls.else_code cond_control_flag_init = cls.cond_control_flag_init # Set up the C++ classes - mcls.buildCppClasses(cls, name, Name, "", code, flag_code, - cond_check, else_code, cond_control_flag_init) + mcls.buildCppClasses(cls, name, Name, "", code, big_code, + flag_code, cond_check, else_code, + cond_control_flag_init) # Hook into the microassembler dict global microopClasses @@ -352,6 +376,7 @@ let {{ abstract = True # Default template parameter values + big_code = "" flag_code = "" cond_check = "true" else_code = ";" @@ -372,26 +397,48 @@ let {{ self.className += "Flags" def getAllocator(self, microFlags): - className = self.className - if self.mnemonic == self.base_mnemonic + 'i': - className += "Imm" - allocator = '''new %(class_name)s(machInst, macrocodeBlock, - %(flags)s, %(src1)s, %(op2)s, %(dest)s, - %(dataSize)s, %(ext)s)''' % { - "class_name" : className, - "flags" : self.microFlagsText(microFlags), - "src1" : self.src1, "op2" : self.op2, - "dest" : self.dest, - "dataSize" : self.dataSize, - "ext" : self.ext} - return allocator + if self.big_code != "": + className = self.className + if self.mnemonic == self.base_mnemonic + 'i': + className += "Imm" + allocString = ''' + (%(dataSize)s >= 4) ? + (StaticInstPtr)(new %(class_name)sBig(machInst, + macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, + %(dest)s, %(dataSize)s, %(ext)s)) : + (StaticInstPtr)(new %(class_name)s(machInst, + macrocodeBlock, %(flags)s, %(src1)s, %(op2)s, + %(dest)s, %(dataSize)s, %(ext)s)) + ''' + allocator = allocString % { + "class_name" : className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "op2" : self.op2, + "dest" : self.dest, + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator + else: + className = self.className + if self.mnemonic == self.base_mnemonic + 'i': + className += "Imm" + allocator = '''new %(class_name)s(machInst, macrocodeBlock, + %(flags)s, %(src1)s, %(op2)s, %(dest)s, + %(dataSize)s, %(ext)s)''' % { + "class_name" : className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "op2" : self.op2, + "dest" : self.dest, + "dataSize" : self.dataSize, + "ext" : self.ext} + return allocator class LogicRegOp(RegOp): abstract = True flag_code = ''' //Don't have genFlags handle the OF or CF bits uint64_t mask = CFBit | ECFBit | OFBit; - ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2); //If a logic microop wants to set these, it wants to set them to 0. ccFlagBits &= ~(CFBit & ext); ccFlagBits &= ~(ECFBit & ext); @@ -401,12 +448,12 @@ let {{ class FlagRegOp(RegOp): abstract = True flag_code = \ - "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" + "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);" class SubRegOp(RegOp): abstract = True flag_code = \ - "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" + "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);" class CondRegOp(RegOp): abstract = True @@ -428,31 +475,44 @@ let {{ src1, src2, flags, dataSize) class Add(FlagRegOp): - code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' + code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' + big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' class Or(LogicRegOp): - code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' + code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' + big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' class Adc(FlagRegOp): code = ''' CCFlagBits flags = ccFlagBits; - DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); + DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); + ''' + big_code = ''' + CCFlagBits flags = ccFlagBits; + DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); ''' class Sbb(SubRegOp): code = ''' CCFlagBits flags = ccFlagBits; - DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); + DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); + ''' + big_code = ''' + CCFlagBits flags = ccFlagBits; + DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); ''' class And(LogicRegOp): - code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' + code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' + big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' class Sub(SubRegOp): - code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' + code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' + big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' class Xor(LogicRegOp): - code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' + code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' + big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)' class Mul1s(WrRegOp): code = ''' @@ -505,6 +565,7 @@ let {{ class Mulel(RdRegOp): code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' + big_code = 'DestReg = ProdLow & mask(dataSize * 8);' class Muleh(RdRegOp): def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): @@ -513,6 +574,7 @@ let {{ super(RdRegOp, self).__init__(dest, src1, \ "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' + big_code = 'DestReg = ProdHi & mask(dataSize * 8);' # One or two bit divide class Div1(WrRegOp): @@ -540,7 +602,7 @@ let {{ # Step divide class Div2(RegOp): - code = ''' + divCode = ''' uint64_t dividend = Remainder; uint64_t divisor = Divisor; uint64_t quotient = Quotient; @@ -587,11 +649,13 @@ let {{ } } //Keep track of how many bits there are still to pull in. - DestReg = merge(DestReg, remaining, dataSize); + %s //Record the final results Remainder = remainder; Quotient = quotient; ''' + code = divCode % "DestReg = merge(DestReg, remaining, dataSize);" + big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" flag_code = ''' if (remaining == 0) ccFlagBits = ccFlagBits | (ext & EZFBit); @@ -601,9 +665,11 @@ let {{ class Divq(RdRegOp): code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' + big_code = 'DestReg = Quotient & mask(dataSize * 8);' class Divr(RdRegOp): code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' + big_code = 'DestReg = Remainder & mask(dataSize * 8);' class Mov(CondRegOp): code = 'DestReg = merge(SrcReg1, op2, dataSize)' @@ -616,6 +682,10 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); ''' + big_code = ''' + uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); + DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8); + ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -641,14 +711,19 @@ let {{ ''' class Srl(RegOp): + # Because what happens to the bits shift -in- on a right shift + # is not defined in the C/C++ standard, we have to mask them out + # to be sure they're zero. code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); - // Because what happens to the bits shift -in- on a right shift - // is not defined in the C/C++ standard, we have to mask them out - // to be sure they're zero. uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); ''' + big_code = ''' + uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); + uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); + DestReg = (psrc1 >> shiftAmt) & logicalMask; + ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -671,15 +746,21 @@ let {{ ''' class Sra(RegOp): + # Because what happens to the bits shift -in- on a right shift + # is not defined in the C/C++ standard, we have to sign extend + # them manually to be sure. code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); - // Because what happens to the bits shift -in- on a right shift - // is not defined in the C/C++ standard, we have to sign extend - // them manually to be sure. uint64_t arithMask = (shiftAmt == 0) ? 0 : -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); ''' + big_code = ''' + uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); + uint64_t arithMask = (shiftAmt == 0) ? 0 : + -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); + DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8); + ''' flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -704,13 +785,11 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8); - if(realShiftAmt) - { + if (realShiftAmt) { uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); DestReg = merge(DestReg, top | bottom, dataSize); - } - else + } else DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' @@ -739,16 +818,14 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); - if(realShiftAmt) - { + if (realShiftAmt) { CCFlagBits flags = ccFlagBits; uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); if (realShiftAmt > 1) top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); DestReg = merge(DestReg, top | bottom, dataSize); - } - else + } else DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' @@ -780,14 +857,12 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8); - if(realShiftAmt) - { + if (realShiftAmt) { uint64_t top = psrc1 << realShiftAmt; uint64_t bottom = bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); DestReg = merge(DestReg, top | bottom, dataSize); - } - else + } else DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' @@ -816,8 +891,7 @@ let {{ uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); - if(realShiftAmt) - { + if (realShiftAmt) { CCFlagBits flags = ccFlagBits; uint64_t top = psrc1 << realShiftAmt; uint64_t bottom = flags.cf << (realShiftAmt - 1); @@ -826,8 +900,7 @@ let {{ bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt + 1); DestReg = merge(DestReg, top | bottom, dataSize); - } - else + } else DestReg = merge(DestReg, DestReg, dataSize); ''' flag_code = ''' @@ -853,10 +926,10 @@ let {{ ''' class Sld(RegOp): - code = ''' + sldCode = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t dataBits = dataSize * 8; - uint8_t realShiftAmt = shiftAmt % (2 * dataBits); + uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); uint64_t result; if (realShiftAmt == 0) { result = psrc1; @@ -867,8 +940,10 @@ let {{ result = (DoubleBits << (realShiftAmt - dataBits)) | (psrc1 >> (2 * dataBits - realShiftAmt)); } - DestReg = merge(DestReg, result, dataSize); + %s ''' + code = sldCode % "DestReg = merge(DestReg, result, dataSize);" + big_code = sldCode % "DestReg = result & mask(dataSize * 8);" flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -899,10 +974,10 @@ let {{ ''' class Srd(RegOp): - code = ''' + srdCode = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t dataBits = dataSize * 8; - uint8_t realShiftAmt = shiftAmt % (2 * dataBits); + uint8_t realShiftAmt = shiftAmt %% (2 * dataBits); uint64_t result; if (realShiftAmt == 0) { result = psrc1; @@ -919,8 +994,10 @@ let {{ logicalMask) | (psrc1 << (2 * dataBits - realShiftAmt)); } - DestReg = merge(DestReg, result, dataSize); + %s ''' + code = srdCode % "DestReg = merge(DestReg, result, dataSize);" + big_code = srdCode % "DestReg = result & mask(dataSize * 8);" flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { @@ -986,6 +1063,12 @@ let {{ ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : (ccFlagBits & ~EZFBit); ''' + big_code = ''' + int flag = bits(ccFlagBits, imm8); + DestReg = flag & mask(dataSize * 8); + ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : + (ccFlagBits & ~EZFBit); + ''' def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): super(Ruflag, self).__init__(dest, \ @@ -1000,6 +1083,14 @@ let {{ ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : (ccFlagBits & ~EZFBit); ''' + big_code = ''' + MiscReg flagMask = 0x3F7FDD5; + MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; + int flag = bits(flags, imm8); + DestReg = flag & mask(dataSize * 8); + ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : + (ccFlagBits & ~EZFBit); + ''' def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): super(Rflag, self).__init__(dest, \ @@ -1015,6 +1106,15 @@ let {{ val = sign_bit ? (val | ~maskVal) : (val & maskVal); DestReg = merge(DestReg, val, dataSize); ''' + big_code = ''' + IntReg val = psrc1; + // Mask the bit position so that it wraps. + int bitPos = op2 & (dataSize * 8 - 1); + int sign_bit = bits(val, bitPos, bitPos); + uint64_t maskVal = mask(bitPos+1); + val = sign_bit ? (val | ~maskVal) : (val & maskVal); + DestReg = val & mask(dataSize * 8); + ''' flag_code = ''' if (!sign_bit) ccFlagBits = ccFlagBits & @@ -1026,12 +1126,13 @@ let {{ class Zext(RegOp): code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' + big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' class Rddr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Rddr, self).__init__(dest, \ src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) - code = ''' + rdrCode = ''' CR4 cr4 = CR4Op; DR7 dr7 = DR7Op; if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { @@ -1039,9 +1140,11 @@ let {{ } else if (dr7.gd) { fault = new DebugException(); } else { - DestReg = merge(DestReg, DebugSrc1, dataSize); + %s } ''' + code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" + big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" class Wrdr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): @@ -1066,13 +1169,15 @@ let {{ def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Rdcr, self).__init__(dest, \ src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) - code = ''' + rdcrCode = ''' if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { fault = new InvalidOpcode(); } else { - DestReg = merge(DestReg, ControlSrc1, dataSize); + %s } ''' + code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" + big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" class Wrcr(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): @@ -1154,24 +1259,20 @@ let {{ ''' class Rdbase(SegOp): - code = ''' - DestReg = merge(DestReg, SegBaseSrc1, dataSize); - ''' + code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);' + big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);' class Rdlimit(SegOp): - code = ''' - DestReg = merge(DestReg, SegLimitSrc1, dataSize); - ''' + code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);' + big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);' class RdAttr(SegOp): - code = ''' - DestReg = merge(DestReg, SegAttrSrc1, dataSize); - ''' + code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);' + big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);' class Rdsel(SegOp): - code = ''' - DestReg = merge(DestReg, SegSelSrc1, dataSize); - ''' + code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' + big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' class Rdval(RegOp): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): diff --git a/src/arch/x86/microcode_rom.hh b/src/arch/x86/microcode_rom.hh index f8ad410ce..84c503bb9 100644 --- a/src/arch/x86/microcode_rom.hh +++ b/src/arch/x86/microcode_rom.hh @@ -32,6 +32,7 @@ #define __ARCH_X86_MICROCODE_ROM_HH__ #include "arch/x86/emulenv.hh" +#include "arch/x86/insts/badmicroop.hh" #include "cpu/static_inst.hh" namespace X86ISAInst @@ -60,8 +61,10 @@ namespace X86ISAInst fetchMicroop(MicroPC microPC, StaticInstPtr curMacroop) { microPC = normalMicroPC(microPC); - assert(microPC < numMicroops); - return genFuncs[microPC](curMacroop); + if (microPC >= numMicroops) + return X86ISA::badMicroop; + else + return genFuncs[microPC](curMacroop); } }; } diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index c06ec18bc..5c67e28e1 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -225,7 +225,11 @@ namespace X86ISA { assert(emiIsReady); emiIsReady = false; - nextPC.npc(nextPC.pc() + getInstSize()); + if (!nextPC.size()) { + Addr size = getInstSize(); + nextPC.size(size); + nextPC.npc(nextPC.pc() + size); + } return emi; } }; diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 5a208446a..4641141d3 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -222,7 +222,61 @@ namespace X86ISA return true; } - typedef GenericISA::UPCState<MachInst> PCState; + class PCState : public GenericISA::UPCState<MachInst> + { + protected: + typedef GenericISA::UPCState<MachInst> Base; + + uint8_t _size; + + public: + void + set(Addr val) + { + Base::set(val); + _size = 0; + } + + PCState() {} + PCState(Addr val) { set(val); } + + uint8_t size() const { return _size; } + void size(uint8_t newSize) { _size = newSize; } + + bool + branching() const + { + return this->npc() != this->pc() + size(); + } + + void + advance() + { + Base::advance(); + _size = 0; + } + + void + uEnd() + { + Base::uEnd(); + _size = 0; + } + + void + serialize(std::ostream &os) + { + Base::serialize(os); + SERIALIZE_SCALAR(_size); + } + + void + unserialize(Checkpoint *cp, const std::string §ion) + { + Base::unserialize(cp, section); + UNSERIALIZE_SCALAR(_size); + } + }; struct CoreSpecific { int core_type; diff --git a/src/base/SConscript b/src/base/SConscript index 2bb6b13ab..3f069bf9e 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -35,6 +35,7 @@ if env['CP_ANNOTATE']: Source('cp_annotate.cc') Source('atomicio.cc') Source('bigint.cc') +Source('bitmap.cc') Source('callback.cc') Source('circlebuf.cc') Source('cprintf.cc') diff --git a/src/base/bitmap.cc b/src/base/bitmap.cc new file mode 100644 index 000000000..0d2a9302b --- /dev/null +++ b/src/base/bitmap.cc @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: William Wang + * Ali Saidi + */ + +#include <cassert> + +#include "base/bitmap.hh" +#include "base/misc.hh" + +// bitmap class ctor +Bitmap::Bitmap(VideoConvert::Mode _mode, uint16_t w, uint16_t h, uint8_t *d) + : mode(_mode), height(h), width(w), data(d), + vc(mode, VideoConvert::rgb8888, width, height) +{ +} + +void +Bitmap::write(std::ostream *bmp) +{ + assert(data); + + // For further information see: http://en.wikipedia.org/wiki/BMP_file_format + Magic magic = {{'B','M'}}; + Header header = {sizeof(VideoConvert::Rgb8888) * width * height , 0, 0, 54}; + Info info = {sizeof(Info), width, height, 1, + sizeof(VideoConvert::Rgb8888) * 8, 0, + sizeof(VideoConvert::Rgb8888) * width * height, 1, 1, 0, 0}; + + bmp->write(reinterpret_cast<char*>(&magic), sizeof(magic)); + bmp->write(reinterpret_cast<char*>(&header), sizeof(header)); + bmp->write(reinterpret_cast<char*>(&info), sizeof(info)); + + uint8_t *tmp = vc.convert(data); + uint32_t *tmp32 = (uint32_t*)tmp; + + // BMP start store data left to right starting with the bottom row + // so we need to do some creative flipping + for (int i = height - 1; i >= 0; i--) + for (int j = 0; j < width; j++) + bmp->write((char*)&tmp32[i * width + j], sizeof(uint32_t)); + + bmp->flush(); + + delete [] tmp; +} + diff --git a/src/base/bitmap.hh b/src/base/bitmap.hh new file mode 100644 index 000000000..9dfaa87a1 --- /dev/null +++ b/src/base/bitmap.hh @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: William Wang + * Ali Saidi + */ +#ifndef __BASE_BITMAP_HH__ +#define __BASE_BITMAP_HH__ + +#include <fstream> + +#include "base/vnc/convert.hh" + +/** + * @file Declaration of a class that writes a frame buffer to a bitmap + */ + + +// write frame buffer into a bitmap picture +class Bitmap +{ + public: + /** Create a Bitmap creator that takes data in the given mode & size + * and outputs to an fstream + * @param mode the type of data that is being provided + * @param h the hight of the image + * @param w the width of the image + * @param d the data for the image in mode + */ + Bitmap(VideoConvert::Mode mode, uint16_t w, uint16_t h, uint8_t *d); + + /** Provide the converter with the data that should be output. It will be + * converted into rgb8888 and write out when write() is called. + * @param d the data + */ + void rawData(uint8_t* d) { data = d; } + + /** Write the provided data into the fstream provided + * @param bmp stream to write to + */ + void write(std::ostream *bmp); + + private: + VideoConvert::Mode mode; + uint16_t height; + uint16_t width; + uint8_t *data; + + VideoConvert vc; + + struct Magic + { + unsigned char magic_number[2]; + }; + + struct Header + { + uint32_t size; + uint16_t reserved1; + uint16_t reserved2; + uint32_t offset; + }; + + struct Info + { + uint32_t Size; + uint32_t Width; + uint32_t Height; + uint16_t Planes; + uint16_t BitCount; + uint32_t Compression; + uint32_t SizeImage; + uint32_t XPelsPerMeter; + uint32_t YPelsPerMeter; + uint32_t ClrUsed; + uint32_t ClrImportant; + }; +}; + +#endif // __BASE_BITMAP_HH__ + diff --git a/src/base/compiler.hh b/src/base/compiler.hh index 2c655af60..3315fb2f7 100644 --- a/src/base/compiler.hh +++ b/src/base/compiler.hh @@ -41,6 +41,7 @@ #define M5_PRAGMA_NORETURN(x) #define M5_DUMMY_RETURN #define M5_VAR_USED __attribute__((unused)) +#define M5_ATTR_PACKED __attribute__ ((__packed__)) #elif defined(__SUNPRO_CC) // this doesn't do anything with sun cc, but why not #define M5_ATTR_NORETURN __sun_attr__((__noreturn__)) @@ -48,6 +49,7 @@ #define DO_PRAGMA(x) _Pragma(#x) #define M5_VAR_USED #define M5_PRAGMA_NORETURN(x) DO_PRAGMA(does_not_return(x)) +#define M5_ATTR_PACKED __attribute__ ((__packed__)) #else #error "Need to define compiler options in base/compiler.hh" #endif diff --git a/src/base/vnc/SConscript b/src/base/vnc/SConscript new file mode 100644 index 000000000..c92676555 --- /dev/null +++ b/src/base/vnc/SConscript @@ -0,0 +1,48 @@ +# -*- mode:python -*- + +# Copyright (c) 2010 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: William Wang + +Import('*') + +if env['FULL_SYSTEM']: + SimObject('VncServer.py') + Source('vncserver.cc') + TraceFlag('VNC') + +Source('convert.cc') + diff --git a/src/base/vnc/VncServer.py b/src/base/vnc/VncServer.py new file mode 100644 index 000000000..21eb3ed28 --- /dev/null +++ b/src/base/vnc/VncServer.py @@ -0,0 +1,45 @@ +# Copyright (c) 2010 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: William Wang + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * + +class VncServer(SimObject): + type = 'VncServer' + port = Param.TcpPort(5900, "listen port") + number = Param.Int(0, "vnc client number") diff --git a/src/base/vnc/convert.cc b/src/base/vnc/convert.cc new file mode 100644 index 000000000..ea7a9b1c5 --- /dev/null +++ b/src/base/vnc/convert.cc @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * William Wang + */ + +#include <cassert> + +#include "base/misc.hh" +#include "base/vnc/convert.hh" + +/** @file + * This file provides conversion functions for a variety of video modes + */ + +VideoConvert::VideoConvert(Mode input_mode, Mode output_mode, int _width, + int _height) + : inputMode(input_mode), outputMode(output_mode), width(_width), + height(_height) +{ + if (inputMode != bgr565 && inputMode != rgb565 && inputMode != bgr8888) + fatal("Only support converting from bgr565, rdb565, and bgr8888\n"); + + if (outputMode != rgb8888) + fatal("Only support converting to rgb8888\n"); + + assert(0 < height && height < 4000); + assert(0 < width && width < 4000); +} + +VideoConvert::~VideoConvert() +{ +} + +uint8_t* +VideoConvert::convert(uint8_t *fb) +{ + switch (inputMode) { + case bgr565: + return m565rgb8888(fb, true); + case rgb565: + return m565rgb8888(fb, false); + case bgr8888: + return bgr8888rgb8888(fb); + default: + panic("Unimplemented Mode\n"); + } +} + +uint8_t* +VideoConvert::m565rgb8888(uint8_t *fb, bool bgr) +{ + uint8_t *out = new uint8_t[area() * sizeof(uint32_t)]; + uint32_t *out32 = (uint32_t*)out; + + uint16_t *in16 = (uint16_t*)fb; + + for (int x = 0; x < area(); x++) { + Bgr565 inpx; + Rgb8888 outpx = 0; + + inpx = in16[x]; + + if (bgr) { + outpx.red = inpx.blue << 3; + outpx.green = inpx.green << 2; + outpx.blue = inpx.red << 3; + } else { + outpx.blue = inpx.blue << 3; + outpx.green = inpx.green << 2; + outpx.red = inpx.red << 3; + } + + out32[x] = outpx; + } + + return out; +} + + +uint8_t* +VideoConvert::bgr8888rgb8888(uint8_t *fb) +{ + uint8_t *out = new uint8_t[area() * sizeof(uint32_t)]; + uint32_t *out32 = (uint32_t*)out; + + uint32_t *in32 = (uint32_t*)fb; + + for (int x = 0; x < area(); x++) { + Rgb8888 outpx = 0; + Bgr8888 inpx; + + + inpx = in32[x]; + + outpx.red = inpx.blue; + outpx.green = inpx.green; + outpx.blue = inpx.red; + + out32[x] = outpx; + } + + return out; +} + diff --git a/src/base/vnc/convert.hh b/src/base/vnc/convert.hh new file mode 100644 index 000000000..68a21d677 --- /dev/null +++ b/src/base/vnc/convert.hh @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +/** @file + * This file provides conversion functions for a variety of video modes + */ + +#ifndef __BASE_VNC_CONVERT_HH__ +#define __BASE_VNC_CONVERT_HH__ + +#include "base/bitunion.hh" + +class VideoConvert +{ + public: + enum Mode { + UnknownMode, + bgr565, + rgb565, + bgr8888, + rgb8888, + rgb888, + bgr888, + bgr444, + bgr4444, + rgb444, + rgb4444, + }; + + // supports bpp32 RGB (bmp) and bpp16 5:6:5 mode BGR (linux) + BitUnion32(Rgb8888) + Bitfield<7,0> blue; + Bitfield<15,8> green; + Bitfield<23,16> red; + Bitfield<31,24> alpha; + EndBitUnion(Rgb8888) + + BitUnion32(Bgr8888) + Bitfield<7,0> red; + Bitfield<15,8> green; + Bitfield<23,16> blue; + Bitfield<31,24> alpha; + EndBitUnion(Bgr8888) + + BitUnion16(Bgr565) + Bitfield<4,0> red; + Bitfield<10,5> green; + Bitfield<15,11> blue; + EndBitUnion(Bgr565) + + BitUnion16(Rgb565) + Bitfield<4,0> red; + Bitfield<10,5> green; + Bitfield<15,11> blue; + EndBitUnion(Rgb565) + + /** Setup the converter with the given parameters + * @param input_mode type of data that will be provided + * @param output_mode type of data that should be output + * @param _width width of the frame buffer + * @param _height height of the frame buffer + */ + VideoConvert(Mode input_mode, Mode output_mode, int _width, int _height); + + /** Destructor + */ + ~VideoConvert(); + + /** Convert the provided frame buffer data into the format specified in the + * constructor. + * @param fb the frame buffer to convert + * @return the converted data (user must free) + */ + uint8_t* convert(uint8_t *fb); + + /** Return the number of pixels that this buffer specifies + * @return number of pixels + */ + int area() { return width * height; } + + private: + + /** + * Convert a bgr8888 input to rgb8888. + * @param fb the data to convert + * @return converted data + */ + uint8_t* bgr8888rgb8888(uint8_t *fb); + + /** + * Convert a bgr565 or rgb565 input to rgb8888. + * @param fb the data to convert + * @param bgr true if the input data is bgr565 + * @return converted data + */ + uint8_t* m565rgb8888(uint8_t *fb, bool bgr); + + Mode inputMode; + Mode outputMode; + int width; + int height; +}; + +#endif // __BASE_VNC_CONVERT_HH__ + diff --git a/src/base/vnc/vncserver.cc b/src/base/vnc/vncserver.cc new file mode 100644 index 000000000..8936fa67b --- /dev/null +++ b/src/base/vnc/vncserver.cc @@ -0,0 +1,703 @@ +/* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * William Wang + */ + +/** @file + * Implementiation of a VNC server + */ + +#include <cstdio> + +#include <sys/ioctl.h> +#include <sys/termios.h> +#include <errno.h> +#include <poll.h> +#include <unistd.h> + +#include "base/atomicio.hh" +#include "base/misc.hh" +#include "base/socket.hh" +#include "base/trace.hh" +#include "base/vnc/vncserver.hh" +#include "sim/byteswap.hh" + +using namespace std; + +/** + * Poll event for the listen socket + */ +VncServer::ListenEvent::ListenEvent(VncServer *vs, int fd, int e) + : PollEvent(fd, e), vncserver(vs) +{ +} + +void +VncServer::ListenEvent::process(int revent) +{ + vncserver->accept(); +} + +/** + * Poll event for the data socket + */ +VncServer::DataEvent::DataEvent(VncServer *vs, int fd, int e) + : PollEvent(fd, e), vncserver(vs) +{ +} + +void +VncServer::DataEvent::process(int revent) +{ + if (revent & POLLIN) + vncserver->data(); + else if (revent & POLLNVAL) + vncserver->detach(); +} + +/** + * VncServer + */ +VncServer::VncServer(const Params *p) + : SimObject(p), listenEvent(NULL), dataEvent(NULL), number(p->number), + dataFd(-1), _videoWidth(1), _videoHeight(1), clientRfb(0), keyboard(NULL), + mouse(NULL), sendUpdate(false), videoMode(VideoConvert::UnknownMode), + vc(NULL) +{ + if (p->port) + listen(p->port); + + curState = WaitForProtocolVersion; + + + // currently we only support this one pixel format + // unpacked 32bit rgb (rgb888 + 8 bits of nothing/alpha) + // keep it around for telling the client and making + // sure the client cooperates + pixelFormat.bpp = 32; + pixelFormat.depth = 24; + pixelFormat.bigendian = 0; + pixelFormat.truecolor = 1; + pixelFormat.redmax = 0xff; + pixelFormat.greenmax = 0xff; + pixelFormat.bluemax = 0xff; + pixelFormat.redshift = 16; + pixelFormat.greenshift = 8; + pixelFormat.blueshift = 0; + + + DPRINTF(VNC, "Vnc server created at port %d\n", p->port); +} + +VncServer::~VncServer() +{ + if (dataFd != -1) + ::close(dataFd); + + if (listenEvent) + delete listenEvent; + + if (dataEvent) + delete dataEvent; +} + + +//socket creation and vnc client attach +void +VncServer::listen(int port) +{ + if (ListenSocket::allDisabled()) { + warn_once("Sockets disabled, not accepting vnc client connections"); + return; + } + + while (!listener.listen(port, true)) { + DPRINTF(VNC, + "can't bind address vnc server port %d in use PID %d\n", + port, getpid()); + port++; + } + + int p1, p2; + p2 = name().rfind('.') - 1; + p1 = name().rfind('.', p2); + ccprintf(cerr, "Listening for %s connection on port %d\n", + name().substr(p1 + 1, p2 - p1), port); + + listenEvent = new ListenEvent(this, listener.getfd(), POLLIN); + pollQueue.schedule(listenEvent); +} + +// attach a vnc client +void +VncServer::accept() +{ + if (!listener.islistening()) + panic("%s: cannot accept a connection if not listening!", name()); + + int fd = listener.accept(true); + if (dataFd != -1) { + char message[] = "vnc server already attached!\n"; + atomic_write(fd, message, sizeof(message)); + ::close(fd); + return; + } + + dataFd = fd; + + // Send our version number to the client + write((uint8_t*)vncVersion(), strlen(vncVersion())); + + // read the client response + dataEvent = new DataEvent(this, dataFd, POLLIN); + pollQueue.schedule(dataEvent); + + inform("VNC client attached\n"); +} + +// data called by data event +void +VncServer::data() +{ + // We have new data, see if we can handle it + size_t len; + DPRINTF(VNC, "Vnc client message recieved\n"); + + switch (curState) { + case WaitForProtocolVersion: + checkProtocolVersion(); + break; + case WaitForSecurityResponse: + checkSecurity(); + break; + case WaitForClientInit: + // Don't care about shared, just need to read it out of the socket + uint8_t shared; + len = read(&shared); + assert(len == 1); + + // Send our idea of the frame buffer + sendServerInit(); + + break; + case NormalPhase: + uint8_t message_type; + len = read(&message_type); + if (!len) { + detach(); + return; + } + assert(len == 1); + + switch (message_type) { + case ClientSetPixelFormat: + setPixelFormat(); + break; + case ClientSetEncodings: + setEncodings(); + break; + case ClientFrameBufferUpdate: + requestFbUpdate(); + break; + case ClientKeyEvent: + recvKeyboardInput(); + break; + case ClientPointerEvent: + recvPointerInput(); + break; + case ClientCutText: + recvCutText(); + break; + default: + panic("Unimplemented message type recv from client: %d\n", + message_type); + break; + } + break; + default: + panic("Unknown vnc server state\n"); + } +} + + +// read from socket +size_t +VncServer::read(uint8_t *buf, size_t len) +{ + if (dataFd < 0) + panic("vnc not properly attached.\n"); + + size_t ret; + do { + ret = ::read(dataFd, buf, len); + } while (ret == -1 && errno == EINTR); + + + if (ret <= 0){ + DPRINTF(VNC, "Read failed.\n"); + detach(); + return 0; + } + + return ret; +} + +size_t +VncServer::read1(uint8_t *buf, size_t len) +{ + size_t read_len M5_VAR_USED; + read_len = read(buf + 1, len - 1); + assert(read_len == len - 1); + return read_len; +} + + +template<typename T> +size_t +VncServer::read(T* val) +{ + return read((uint8_t*)val, sizeof(T)); +} + +// write to socket +size_t +VncServer::write(const uint8_t *buf, size_t len) +{ + if (dataFd < 0) + panic("Vnc client not properly attached.\n"); + + ssize_t ret; + ret = atomic_write(dataFd, buf, len); + + if (ret < len) + detach(); + + return ret; +} + +template<typename T> +size_t +VncServer::write(T* val) +{ + return write((uint8_t*)val, sizeof(T)); +} + +size_t +VncServer::write(const char* str) +{ + return write((uint8_t*)str, strlen(str)); +} + +// detach a vnc client +void +VncServer::detach() +{ + if (dataFd != -1) { + ::close(dataFd); + dataFd = -1; + } + + if (!dataEvent || !dataEvent->queued()) + return; + + pollQueue.remove(dataEvent); + delete dataEvent; + dataEvent = NULL; + curState = WaitForProtocolVersion; + + inform("VNC client detached\n"); + DPRINTF(VNC, "detach vnc client %d\n", number); +} + +void +VncServer::sendError(const char* error_msg) +{ + uint32_t len = strlen(error_msg); + write(&len); + write(error_msg); +} + +void +VncServer::checkProtocolVersion() +{ + assert(curState == WaitForProtocolVersion); + + size_t len M5_VAR_USED; + char version_string[13]; + + // Null terminate the message so it's easier to work with + version_string[12] = 0; + + len = read((uint8_t*)version_string, 12); + assert(len == 12); + + uint32_t major, minor; + + // Figure out the major/minor numbers + if (sscanf(version_string, "RFB %03d.%03d\n", &major, &minor) != 2) { + warn(" Malformed protocol version %s\n", version_string); + sendError("Malformed protocol version\n"); + detach(); + } + + DPRINTF(VNC, "Client request protocol version %d.%d\n", major, minor); + + // If it's not 3.X we don't support it + if (major != 3 || minor < 2) { + warn("Unsupported VNC client version... disconnecting\n"); + uint8_t err = AuthInvalid; + write(&err); + detach(); + } + // Auth is different based on version number + if (minor < 7) { + uint32_t sec_type = htobe((uint32_t)AuthNone); + write(&sec_type); + } else { + uint8_t sec_cnt = 1; + uint8_t sec_type = htobe((uint8_t)AuthNone); + write(&sec_cnt); + write(&sec_type); + } + + // Wait for client to respond + curState = WaitForSecurityResponse; +} + +void +VncServer::checkSecurity() +{ + assert(curState == WaitForSecurityResponse); + + uint8_t security_type; + size_t len M5_VAR_USED = read(&security_type); + + assert(len == 1); + + if (security_type != AuthNone) { + warn("Unknown VNC security type\n"); + sendError("Unknown security type\n"); + } + + DPRINTF(VNC, "Sending security auth OK\n"); + + uint32_t success = htobe(VncOK); + write(&success); + curState = WaitForClientInit; +} + +void +VncServer::sendServerInit() +{ + ServerInitMsg msg; + + DPRINTF(VNC, "Sending server init message to client\n"); + + msg.fbWidth = htobe(videoWidth()); + msg.fbHeight = htobe(videoHeight()); + + msg.px.bpp = htobe(pixelFormat.bpp); + msg.px.depth = htobe(pixelFormat.depth); + msg.px.bigendian = htobe(pixelFormat.bigendian); + msg.px.truecolor = htobe(pixelFormat.truecolor); + msg.px.redmax = htobe(pixelFormat.redmax); + msg.px.greenmax = htobe(pixelFormat.greenmax); + msg.px.bluemax = htobe(pixelFormat.bluemax); + msg.px.redshift = htobe(pixelFormat.redshift); + msg.px.greenshift = htobe(pixelFormat.greenshift); + msg.px.blueshift = htobe(pixelFormat.blueshift); + memset(msg.px.padding, 0, 3); + msg.namelen = 2; + msg.namelen = htobe(msg.namelen); + memcpy(msg.name, "M5", 2); + + write(&msg); + curState = NormalPhase; +} + + +void +VncServer::setPixelFormat() +{ + DPRINTF(VNC, "Received pixel format from client message\n"); + + PixelFormatMessage pfm; + read1((uint8_t*)&pfm, sizeof(PixelFormatMessage)); + + DPRINTF(VNC, " -- bpp = %d; depth = %d; be = %d\n", pfm.px.bpp, + pfm.px.depth, pfm.px.bigendian); + DPRINTF(VNC, " -- true color = %d red,green,blue max = %d,%d,%d\n", + pfm.px.truecolor, betoh(pfm.px.redmax), betoh(pfm.px.greenmax), + betoh(pfm.px.bluemax)); + DPRINTF(VNC, " -- red,green,blue shift = %d,%d,%d\n", pfm.px.redshift, + pfm.px.greenshift, pfm.px.blueshift); + + if (betoh(pfm.px.bpp) != pixelFormat.bpp || + betoh(pfm.px.depth) != pixelFormat.depth || + betoh(pfm.px.bigendian) != pixelFormat.bigendian || + betoh(pfm.px.truecolor) != pixelFormat.truecolor || + betoh(pfm.px.redmax) != pixelFormat.redmax || + betoh(pfm.px.greenmax) != pixelFormat.greenmax || + betoh(pfm.px.bluemax) != pixelFormat.bluemax || + betoh(pfm.px.redshift) != pixelFormat.redshift || + betoh(pfm.px.greenshift) != pixelFormat.greenshift || + betoh(pfm.px.blueshift) != pixelFormat.blueshift) + fatal("VNC client doesn't support true color raw encoding\n"); +} + +void +VncServer::setEncodings() +{ + DPRINTF(VNC, "Received supported encodings from client\n"); + + PixelEncodingsMessage pem; + read1((uint8_t*)&pem, sizeof(PixelEncodingsMessage)); + + pem.num_encodings = betoh(pem.num_encodings); + + DPRINTF(VNC, " -- %d encoding present\n", pem.num_encodings); + supportsRawEnc = supportsResizeEnc = false; + + for (int x = 0; x < pem.num_encodings; x++) { + int32_t encoding; + size_t len M5_VAR_USED; + len = read(&encoding); + assert(len == sizeof(encoding)); + DPRINTF(VNC, " -- supports %d\n", betoh(encoding)); + + switch (betoh(encoding)) { + case EncodingRaw: + supportsRawEnc = true; + break; + case EncodingDesktopSize: + supportsResizeEnc = true; + break; + } + } + + if (!supportsRawEnc) + fatal("VNC clients must always support raw encoding\n"); +} + +void +VncServer::requestFbUpdate() +{ + DPRINTF(VNC, "Received frame buffer update request from client\n"); + + FrameBufferUpdateReq fbr; + read1((uint8_t*)&fbr, sizeof(FrameBufferUpdateReq)); + + fbr.x = betoh(fbr.x); + fbr.y = betoh(fbr.y); + fbr.width = betoh(fbr.width); + fbr.height = betoh(fbr.height); + + DPRINTF(VNC, " -- x = %d y = %d w = %d h = %d\n", fbr.x, fbr.y, fbr.width, + fbr.height); + + sendFrameBufferUpdate(); +} + +void +VncServer::recvKeyboardInput() +{ + DPRINTF(VNC, "Received keyboard input from client\n"); + KeyEventMessage kem; + read1((uint8_t*)&kem, sizeof(KeyEventMessage)); + + kem.key = betoh(kem.key); + DPRINTF(VNC, " -- received key code %d (%s)\n", kem.key, kem.down_flag ? + "down" : "up"); + + if (keyboard) + keyboard->keyPress(kem.key, kem.down_flag); +} + +void +VncServer::recvPointerInput() +{ + DPRINTF(VNC, "Received pointer input from client\n"); + PointerEventMessage pem; + + read1((uint8_t*)&pem, sizeof(PointerEventMessage));; + + pem.x = betoh(pem.x); + pem.y = betoh(pem.y); + DPRINTF(VNC, " -- pointer at x = %d y = %d buttons = %#x\n", pem.x, pem.y, + pem.button_mask); + + if (mouse) + mouse->mouseAt(pem.x, pem.y, pem.button_mask); +} + +void +VncServer::recvCutText() +{ + DPRINTF(VNC, "Received client copy buffer message\n"); + + ClientCutTextMessage cct; + read1((uint8_t*)&cct, sizeof(ClientCutTextMessage)); + + char str[1025]; + size_t data_len = betoh(cct.length); + DPRINTF(VNC, "String length %d\n", data_len); + while (data_len > 0) { + size_t len; + size_t bytes_to_read = data_len > 1024 ? 1024 : data_len; + len = read((uint8_t*)&str, bytes_to_read); + str[bytes_to_read] = 0; + data_len -= len; + assert(data_len >= 0); + DPRINTF(VNC, "Buffer: %s\n", str); + } + +} + + +void +VncServer::sendFrameBufferUpdate() +{ + + if (!clientRfb || dataFd <= 0 || curState != NormalPhase || !sendUpdate) { + DPRINTF(VNC, "NOT sending framebuffer update\n"); + return; + } + + assert(vc); + + // The client will request data constantly, unless we throttle it + sendUpdate = false; + + DPRINTF(VNC, "Sending framebuffer update\n"); + + FrameBufferUpdate fbu; + FrameBufferRect fbr; + + fbu.type = ServerFrameBufferUpdate; + fbu.num_rects = 1; + fbr.x = 0; + fbr.y = 0; + fbr.width = videoWidth(); + fbr.height = videoHeight(); + fbr.encoding = EncodingRaw; + + // fix up endian + fbu.num_rects = htobe(fbu.num_rects); + fbr.x = htobe(fbr.x); + fbr.y = htobe(fbr.y); + fbr.width = htobe(fbr.width); + fbr.height = htobe(fbr.height); + fbr.encoding = htobe(fbr.encoding); + + // send headers to client + write(&fbu); + write(&fbr); + + assert(clientRfb); + + uint8_t *tmp = vc->convert(clientRfb); + write(tmp, videoWidth() * videoHeight() * sizeof(uint32_t)); + delete [] tmp; + +} + +void +VncServer::sendFrameBufferResized() +{ + assert(clientRfb && dataFd > 0 && curState == NormalPhase); + DPRINTF(VNC, "Sending framebuffer resize\n"); + + FrameBufferUpdate fbu; + FrameBufferRect fbr; + + fbu.type = ServerFrameBufferUpdate; + fbu.num_rects = 1; + fbr.x = 0; + fbr.y = 0; + fbr.width = videoWidth(); + fbr.height = videoHeight(); + fbr.encoding = EncodingDesktopSize; + + // fix up endian + fbu.num_rects = htobe(fbu.num_rects); + fbr.x = htobe(fbr.x); + fbr.y = htobe(fbr.y); + fbr.width = htobe(fbr.width); + fbr.height = htobe(fbr.height); + fbr.encoding = htobe(fbr.encoding); + + // send headers to client + write(&fbu); + write(&fbr); + + // No actual data is sent in this message +} + +void +VncServer::setFrameBufferParams(VideoConvert::Mode mode, int width, int height) +{ + DPRINTF(VNC, "Updating video params: mode: %d width: %d height: %d\n", mode, + width, height); + + if (mode != videoMode || width != videoWidth() || height != videoHeight()) { + videoMode = mode; + _videoWidth = width; + _videoHeight = height; + + if (vc) + delete vc; + + vc = new VideoConvert(mode, VideoConvert::rgb8888, videoWidth(), + videoHeight()); + + if (dataFd > 0 && clientRfb && curState == NormalPhase) { + if (supportsResizeEnc) + sendFrameBufferResized(); + else + // The frame buffer changed size and we can't update the client + detach(); + } + } +} + +// create the VNC server object +VncServer * +VncServerParams::create() +{ + return new VncServer(this); +} diff --git a/src/base/vnc/vncserver.hh b/src/base/vnc/vncserver.hh new file mode 100644 index 000000000..23b097b11 --- /dev/null +++ b/src/base/vnc/vncserver.hh @@ -0,0 +1,475 @@ +/* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + * William Wang + */ + +/** @file + * Declaration of a VNC server + */ + +#ifndef __DEV_VNC_SERVER_HH__ +#define __DEV_VNC_SERVER_HH__ + +#include <iostream> + +#include "base/circlebuf.hh" +#include "base/pollevent.hh" +#include "base/socket.hh" +#include "base/vnc/convert.hh" +#include "cpu/intr_control.hh" +#include "sim/sim_object.hh" +#include "params/VncServer.hh" + +/** + * A device that expects to receive input from the vnc server should derrive + * (through mulitple inheritence if necessary from VncKeyboard or VncMouse + * and call setKeyboard() or setMouse() respectively on the vnc server. + */ +class VncKeyboard +{ + public: + /** + * Called when the vnc server receives a key press event from the + * client. + * @param key the key passed is an x11 keysym + * @param down is the key now down or up? + */ + virtual void keyPress(uint32_t key, bool down) = 0; +}; + +class VncMouse +{ + public: + /** + * called whenever the mouse moves or it's button state changes + * buttons is a simple mask with each button (0-8) corresponding to + * a bit position in the byte with 1 being down and 0 being up + * @param x the x position of the mouse + * @param y the y position of the mouse + * @param buttos the button state as described above + */ + virtual void mouseAt(uint16_t x, uint16_t y, uint8_t buttons) = 0; +}; + +class VncServer : public SimObject +{ + public: + + /** + * \defgroup VncConstants A set of constants and structs from the VNC spec + * @{ + */ + /** Authentication modes */ + const static uint32_t AuthInvalid = 0; + const static uint32_t AuthNone = 1; + + /** Error conditions */ + const static uint32_t VncOK = 0; + + /** Client -> Server message IDs */ + enum ClientMessages { + ClientSetPixelFormat = 0, + ClientSetEncodings = 2, + ClientFrameBufferUpdate = 3, + ClientKeyEvent = 4, + ClientPointerEvent = 5, + ClientCutText = 6 + }; + + /** Server -> Client message IDs */ + enum ServerMessages { + ServerFrameBufferUpdate = 0, + ServerSetColorMapEntries = 1, + ServerBell = 2, + ServerCutText = 3 + }; + + /** Encoding types */ + enum EncodingTypes { + EncodingRaw = 0, + EncodingCopyRect = 1, + EncodingHextile = 5, + EncodingDesktopSize = -223 + }; + + /** keyboard/mouse support */ + enum MouseEvents { + MouseLeftButton = 0x1, + MouseRightButton = 0x2, + MouseMiddleButton = 0x4 + }; + + const char* vncVersion() const + { + return "RFB 003.008\n"; + } + + enum ConnectionState { + WaitForProtocolVersion, + WaitForSecurityResponse, + WaitForClientInit, + InitializationPhase, + NormalPhase + }; + + struct PixelFormat { + uint8_t bpp; + uint8_t depth; + uint8_t bigendian; + uint8_t truecolor; + uint16_t redmax; + uint16_t greenmax; + uint16_t bluemax; + uint8_t redshift; + uint8_t greenshift; + uint8_t blueshift; + uint8_t padding[3]; + } M5_ATTR_PACKED; + + struct ServerInitMsg { + uint16_t fbWidth; + uint16_t fbHeight; + PixelFormat px; + uint32_t namelen; + char name[2]; // just to put M5 in here + } M5_ATTR_PACKED; + + struct PixelFormatMessage { + uint8_t type; + uint8_t padding[3]; + PixelFormat px; + } M5_ATTR_PACKED; + + struct PixelEncodingsMessage { + uint8_t type; + uint8_t padding; + uint16_t num_encodings; + } M5_ATTR_PACKED; + + struct FrameBufferUpdateReq { + uint8_t type; + uint8_t incremental; + uint16_t x; + uint16_t y; + uint16_t width; + uint16_t height; + } M5_ATTR_PACKED; + + struct KeyEventMessage { + uint8_t type; + uint8_t down_flag; + uint8_t padding[2]; + uint32_t key; + } M5_ATTR_PACKED; + + struct PointerEventMessage { + uint8_t type; + uint8_t button_mask; + uint16_t x; + uint16_t y; + } M5_ATTR_PACKED; + + struct ClientCutTextMessage { + uint8_t type; + uint8_t padding[3]; + uint32_t length; + } M5_ATTR_PACKED; + + struct FrameBufferUpdate { + uint8_t type; + uint8_t padding; + uint16_t num_rects; + } M5_ATTR_PACKED; + + struct FrameBufferRect { + uint16_t x; + uint16_t y; + uint16_t width; + uint16_t height; + int32_t encoding; + } M5_ATTR_PACKED; + + struct ServerCutText { + uint8_t type; + uint8_t padding[3]; + uint32_t length; + } M5_ATTR_PACKED; + + /** @} */ + + protected: + /** ListenEvent to accept a vnc client connection */ + class ListenEvent: public PollEvent + { + protected: + VncServer *vncserver; + + public: + ListenEvent(VncServer *vs, int fd, int e); + void process(int revent); + }; + + friend class ListenEvent; + ListenEvent *listenEvent; + + /** DataEvent to read data from vnc */ + class DataEvent: public PollEvent + { + protected: + VncServer *vncserver; + + public: + DataEvent(VncServer *vs, int fd, int e); + void process(int revent); + }; + + friend class DataEvent; + DataEvent *dataEvent; + + int number; + int dataFd; // data stream file describer + + ListenSocket listener; + + void listen(int port); + void accept(); + void data(); + void detach(); + + public: + typedef VncServerParams Params; + VncServer(const Params *p); + ~VncServer(); + + // RFB + protected: + + /** The rfb prototol state the connection is in */ + ConnectionState curState; + + /** the width of the frame buffer we are sending to the client */ + uint16_t _videoWidth; + + /** the height of the frame buffer we are sending to the client */ + uint16_t _videoHeight; + + /** pointer to the actual data that is stored in the frame buffer device */ + uint8_t* clientRfb; + + /** The device to notify when we get key events */ + VncKeyboard *keyboard; + + /** The device to notify when we get mouse events */ + VncMouse *mouse; + + /** An update needs to be sent to the client. Without doing this the + * client will constantly request data that is pointless */ + bool sendUpdate; + + /** The one and only pixel format we support */ + PixelFormat pixelFormat; + + /** If the vnc client supports receiving raw data. It always should */ + bool supportsRawEnc; + + /** If the vnc client supports the desktop resize command */ + bool supportsResizeEnc; + + /** The mode of data we're getting frame buffer in */ + VideoConvert::Mode videoMode; + + /** The video converter that transforms data for us */ + VideoConvert *vc; + + protected: + /** + * vnc client Interface + */ + + /** Send an error message to the client + * @param error_msg text to send describing the error + */ + void sendError(const char* error_msg); + + /** Read some data from the client + * @param buf the data to read + * @param len the amount of data to read + * @return length read + */ + size_t read(uint8_t *buf, size_t len); + + /** Read len -1 bytes from the client into the buffer provided + 1 + * assert that we read enough bytes. This function exists to handle + * reading all of the protocol structs above when we've already read + * the first byte which describes which one we're reading + * @param buf the address of the buffer to add one to and read data into + * @param len the amount of data + 1 to read + * @return length read + */ + size_t read1(uint8_t *buf, size_t len); + + + /** Templated version of the read function above to + * read simple data to the client + * @param val data to recv from the client + */ + template <typename T> size_t read(T* val); + + + /** Write a buffer to the client. + * @param buf buffer to send + * @param len length of the buffer + * @return number of bytes sent + */ + size_t write(const uint8_t *buf, size_t len); + + /** Templated version of the write function above to + * write simple data to the client + * @param val data to send to the client + */ + template <typename T> size_t write(T* val); + + /** Send a string to the client + * @param str string to transmit + */ + size_t write(const char* str); + + /** Check the client's protocol verion for compatibility and send + * the security types we support + */ + void checkProtocolVersion(); + + /** Check that the security exchange was successful + */ + void checkSecurity(); + + /** Send client our idea about what the frame buffer looks like */ + void sendServerInit(); + + /** Send an error message to the client when something goes wrong + * @param error_msg error to send + */ + void sendError(std::string error_msg); + + /** Send a updated frame buffer to the client. + * @todo this doesn't do anything smart and just sends the entire image + */ + void sendFrameBufferUpdate(); + + /** Receive pixel foramt message from client and process it. */ + void setPixelFormat(); + + /** Receive encodings message from client and process it. */ + void setEncodings(); + + /** Receive message from client asking for updated frame buffer */ + void requestFbUpdate(); + + /** Receive message from client providing new keyboard input */ + void recvKeyboardInput(); + + /** Recv message from client providing new mouse movement or button click */ + void recvPointerInput(); + + /** Receive message from client that there is text in it's paste buffer. + * This is a no-op at the moment, but perhaps we would want to be able to + * paste it at some point. + */ + void recvCutText(); + + /** Tell the client that the frame buffer resized. This happens when the + * simulated system changes video modes (E.g. X11 starts). + */ + void sendFrameBufferResized(); + + public: + /** Set the address of the frame buffer we are going to show. + * To avoid copying, just have the display controller + * tell us where the data is instead of constanly copying it around + * @param rfb frame buffer that we're going to use + */ + void + setFramebufferAddr(uint8_t* rfb) + { + clientRfb = rfb; + } + + /** Set up the device that would like to receive notifications when keys are + * pressed in the vnc client keyboard + * @param _keyboard an object that derrives from VncKeyboard + */ + void setKeyboard(VncKeyboard *_keyboard) { keyboard = _keyboard; } + + /** Setup the device that would like to receive notifications when mouse + * movements or button presses are received from the vnc client. + * @param _mouse an object that derrives from VncMouse + */ + void setMouse(VncMouse *_mouse) { mouse = _mouse; } + + /** The frame buffer uses this call to notify the vnc server that + * the frame buffer has been updated and a new image needs to be sent to the + * client + */ + void + setDirty() + { + sendUpdate = true; + sendFrameBufferUpdate(); + } + + /** What is the width of the screen we're displaying. + * This is used for pointer/tablet devices that need to know to calculate + * the correct value to send to the device driver. + * @return the width of the simulated screen + */ + uint16_t videoWidth() { return _videoWidth; } + + /** What is the height of the screen we're displaying. + * This is used for pointer/tablet devices that need to know to calculate + * the correct value to send to the device driver. + * @return the height of the simulated screen + */ + uint16_t videoHeight() { return _videoHeight; } + + /** Set the mode of the data the frame buffer will be sending us + * @param mode the mode + */ + void setFrameBufferParams(VideoConvert::Mode mode, int width, int height); +}; + +#endif diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 0c566ec65..8b6662d70 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2004-2006 The Regents of The University of Michigan * Copyright (c) 2009 The University of Edinburgh * All rights reserved. @@ -150,6 +162,29 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Finish a DTB address translation. */ void finishTranslation(WholeTranslationState *state); + /** True if the DTB address translation has started. */ + bool translationStarted; + + /** True if the DTB address translation has completed. */ + bool translationCompleted; + + /** + * Returns true if the DTB address translation is being delayed due to a hw + * page table walk. + */ + bool isTranslationDelayed() const + { + return (translationStarted && !translationCompleted); + } + + /** + * Saved memory requests (needed when the DTB address translation is + * delayed due to a hw page table walk). + */ + RequestPtr savedReq; + RequestPtr savedSreqLow; + RequestPtr savedSreqHigh; + /** @todo: Consider making this private. */ public: /** The sequence number of the instruction. */ @@ -835,33 +870,42 @@ BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags) { reqMade = true; - Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), - thread->contextId(), threadNumber); - + Request *req = NULL; Request *sreqLow = NULL; Request *sreqHigh = NULL; - // Only split the request if the ISA supports unaligned accesses. - if (TheISA::HasUnalignedMemAcc) { - splitRequest(req, sreqLow, sreqHigh); - } - initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); - - if (fault == NoFault) { - effAddr = req->getVaddr(); - effAddrValid = true; - fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); + if (reqMade && translationStarted) { + req = savedReq; + sreqLow = savedSreqLow; + sreqHigh = savedSreqHigh; } else { - // Commit will have to clean up whatever happened. Set this - // instruction as executed. - this->setExecuted(); + req = new Request(asid, addr, size, flags, this->pc.instAddr(), + thread->contextId(), threadNumber); + + // Only split the request if the ISA supports unaligned accesses. + if (TheISA::HasUnalignedMemAcc) { + splitRequest(req, sreqLow, sreqHigh); + } + initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); } - if (fault != NoFault) { - // Return a fixed value to keep simulation deterministic even - // along misspeculated paths. - if (data) - bzero(data, size); + if (translationCompleted) { + if (fault == NoFault) { + effAddr = req->getVaddr(); + effAddrValid = true; + fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); + } else { + // Commit will have to clean up whatever happened. Set this + // instruction as executed. + this->setExecuted(); + } + + if (fault != NoFault) { + // Return a fixed value to keep simulation deterministic even + // along misspeculated paths. + if (data) + bzero(data, size); + } } if (traceData) { @@ -897,19 +941,26 @@ BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, } reqMade = true; - Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), - thread->contextId(), threadNumber); - + Request *req = NULL; Request *sreqLow = NULL; Request *sreqHigh = NULL; - // Only split the request if the ISA supports unaligned accesses. - if (TheISA::HasUnalignedMemAcc) { - splitRequest(req, sreqLow, sreqHigh); + if (reqMade && translationStarted) { + req = savedReq; + sreqLow = savedSreqLow; + sreqHigh = savedSreqHigh; + } else { + req = new Request(asid, addr, size, flags, this->pc.instAddr(), + thread->contextId(), threadNumber); + + // Only split the request if the ISA supports unaligned accesses. + if (TheISA::HasUnalignedMemAcc) { + splitRequest(req, sreqLow, sreqHigh); + } + initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); } - initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); - if (fault == NoFault) { + if (fault == NoFault && translationCompleted) { effAddr = req->getVaddr(); effAddrValid = true; fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); @@ -953,6 +1004,8 @@ BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh, uint64_t *res, BaseTLB::Mode mode) { + translationStarted = true; + if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { WholeTranslationState *state = new WholeTranslationState(req, NULL, res, mode); @@ -961,6 +1014,12 @@ BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, DataTranslation<BaseDynInst<Impl> > *trans = new DataTranslation<BaseDynInst<Impl> >(this, state); cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); + if (!translationCompleted) { + // Save memory requests. + savedReq = state->mainReq; + savedSreqLow = state->sreqLow; + savedSreqHigh = state->sreqHigh; + } } else { WholeTranslationState *state = new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); @@ -973,6 +1032,12 @@ BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); + if (!translationCompleted) { + // Save memory requests. + savedReq = state->mainReq; + savedSreqLow = state->sreqLow; + savedSreqHigh = state->sreqHigh; + } } } @@ -998,6 +1063,8 @@ BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) state->deleteReqs(); } delete state; + + translationCompleted = true; } #endif // __CPU_BASE_DYN_INST_HH__ diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh index 74f199d5f..7e4d25322 100644 --- a/src/cpu/base_dyn_inst_impl.hh +++ b/src/cpu/base_dyn_inst_impl.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2004-2006 The Regents of The University of Michigan * All rights reserved. * @@ -107,6 +119,9 @@ BaseDynInst<Impl>::initVars() effAddrValid = false; physEffAddr = 0; + translationStarted = false; + translationCompleted = false; + isUncacheable = false; reqMade = false; readyRegs = 0; diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript index ae5ec0257..b9c526763 100644 --- a/src/cpu/inorder/SConscript +++ b/src/cpu/inorder/SConscript @@ -55,7 +55,7 @@ if 'InOrderCPU' in env['CPU_MODELS']: TraceFlag('ThreadModel') TraceFlag('RefCount') TraceFlag('AddrDep') - + TraceFlag('SkedCache') CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU', 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred', @@ -63,7 +63,6 @@ if 'InOrderCPU' in env['CPU_MODELS']: 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource', 'ThreadModel', 'AddrDep']) - Source('pipeline_traits.cc') Source('inorder_dyn_inst.cc') Source('inorder_cpu_builder.cc') Source('inorder_trace.cc') diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index ffdcae7df..3a705258d 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -334,9 +334,14 @@ InOrderCPU::InOrderCPU(Params *params) dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0); dummyReqInst->setSquashed(); + dummyReqInst->resetInstCount(); dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0); dummyBufferInst->setSquashed(); + dummyBufferInst->resetInstCount(); + + endOfSkedIt = skedCache.end(); + frontEndSked = createFrontEndSked(); lastRunningCycle = curTick(); @@ -348,7 +353,6 @@ InOrderCPU::InOrderCPU(Params *params) reset(); #endif - dummyBufferInst->resetInstCount(); // Schedule First Tick Event, CPU will reschedule itself from here on out. scheduleTickEvent(0); @@ -359,6 +363,118 @@ InOrderCPU::~InOrderCPU() delete resPool; } +std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache; + +RSkedPtr +InOrderCPU::createFrontEndSked() +{ + RSkedPtr res_sked = new ResourceSked(); + int stage_num = 0; + StageScheduler F(res_sked, stage_num++); + StageScheduler D(res_sked, stage_num++); + + // FETCH + F.needs(FetchSeq, FetchSeqUnit::AssignNextPC); + F.needs(ICache, FetchUnit::InitiateFetch); + + // DECODE + D.needs(ICache, FetchUnit::CompleteFetch); + D.needs(Decode, DecodeUnit::DecodeInst); + D.needs(BPred, BranchPredictor::PredictBranch); + D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC); + + + DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n"); + + return res_sked; +} + +RSkedPtr +InOrderCPU::createBackEndSked(DynInstPtr inst) +{ + RSkedPtr res_sked = lookupSked(inst); + if (res_sked != NULL) { + DPRINTF(SkedCache, "Found %s in sked cache.\n", + inst->instName()); + return res_sked; + } else { + res_sked = new ResourceSked(); + } + + int stage_num = ThePipeline::BackEndStartStage; + StageScheduler X(res_sked, stage_num++); + StageScheduler M(res_sked, stage_num++); + StageScheduler W(res_sked, stage_num++); + + if (!inst->staticInst) { + warn_once("Static Instruction Object Not Set. Can't Create" + " Back End Schedule"); + return NULL; + } + + // EXECUTE + for (int idx=0; idx < inst->numSrcRegs(); idx++) { + if (!idx || !inst->isStore()) { + X.needs(RegManager, UseDefUnit::ReadSrcReg, idx); + } + } + + if ( inst->isNonSpeculative() ) { + // skip execution of non speculative insts until later + } else if ( inst->isMemRef() ) { + if ( inst->isLoad() ) { + X.needs(AGEN, AGENUnit::GenerateAddr); + } + } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) { + X.needs(MDU, MultDivUnit::StartMultDiv); + } else { + X.needs(ExecUnit, ExecutionUnit::ExecuteInst); + } + + if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) { + X.needs(MDU, MultDivUnit::EndMultDiv); + } + + // MEMORY + if ( inst->isLoad() ) { + M.needs(DCache, CacheUnit::InitiateReadData); + } else if ( inst->isStore() ) { + if ( inst->numSrcRegs() >= 2 ) { + M.needs(RegManager, UseDefUnit::ReadSrcReg, 1); + } + M.needs(AGEN, AGENUnit::GenerateAddr); + M.needs(DCache, CacheUnit::InitiateWriteData); + } + + + // WRITEBACK + if ( inst->isLoad() ) { + W.needs(DCache, CacheUnit::CompleteReadData); + } else if ( inst->isStore() ) { + W.needs(DCache, CacheUnit::CompleteWriteData); + } + + if ( inst->isNonSpeculative() ) { + if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction"); + W.needs(ExecUnit, ExecutionUnit::ExecuteInst); + } + + for (int idx=0; idx < inst->numDestRegs(); idx++) { + W.needs(RegManager, UseDefUnit::WriteDestReg, idx); + } + + W.needs(Grad, GraduationUnit::GraduateInst); + + // Insert Front Schedule into our cache of + // resource schedules + addToSkedCache(inst, res_sked); + + DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n", + inst->instName(), inst->getMachInst()); + res_sked->print(); + + return res_sked; +} void InOrderCPU::regStats() @@ -1299,14 +1415,6 @@ InOrderCPU::cleanUpRemovedInsts() DynInstPtr inst = *removeList.front(); ThreadID tid = inst->threadNumber; - // Make Sure Resource Schedule Is Emptied Out - ThePipeline::ResSchedule *inst_sched = &inst->resSched; - while (!inst_sched->empty()) { - ScheduleEntry* sch_entry = inst_sched->top(); - inst_sched->pop(); - delete sch_entry; - } - // Remove From Register Dependency Map, If Necessary archRegDepMap[(*removeList.front())->threadNumber]. remove((*removeList.front())); @@ -1314,8 +1422,8 @@ InOrderCPU::cleanUpRemovedInsts() // Clear if Non-Speculative if (inst->staticInst && - inst->seqNum == nonSpecSeqNum[tid] && - nonSpecInstActive[tid] == true) { + inst->seqNum == nonSpecSeqNum[tid] && + nonSpecInstActive[tid] == true) { nonSpecInstActive[tid] = false; } diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 9ff0f12ce..2a5c815e1 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -296,6 +296,91 @@ class InOrderCPU : public BaseCPU TheISA::TLB *getITBPtr(); TheISA::TLB *getDTBPtr(); + /** Accessor Type for the SkedCache */ + typedef uint32_t SkedID; + + /** Cache of Instruction Schedule using the instruction's name as a key */ + static std::map<SkedID, ThePipeline::RSkedPtr> skedCache; + + typedef std::map<SkedID, ThePipeline::RSkedPtr>::iterator SkedCacheIt; + + /** Initialized to last iterator in map, signifying a invalid entry + on map searches + */ + SkedCacheIt endOfSkedIt; + + ThePipeline::RSkedPtr frontEndSked; + + /** Add a new instruction schedule to the schedule cache */ + void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked) + { + SkedID sked_id = genSkedID(inst); + skedCache[sked_id] = inst_sked; + } + + + /** Find a instruction schedule */ + ThePipeline::RSkedPtr lookupSked(DynInstPtr inst) + { + SkedID sked_id = genSkedID(inst); + SkedCacheIt lookup_it = skedCache.find(sked_id); + + if (lookup_it != endOfSkedIt) { + return (*lookup_it).second; + } else { + return NULL; + } + } + + static const uint8_t INST_OPCLASS = 26; + static const uint8_t INST_LOAD = 25; + static const uint8_t INST_STORE = 24; + static const uint8_t INST_CONTROL = 23; + static const uint8_t INST_NONSPEC = 22; + static const uint8_t INST_DEST_REGS = 18; + static const uint8_t INST_SRC_REGS = 14; + + inline SkedID genSkedID(DynInstPtr inst) + { + SkedID id = 0; + id = (inst->opClass() << INST_OPCLASS) | + (inst->isLoad() << INST_LOAD) | + (inst->isStore() << INST_STORE) | + (inst->isControl() << INST_CONTROL) | + (inst->isNonSpeculative() << INST_NONSPEC) | + (inst->numDestRegs() << INST_DEST_REGS) | + (inst->numSrcRegs() << INST_SRC_REGS); + return id; + } + + ThePipeline::RSkedPtr createFrontEndSked(); + ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst); + + class StageScheduler { + private: + ThePipeline::RSkedPtr rsked; + int stageNum; + int nextTaskPriority; + + public: + StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num) + : rsked(_rsked), stageNum(stage_num), + nextTaskPriority(0) + { } + + void needs(int unit, int request) { + rsked->push(new ScheduleEntry( + stageNum, nextTaskPriority++, unit, request + )); + } + + void needs(int unit, int request, int param) { + rsked->push(new ScheduleEntry( + stageNum, nextTaskPriority++, unit, request, param + )); + } + }; + public: /** Registers statistics. */ diff --git a/src/cpu/inorder/first_stage.cc b/src/cpu/inorder/first_stage.cc index 71c6ec3e0..b656ca1c7 100644 --- a/src/cpu/inorder/first_stage.cc +++ b/src/cpu/inorder/first_stage.cc @@ -181,7 +181,7 @@ FirstStage::processInsts(ThreadID tid) inst->setInstListIt(cpu->addInst(inst)); // Create Front-End Resource Schedule For Instruction - ThePipeline::createFrontEndSchedule(inst); + inst->setFrontSked(cpu->frontEndSked); } int reqs_processed = 0; diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index 6afe35862..e9deb7625 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -51,7 +51,7 @@ InOrderDynInst::InOrderDynInst(TheISA::ExtMachInst machInst, const TheISA::PCState &instPC, const TheISA::PCState &_predPC, InstSeqNum seq_num, InOrderCPU *cpu) - : staticInst(machInst, instPC.instAddr()), traceData(NULL), cpu(cpu) + : staticInst(machInst, instPC.instAddr()), traceData(NULL), cpu(cpu) { seqNum = seq_num; @@ -108,6 +108,8 @@ InOrderDynInst::setMachInst(ExtMachInst machInst) void InOrderDynInst::initVars() { + inFrontEnd = true; + fetchMemReq = NULL; dataMemReq = NULL; splitMemData = NULL; @@ -123,7 +125,6 @@ InOrderDynInst::initVars() readyRegs = 0; nextStage = 0; - nextInstStageNum = 0; for(int i = 0; i < MaxInstDestRegs; i++) instResult[i].val.integer = 0; @@ -206,8 +207,6 @@ InOrderDynInst::~InOrderDynInst() --instcount; - deleteStages(); - DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed" " (active insts: %i)\n", threadNumber, seqNum, instcount); } @@ -282,29 +281,6 @@ InOrderDynInst::completeAcc(Packet *pkt) return this->fault; } -InstStage *InOrderDynInst::addStage() -{ - this->currentInstStage = new InstStage(this, nextInstStageNum++); - instStageList.push_back( this->currentInstStage ); - return this->currentInstStage; -} - -InstStage *InOrderDynInst::addStage(int stage_num) -{ - nextInstStageNum = stage_num; - return InOrderDynInst::addStage(); -} - -void InOrderDynInst::deleteStages() { - std::list<InstStage*>::iterator list_it = instStageList.begin(); - std::list<InstStage*>::iterator list_end = instStageList.end(); - - while(list_it != list_end) { - delete *list_it; - list_it++; - } -} - Fault InOrderDynInst::memAccess() { diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index 1c0ee4384..0e6be3da2 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -210,9 +210,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Data used for a store for operation. */ uint64_t storeData; - /** The resource schedule for this inst */ - ThePipeline::ResSchedule resSched; - /** List of active resource requests for this instruction */ std::list<ResourceRequest*> reqList; @@ -304,11 +301,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted int nextStage; - /* vars to keep track of InstStage's - used for resource sched defn */ - int nextInstStageNum; - ThePipeline::InstStage *currentInstStage; - std::list<ThePipeline::InstStage*> instStageList; - private: /** Function to initialize variables in the constructors. */ void initVars(); @@ -337,9 +329,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted //////////////////////////////////////////////////////////// std::string instName() { return staticInst->getName(); } - void setMachInst(ExtMachInst inst); + ExtMachInst getMachInst() { return staticInst->machInst; } + /** Sets the StaticInst. */ void setStaticInst(StaticInstPtr &static_inst); @@ -411,68 +404,88 @@ class InOrderDynInst : public FastAlloc, public RefCounted // RESOURCE SCHEDULING // ///////////////////////////////////////////// + typedef ThePipeline::RSkedPtr RSkedPtr; + bool inFrontEnd; - void setNextStage(int stage_num) { nextStage = stage_num; } - int getNextStage() { return nextStage; } + RSkedPtr frontSked; + RSkedIt frontSked_end; + + RSkedPtr backSked; + RSkedIt backSked_end; - ThePipeline::InstStage *addStage(); - ThePipeline::InstStage *addStage(int stage); - ThePipeline::InstStage *currentStage() { return currentInstStage; } - void deleteStages(); + RSkedIt curSkedEntry; + + void setFrontSked(RSkedPtr front_sked) + { + frontSked = front_sked; + frontSked_end.init(frontSked); + frontSked_end = frontSked->end(); + //DPRINTF(InOrderDynInst, "Set FrontSked End to : %x \n" , + // frontSked_end.getIt()/*, frontSked->end()*/); + //assert(frontSked_end == frontSked->end()); + + // This initializes instruction to be able + // to walk the resource schedule + curSkedEntry.init(frontSked); + curSkedEntry = frontSked->begin(); + } - /** Add A Entry To Reource Schedule */ - void addToSched(ScheduleEntry* sched_entry) - { resSched.push(sched_entry); } + void setBackSked(RSkedPtr back_sked) + { + backSked = back_sked; + backSked_end.init(backSked); + backSked_end = backSked->end(); + } + void setNextStage(int stage_num) { nextStage = stage_num; } + int getNextStage() { return nextStage; } /** Print Resource Schedule */ - /** @NOTE: DEBUG ONLY */ - void printSched() + void printSked() { - ThePipeline::ResSchedule tempSched; - std::cerr << "\tInst. Res. Schedule: "; - while (!resSched.empty()) { - std::cerr << '\t' << resSched.top()->stageNum << "-" - << resSched.top()->resNum << ", "; - - tempSched.push(resSched.top()); - resSched.pop(); + if (frontSked != NULL) { + frontSked->print(); } - std::cerr << std::endl; - resSched = tempSched; + if (backSked != NULL) { + backSked->print(); + } } /** Return Next Resource Stage To Be Used */ int nextResStage() { - if (resSched.empty()) - return -1; - else - return resSched.top()->stageNum; + assert((inFrontEnd && curSkedEntry != frontSked_end) || + (!inFrontEnd && curSkedEntry != backSked_end)); + + return curSkedEntry->stageNum; } /** Return Next Resource To Be Used */ int nextResource() { - if (resSched.empty()) - return -1; - else - return resSched.top()->resNum; + assert((inFrontEnd && curSkedEntry != frontSked_end) || + (!inFrontEnd && curSkedEntry != backSked_end)); + + return curSkedEntry->resNum; } - /** Remove & Deallocate a schedule entry */ - void popSchedEntry() + /** Finish using a schedule entry, increment to next entry */ + bool finishSkedEntry() { - if (!resSched.empty()) { - ScheduleEntry* sked = resSched.top(); - resSched.pop(); - if (sked != 0) { - delete sked; - - } + curSkedEntry++; + + if (inFrontEnd && curSkedEntry == frontSked_end) { + assert(backSked != NULL); + curSkedEntry.init(backSked); + curSkedEntry = backSked->begin(); + inFrontEnd = false; + } else if (!inFrontEnd && curSkedEntry == backSked_end) { + return true; } + + return false; } /** Release a Resource Request (Currently Unused) */ diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc index 744ffd4d2..bc31a8537 100644 --- a/src/cpu/inorder/pipeline_stage.cc +++ b/src/cpu/inorder/pipeline_stage.cc @@ -944,11 +944,16 @@ PipelineStage::processInstSchedule(DynInstPtr inst,int &reqs_processed) "completed.\n", tid, inst->seqNum, cpu->resPool->name(res_num)); - inst->popSchedEntry(); - reqs_processed++; req->stagePasses++; + + bool done_in_pipeline = inst->finishSkedEntry(); + if (done_in_pipeline) { + DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] finished " + "in pipeline.\n", tid, inst->seqNum); + break; + } } else { DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s failed." "\n", tid, inst->seqNum, cpu->resPool->name(res_num)); @@ -982,7 +987,7 @@ PipelineStage::processInstSchedule(DynInstPtr inst,int &reqs_processed) // Activate Next Ready Thread at end of cycle DPRINTF(ThreadModel, "Attempting to activate next ready " "thread due to cache miss.\n"); - cpu->activateNextReadyContext(); + cpu->activateNextReadyContext(); } // Mark request for deletion diff --git a/src/cpu/inorder/pipeline_traits.cc b/src/cpu/inorder/pipeline_traits.cc deleted file mode 100644 index a6fad68f7..000000000 --- a/src/cpu/inorder/pipeline_traits.cc +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - * - */ - -#include "cpu/inorder/pipeline_traits.hh" -#include "cpu/inorder/inorder_dyn_inst.hh" -#include "cpu/inorder/resources/resource_list.hh" - -using namespace std; - -namespace ThePipeline { - -//@TODO: create my own Instruction Schedule Class -//that operates as a Priority QUEUE -int getNextPriority(DynInstPtr &inst, int stage_num) -{ - int cur_pri = 20; - - /* - std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>, - entryCompare>::iterator sked_it = inst->resSched.begin(); - - std::priority_queue<ScheduleEntry*, std::vector<ScheduleEntry*>, - entryCompare>::iterator sked_end = inst->resSched.end(); - - while (sked_it != sked_end) { - - if (sked_it.top()->stageNum == stage_num) { - cur_pri = sked_it.top()->priority; - } - - sked_it++; - } - */ - - return cur_pri; -} - -void createFrontEndSchedule(DynInstPtr &inst) -{ - InstStage *F = inst->addStage(); - InstStage *D = inst->addStage(); - - // FETCH - F->needs(FetchSeq, FetchSeqUnit::AssignNextPC); - F->needs(ICache, FetchUnit::InitiateFetch); - - // DECODE - D->needs(ICache, FetchUnit::CompleteFetch); - D->needs(Decode, DecodeUnit::DecodeInst); - D->needs(BPred, BranchPredictor::PredictBranch); - D->needs(FetchSeq, FetchSeqUnit::UpdateTargetPC); - - inst->resSched.init(); -} - -bool createBackEndSchedule(DynInstPtr &inst) -{ - if (!inst->staticInst) { - return false; - } - - InstStage *X = inst->addStage(); - InstStage *M = inst->addStage(); - InstStage *W = inst->addStage(); - - // EXECUTE - for (int idx=0; idx < inst->numSrcRegs(); idx++) { - if (!idx || !inst->isStore()) { - X->needs(RegManager, UseDefUnit::ReadSrcReg, idx); - } - } - - if ( inst->isNonSpeculative() ) { - // skip execution of non speculative insts until later - } else if ( inst->isMemRef() ) { - if ( inst->isLoad() ) { - X->needs(AGEN, AGENUnit::GenerateAddr); - } - } else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) { - X->needs(MDU, MultDivUnit::StartMultDiv); - } else { - X->needs(ExecUnit, ExecutionUnit::ExecuteInst); - } - - if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) { - X->needs(MDU, MultDivUnit::EndMultDiv); - } - - // MEMORY - if ( inst->isLoad() ) { - M->needs(DCache, CacheUnit::InitiateReadData); - } else if ( inst->isStore() ) { - if ( inst->numSrcRegs() >= 2 ) { - M->needs(RegManager, UseDefUnit::ReadSrcReg, 1); - } - M->needs(AGEN, AGENUnit::GenerateAddr); - M->needs(DCache, CacheUnit::InitiateWriteData); - } - - - // WRITEBACK - if ( inst->isLoad() ) { - W->needs(DCache, CacheUnit::CompleteReadData); - } else if ( inst->isStore() ) { - W->needs(DCache, CacheUnit::CompleteWriteData); - } - - if ( inst->isNonSpeculative() ) { - if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction"); - W->needs(ExecUnit, ExecutionUnit::ExecuteInst); - } - - for (int idx=0; idx < inst->numDestRegs(); idx++) { - W->needs(RegManager, UseDefUnit::WriteDestReg, idx); - } - - W->needs(Grad, GraduationUnit::GraduateInst); - - return true; -} - -InstStage::InstStage(DynInstPtr inst, int stage_num) -{ - stageNum = stage_num; - nextTaskPriority = 0; - instSched = &inst->resSched; -} - -void -InstStage::needs(int unit, int request) { - instSched->push( new ScheduleEntry( - stageNum, nextTaskPriority++, unit, request - )); -} - -void -InstStage::needs(int unit, int request, int param) { - instSched->push( new ScheduleEntry( - stageNum, nextTaskPriority++, unit, request, param - )); -} - -}; diff --git a/src/cpu/inorder/pipeline_traits.hh b/src/cpu/inorder/pipeline_traits.hh index df964e254..75f01adb1 100644 --- a/src/cpu/inorder/pipeline_traits.hh +++ b/src/cpu/inorder/pipeline_traits.hh @@ -77,23 +77,7 @@ namespace ThePipeline { // RESOURCE SCHEDULING ////////////////////////// typedef ResourceSked ResSchedule; - - void createFrontEndSchedule(DynInstPtr &inst); - bool createBackEndSchedule(DynInstPtr &inst); - int getNextPriority(DynInstPtr &inst, int stage_num); - - class InstStage { - private: - int nextTaskPriority; - int stageNum; - ResSchedule *instSched; - - public: - InstStage(DynInstPtr inst, int stage_num); - - void needs(int unit, int request); - void needs(int unit, int request, int param); - }; + typedef ResourceSked* RSkedPtr; }; diff --git a/src/cpu/inorder/resource.cc b/src/cpu/inorder/resource.cc index 51beb5aa0..72b45dda8 100644 --- a/src/cpu/inorder/resource.cc +++ b/src/cpu/inorder/resource.cc @@ -184,8 +184,8 @@ Resource::request(DynInstPtr inst) if (slot_num != -1) { // Get Stage # from Schedule Entry - stage_num = inst->resSched.top()->stageNum; - unsigned cmd = inst->resSched.top()->cmd; + stage_num = inst->curSkedEntry->stageNum; + unsigned cmd = inst->curSkedEntry->cmd; // Generate Resource Request inst_req = getRequest(inst, stage_num, id, slot_num, cmd); diff --git a/src/cpu/inorder/resource_pool.cc b/src/cpu/inorder/resource_pool.cc index a037cbe9e..e1914623a 100644 --- a/src/cpu/inorder/resource_pool.cc +++ b/src/cpu/inorder/resource_pool.cc @@ -91,6 +91,7 @@ ResourcePool::ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params) resources.push_back(new InstBuffer("Fetch-Buffer-T1", FetchBuff2, 4, 0, _cpu, params)); + } ResourcePool::~ResourcePool() @@ -122,6 +123,16 @@ ResourcePool::name() return cpu->name() + ".ResourcePool"; } +void +ResourcePool::print() +{ + for (int i=0; i < resources.size(); i++) { + DPRINTF(InOrderDynInst, "Res:%i %s\n", + i, resources[i]->name()); + } + +} + void ResourcePool::regStats() diff --git a/src/cpu/inorder/resource_pool.hh b/src/cpu/inorder/resource_pool.hh index e8061d3ff..fde38b4e9 100644 --- a/src/cpu/inorder/resource_pool.hh +++ b/src/cpu/inorder/resource_pool.hh @@ -130,6 +130,8 @@ class ResourcePool { void init(); + void print(); + /** Register Statistics in All Resources */ void regStats(); diff --git a/src/cpu/inorder/resource_sked.cc b/src/cpu/inorder/resource_sked.cc index 4104e6989..4cf791228 100644 --- a/src/cpu/inorder/resource_sked.cc +++ b/src/cpu/inorder/resource_sked.cc @@ -34,30 +34,30 @@ #include <vector> #include <list> -#include <stdio.h> +#include <cstdio> using namespace std; using namespace ThePipeline; ResourceSked::ResourceSked() { - sked.resize(NumStages); + stages.resize(NumStages); } void ResourceSked::init() { - assert(!sked[0].empty()); + assert(!stages[0].empty()); - curSkedEntry = sked[0].begin(); + curSkedEntry = stages[0].begin(); } int ResourceSked::size() { int total = 0; - for (int i = 0; i < sked.size(); i++) { - total += sked[i].size(); + for (int i = 0; i < stages.size(); i++) { + total += stages[i].size(); } return total; @@ -69,6 +69,26 @@ ResourceSked::empty() return size() == 0; } + +ResourceSked::SkedIt +ResourceSked::begin() +{ + int num_stages = stages.size(); + for (int i = 0; i < num_stages; i++) { + if (stages[i].size() > 0) + return stages[i].begin(); + } + + return stages[num_stages - 1].end(); +} + +ResourceSked::SkedIt +ResourceSked::end() +{ + int num_stages = stages.size(); + return stages[num_stages - 1].end(); +} + ScheduleEntry* ResourceSked::top() { @@ -82,18 +102,18 @@ ResourceSked::pop() { int stage_num = (*curSkedEntry)->stageNum; - sked[stage_num].erase(curSkedEntry); + stages[stage_num].erase(curSkedEntry); - if (!sked[stage_num].empty()) { - curSkedEntry = sked[stage_num].begin(); + if (!stages[stage_num].empty()) { + curSkedEntry = stages[stage_num].begin(); } else { int next_stage = stage_num + 1; while (next_stage < NumStages) { - if (sked[next_stage].empty()) { + if (stages[next_stage].empty()) { next_stage++; } else { - curSkedEntry = sked[next_stage].begin(); + curSkedEntry = stages[next_stage].begin(); break; } } @@ -108,7 +128,7 @@ ResourceSked::push(ScheduleEntry* sked_entry) SkedIt pri_iter = findIterByPriority(sked_entry, stage_num); - sked[stage_num].insert(pri_iter, sked_entry); + stages[stage_num].insert(pri_iter, sked_entry); } void @@ -122,23 +142,23 @@ ResourceSked::pushBefore(ScheduleEntry* sked_entry, int sked_cmd, SkedIt pri_iter = findIterByCommand(sked_entry, stage_num, sked_cmd, sked_cmd_idx); - assert(pri_iter != sked[stage_num].end() && + assert(pri_iter != stages[stage_num].end() && "Could not find command to insert in front of."); - sked[stage_num].insert(pri_iter, sked_entry); + stages[stage_num].insert(pri_iter, sked_entry); } ResourceSked::SkedIt ResourceSked::findIterByPriority(ScheduleEntry* sked_entry, int stage_num) { - if (sked[stage_num].empty()) { - return sked[stage_num].end(); + if (stages[stage_num].empty()) { + return stages[stage_num].end(); } int priority = sked_entry->priority; - SkedIt sked_it = sked[stage_num].begin(); - SkedIt sked_end = sked[stage_num].end(); + SkedIt sked_it = stages[stage_num].begin(); + SkedIt sked_end = stages[stage_num].end(); while (sked_it != sked_end) { if ((*sked_it)->priority > priority) @@ -154,12 +174,12 @@ ResourceSked::SkedIt ResourceSked::findIterByCommand(ScheduleEntry* sked_entry, int stage_num, int sked_cmd, int sked_cmd_idx) { - if (sked[stage_num].empty()) { - return sked[stage_num].end(); + if (stages[stage_num].empty()) { + return stages[stage_num].end(); } - SkedIt sked_it = sked[stage_num].begin(); - SkedIt sked_end = sked[stage_num].end(); + SkedIt sked_it = stages[stage_num].begin(); + SkedIt sked_end = stages[stage_num].end(); while (sked_it != sked_end) { if ((*sked_it)->cmd == sked_cmd && @@ -175,12 +195,16 @@ ResourceSked::findIterByCommand(ScheduleEntry* sked_entry, int stage_num, void ResourceSked::print() { - for (int i = 0; i < sked.size(); i++) { - cprintf("Stage %i\n====\n", i); - SkedIt sked_it = sked[i].begin(); - SkedIt sked_end = sked[i].end(); + for (int i = 0; i < stages.size(); i++) { + //ccprintf(cerr, "Stage %i\n====\n", i); + SkedIt sked_it = stages[i].begin(); + SkedIt sked_end = stages[i].end(); while (sked_it != sked_end) { - cprintf("\t res:%i cmd:%i idx:%i\n", (*sked_it)->resNum, (*sked_it)->cmd, (*sked_it)->idx); + DPRINTF(SkedCache, "\t stage:%i res:%i cmd:%i idx:%i\n", + (*sked_it)->stageNum, + (*sked_it)->resNum, + (*sked_it)->cmd, + (*sked_it)->idx); sked_it++; } } diff --git a/src/cpu/inorder/resource_sked.hh b/src/cpu/inorder/resource_sked.hh index 22e29d728..bd002e161 100644 --- a/src/cpu/inorder/resource_sked.hh +++ b/src/cpu/inorder/resource_sked.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 The Regents of The University of Michigan + * Copyright (c) 2010-2011 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,7 +34,19 @@ #include <vector> #include <list> +#include <cstdlib> +/** ScheduleEntry class represents a single function that an instruction + wants to do at any pipeline stage. For example, if an instruction + needs to be decoded and do a branch prediction all in one stage + then each of those tasks would need it's own ScheduleEntry. + + Each schedule entry corresponds to some resource that the instruction + wants to interact with. + + The file pipeline_traits.cc shows how a typical instruction schedule is + made up of these schedule entries. +*/ class ScheduleEntry { public: ScheduleEntry(int stage_num, int _priority, int res_num, int _cmd = 0, @@ -43,45 +55,225 @@ class ScheduleEntry { idx(_idx), priority(_priority) { } - // Stage number to perform this service. + /** Stage number to perform this service. */ int stageNum; - // Resource ID to access + /** Resource ID to access */ int resNum; - // See specific resource for meaning + /** See specific resource for meaning */ unsigned cmd; - // See specific resource for meaning + /** See specific resource for meaning */ unsigned idx; - // Some Resources May Need Priority + /** Some Resources May Need Priority */ int priority; }; +/** The ResourceSked maintains the complete schedule + for an instruction. That schedule includes what + resources an instruction wants to acquire at each + pipeline stage and is represented by a collection + of ScheduleEntry objects (described above) that + must be executed in-order. + + In every pipeline stage, the InOrder model will + process all entries on the resource schedule for + that stage and then send the instruction to the next + stage if and only if the instruction successfully + completed each ScheduleEntry. +*/ class ResourceSked { public: typedef std::list<ScheduleEntry*>::iterator SkedIt; + typedef std::vector<std::list<ScheduleEntry*> > StageList; ResourceSked(); + /** Initializee the current entry pointer to + pipeline stage 0 and the 1st schedule entry + */ void init(); + /** Goes through the remaining stages on the schedule + and sums all the remaining entries left to be + processed + */ int size(); + + /** Is the schedule empty? */ bool empty(); + + /** Beginning Entry of this schedule */ + SkedIt begin(); + + /** Ending Entry of this schedule */ + SkedIt end(); + + /** What is the next task for this instruction schedule? */ ScheduleEntry* top(); + + /** Top() Task is completed, remove it from schedule */ void pop(); + + /** Add To Schedule based on stage num and priority of + Schedule Entry + */ void push(ScheduleEntry* sked_entry); + + /** Add Schedule Entry to be in front of another Entry */ void pushBefore(ScheduleEntry* sked_entry, int sked_cmd, int sked_cmd_idx); + + /** Print what's left on the instruction schedule */ void print(); + StageList *getStages() + { + return &stages; + } + private: + /** Current Schedule Entry Pointer */ SkedIt curSkedEntry; - std::vector<std::list<ScheduleEntry*> > sked; + /** The Stage-by-Stage Resource Schedule: + Resized to Number of Stages in the constructor + */ + StageList stages; + + /** Find a place to insert the instruction using the + schedule entries priority + */ SkedIt findIterByPriority(ScheduleEntry *sked_entry, int stage_num); + + /** Find a place to insert the instruction using a particular command + to look for. + */ SkedIt findIterByCommand(ScheduleEntry *sked_entry, int stage_num, int sked_cmd, int sked_cmd_idx = -1); }; +/** Wrapper class around the SkedIt iterator in the Resource Sked so that + we can use ++ operator to automatically go to the next available + resource schedule entry but otherwise maintain same functionality + as a normal iterator. +*/ +class RSkedIt +{ + public: + RSkedIt() + : curStage(0), numStages(0) + { } + + + /** init() must be called before the use of any other member + in the RSkedIt class. + */ + void init(ResourceSked* rsked) + { + stages = rsked->getStages(); + numStages = stages->size(); + } + + /* Update the encapsulated "myIt" iterator, but only + update curStage/curStage_end if the iterator is valid. + The iterator could be invalid in the case where + someone is saving the end of a list (i.e. std::list->end()) + */ + RSkedIt operator=(ResourceSked::SkedIt const &rhs) + { + myIt = rhs; + if (myIt != (*stages)[numStages-1].end()) { + curStage = (*myIt)->stageNum; + curStage_end = (*stages)[curStage].end(); + } + return *this; + } + + /** Increment to the next entry in current stage. + If no more entries then find the next stage that has + resource schedule to complete. + If no more stages, then return the end() iterator from + the last stage to indicate we are done. + */ + RSkedIt &operator++(int unused) + { + if (++myIt == curStage_end) { + curStage++; + while (curStage < numStages) { + if ((*stages)[curStage].empty()) { + curStage++; + } else { + myIt = (*stages)[curStage].begin(); + curStage_end = (*stages)[curStage].end(); + return *this; + } + } + + myIt = (*stages)[numStages - 1].end(); + } + + return *this; + } + + /** The "pointer" operator can be used on a RSkedIt and it + will use the encapsulated iterator + */ + ScheduleEntry* operator->() + { + return *myIt; + } + + /** Dereferencing a RSKedIt will access the encapsulated + iterator + */ + ScheduleEntry* operator*() + { + return *myIt; + } + + /** Equality for RSkedIt only compares the "myIt" iterators, + as the other members are just ancillary + */ + bool operator==(RSkedIt const &rhs) + { + return this->myIt == rhs.myIt; + } + + /** Inequality for RSkedIt only compares the "myIt" iterators, + as the other members are just ancillary + */ + bool operator!=(RSkedIt const &rhs) + { + return this->myIt != rhs.myIt; + } + + /* The == and != operator overloads should be sufficient + here if need otherwise direct access to the schedule + iterator, then this can be used */ + ResourceSked::SkedIt getIt() + { + return myIt; + } + + private: + /** Schedule Iterator that this class is encapsulating */ + ResourceSked::SkedIt myIt; + + /** Ptr to resource schedule that the 'myIt' iterator + belongs to + */ + ResourceSked::StageList *stages; + + /** The last iterator in the current stage. */ + ResourceSked::SkedIt curStage_end; + + /** Current Stage that "myIt" refers to. */ + int curStage; + + /** Number of stages in the "*stages" object. */ + int numStages; +}; + #endif //__CPU_INORDER_RESOURCE_SKED_HH__ diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 8b4dd4402..8cd105493 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -260,7 +260,7 @@ CacheUnit::findRequest(DynInstPtr inst) if (cache_req && cache_req->getInst() == inst && - cache_req->instIdx == inst->resSched.top()->idx) { + cache_req->instIdx == inst->curSkedEntry->idx) { return cache_req; } map_it++; @@ -296,7 +296,7 @@ ResReqPtr CacheUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, int slot_num, unsigned cmd) { - ScheduleEntry* sched_entry = inst->resSched.top(); + ScheduleEntry* sched_entry = *inst->curSkedEntry; if (!inst->validMemAddr()) { panic("Mem. Addr. must be set before requesting cache access\n"); @@ -346,7 +346,7 @@ CacheUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, return new CacheRequest(this, inst, stage_num, id, slot_num, sched_entry->cmd, 0, pkt_cmd, 0/*flags*/, this->cpu->readCpuId(), - inst->resSched.top()->idx); + inst->curSkedEntry->idx); } void @@ -357,17 +357,17 @@ CacheUnit::requestAgain(DynInstPtr inst, bool &service_request) // Check to see if this instruction is requesting the same command // or a different one - if (cache_req->cmd != inst->resSched.top()->cmd && - cache_req->instIdx == inst->resSched.top()->idx) { + if (cache_req->cmd != inst->curSkedEntry->cmd && + cache_req->instIdx == inst->curSkedEntry->idx) { // If different, then update command in the request - cache_req->cmd = inst->resSched.top()->cmd; + cache_req->cmd = inst->curSkedEntry->cmd; DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: Updating the command for this " "instruction\n ", inst->readTid(), inst->seqNum); service_request = true; - } else if (inst->resSched.top()->idx != CacheUnit::InitSecondSplitRead && - inst->resSched.top()->idx != CacheUnit::InitSecondSplitWrite) { + } else if (inst->curSkedEntry->idx != CacheUnit::InitSecondSplitRead && + inst->curSkedEntry->idx != CacheUnit::InitSecondSplitWrite) { // If same command, just check to see if memory access was completed // but dont try to re-execute DPRINTF(InOrderCachePort, @@ -487,14 +487,20 @@ CacheUnit::read(DynInstPtr inst, Addr addr, inst->splitMemData = new uint8_t[size]; if (!inst->splitInstSked) { + assert(0 && "Split Requests Not Supported for Now..."); + // Schedule Split Read/Complete for Instruction // ============================== int stage_num = cache_req->getStageNum(); - - int stage_pri = ThePipeline::getNextPriority(inst, stage_num); + RSkedPtr inst_sked = (stage_num >= ThePipeline::BackEndStartStage) ? + inst->backSked : inst->frontSked; + + // this is just an arbitrarily high priority to ensure that this + // gets pushed to the back of the list + int stage_pri = 20; int isplit_cmd = CacheUnit::InitSecondSplitRead; - inst->resSched.push(new + inst_sked->push(new ScheduleEntry(stage_num, stage_pri, cpu->resPool->getResIdx(DCache), @@ -502,7 +508,7 @@ CacheUnit::read(DynInstPtr inst, Addr addr, 1)); int csplit_cmd = CacheUnit::CompleteSecondSplitRead; - inst->resSched.push(new + inst_sked->push(new ScheduleEntry(stage_num + 1, 1/*stage_pri*/, cpu->resPool->getResIdx(DCache), @@ -590,27 +596,33 @@ CacheUnit::write(DynInstPtr inst, uint8_t *data, unsigned size, inst->splitInst = true; if (!inst->splitInstSked) { + assert(0 && "Split Requests Not Supported for Now..."); + // Schedule Split Read/Complete for Instruction // ============================== int stage_num = cache_req->getStageNum(); + RSkedPtr inst_sked = (stage_num >= ThePipeline::BackEndStartStage) ? + inst->backSked : inst->frontSked; - int stage_pri = ThePipeline::getNextPriority(inst, stage_num); + // this is just an arbitrarily high priority to ensure that this + // gets pushed to the back of the list + int stage_pri = 20; int isplit_cmd = CacheUnit::InitSecondSplitWrite; - inst->resSched.push(new - ScheduleEntry(stage_num, - stage_pri, - cpu->resPool->getResIdx(DCache), - isplit_cmd, - 1)); + inst_sked->push(new + ScheduleEntry(stage_num, + stage_pri, + cpu->resPool->getResIdx(DCache), + isplit_cmd, + 1)); int csplit_cmd = CacheUnit::CompleteSecondSplitWrite; - inst->resSched.push(new - ScheduleEntry(stage_num + 1, - 1/*stage_pri*/, - cpu->resPool->getResIdx(DCache), - csplit_cmd, - 1)); + inst_sked->push(new + ScheduleEntry(stage_num + 1, + 1/*stage_pri*/, + cpu->resPool->getResIdx(DCache), + csplit_cmd, + 1)); inst->splitInstSked = true; } else { DPRINTF(InOrderCachePort, "[tid:%i] sn:%i] Retrying Split Read " diff --git a/src/cpu/inorder/resources/decode_unit.cc b/src/cpu/inorder/resources/decode_unit.cc index c2f7ae22d..42857c783 100644 --- a/src/cpu/inorder/resources/decode_unit.cc +++ b/src/cpu/inorder/resources/decode_unit.cc @@ -57,13 +57,16 @@ DecodeUnit::execute(int slot_num) { case DecodeInst: { - bool done_sked = ThePipeline::createBackEndSchedule(inst); + inst->setBackSked(cpu->createBackEndSked(inst)); - if (done_sked) { + if (inst->backSked != NULL) { DPRINTF(InOrderDecode, "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n", tid, inst->seqNum); regDepMap[tid]->insert(inst); + + //inst->printSked(); + decode_req->done(); } else { DPRINTF(Resource, diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc index 0e9866708..0a5483aff 100644 --- a/src/cpu/inorder/resources/fetch_unit.cc +++ b/src/cpu/inorder/resources/fetch_unit.cc @@ -118,7 +118,7 @@ ResReqPtr FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, int slot_num, unsigned cmd) { - ScheduleEntry* sched_entry = inst->resSched.top(); + ScheduleEntry* sched_entry = *inst->curSkedEntry; if (!inst->validMemAddr()) { panic("Mem. Addr. must be set before requesting cache access\n"); @@ -144,7 +144,7 @@ FetchUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, return new CacheRequest(this, inst, stage_num, id, slot_num, sched_entry->cmd, 0, pkt_cmd, 0/*flags*/, this->cpu->readCpuId(), - inst->resSched.top()->idx); + inst->curSkedEntry->idx); } void @@ -447,7 +447,7 @@ FetchUnit::processCacheCompletion(PacketPtr pkt) short asid = cpu->asid[tid]; assert(!cache_req->isSquashed()); - assert(inst->resSched.top()->cmd == CompleteFetch); + assert(inst->curSkedEntry->cmd == CompleteFetch); DPRINTF(InOrderCachePort, "[tid:%u]: [sn:%i]: Processing fetch access for block %#x\n", diff --git a/src/cpu/inorder/resources/graduation_unit.cc b/src/cpu/inorder/resources/graduation_unit.cc index 8ccdaa36a..362641b54 100644 --- a/src/cpu/inorder/resources/graduation_unit.cc +++ b/src/cpu/inorder/resources/graduation_unit.cc @@ -52,14 +52,15 @@ GraduationUnit::execute(int slot_num) ResourceRequest* grad_req = reqMap[slot_num]; DynInstPtr inst = reqMap[slot_num]->inst; ThreadID tid = inst->readTid(); - int stage_num = inst->resSched.top()->stageNum; + int stage_num = inst->curSkedEntry->stageNum; switch (grad_req->cmd) { case GraduateInst: { // Make sure this is the last thing on the resource schedule - assert(inst->resSched.size() == 1); + // @todo: replace this check + // assert(inst->resSched.size() == 1); // Handle Any Faults Before Graduating Instruction if (inst->fault != NoFault) { diff --git a/src/cpu/inorder/resources/inst_buffer.cc b/src/cpu/inorder/resources/inst_buffer.cc index 18dd26a78..988fcd4da 100644 --- a/src/cpu/inorder/resources/inst_buffer.cc +++ b/src/cpu/inorder/resources/inst_buffer.cc @@ -99,19 +99,22 @@ InstBuffer::execute(int slot_idx) inst->seqNum, next_stage); // Add to schedule: Insert into buffer in next stage - int stage_pri = ThePipeline::getNextPriority(inst, - next_stage); + int stage_pri = 20; + RSkedPtr insert_sked = (stage_num >= ThePipeline::BackEndStartStage) ? + inst->backSked : inst->frontSked; - inst->resSched.push(new ScheduleEntry(next_stage, + insert_sked->push(new ScheduleEntry(next_stage, stage_pri, id, InstBuffer::InsertInst)); // Add to schedule: Remove from buffer in next next (bypass) // stage - stage_pri = ThePipeline::getNextPriority(inst, bypass_stage); + stage_pri = 20; + RSkedPtr bypass_sked = (stage_num >= ThePipeline::BackEndStartStage) ? + inst->backSked : inst->frontSked; - inst->resSched.push(new ScheduleEntry(bypass_stage, + bypass_sked->push(new ScheduleEntry(bypass_stage, stage_pri, id, InstBuffer::RemoveInst)); diff --git a/src/cpu/inorder/resources/inst_buffer_new.cc b/src/cpu/inorder/resources/inst_buffer_new.cc deleted file mode 100644 index 2e5a9666a..000000000 --- a/src/cpu/inorder/resources/inst_buffer_new.cc +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - * - */ - -#include <vector> -#include <list> - -#include "arch/isa_traits.hh" -#include "config/the_isa.hh" -#include "cpu/inorder/pipeline_traits.hh" -#include "cpu/inorder/resources/inst_buffer.hh" -#include "cpu/inorder/cpu.hh" - -using namespace std; -using namespace TheISA; -using namespace ThePipeline; - -InstBuffer::InstBuffer(string res_name, int res_id, int res_width, - int res_latency, InOrderCPU *_cpu) - : Resource(res_name, res_id, res_width, res_latency, _cpu) -{ } - -ResReqPtr -InstBuffer::getRequest(DynInstPtr inst, int stage_num, int res_idx, - int slot_num) -{ - // After this is working, change this to a reinterpret cast - // for performance considerations - InstBufferEntry* ib_entry = dynamic_cast<InstBufferEntry*>(inst->resSched.top()); - assert(ib_entry); - - return new InstBufferRequest(this, inst, stage_num, id, slot_num, - ib_entry->cmd); -} - -void -InstBuffer::execute(int slot_idx) -{ - // After this is working, change this to a reinterpret cast - // for performance considerations - InstBufferRequest* ib_req = dynamic_cast<InstBufferRequest*>(reqMap[slot_idx]); - assert(ib_req); - - DynInstPtr inst = ib_req->inst; - ThreadID tid = inst->readTid(); - int seq_num = inst->seqNum; - ib_req->fault = NoFault; - - switch (ib_req->cmd) - { - case InsertInst: - { - DPRINTF(Resource, "[tid:%i]: Inserting [sn:%i] into buffer.\n", - tid, seq_num); - insert(inst); - ib_req->done(); - } - break; - - case RemoveInst: - { - DPRINTF(Resource, "[tid:%i]: Removing [sn:%i] from buffer.\n", - tid, seq_num); - remove(inst); - ib_req->done(); - } - break; - - default: - fatal("Unrecognized command to %s", resName); - } - - DPRINTF(Resource, "Buffer now contains %i insts.\n", instList.size()); -} - -void -InstBuffer::insert(DynInstPtr inst) -{ - instList.push_back(inst); -} - -void -InstBuffer::remove(DynInstPtr inst) -{ - std::list<DynInstPtr>::iterator list_it = instList.begin(); - std::list<DynInstPtr>::iterator list_end = instList.end(); - - while (list_it != list_end) { - if((*list_it) == inst) { - instList.erase(list_it); - break; - } - list_it++; - } -} - -void -InstBuffer::pop() -{ instList.pop_front(); } - -ThePipeline::DynInstPtr -InstBuffer::top() -{ return instList.front(); } - -void -InstBuffer::squash(InstSeqNum squash_seq_num, ThreadID tid) -{ - list<DynInstPtr>::iterator list_it = instList.begin(); - list<DynInstPtr>::iterator list_end = instList.end(); - queue<list<DynInstPtr>::iterator> remove_list; - - // Collect All Instructions to be Removed in Remove List - while (list_it != list_end) { - if((*list_it)->seqNum > squash_seq_num) { - DPRINTF(Resource, "[tid:%i]: Squashing [sn:%i] in resource.\n", - tid, (*list_it)->seqNum); - (*list_it)->setSquashed(); - remove_list.push(list_it); - } - - list_it++; - } - - // Removed Instructions from InstList & Clear Remove List - while (!remove_list.empty()) { - instList.erase(remove_list.front()); - remove_list.pop(); - } - - Resource::squash(squash_seq_num, tid); -} diff --git a/src/cpu/inorder/resources/inst_buffer_new.hh b/src/cpu/inorder/resources/inst_buffer_new.hh deleted file mode 100644 index b1d5a7b09..000000000 --- a/src/cpu/inorder/resources/inst_buffer_new.hh +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2007 MIPS Technologies, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - * - */ - -#ifndef __CPU_INORDER_INST_BUFF_UNIT_HH__ -#define __CPU_INORDER_INST_BUFF_UNIT_HH__ - -#include <vector> -#include <list> -#include <string> - -#include "cpu/inorder/resource.hh" -#include "cpu/inorder/inorder_dyn_inst.hh" -#include "cpu/inorder/pipeline_traits.hh" -#include "cpu/inorder/cpu.hh" - -class InstBuffer : public Resource { - public: - typedef InOrderDynInst::DynInstPtr DynInstPtr; - - public: - enum Command { - InsertInst, - InsertAddr, - RemoveInst, - RemoveAddr - }; - - public: - InstBuffer(std::string res_name, int res_id, int res_width, - int res_latency, InOrderCPU *_cpu); - virtual ~InstBuffer() {} - - virtual ResourceRequest* getRequest(DynInstPtr _inst, int stage_num, - int res_idx, int slot_num); - - virtual void execute(int slot_num); - - virtual void insert(DynInstPtr inst); - - virtual void remove(DynInstPtr inst); - - virtual void pop(); - - virtual DynInstPtr top(); - - virtual void squash(InstSeqNum squash_seq_num, ThreadID tid); - - protected: - /** List of instructions this resource is currently - * processing. - */ - std::list<DynInstPtr> instList; - - /** @todo: Add Resource Stats Here */ - -}; - -struct InstBufferEntry : public ThePipeline::ScheduleEntry { - InstBufferEntry(int stage_num, int res_num, InstBuffer::Command _cmd) : - ScheduleEntry(stage_num, res_num), cmd(_cmd) - { } - - InstBuffer::Command cmd; -}; - -class InstBufferRequest : public ResourceRequest { - public: - typedef InOrderDynInst::DynInstPtr DynInstPtr; - - public: - InstBufferRequest(InstBuffer *res, DynInstPtr inst, int stage_num, int res_idx, int slot_num, - InstBuffer::Command _cmd) - : ResourceRequest(res, inst, stage_num, res_idx, slot_num), - cmd(_cmd) - { } - - InstBuffer::Command cmd; -}; - - -#endif //__CPU_INORDER_INST_BUFF_UNIT_HH__ diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc index 5aa0b0aa1..042fb590b 100644 --- a/src/cpu/inorder/resources/mult_div_unit.cc +++ b/src/cpu/inorder/resources/mult_div_unit.cc @@ -110,9 +110,9 @@ MultDivUnit::requestAgain(DynInstPtr inst, bool &service_request) // Check to see if this instruction is requesting the same command // or a different one - if (mult_div_req->cmd != inst->resSched.top()->cmd) { + if (mult_div_req->cmd != inst->curSkedEntry->cmd) { // If different, then update command in the request - mult_div_req->cmd = inst->resSched.top()->cmd; + mult_div_req->cmd = inst->curSkedEntry->cmd; DPRINTF(InOrderMDU, "[tid:%i]: [sn:%i]: Updating the command for this " "instruction\n", inst->readTid(), inst->seqNum); @@ -132,7 +132,7 @@ MultDivUnit::getSlot(DynInstPtr inst) // If we have this instruction's request already then return if (slot_num != -1 && - inst->resSched.top()->cmd == reqMap[slot_num]->cmd) + inst->curSkedEntry->cmd == reqMap[slot_num]->cmd) return slot_num; unsigned repeat_rate = 0; diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc index 59840d15b..2e19ea928 100644 --- a/src/cpu/inorder/resources/tlb_unit.cc +++ b/src/cpu/inorder/resources/tlb_unit.cc @@ -217,7 +217,7 @@ TLBUnitEvent::process() // Effectively NOP the instruction but still allow it // to commit //while (!inst->resSched.empty() && - // inst->resSched.top()->stageNum != ThePipeline::NumStages - 1) { + // inst->curSkedEntry->stageNum != ThePipeline::NumStages - 1) { //inst->resSched.pop(); //} } diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc index 743011573..538b20246 100644 --- a/src/cpu/inorder/resources/use_def.cc +++ b/src/cpu/inorder/resources/use_def.cc @@ -93,7 +93,7 @@ UseDefUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx, int slot_num, unsigned cmd) { return new UseDefRequest(this, inst, stage_num, id, slot_num, cmd, - inst->resSched.top()->idx); + inst->curSkedEntry->idx); } @@ -110,8 +110,8 @@ UseDefUnit::findRequest(DynInstPtr inst) if (ud_req && ud_req->getInst() == inst && - ud_req->cmd == inst->resSched.top()->cmd && - ud_req->useDefIdx == inst->resSched.top()->idx) { + ud_req->cmd == inst->curSkedEntry->cmd && + ud_req->useDefIdx == inst->curSkedEntry->idx) { return ud_req; } map_it++; diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 92691720b..647c48a76 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -137,6 +137,10 @@ class DefaultFetch {} void + markDelayed() + {} + + void finish(Fault fault, RequestPtr req, ThreadContext *tc, BaseTLB::Mode mode) { diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index d0c83d586..d2cde496e 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -604,6 +604,9 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) ThreadID tid = mem_req->threadId(); Addr block_PC = mem_req->getVaddr(); + // Wake up CPU if it was idle + cpu->wakeCPU(); + // If translation was successful, attempt to read the icache block. if (fault == NoFault) { // Build packet here. @@ -654,6 +657,9 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req) instruction->fault = fault; wroteToTimeBuffer = true; + DPRINTF(Activity, "Activity this cycle.\n"); + cpu->activityThisCycle(); + fetchStatus[tid] = TrapPending; DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid); @@ -1064,6 +1070,8 @@ DefaultFetch<Impl>::fetch(bool &status_change) Addr pcOffset = fetchOffset[tid]; Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; + bool inRom = isRomMicroPC(thisPC.microPC()); + // If returning from the delay of a cache miss, then update the status // to running, otherwise do the cache access. Possibly move this up // to tick() function. @@ -1077,7 +1085,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) Addr block_PC = icacheBlockAlignPC(fetchAddr); // Unless buffer already got the block, fetch it from icache. - if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid]) { + if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) { DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read " "instruction, starting at PC %s.\n", tid, thisPC); @@ -1149,7 +1157,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) !predictedBranch) { // If we need to process more memory, do it now. - if (!curMacroop && !predecoder.extMachInstReady()) { + if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) { if (ISA_HAS_DELAY_SLOT && pcOffset == 0) { // Walk past any annulled delay slot instructions. Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask; @@ -1175,7 +1183,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) // Extract as many instructions and/or microops as we can from // the memory we've processed so far. do { - if (!curMacroop) { + if (!(curMacroop || inRom)) { if (predecoder.extMachInstReady()) { ExtMachInst extMachInst; @@ -1196,8 +1204,13 @@ DefaultFetch<Impl>::fetch(bool &status_change) break; } } - if (curMacroop) { - staticInst = curMacroop->fetchMicroop(thisPC.microPC()); + if (curMacroop || inRom) { + if (inRom) { + staticInst = cpu->microcodeRom.fetchMicroop( + thisPC.microPC(), curMacroop); + } else { + staticInst = curMacroop->fetchMicroop(thisPC.microPC()); + } if (staticInst->isLastMicroop()) { curMacroop = NULL; pcOffset = 0; diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 3f3761ff3..03f73c798 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -1241,12 +1241,33 @@ DefaultIEW<Impl>::executeInsts() // Loads will mark themselves as executed, and their writeback // event adds the instruction to the queue to commit fault = ldstQueue.executeLoad(inst); + + if (inst->isTranslationDelayed() && + fault == NoFault) { + // A hw page table walk is currently going on; the + // instruction must be deferred. + DPRINTF(IEW, "Execute: Delayed translation, deferring " + "load.\n"); + instQueue.deferMemInst(inst); + continue; + } + if (inst->isDataPrefetch() || inst->isInstPrefetch()) { fault = NoFault; } } else if (inst->isStore()) { fault = ldstQueue.executeStore(inst); + if (inst->isTranslationDelayed() && + fault == NoFault) { + // A hw page table walk is currently going on; the + // instruction must be deferred. + DPRINTF(IEW, "Execute: Delayed translation, deferring " + "store.\n"); + instQueue.deferMemInst(inst); + continue; + } + // If the store had a fault then it may not have a mem req if (fault != NoFault || inst->readPredicate() == false || !inst->isStoreConditional()) { diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh index be936e204..64df35743 100644 --- a/src/cpu/o3/inst_queue.hh +++ b/src/cpu/o3/inst_queue.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2004-2006 The Regents of The University of Michigan * All rights reserved. * @@ -180,6 +192,11 @@ class InstructionQueue */ DynInstPtr getInstToExecute(); + /** Returns a memory instruction that was referred due to a delayed DTB + * translation if it is now ready to execute. + */ + DynInstPtr getDeferredMemInstToExecute(); + /** * Records the instruction as the producer of a register without * adding it to the rest of the IQ. @@ -223,6 +240,12 @@ class InstructionQueue /** Completes a memory operation. */ void completeMemInst(DynInstPtr &completed_inst); + /** + * Defers a memory instruction when its DTB translation incurs a hw + * page table walk. + */ + void deferMemInst(DynInstPtr &deferred_inst); + /** Indicates an ordering violation between a store and a load. */ void violation(DynInstPtr &store, DynInstPtr &faulting_load); @@ -284,6 +307,11 @@ class InstructionQueue /** List of instructions that are ready to be executed. */ std::list<DynInstPtr> instsToExecute; + /** List of instructions waiting for their DTB translation to + * complete (hw page table walk in progress). + */ + std::list<DynInstPtr> deferredMemInsts; + /** * Struct for comparing entries to be added to the priority queue. * This gives reverse ordering to the instructions in terms of diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 91cb2f0c8..aa21a0edc 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2004-2006 The Regents of The University of Michigan * All rights reserved. * @@ -397,6 +409,7 @@ InstructionQueue<Impl>::resetState() } nonSpecInsts.clear(); listOrder.clear(); + deferredMemInsts.clear(); } template <class Impl> @@ -733,6 +746,15 @@ InstructionQueue<Impl>::scheduleReadyInsts() IssueStruct *i2e_info = issueToExecuteQueue->access(0); + DynInstPtr deferred_mem_inst; + int total_deferred_mem_issued = 0; + while (total_deferred_mem_issued < totalWidth && + (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { + issueToExecuteQueue->access(0)->size++; + instsToExecute.push_back(deferred_mem_inst); + total_deferred_mem_issued++; + } + // Have iterator to head of the list // While I haven't exceeded bandwidth or reached the end of the list, // Try to get a FU that can do what this op needs. @@ -745,7 +767,7 @@ InstructionQueue<Impl>::scheduleReadyInsts() ListOrderIt order_end_it = listOrder.end(); int total_issued = 0; - while (total_issued < totalWidth && + while (total_issued < (totalWidth - total_deferred_mem_issued) && iewStage->canIssue() && order_it != order_end_it) { OpClass op_class = (*order_it).queueType; @@ -858,7 +880,7 @@ InstructionQueue<Impl>::scheduleReadyInsts() iqInstsIssued+= total_issued; // If we issued any instructions, tell the CPU we had activity. - if (total_issued) { + if (total_issued || total_deferred_mem_issued) { cpu->activityThisCycle(); } else { DPRINTF(IQ, "Not able to schedule any instructions.\n"); @@ -1021,6 +1043,11 @@ void InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) { DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); + + // Reset DTB translation state + resched_inst->translationStarted = false; + resched_inst->translationCompleted = false; + resched_inst->clearCanIssue(); memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); } @@ -1051,6 +1078,28 @@ InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) template <class Impl> void +InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) +{ + deferredMemInsts.push_back(deferred_inst); +} + +template <class Impl> +typename Impl::DynInstPtr +InstructionQueue<Impl>::getDeferredMemInstToExecute() +{ + for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); + ++it) { + if ((*it)->translationCompleted) { + DynInstPtr ret = *it; + deferredMemInsts.erase(it); + return ret; + } + } + return NULL; +} + +template <class Impl> +void InstructionQueue<Impl>::violation(DynInstPtr &store, DynInstPtr &faulting_load) { diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index dd3604ffe..b5d337935 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -445,12 +445,16 @@ LSQUnit<Impl>::executeLoad(DynInstPtr &inst) Fault load_fault = NoFault; DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", - inst->pcState(),inst->seqNum); + inst->pcState(), inst->seqNum); assert(!inst->isSquashed()); load_fault = inst->initiateAcc(); + if (inst->isTranslationDelayed() && + load_fault == NoFault) + return load_fault; + // If the instruction faulted or predicated false, then we need to send it // along to commit without the instruction completing. if (load_fault != NoFault || inst->readPredicate() == false) { @@ -532,6 +536,10 @@ LSQUnit<Impl>::executeStore(DynInstPtr &store_inst) Fault store_fault = store_inst->initiateAcc(); + if (store_inst->isTranslationDelayed() && + store_fault == NoFault) + return store_fault; + if (store_inst->readPredicate() == false) store_inst->forwardOldRegs(); diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 453699f84..ab1ff91e8 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -752,6 +752,7 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc) } else { delete req; // fetch fault: advance directly to next instruction (fault handler) + _status = Running; advanceInst(fault); } @@ -805,12 +806,11 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) if (curStaticInst && curStaticInst->isMemRef()) { // load or store: just send to dcache Fault fault = curStaticInst->initiateAcc(this, traceData); - if (_status != Running) { - // instruction will complete in dcache response callback - assert(_status == DcacheWaitResponse || - _status == DcacheRetry || DTBWaitResponse); - assert(fault == NoFault); - } else { + + // If we're not running now the instruction will complete in a dcache + // response callback or the instruction faulted and has started an + // ifetch + if (_status == Running) { if (fault != NoFault && traceData) { // If there was a fault, we shouldn't trace this instruction. delete traceData; diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 2b0c8942a..a7a3eb7c3 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -108,6 +108,13 @@ class TimingSimpleCPU : public BaseSimpleCPU {} void + markDelayed() + { + assert(cpu->_status == Running); + cpu->_status = ITBWaitResponse; + } + + void finish(Fault fault, RequestPtr req, ThreadContext *tc, BaseTLB::Mode mode) { diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh index 7db7c381a..60953540f 100644 --- a/src/cpu/translation.hh +++ b/src/cpu/translation.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2002-2005 The Regents of The University of Michigan * Copyright (c) 2009 The University of Edinburgh * All rights reserved. @@ -53,6 +65,7 @@ class WholeTranslationState Fault faults[2]; public: + bool delay; bool isSplit; RequestPtr mainReq; RequestPtr sreqLow; @@ -67,8 +80,8 @@ class WholeTranslationState */ WholeTranslationState(RequestPtr _req, uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode) - : outstanding(1), isSplit(false), mainReq(_req), sreqLow(NULL), - sreqHigh(NULL), data(_data), res(_res), mode(_mode) + : outstanding(1), delay(false), isSplit(false), mainReq(_req), + sreqLow(NULL), sreqHigh(NULL), data(_data), res(_res), mode(_mode) { faults[0] = faults[1] = NoFault; assert(mode == BaseTLB::Read || mode == BaseTLB::Write); @@ -82,8 +95,9 @@ class WholeTranslationState WholeTranslationState(RequestPtr _req, RequestPtr _sreqLow, RequestPtr _sreqHigh, uint8_t *_data, uint64_t *_res, BaseTLB::Mode _mode) - : outstanding(2), isSplit(true), mainReq(_req), sreqLow(_sreqLow), - sreqHigh(_sreqHigh), data(_data), res(_res), mode(_mode) + : outstanding(2), delay(false), isSplit(true), mainReq(_req), + sreqLow(_sreqLow), sreqHigh(_sreqHigh), data(_data), res(_res), + mode(_mode) { faults[0] = faults[1] = NoFault; assert(mode == BaseTLB::Read || mode == BaseTLB::Write); @@ -221,6 +235,16 @@ class DataTranslation : public BaseTLB::Translation } /** + * Signal the translation state that the translation has been delayed due + * to a hw page table walk. Split requests are transparently handled. + */ + void + markDelayed() + { + state->delay = true; + } + + /** * Finish this part of the translation and indicate that the whole * translation is complete if the state says so. */ diff --git a/src/dev/SConscript b/src/dev/SConscript index 7cdea7961..5243da683 100644 --- a/src/dev/SConscript +++ b/src/dev/SConscript @@ -69,6 +69,7 @@ if env['FULL_SYSTEM']: Source('pcidev.cc') Source('pktfifo.cc') Source('platform.cc') + Source('ps2.cc') Source('simple_disk.cc') Source('sinic.cc') Source('terminal.cc') diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index cdc06e4ef..ef3f68a88 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -52,6 +52,14 @@ class AmbaDevice(BasicPioDevice): abstract = True amba_id = Param.UInt32("ID of AMBA device for kernel detection") +class AmbaIntDevice(AmbaDevice): + type = 'AmbaIntDevice' + abstract = True + gic = Param.Gic(Parent.any, "Gic to use for interrupting") + int_num = Param.UInt32("Interrupt number that connects to GIC") + int_delay = Param.Latency("100ns", + "Time between action and interrupt generation by device") + class AmbaDmaDevice(DmaDevice): type = 'AmbaDmaDevice' abstract = True @@ -94,16 +102,17 @@ class Sp804(AmbaDevice): clock1 = Param.Clock('1MHz', "Clock speed of the input") amba_id = 0x00141804 -class Pl050(AmbaDevice): +class Pl050(AmbaIntDevice): type = 'Pl050' - gic = Param.Gic(Parent.any, "Gic to use for interrupting") - int_num = Param.UInt32("Interrupt number that connects to GIC") - int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") + vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") + is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") + int_delay = '1us' amba_id = 0x00141050 class Pl111(AmbaDmaDevice): type = 'Pl111' clock = Param.Clock('24MHz', "Clock speed of the input") + vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") amba_id = 0x00141111 class RealView(Platform): @@ -121,7 +130,7 @@ class RealViewPBX(RealView): timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) clcd = Pl111(pio_addr=0x10020000, int_num=55) kmi0 = Pl050(pio_addr=0x10006000, int_num=52) - kmi1 = Pl050(pio_addr=0x10007000, int_num=53) + kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x4000000) @@ -140,7 +149,7 @@ class RealViewPBX(RealView): aaci_fake = AmbaFake(pio_addr=0x10004000) mmc_fake = AmbaFake(pio_addr=0x10005000) rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) - + cf0_fake = IsaFake(pio_addr=0x18000000, pio_size=0xfff) # Attach I/O devices that are on chip @@ -175,6 +184,7 @@ class RealViewPBX(RealView): self.mmc_fake.pio = bus.port self.rtc_fake.pio = bus.port self.flash_fake.pio = bus.port + self.cf0_fake.pio = bus.port # Reference for memory map and interrupt number # RealView Emulation Baseboard User Guide (ARM DUI 0143B) @@ -187,7 +197,7 @@ class RealViewEB(RealView): timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) clcd = Pl111(pio_addr=0x10020000, int_num=23) kmi0 = Pl050(pio_addr=0x10006000, int_num=20) - kmi1 = Pl050(pio_addr=0x10007000, int_num=21) + kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") dmac_fake = AmbaFake(pio_addr=0x10030000) diff --git a/src/dev/arm/amba_device.cc b/src/dev/arm/amba_device.cc index e5d53d6a3..37eb77ae1 100644 --- a/src/dev/arm/amba_device.cc +++ b/src/dev/arm/amba_device.cc @@ -47,11 +47,19 @@ #include "mem/packet_access.hh" const uint64_t AmbaVendor = ULL(0xb105f00d00000000); + AmbaDevice::AmbaDevice(const Params *p) : BasicPioDevice(p), ambaId(AmbaVendor | p->amba_id) { } +AmbaIntDevice::AmbaIntDevice(const Params *p) + : AmbaDevice(p), intNum(p->int_num), gic(p->gic), intDelay(p->int_delay) +{ +} + + + AmbaDmaDevice::AmbaDmaDevice(const Params *p) : DmaDevice(p), ambaId(AmbaVendor | p->amba_id), pioAddr(p->pio_addr), pioSize(0), diff --git a/src/dev/arm/amba_device.hh b/src/dev/arm/amba_device.hh index 1782fb003..297a78f82 100644 --- a/src/dev/arm/amba_device.hh +++ b/src/dev/arm/amba_device.hh @@ -55,6 +55,7 @@ #include "mem/packet.hh" #include "mem/packet_access.hh" #include "params/AmbaDevice.hh" +#include "params/AmbaIntDevice.hh" #include "params/AmbaDmaDevice.hh" namespace AmbaDev { @@ -81,6 +82,18 @@ class AmbaDevice : public BasicPioDevice AmbaDevice(const Params *p); }; +class AmbaIntDevice : public AmbaDevice +{ + protected: + int intNum; + Gic *gic; + Tick intDelay; + + public: + typedef AmbaIntDeviceParams Params; + AmbaIntDevice(const Params *p); +}; + class AmbaDmaDevice : public DmaDevice { protected: diff --git a/src/dev/arm/kmi.cc b/src/dev/arm/kmi.cc index 6cd61fd09..adf1439b3 100644 --- a/src/dev/arm/kmi.cc +++ b/src/dev/arm/kmi.cc @@ -37,21 +37,31 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: William Wang + * Authors: Ali Saidi + * William Wang */ #include "base/trace.hh" +#include "base/vnc/vncserver.hh" #include "dev/arm/amba_device.hh" #include "dev/arm/kmi.hh" +#include "dev/ps2.hh" #include "mem/packet.hh" #include "mem/packet_access.hh" Pl050::Pl050(const Params *p) - : AmbaDevice(p), control(0x00), status(0x43), kmidata(0x00), clkdiv(0x00), - intreg(0x00), intNum(p->int_num), gic(p->gic), intDelay(p->int_delay), - intEvent(this) + : AmbaIntDevice(p), control(0), status(0x43), clkdiv(0), interrupts(0), + rawInterrupts(0), ackNext(false), shiftDown(false), vnc(p->vnc), + driverInitialized(false), intEvent(this) { pioSize = 0xfff; + + if (vnc) { + if (!p->is_mouse) + vnc->setKeyboard(this); + else + vnc->setMouse(this); + } } Tick @@ -62,28 +72,39 @@ Pl050::read(PacketPtr pkt) Addr daddr = pkt->getAddr() - pioAddr; pkt->allocate(); - DPRINTF(Pl050, " read register %#x size=%d\n", daddr, pkt->getSize()); - // use a temporary data since the KMI registers are read/written with - // different size operations - // uint32_t data = 0; switch (daddr) { case kmiCr: + DPRINTF(Pl050, "Read Commmand: %#x\n", (uint32_t)control); data = control; break; case kmiStat: + if (rxQueue.empty()) + status.rxfull = 0; + else + status.rxfull = 1; + + DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status); data = status; break; case kmiData: - data = kmidata; + if (rxQueue.empty()) { + data = 0; + } else { + data = rxQueue.front(); + rxQueue.pop_front(); + } + DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data); + updateIntStatus(); break; case kmiClkDiv: data = clkdiv; break; case kmiISR: - data = intreg; + data = interrupts; + DPRINTF(Pl050, "Read Interrupts: %#x\n", (uint32_t)interrupts); break; default: if (AmbaDev::readId(pkt, ambaId, pioAddr)) { @@ -123,65 +144,224 @@ Pl050::write(PacketPtr pkt) Addr daddr = pkt->getAddr() - pioAddr; - DPRINTF(Pl050, " write register %#x value %#x size=%d\n", daddr, - pkt->get<uint8_t>(), pkt->getSize()); + assert(pkt->getSize() == sizeof(uint8_t)); - // use a temporary data since the KMI registers are read/written with - // different size operations - // - uint32_t data = 0; - switch (pkt->getSize()) { - case 1: - data = pkt->get<uint8_t>(); + switch (daddr) { + case kmiCr: + DPRINTF(Pl050, "Write Commmand: %#x\n", (uint32_t)pkt->get<uint8_t>()); + control = pkt->get<uint8_t>(); + updateIntStatus(); break; - case 2: - data = pkt->get<uint16_t>(); + case kmiData: + DPRINTF(Pl050, "Write Data: %#x\n", (uint32_t)pkt->get<uint8_t>()); + processCommand(pkt->get<uint8_t>()); + updateIntStatus(); break; - case 4: - data = pkt->get<uint32_t>(); + case kmiClkDiv: + clkdiv = pkt->get<uint8_t>(); break; default: - panic("KMI write size too big?\n"); + warn("Tried to write PL050 at offset %#x that doesn't exist\n", daddr); break; } + pkt->makeAtomicResponse(); + return pioDelay; +} +void +Pl050::processCommand(uint8_t byte) +{ + using namespace Ps2; - switch (daddr) { - case kmiCr: - control = data; + if (ackNext) { + ackNext--; + rxQueue.push_back(Ack); + updateIntStatus(); + return; + } + + switch (byte) { + case Ps2Reset: + rxQueue.push_back(Ack); + rxQueue.push_back(SelfTestPass); break; - case kmiStat: - panic("Tried to write PL050 register(read only) at offset %#x\n", - daddr); + case SetResolution: + case SetRate: + case SetStatusLed: + case SetScaling1_1: + case SetScaling1_2: + rxQueue.push_back(Ack); + ackNext = 1; break; - case kmiData: - kmidata = data; + case ReadId: + rxQueue.push_back(Ack); + if (params()->is_mouse) + rxQueue.push_back(MouseId); + else + rxQueue.push_back(KeyboardId); break; - case kmiClkDiv: - clkdiv = data; + case TpReadId: + if (!params()->is_mouse) + break; + // We're not a trackpoint device, this should make the probe go away + rxQueue.push_back(Ack); + rxQueue.push_back(0); + rxQueue.push_back(0); + // fall through + case Disable: + case Enable: + rxQueue.push_back(Ack); break; - case kmiISR: - panic("Tried to write PL050 register(read only) at offset %#x\n", - daddr); + case StatusRequest: + rxQueue.push_back(Ack); + rxQueue.push_back(0); + rxQueue.push_back(2); // default resolution + rxQueue.push_back(100); // default sample rate break; - default: - warn("Tried to write PL050 at offset %#x that doesn't exist\n", daddr); + case TouchKitId: + ackNext = 2; + rxQueue.push_back(Ack); + rxQueue.push_back(TouchKitId); + rxQueue.push_back(1); + rxQueue.push_back('A'); + + driverInitialized = true; break; + default: + panic("Unknown byte received: %d\n", byte); } - pkt->makeAtomicResponse(); - return pioDelay; + + updateIntStatus(); +} + + +void +Pl050::updateIntStatus() +{ + if (!rxQueue.empty()) + rawInterrupts.rx = 1; + else + rawInterrupts.rx = 0; + + interrupts.tx = rawInterrupts.tx & control.txint_enable; + interrupts.rx = rawInterrupts.rx & control.rxint_enable; + + DPRINTF(Pl050, "rawInterupts=%#x control=%#x interrupts=%#x\n", + (uint32_t)rawInterrupts, (uint32_t)control, (uint32_t)interrupts); + + if (interrupts && !intEvent.scheduled()) + schedule(intEvent, curTick() + intDelay); } void Pl050::generateInterrupt() { - if (intreg.rxintr || intreg.txintr) { + + if (interrupts) { gic->sendInt(intNum); - DPRINTF(Pl050, " -- Generated\n"); + DPRINTF(Pl050, "Generated interrupt\n"); } } +void +Pl050::mouseAt(uint16_t x, uint16_t y, uint8_t buttons) +{ + using namespace Ps2; + + // If the driver hasn't initialized the device yet, no need to try and send + // it anything. Similarly we can get vnc mouse events orders of maginture + // faster than m5 can process them. Only queue up two sets mouse movements + // and don't add more until those are processed. + if (!driverInitialized || rxQueue.size() > 10) + return; + + // We shouldn't be here unless a vnc server called us in which case + // we should have a pointer to it + assert(vnc); + + // Convert screen coordinates to touchpad coordinates + uint16_t _x = (2047.0/vnc->videoWidth()) * x; + uint16_t _y = (2047.0/vnc->videoHeight()) * y; + + rxQueue.push_back(buttons); + rxQueue.push_back(_x >> 7); + rxQueue.push_back(_x & 0x7f); + rxQueue.push_back(_y >> 7); + rxQueue.push_back(_y & 0x7f); + + updateIntStatus(); +} + + +void +Pl050::keyPress(uint32_t key, bool down) +{ + using namespace Ps2; + + std::list<uint8_t> keys; + + // convert the X11 keysym into ps2 codes + keySymToPs2(key, down, shiftDown, keys); + + // Insert into our queue of charecters + rxQueue.splice(rxQueue.end(), keys); + updateIntStatus(); +} + +void +Pl050::serialize(std::ostream &os) +{ + uint8_t ctrlreg = control; + SERIALIZE_SCALAR(ctrlreg); + + uint8_t stsreg = status; + SERIALIZE_SCALAR(stsreg); + SERIALIZE_SCALAR(clkdiv); + + uint8_t ints = interrupts; + SERIALIZE_SCALAR(ints); + + uint8_t raw_ints = rawInterrupts; + SERIALIZE_SCALAR(raw_ints); + + SERIALIZE_SCALAR(ackNext); + SERIALIZE_SCALAR(shiftDown); + SERIALIZE_SCALAR(driverInitialized); + + arrayParamOut(os, "rxQueue", rxQueue); +} + +void +Pl050::unserialize(Checkpoint *cp, const std::string §ion) +{ + uint8_t ctrlreg; + UNSERIALIZE_SCALAR(ctrlreg); + control = ctrlreg; + + uint8_t stsreg; + UNSERIALIZE_SCALAR(stsreg); + status = stsreg; + + UNSERIALIZE_SCALAR(clkdiv); + + uint8_t ints; + UNSERIALIZE_SCALAR(ints); + interrupts = ints; + + uint8_t raw_ints; + UNSERIALIZE_SCALAR(raw_ints); + rawInterrupts = raw_ints; + + UNSERIALIZE_SCALAR(ackNext); + UNSERIALIZE_SCALAR(shiftDown); + UNSERIALIZE_SCALAR(driverInitialized); + + arrayParamIn(cp, section, "rxQueue", rxQueue); +} + + + Pl050 * Pl050Params::create() { diff --git a/src/dev/arm/kmi.hh b/src/dev/arm/kmi.hh index c96dd55a9..1e25f8974 100644 --- a/src/dev/arm/kmi.hh +++ b/src/dev/arm/kmi.hh @@ -48,13 +48,16 @@ #ifndef __DEV_ARM_PL050_HH__ #define __DEV_ARM_PL050_HH__ +#include <list> + #include "base/range.hh" -#include "dev/io_device.hh" +#include "base/vnc/vncserver.hh" +#include "dev/arm/amba_device.hh" #include "params/Pl050.hh" class Gic; -class Pl050 : public AmbaDevice +class Pl050 : public AmbaIntDevice, public VncKeyboard, public VncMouse { protected: static const int kmiCr = 0x000; @@ -63,34 +66,68 @@ class Pl050 : public AmbaDevice static const int kmiClkDiv = 0x00C; static const int kmiISR = 0x010; - // control register - uint8_t control; + BitUnion8(ControlReg) + Bitfield<0> force_clock_low; + Bitfield<1> force_data_low; + Bitfield<2> enable; + Bitfield<3> txint_enable; + Bitfield<4> rxint_enable; + Bitfield<5> type; + EndBitUnion(ControlReg) - // status register - uint8_t status; + /** control register + */ + ControlReg control; + + /** KMI status register */ + BitUnion8(StatusReg) + Bitfield<0> data_in; + Bitfield<1> clk_in; + Bitfield<2> rxparity; + Bitfield<3> rxbusy; + Bitfield<4> rxfull; + Bitfield<5> txbusy; + Bitfield<6> txempty; + EndBitUnion(StatusReg) + + StatusReg status; + + /** clock divisor register + * This register is just kept around to satisfy reads after driver does + * writes. The divsor does nothing, as we're not actually signaling ps2 + * serial commands to anything. + */ + uint8_t clkdiv; - // received data (read) or data to be transmitted (write) - uint8_t kmidata; + BitUnion8(InterruptReg) + Bitfield<0> rx; + Bitfield<1> tx; + EndBitUnion(InterruptReg) - // clock divisor register - uint8_t clkdiv; + /** interrupt status register. */ + InterruptReg interrupts; + + /** raw interrupt register (unmasked) */ + InterruptReg rawInterrupts; - BitUnion8(IntReg) - Bitfield<0> txintr; - Bitfield<1> rxintr; - EndBitUnion(IntReg) + /** If the controller should ignore the next data byte and acknowledge it. + * The driver is attempting to setup some feature we don't care about + */ + int ackNext; - /** interrupt mask register. */ - IntReg intreg; + /** is the shift key currently down */ + bool shiftDown; - /** Interrupt number to generate */ - int intNum; + /** The vnc server we're connected to (if any) */ + VncServer *vnc; - /** Gic to use for interrupting */ - Gic *gic; + /** If the linux driver has initialized the device yet and thus can we send + * mouse data */ + bool driverInitialized; - /** Delay before interrupting */ - Tick intDelay; + /** Update the status of the interrupt registers and schedule an interrupt + * if required */ + void updateIntStatus(); /** Function to generate interrupt */ void generateInterrupt(); @@ -98,6 +135,15 @@ class Pl050 : public AmbaDevice /** Wrapper to create an event out of the thing */ EventWrapper<Pl050, &Pl050::generateInterrupt> intEvent; + /** Receive queue. This list contains all the pending commands that + * need to be sent to the driver + */ + std::list<uint8_t> rxQueue; + + /** Handle a command sent to the kmi and respond appropriately + */ + void processCommand(uint8_t byte); + public: typedef Pl050Params Params; const Params * @@ -111,12 +157,11 @@ class Pl050 : public AmbaDevice virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - /** - * Return if we have an interrupt pending - * @return interrupt status - * @todo fix me when implementation improves - */ - virtual bool intStatus() { return false; } + virtual void mouseAt(uint16_t x, uint16_t y, uint8_t buttons); + virtual void keyPress(uint32_t key, bool down); + + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); }; -#endif +#endif // __DEV_ARM_PL050_HH__ diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc index e597bf272..e884d9b58 100644 --- a/src/dev/arm/pl111.cc +++ b/src/dev/arm/pl111.cc @@ -35,9 +35,13 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: William Wang + * Ali Saidi */ +#include "base/bitmap.hh" +#include "base/output.hh" #include "base/trace.hh" +#include "base/vnc/vncserver.hh" #include "dev/arm/amba_device.hh" #include "dev/arm/gic.hh" #include "dev/arm/pl111.hh" @@ -50,20 +54,27 @@ using namespace AmbaDev; Pl111::Pl111(const Params *p) : AmbaDmaDevice(p), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0), lcdTiming3(0), lcdUpbase(0), lcdLpbase(0), lcdControl(0), lcdImsc(0), - lcdRis(0), lcdMis(0), lcdIcr(0), lcdUpcurr(0), lcdLpcurr(0), + lcdRis(0), lcdMis(0), clcdCrsrCtrl(0), clcdCrsrConfig(0), clcdCrsrPalette0(0), clcdCrsrPalette1(0), clcdCrsrXY(0), clcdCrsrClip(0), clcdCrsrImsc(0), clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0), clock(p->clock), - height(0), width(0), startTime(0), startAddr(0), maxAddr(0), curAddr(0), + vncserver(p->vnc), bmp(NULL), width(LcdMaxWidth), height(LcdMaxHeight), + bytesPerPixel(4), startTime(0), startAddr(0), maxAddr(0), curAddr(0), waterMark(0), dmaPendingNum(0), readEvent(this), fillFifoEvent(this), dmaDoneEvent(maxOutstandingDma, this), intEvent(this) { pioSize = 0xFFFF; + pic = simout.create("framebuffer.bmp", true); + + dmaBuffer = new uint8_t[LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t)]; + memset(lcdPalette, 0, sizeof(lcdPalette)); memset(cursorImage, 0, sizeof(cursorImage)); memset(dmaBuffer, 0, sizeof(dmaBuffer)); - memset(frameBuffer, 0, sizeof(frameBuffer)); + + if (vncserver) + vncserver->setFramebufferAddr(dmaBuffer); } // read registers and frame buffer @@ -75,111 +86,105 @@ Pl111::read(PacketPtr pkt) uint32_t data = 0; - if ((pkt->getAddr()& 0xffff0000) == pioAddr) { + assert(pkt->getAddr() >= pioAddr && + pkt->getAddr() < pioAddr + pioSize); - assert(pkt->getAddr() >= pioAddr && - pkt->getAddr() < pioAddr + pioSize); + Addr daddr = pkt->getAddr() - pioAddr; + pkt->allocate(); - Addr daddr = pkt->getAddr()&0xFFFF; - pkt->allocate(); + DPRINTF(PL111, " read register %#x size=%d\n", daddr, pkt->getSize()); - DPRINTF(PL111, " read register %#x size=%d\n", daddr, pkt->getSize()); - - switch (daddr) { - case LcdTiming0: - data = lcdTiming0; - break; - case LcdTiming1: - data = lcdTiming1; - break; - case LcdTiming2: - data = lcdTiming2; - break; - case LcdTiming3: - data = lcdTiming3; - break; - case LcdUpBase: - data = lcdUpbase; - break; - case LcdLpBase: - data = lcdLpbase; - break; - case LcdControl: - data = lcdControl; - break; - case LcdImsc: - warn("LCD interrupt set/clear function not supported\n"); - data = lcdImsc; - break; - case LcdRis: - warn("LCD Raw interrupt status function not supported\n"); - data = lcdRis; - break; - case LcdMis: - warn("LCD Masked interrupt status function not supported\n"); - data = lcdMis; - break; - case LcdIcr: - panic("LCD register at offset %#x is Write-Only\n", daddr); - break; - case LcdUpCurr: - data = lcdUpcurr; - break; - case LcdLpCurr: - data = lcdLpcurr; - break; - case ClcdCrsrCtrl: - data = clcdCrsrCtrl; - break; - case ClcdCrsrConfig: - data = clcdCrsrConfig; - break; - case ClcdCrsrPalette0: - data = clcdCrsrPalette0; - break; - case ClcdCrsrPalette1: - data = clcdCrsrPalette1; - break; - case ClcdCrsrXY: - data = clcdCrsrXY; - break; - case ClcdCrsrClip: - data = clcdCrsrClip; - break; - case ClcdCrsrImsc: - data = clcdCrsrImsc; - break; - case ClcdCrsrIcr: - panic("CLCD register at offset %#x is Write-Only\n", daddr); - break; - case ClcdCrsrRis: - data = clcdCrsrRis; - break; - case ClcdCrsrMis: - data = clcdCrsrMis; - break; - default: - if (AmbaDev::readId(pkt, AMBA_ID, pioAddr)) { - // Hack for variable size accesses - data = pkt->get<uint32_t>(); - break; - } else if (daddr >= CrsrImage && daddr <= 0xBFC) { - // CURSOR IMAGE - int index; - index = (daddr - CrsrImage) >> 2; - data= cursorImage[index]; - break; - } else if (daddr >= LcdPalette && daddr <= 0x3FC) { - // LCD Palette - int index; - index = (daddr - LcdPalette) >> 2; - data = lcdPalette[index]; - break; - } else { - panic("Tried to read CLCD register at offset %#x that \ + switch (daddr) { + case LcdTiming0: + data = lcdTiming0; + break; + case LcdTiming1: + data = lcdTiming1; + break; + case LcdTiming2: + data = lcdTiming2; + break; + case LcdTiming3: + data = lcdTiming3; + break; + case LcdUpBase: + data = lcdUpbase; + break; + case LcdLpBase: + data = lcdLpbase; + break; + case LcdControl: + data = lcdControl; + break; + case LcdImsc: + data = lcdImsc; + break; + case LcdRis: + data = lcdRis; + break; + case LcdMis: + data = lcdMis; + break; + case LcdIcr: + panic("LCD register at offset %#x is Write-Only\n", daddr); + break; + case LcdUpCurr: + data = curAddr; + break; + case LcdLpCurr: + data = curAddr; + break; + case ClcdCrsrCtrl: + data = clcdCrsrCtrl; + break; + case ClcdCrsrConfig: + data = clcdCrsrConfig; + break; + case ClcdCrsrPalette0: + data = clcdCrsrPalette0; + break; + case ClcdCrsrPalette1: + data = clcdCrsrPalette1; + break; + case ClcdCrsrXY: + data = clcdCrsrXY; + break; + case ClcdCrsrClip: + data = clcdCrsrClip; + break; + case ClcdCrsrImsc: + data = clcdCrsrImsc; + break; + case ClcdCrsrIcr: + panic("CLCD register at offset %#x is Write-Only\n", daddr); + break; + case ClcdCrsrRis: + data = clcdCrsrRis; + break; + case ClcdCrsrMis: + data = clcdCrsrMis; + break; + default: + if (AmbaDev::readId(pkt, AMBA_ID, pioAddr)) { + // Hack for variable size accesses + data = pkt->get<uint32_t>(); + break; + } else if (daddr >= CrsrImage && daddr <= 0xBFC) { + // CURSOR IMAGE + int index; + index = (daddr - CrsrImage) >> 2; + data= cursorImage[index]; + break; + } else if (daddr >= LcdPalette && daddr <= 0x3FC) { + // LCD Palette + int index; + index = (daddr - LcdPalette) >> 2; + data = lcdPalette[index]; + break; + } else { + panic("Tried to read CLCD register at offset %#x that \ doesn't exist\n", daddr); - break; - } + break; } } @@ -226,119 +231,133 @@ Pl111::write(PacketPtr pkt) break; } - if ((pkt->getAddr()& 0xffff0000) == pioAddr) { + assert(pkt->getAddr() >= pioAddr && + pkt->getAddr() < pioAddr + pioSize); - assert(pkt->getAddr() >= pioAddr && - pkt->getAddr() < pioAddr + pioSize); + Addr daddr = pkt->getAddr() - pioAddr; - Addr daddr = pkt->getAddr() - pioAddr; + DPRINTF(PL111, " write register %#x value %#x size=%d\n", daddr, + pkt->get<uint8_t>(), pkt->getSize()); - DPRINTF(PL111, " write register %#x value %#x size=%d\n", daddr, - pkt->get<uint8_t>(), pkt->getSize()); + switch (daddr) { + case LcdTiming0: + lcdTiming0 = data; + // width = 16 * (PPL+1) + width = (lcdTiming0.ppl + 1) << 4; + break; + case LcdTiming1: + lcdTiming1 = data; + // height = LPP + 1 + height = (lcdTiming1.lpp) + 1; + break; + case LcdTiming2: + lcdTiming2 = data; + break; + case LcdTiming3: + lcdTiming3 = data; + break; + case LcdUpBase: + lcdUpbase = data; + DPRINTF(PL111, "####### Upper panel base set to: %#x #######\n", lcdUpbase); + break; + case LcdLpBase: + warn("LCD dual screen mode not supported\n"); + lcdLpbase = data; + DPRINTF(PL111, "###### Lower panel base set to: %#x #######\n", lcdLpbase); + break; + case LcdControl: + int old_lcdpwr; + old_lcdpwr = lcdControl.lcdpwr; + lcdControl = data; + + DPRINTF(PL111, "LCD power is:%d\n", lcdControl.lcdpwr); + + // LCD power enable + if (lcdControl.lcdpwr && !old_lcdpwr) { + updateVideoParams(); + DPRINTF(PL111, " lcd size: height %d width %d\n", height, width); + waterMark = lcdControl.watermark ? 8 : 4; + startDma(); + } + break; + case LcdImsc: + lcdImsc = data; + if (lcdImsc.vcomp) + panic("Interrupting on vcomp not supported\n"); - switch (daddr) { - case LcdTiming0: - lcdTiming0 = data; - // width = 16 * (PPL+1) - width = (lcdTiming0.ppl + 1) << 4; - break; - case LcdTiming1: - lcdTiming1 = data; - // height = LPP + 1 - height = (lcdTiming1.lpp) + 1; - break; - case LcdTiming2: - lcdTiming2 = data; - break; - case LcdTiming3: - lcdTiming3 = data; - break; - case LcdUpBase: - lcdUpbase = data; - break; - case LcdLpBase: - warn("LCD dual screen mode not supported\n"); - lcdLpbase = data; - break; - case LcdControl: - int old_lcdpwr; - old_lcdpwr = lcdControl.lcdpwr; - lcdControl = data; - // LCD power enable - if (lcdControl.lcdpwr&&!old_lcdpwr) { - DPRINTF(PL111, " lcd size: height %d width %d\n", height, width); - waterMark = lcdControl.watermark ? 8 : 4; - readFramebuffer(); - } - break; - case LcdImsc: - warn("LCD interrupt mask set/clear not supported\n"); - lcdImsc = data; - break; - case LcdRis: - warn("LCD register at offset %#x is Read-Only\n", daddr); - break; - case LcdMis: - warn("LCD register at offset %#x is Read-Only\n", daddr); - break; - case LcdIcr: - warn("LCD interrupt clear not supported\n"); - lcdIcr = data; - break; - case LcdUpCurr: - warn("LCD register at offset %#x is Read-Only\n", daddr); - break; - case LcdLpCurr: - warn("LCD register at offset %#x is Read-Only\n", daddr); - break; - case ClcdCrsrCtrl: - clcdCrsrCtrl = data; - break; - case ClcdCrsrConfig: - clcdCrsrConfig = data; - break; - case ClcdCrsrPalette0: - clcdCrsrPalette0 = data; - break; - case ClcdCrsrPalette1: - clcdCrsrPalette1 = data; - break; - case ClcdCrsrXY: - clcdCrsrXY = data; - break; - case ClcdCrsrClip: - clcdCrsrClip = data; - break; - case ClcdCrsrImsc: - clcdCrsrImsc = data; - break; - case ClcdCrsrIcr: - clcdCrsrIcr = data; - break; - case ClcdCrsrRis: - warn("CLCD register at offset %#x is Read-Only\n", daddr); - break; - case ClcdCrsrMis: - warn("CLCD register at offset %#x is Read-Only\n", daddr); - break; - default: - if (daddr >= CrsrImage && daddr <= 0xBFC) { - // CURSOR IMAGE - int index; - index = (daddr - CrsrImage) >> 2; - cursorImage[index] = data; - break; - } else if (daddr >= LcdPalette && daddr <= 0x3FC) { - // LCD Palette - int index; - index = (daddr - LcdPalette) >> 2; - lcdPalette[index] = data; - break; - } else { - panic("Tried to write PL111 register at offset %#x that \ + lcdMis = lcdImsc & lcdRis; + + if (!lcdMis) + gic->clearInt(intNum); + + break; + case LcdRis: + panic("LCD register at offset %#x is Read-Only\n", daddr); + break; + case LcdMis: + panic("LCD register at offset %#x is Read-Only\n", daddr); + break; + case LcdIcr: + lcdRis = lcdRis & ~data; + lcdMis = lcdImsc & lcdRis; + + if (!lcdMis) + gic->clearInt(intNum); + + break; + case LcdUpCurr: + panic("LCD register at offset %#x is Read-Only\n", daddr); + break; + case LcdLpCurr: + panic("LCD register at offset %#x is Read-Only\n", daddr); + break; + case ClcdCrsrCtrl: + clcdCrsrCtrl = data; + break; + case ClcdCrsrConfig: + clcdCrsrConfig = data; + break; + case ClcdCrsrPalette0: + clcdCrsrPalette0 = data; + break; + case ClcdCrsrPalette1: + clcdCrsrPalette1 = data; + break; + case ClcdCrsrXY: + clcdCrsrXY = data; + break; + case ClcdCrsrClip: + clcdCrsrClip = data; + break; + case ClcdCrsrImsc: + clcdCrsrImsc = data; + break; + case ClcdCrsrIcr: + clcdCrsrIcr = data; + break; + case ClcdCrsrRis: + panic("CLCD register at offset %#x is Read-Only\n", daddr); + break; + case ClcdCrsrMis: + panic("CLCD register at offset %#x is Read-Only\n", daddr); + break; + default: + if (daddr >= CrsrImage && daddr <= 0xBFC) { + // CURSOR IMAGE + int index; + index = (daddr - CrsrImage) >> 2; + cursorImage[index] = data; + break; + } else if (daddr >= LcdPalette && daddr <= 0x3FC) { + // LCD Palette + int index; + index = (daddr - LcdPalette) >> 2; + lcdPalette[index] = data; + break; + } else { + panic("Tried to write PL111 register at offset %#x that \ doesn't exist\n", daddr); - break; - } + break; } } @@ -347,17 +366,75 @@ Pl111::write(PacketPtr pkt) } void +Pl111::updateVideoParams() +{ + if (lcdControl.lcdbpp == bpp24) { + bytesPerPixel = 4; + } else if (lcdControl.lcdbpp == bpp16m565) { + bytesPerPixel = 2; + } + + if (vncserver) { + if (lcdControl.lcdbpp == bpp24 && lcdControl.bgr) + vncserver->setFrameBufferParams(VideoConvert::bgr8888, width, + height); + else if (lcdControl.lcdbpp == bpp24 && !lcdControl.bgr) + vncserver->setFrameBufferParams(VideoConvert::rgb8888, width, + height); + else if (lcdControl.lcdbpp == bpp16m565 && lcdControl.bgr) + vncserver->setFrameBufferParams(VideoConvert::bgr565, width, + height); + else if (lcdControl.lcdbpp == bpp16m565 && !lcdControl.bgr) + vncserver->setFrameBufferParams(VideoConvert::rgb565, width, + height); + else + panic("Unimplemented video mode\n"); + } + + if (bmp) + delete bmp; + + if (lcdControl.lcdbpp == bpp24 && lcdControl.bgr) + bmp = new Bitmap(VideoConvert::bgr8888, width, height, dmaBuffer); + else if (lcdControl.lcdbpp == bpp24 && !lcdControl.bgr) + bmp = new Bitmap(VideoConvert::rgb8888, width, height, dmaBuffer); + else if (lcdControl.lcdbpp == bpp16m565 && lcdControl.bgr) + bmp = new Bitmap(VideoConvert::bgr565, width, height, dmaBuffer); + else if (lcdControl.lcdbpp == bpp16m565 && !lcdControl.bgr) + bmp = new Bitmap(VideoConvert::rgb565, width, height, dmaBuffer); + else + panic("Unimplemented video mode\n"); +} + +void +Pl111::startDma() +{ + if (dmaPendingNum != 0 || readEvent.scheduled()) + return; + readFramebuffer(); +} + +void Pl111::readFramebuffer() { // initialization for dma read from frame buffer to dma buffer - uint32_t length = height*width; - if (startAddr != lcdUpbase) { + uint32_t length = height * width; + if (startAddr != lcdUpbase) startAddr = lcdUpbase; - } + + // Updating base address, interrupt if we're supposed to + lcdRis.baseaddr = 1; + if (!intEvent.scheduled()) + schedule(intEvent, nextCycle()); + curAddr = 0; startTime = curTick(); - maxAddr = static_cast<Addr>(length*sizeof(uint32_t)); - dmaPendingNum =0 ; + + maxAddr = static_cast<Addr>(length * bytesPerPixel); + + DPRINTF(PL111, " lcd frame buffer size of %d bytes \n", maxAddr); + + dmaPendingNum = 0; fillFifo(); } @@ -369,11 +446,16 @@ Pl111::fillFifo() // concurrent dma reads need different dma done events // due to assertion in scheduling state ++dmaPendingNum; - DPRINTF(PL111, " ++ DMA pending number %d read addr %#x\n", - dmaPendingNum, curAddr); + assert(!dmaDoneEvent[dmaPendingNum-1].scheduled()); - dmaRead(curAddr + startAddr, dmaSize, &dmaDoneEvent[dmaPendingNum-1], - curAddr + dmaBuffer); + + // We use a uncachable request here because the requests from the CPU + // will be uncacheable as well. If we have uncacheable and cacheable + // requests in the memory system for the same address it won't be + // pleased + dmaPort->dmaAction(MemCmd::ReadReq, curAddr + startAddr, dmaSize, + &dmaDoneEvent[dmaPendingNum-1], curAddr + dmaBuffer, 0, + Request::UNCACHEABLE); curAddr += dmaSize; } } @@ -381,27 +463,34 @@ Pl111::fillFifo() void Pl111::dmaDone() { - Tick maxFrameTime = lcdTiming2.cpl*height*clock; + Tick maxFrameTime = lcdTiming2.cpl * height * clock; --dmaPendingNum; - DPRINTF(PL111, " -- DMA pending number %d\n", dmaPendingNum); - if (maxAddr == curAddr && !dmaPendingNum) { - if ((curTick() - startTime) > maxFrameTime) + if ((curTick() - startTime) > maxFrameTime) { warn("CLCD controller buffer underrun, took %d cycles when should" " have taken %d\n", curTick() - startTime, maxFrameTime); + lcdRis.underflow = 1; + if (!intEvent.scheduled()) + schedule(intEvent, nextCycle()); + } - // double buffering so the vnc server doesn't see a tear in the screen - memcpy(frameBuffer, dmaBuffer, maxAddr); assert(!readEvent.scheduled()); + if (vncserver) + vncserver->setDirty(); DPRINTF(PL111, "-- write out frame buffer into bmp\n"); - writeBMP(frameBuffer); + + assert(bmp); + pic->seekp(0); + bmp->write(pic); DPRINTF(PL111, "-- schedule next dma read event at %d tick \n", maxFrameTime + curTick()); - schedule(readEvent, nextCycle(startTime + maxFrameTime)); + + if (lcdControl.lcden) + schedule(readEvent, nextCycle(startTime + maxFrameTime)); } if (dmaPendingNum > (maxOutstandingDma - waterMark)) @@ -409,9 +498,9 @@ Pl111::dmaDone() if (!fillFifoEvent.scheduled()) schedule(fillFifoEvent, nextCycle()); - } + Tick Pl111::nextCycle() { @@ -431,33 +520,6 @@ Pl111::nextCycle(Tick beginTick) return nextTick; } -// write out the frame buffer into a bitmap file -void -Pl111::writeBMP(uint32_t* frameBuffer) -{ - fstream pic; - - // write out bmp head - std::string filename = "./m5out/frameBuffer.bmp"; - pic.open(filename.c_str(), ios::out|ios::binary); - Bitmap bm(pic, height, width); - - DPRINTF(PL111, "-- write out data into bmp\n"); - - // write out frame buffer data - for (int i = height -1; i >= 0; --i) { - for (int j = 0; j< width; ++j) { - uint32_t pixel = frameBuffer[i*width + j]; - pic.write(reinterpret_cast<char*>(&pixel), - sizeof(uint32_t)); - DPRINTF(PL111, " write pixel data %#x at addr %#x\n", - pixel, i*width + j); - } - } - - pic.close(); -} - void Pl111::serialize(std::ostream &os) { @@ -490,9 +552,6 @@ Pl111::serialize(std::ostream &os) uint8_t lcdMis_serial = lcdMis; SERIALIZE_SCALAR(lcdMis_serial); - uint8_t lcdIcr_serial = lcdIcr; - SERIALIZE_SCALAR(lcdIcr_serial); - SERIALIZE_ARRAY(lcdPalette, LcdPaletteSize); SERIALIZE_ARRAY(cursorImage, CrsrImageSize); @@ -518,9 +577,9 @@ Pl111::serialize(std::ostream &os) SERIALIZE_SCALAR(clock); SERIALIZE_SCALAR(height); SERIALIZE_SCALAR(width); + SERIALIZE_SCALAR(bytesPerPixel); - SERIALIZE_ARRAY(dmaBuffer, height*width); - SERIALIZE_ARRAY(frameBuffer, height*width); + SERIALIZE_ARRAY(dmaBuffer, height * width); SERIALIZE_SCALAR(startTime); SERIALIZE_SCALAR(startAddr); SERIALIZE_SCALAR(maxAddr); @@ -569,10 +628,6 @@ Pl111::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_SCALAR(lcdMis_serial); lcdMis = lcdMis_serial; - uint8_t lcdIcr_serial; - UNSERIALIZE_SCALAR(lcdIcr_serial); - lcdIcr = lcdIcr_serial; - UNSERIALIZE_ARRAY(lcdPalette, LcdPaletteSize); UNSERIALIZE_ARRAY(cursorImage, CrsrImageSize); @@ -602,25 +657,29 @@ Pl111::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_SCALAR(clock); UNSERIALIZE_SCALAR(height); UNSERIALIZE_SCALAR(width); + UNSERIALIZE_SCALAR(bytesPerPixel); - UNSERIALIZE_ARRAY(dmaBuffer, height*width); - UNSERIALIZE_ARRAY(frameBuffer, height*width); + UNSERIALIZE_ARRAY(dmaBuffer, height * width); UNSERIALIZE_SCALAR(startTime); UNSERIALIZE_SCALAR(startAddr); UNSERIALIZE_SCALAR(maxAddr); UNSERIALIZE_SCALAR(curAddr); UNSERIALIZE_SCALAR(waterMark); UNSERIALIZE_SCALAR(dmaPendingNum); + + updateVideoParams(); + if (vncserver) + vncserver->setDirty(); } void Pl111::generateInterrupt() { DPRINTF(PL111, "Generate Interrupt: lcdImsc=0x%x lcdRis=0x%x lcdMis=0x%x\n", - lcdImsc, lcdRis, lcdMis); + (uint32_t)lcdImsc, (uint32_t)lcdRis, (uint32_t)lcdMis); lcdMis = lcdImsc & lcdRis; - if (lcdMis.ffufie || lcdMis.nbupie || lcdMis.vtcpie || lcdMis.ahmeie) { + if (lcdMis.underflow || lcdMis.baseaddr || lcdMis.vcomp || lcdMis.ahbmaster) { gic->sendInt(intNum); DPRINTF(PL111, " -- Generated\n"); } @@ -639,15 +698,4 @@ Pl111Params::create() return new Pl111(this); } -// bitmap class ctor -Bitmap::Bitmap(std::fstream& bmp, uint16_t h, uint16_t w) -{ - Magic magic = {{'B','M'}}; - Header header = {sizeof(Color)*w*h , 0, 0, 54}; - Info info = {sizeof(Info), w, h, 1, sizeof(Color)*8, 0, - ( sizeof(Color) *(w*h) ), 1, 1, 0, 0}; - - bmp.write(reinterpret_cast<char*>(&magic), sizeof(magic)); - bmp.write(reinterpret_cast<char*>(&header), sizeof(header)); - bmp.write(reinterpret_cast<char*>(&info), sizeof(info)); -} + diff --git a/src/dev/arm/pl111.hh b/src/dev/arm/pl111.hh index 4e75af4e8..f36dc6810 100644 --- a/src/dev/arm/pl111.hh +++ b/src/dev/arm/pl111.hh @@ -35,6 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Authors: William Wang + * Ali Saidi */ @@ -55,6 +56,8 @@ using namespace std; class Gic; +class VncServer; +class Bitmap; class Pl111: public AmbaDmaDevice { @@ -96,58 +99,69 @@ class Pl111: public AmbaDmaDevice static const int dmaSize = 8; // 64 bits static const int maxOutstandingDma = 16; // 16 deep FIFO of 64 bits + enum LcdMode { + bpp1 = 0, + bpp2, + bpp4, + bpp8, + bpp16, + bpp24, + bpp16m565, + bpp12 + }; + BitUnion8(InterruptReg) - Bitfield<1> ffufie; - Bitfield<2> nbupie; - Bitfield<3> vtcpie; - Bitfield<4> ahmeie; + Bitfield<1> underflow; + Bitfield<2> baseaddr; + Bitfield<3> vcomp; + Bitfield<4> ahbmaster; EndBitUnion(InterruptReg) BitUnion32(TimingReg0) - Bitfield<7,2> ppl; - Bitfield<15,8> hsw; - Bitfield<23,16> hfp; - Bitfield<31,24> hbp; + Bitfield<7,2> ppl; + Bitfield<15,8> hsw; + Bitfield<23,16> hfp; + Bitfield<31,24> hbp; EndBitUnion(TimingReg0) BitUnion32(TimingReg1) - Bitfield<9,0> lpp; - Bitfield<15,10> vsw; - Bitfield<23,16> vfp; - Bitfield<31,24> vbp; + Bitfield<9,0> lpp; + Bitfield<15,10> vsw; + Bitfield<23,16> vfp; + Bitfield<31,24> vbp; EndBitUnion(TimingReg1) BitUnion32(TimingReg2) - Bitfield<4,0> pcdlo; - Bitfield<5> clksel; - Bitfield<10,6> acb; - Bitfield<11> avs; - Bitfield<12> ihs; - Bitfield<13> ipc; - Bitfield<14> ioe; - Bitfield<25,16> cpl; - Bitfield<26> bcd; - Bitfield<31,27> pcdhi; + Bitfield<4,0> pcdlo; + Bitfield<5> clksel; + Bitfield<10,6> acb; + Bitfield<11> avs; + Bitfield<12> ihs; + Bitfield<13> ipc; + Bitfield<14> ioe; + Bitfield<25,16> cpl; + Bitfield<26> bcd; + Bitfield<31,27> pcdhi; EndBitUnion(TimingReg2) BitUnion32(TimingReg3) - Bitfield<6,0> led; - Bitfield<16> lee; + Bitfield<6,0> led; + Bitfield<16> lee; EndBitUnion(TimingReg3) BitUnion32(ControlReg) - Bitfield<0> lcden; - Bitfield<3,1> lcdbpp; - Bitfield<4> lcdbw; - Bitfield<5> lcdtft; - Bitfield<6> lcdmono8; - Bitfield<7> lcddual; - Bitfield<8> bgr; - Bitfield<9> bebo; - Bitfield<10> bepo; - Bitfield<11> lcdpwr; - Bitfield<13,12> lcdvcomp; - Bitfield<16> watermark; + Bitfield<0> lcden; + Bitfield<3,1> lcdbpp; + Bitfield<4> lcdbw; + Bitfield<5> lcdtft; + Bitfield<6> lcdmono8; + Bitfield<7> lcddual; + Bitfield<8> bgr; + Bitfield<9> bebo; + Bitfield<10> bepo; + Bitfield<11> lcdpwr; + Bitfield<13,12> lcdvcomp; + Bitfield<16> watermark; EndBitUnion(ControlReg) /** Horizontal axis panel control register */ @@ -180,15 +194,6 @@ class Pl111: public AmbaDmaDevice /** Masked interrupt status register */ InterruptReg lcdMis; - /** Interrupt clear register */ - InterruptReg lcdIcr; - - /** Upper panel current address value register - ro */ - int lcdUpcurr; - - /** Lower panel current address value register - ro */ - int lcdLpcurr; - /** 256x16-bit color palette registers * 256 palette entries organized as 128 locations of two entries per word */ int lcdPalette[LcdPaletteSize]; @@ -228,17 +233,26 @@ class Pl111: public AmbaDmaDevice /** Clock speed */ Tick clock; - /** Frame buffer height - lines per panel */ - uint16_t height; + /** VNC server */ + VncServer *vncserver; + + /** Helper to write out bitmaps */ + Bitmap *bmp; + + /** Picture of what the current frame buffer looks like */ + std::ostream *pic; /** Frame buffer width - pixels per line */ uint16_t width; - /** CLCDC supports up to 1024x768 */ - uint8_t dmaBuffer[LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t)]; + /** Frame buffer height - lines per panel */ + uint16_t height; - /** Double buffering */ - uint32_t frameBuffer[LcdMaxWidth * LcdMaxHeight]; + /** Bytes per pixel */ + uint8_t bytesPerPixel; + + /** CLCDC supports up to 1024x768 */ + uint8_t *dmaBuffer; /** Start time for frame buffer dma read */ Tick startTime; @@ -258,12 +272,12 @@ class Pl111: public AmbaDmaDevice /** Number of pending dma reads */ int dmaPendingNum; + /** Send updated parameters to the vnc server */ + void updateVideoParams(); + /** DMA framebuffer read */ void readFramebuffer(); - /** Write framebuffer to a bmp file */ - void writeBMP(uint32_t*); - /** Generate dma framebuffer read event */ void generateReadEvent(); @@ -273,6 +287,9 @@ class Pl111: public AmbaDmaDevice /** fillFIFO event */ void fillFifo(); + /** start the dmas off after power is enabled */ + void startDma(); + /** DMA done event */ void dmaDone(); @@ -289,7 +306,7 @@ class Pl111: public AmbaDmaDevice /** DMA done event */ vector<EventWrapper<Pl111, &Pl111::dmaDone> > dmaDoneEvent; - /** Wrapper to create an event out of the thing */ + /** Wrapper to create an event out of the interrupt */ EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent; public: @@ -312,57 +329,6 @@ class Pl111: public AmbaDmaDevice * @param range_list range list to populate with ranges */ void addressRanges(AddrRangeList &range_list); - - /** - * Return if we have an interrupt pending - * @return interrupt status - * @todo fix me when implementation improves - */ - virtual bool intStatus() { return false; } -}; - -// write frame buffer into a bitmap picture -class Bitmap -{ - public: - Bitmap(std::fstream& bmp, uint16_t h, uint16_t w); - - private: - struct Magic - { - unsigned char magic_number[2]; - } magic; - - struct Header - { - uint32_t size; - uint16_t reserved1; - uint16_t reserved2; - uint32_t offset; - } header; - - struct Info - { - uint32_t Size; - uint32_t Width; - uint32_t Height; - uint16_t Planes; - uint16_t BitCount; - uint32_t Compression; - uint32_t SizeImage; - uint32_t XPelsPerMeter; - uint32_t YPelsPerMeter; - uint32_t ClrUsed; - uint32_t ClrImportant; - } info; - - struct Color - { - unsigned char b; - unsigned char g; - unsigned char r; - unsigned char a; - } color; }; #endif diff --git a/src/dev/arm/rv_ctrl.cc b/src/dev/arm/rv_ctrl.cc index c0ba4c7aa..b1bbc065b 100644 --- a/src/dev/arm/rv_ctrl.cc +++ b/src/dev/arm/rv_ctrl.cc @@ -68,6 +68,27 @@ RealViewCtrl::read(PacketPtr pkt) case Flash: pkt->set<uint32_t>(0); break; + case Clcd: + pkt->set<uint32_t>(0x00001F00); + break; + case Osc0: + pkt->set<uint32_t>(0x00012C5C); + break; + case Osc1: + pkt->set<uint32_t>(0x00002CC0); + break; + case Osc2: + pkt->set<uint32_t>(0x00002C75); + break; + case Osc3: + pkt->set<uint32_t>(0x00020211); + break; + case Osc4: + pkt->set<uint32_t>(0x00002C75); + break; + case Lock: + pkt->set<uint32_t>(sysLock); + break; default: panic("Tried to read RealView I/O at offset %#x that doesn't exist\n", daddr); break; @@ -85,6 +106,15 @@ RealViewCtrl::write(PacketPtr pkt) Addr daddr = pkt->getAddr() - pioAddr; switch (daddr) { case Flash: + case Clcd: + case Osc0: + case Osc1: + case Osc2: + case Osc3: + case Osc4: + break; + case Lock: + sysLock.lockVal = pkt->get<uint16_t>(); break; default: panic("Tried to write RVIO at offset %#x that doesn't exist\n", daddr); diff --git a/src/dev/arm/rv_ctrl.hh b/src/dev/arm/rv_ctrl.hh index 00a19d715..ceed5ef2f 100644 --- a/src/dev/arm/rv_ctrl.hh +++ b/src/dev/arm/rv_ctrl.hh @@ -40,6 +40,7 @@ #ifndef __DEV_ARM_RV_HH__ #define __DEV_ARM_RV_HH__ +#include "base/bitunion.hh" #include "base/range.hh" #include "dev/io_device.hh" #include "params/RealViewCtrl.hh" @@ -86,6 +87,14 @@ class RealViewCtrl : public BasicPioDevice TestOsc4 = 0xD0 }; + // system lock value + BitUnion32(SysLockReg) + Bitfield<15,0> lockVal; + Bitfield<16> locked; + EndBitUnion(SysLockReg) + + SysLockReg sysLock; + public: typedef RealViewCtrlParams Params; const Params * @@ -120,4 +129,3 @@ class RealViewCtrl : public BasicPioDevice #endif // __DEV_ARM_RV_HH__ - diff --git a/src/dev/arm/timer_sp804.cc b/src/dev/arm/timer_sp804.cc index 04668d268..e6d2657ea 100644 --- a/src/dev/arm/timer_sp804.cc +++ b/src/dev/arm/timer_sp804.cc @@ -178,11 +178,11 @@ Sp804::Timer::restartCounter(uint32_t val) if (!control.timerEnable) return; - Tick time = clock << power(16, control.timerPrescale); + Tick time = clock * power(16, control.timerPrescale); if (control.timerSize) - time *= bits(val,15,0); - else time *= val; + else + time *= bits(val,15,0); if (zeroEvent.scheduled()) { DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n"); diff --git a/src/dev/ps2.cc b/src/dev/ps2.cc new file mode 100644 index 000000000..fe90ce6bc --- /dev/null +++ b/src/dev/ps2.cc @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#include <list> +#include "x11keysym/keysym.h" + +#include "base/misc.hh" +#include "dev/ps2.hh" + + +namespace Ps2 { + +/** Table to convert simple key symbols (0x00XX) into ps2 bytes. Lower byte + * is the scan code to send and upper byte is if a modifier is required to + * generate it. The table generates us keyboard codes, (e.g. the guest is + * supposed to recognize the keyboard as en_US). A new table would be required + * for another locale. + */ + +static const uint16_t keySymToPs2Byte[128] = { +// 0 / 8 1 / 9 2 / A 3 / B 4 / C 5 / D 6 / E 7 / F + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 0x00-0x07 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 0x08-0x0f + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 0x10-0x17 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, // 0x18-0x1f + 0x0029, 0x0116, 0x0152, 0x0126, 0x0125, 0x012e, 0x013d, 0x0052, // 0x20-0x27 + 0x0146, 0x0145, 0x013e, 0x0155, 0x0041, 0x004e, 0x0049, 0x004a, // 0x28-0x2f + 0x0045, 0x0016, 0x001e, 0x0026, 0x0025, 0x002e, 0x0036, 0x003d, // 0x30-0x37 + 0x003e, 0x0046, 0x014c, 0x004c, 0x0141, 0x0055, 0x0149, 0x014a, // 0x38-0x3f + 0x011e, 0x011c, 0x0132, 0x0121, 0x0123, 0x0124, 0x012b, 0x0134, // 0x40-0x47 + 0x0133, 0x0143, 0x013b, 0x0142, 0x014b, 0x013a, 0x0131, 0x0144, // 0x48-0x4f + 0x014d, 0x0115, 0x012d, 0x011b, 0x012c, 0x013c, 0x012a, 0x011d, // 0x50-0x57 + 0x0122, 0x0135, 0x011a, 0x0054, 0x005d, 0x005b, 0x0136, 0x014e, // 0x58-0x5f + 0x000e, 0x001c, 0x0032, 0x0021, 0x0023, 0x0024, 0x002b, 0x0034, // 0x60-0x67 + 0x0033, 0x0043, 0x003b, 0x0042, 0x004b, 0x003a, 0x0031, 0x0044, // 0x68-0x6f + 0x004d, 0x0015, 0x002d, 0x001b, 0x002c, 0x003c, 0x002a, 0x001d, // 0x70-0x77 + 0x0022, 0x0035, 0x001a, 0x0154, 0x015d, 0x015b, 0x010e, 0x0000 // 0x78-0x7f +}; + +const uint8_t ShiftKey = 0x12; +const uint8_t BreakKey = 0xf0; +const uint8_t ExtendedKey = 0xe0; +const uint32_t UpperKeys = 0xff00; + +void +keySymToPs2(uint32_t key, bool down, bool &cur_shift, + std::list<uint8_t> &keys) +{ + if (key <= XK_asciitilde) { + uint16_t tmp = keySymToPs2Byte[key]; + uint8_t code = tmp & 0xff; + bool shift = tmp >> 8; + + if (down) { + if (!cur_shift && shift) { + keys.push_back(ShiftKey); + cur_shift = true; + } + keys.push_back(code); + } else { + if (cur_shift && !shift) { + keys.push_back(BreakKey); + keys.push_back(ShiftKey); + cur_shift = false; + } + keys.push_back(BreakKey); + keys.push_back(code); + } + } else { + if ((key & UpperKeys) == UpperKeys) { + bool extended = false; + switch (key) { + case XK_BackSpace: + keys.push_back(0x66); + break; + case XK_Tab: + keys.push_back(0x0d); + break; + case XK_Return: + keys.push_back(0x5a); + break; + case XK_Escape: + keys.push_back(0x76); + break; + case XK_Delete: + extended = true; + keys.push_back(0x71); + break; + case XK_Home: + extended = true; + keys.push_back(0x6c); + break; + case XK_Left: + extended = true; + keys.push_back(0x6b); + break; + case XK_Right: + extended = true; + keys.push_back(0x74); + break; + case XK_Down: + extended = true; + keys.push_back(0x72); + break; + case XK_Up: + extended = true; + keys.push_back(0x75); + break; + case XK_Page_Up: + extended = true; + keys.push_back(0x7d); + break; + case XK_Page_Down: + extended = true; + keys.push_back(0x7a); + break; + case XK_End: + extended = true; + keys.push_back(0x69); + break; + case XK_Shift_L: + keys.push_back(0x12); + if (down) + cur_shift = true; + else + cur_shift = false; + break; + case XK_Shift_R: + keys.push_back(0x59); + if (down) + cur_shift = true; + else + cur_shift = false; + break; + case XK_Control_L: + keys.push_back(0x14); + break; + case XK_Control_R: + extended = true; + keys.push_back(0x14); + break; + default: + warn("Unknown extended key %#x\n", key); + return; + } + + if (extended) { + if (down) { + keys.push_front(ExtendedKey); + } else { + keys.push_front(BreakKey); + keys.push_front(ExtendedKey); + } + } else { + if (!down) + keys.push_front(BreakKey); + } + } // upper keys + } // extended keys + return; +} + +} /* namespace Ps2 */ + diff --git a/src/dev/ps2.hh b/src/dev/ps2.hh new file mode 100644 index 000000000..73f3f9cd8 --- /dev/null +++ b/src/dev/ps2.hh @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#ifndef __DEV_PS2_HH__ +#define __DEV_PS2_HH__ + +#include <stdint.h> + +#include "base/bitunion.hh" + +/** @file misc functions and constants required to interface with or emulate ps2 + * devices + */ + +namespace Ps2 { +enum { + Ps2Reset = 0xff, + SelfTestPass = 0xAA, + SetStatusLed = 0xed, + SetResolution = 0xe8, + StatusRequest = 0xe9, + SetScaling1_2 = 0xe7, + SetScaling1_1 = 0xe6, + ReadId = 0xf2, + TpReadId = 0xe1, + Ack = 0xfa, + SetRate = 0xf3, + Enable = 0xf4, + Disable = 0xf6, + KeyboardId = 0xab, + TouchKitId = 0x0a, + MouseId = 0x00, +}; + +/** A bitfield that represents the first byte of a mouse movement packet + */ +BitUnion8(Ps2MouseMovement) + Bitfield<0> leftButton; + Bitfield<1> rightButton; + Bitfield<2> middleButton; + Bitfield<3> one; + Bitfield<4> xSign; + Bitfield<5> ySign; + Bitfield<6> xOverflow; + Bitfield<7> yOverflow; +EndBitUnion(Ps2MouseMovement) + +/** Convert an x11 key symbol into a set of ps2 charecters. + * @param key x11 key symbol + * @param down if the key is being pressed or released + * @param cur_shift if device has already sent a shift + * @param keys list of keys command to send to emulate the x11 key symbol + */ +void keySymToPs2(uint32_t key, bool down, bool &cur_shift, + std::list<uint8_t> &keys); + +} /* namespace Ps2 */ +#endif // __DEV_PS2_HH__ diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index 8744a7122..4442cee41 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -287,20 +287,21 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") if (in_msg.Type == CacheRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); - if (is_valid(L1Dcache_entry)) { - // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Dcache_entry, L1_TBEs[in_msg.LineAddress]); - } - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); if (is_valid(L1Icache_entry)) { // The tag matches for the L1, so the L1 asks the L2 for it. trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Icache_entry, L1_TBEs[in_msg.LineAddress]); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); + if (is_valid(L1Dcache_entry)) { + // The block is in the wrong L1, put the request on the queue to the shared L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Dcache_entry, L1_TBEs[in_msg.LineAddress]); + } + if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, @@ -313,21 +314,23 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") } } } else { - // *** DATA ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); - if (is_valid(L1Icache_entry)) { - // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Icache_entry, L1_TBEs[in_msg.LineAddress]); - } + // *** DATA ACCESS *** Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); if (is_valid(L1Dcache_entry)) { // The tag matches for the L1, so the L1 ask the L2 for it trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Dcache_entry, L1_TBEs[in_msg.LineAddress]); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); + if (is_valid(L1Icache_entry)) { + // The block is in the wrong L1, put the request on the queue to the shared L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Icache_entry, L1_TBEs[in_msg.LineAddress]); + } + if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 4082f23c9..7f0ab62a8 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -338,14 +338,6 @@ machine(L1Cache, "Directory protocol") if (in_msg.Type == CacheRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); - // Check to see if it is in the OTHER L1 - if (is_valid(L1Dcache_entry)) { - // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, L1Dcache_entry, - TBEs[in_msg.LineAddress]); - } - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); if (is_valid(L1Icache_entry)) { // The tag matches for the L1, so the L1 asks the L2 for it. @@ -353,6 +345,14 @@ machine(L1Cache, "Directory protocol") in_msg.LineAddress, L1Icache_entry, TBEs[in_msg.LineAddress]); } else { + + Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); + // Check to see if it is in the OTHER L1 + if (is_valid(L1Dcache_entry)) { + // The block is in the wrong L1, put the request on the queue to the shared L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, L1Dcache_entry, + TBEs[in_msg.LineAddress]); + } if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it trigger(mandatory_request_type_to_event(in_msg.Type), @@ -369,14 +369,6 @@ machine(L1Cache, "Directory protocol") } else { // *** DATA ACCESS *** - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); - // Check to see if it is in the OTHER L1 - if (is_valid(L1Icache_entry)) { - // The block is in the wrong L1, put the request on the queue to the shared L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Icache_entry, TBEs[in_msg.LineAddress]); - } - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); if (is_valid(L1Dcache_entry)) { // The tag matches for the L1, so the L1 ask the L2 for it @@ -384,6 +376,14 @@ machine(L1Cache, "Directory protocol") in_msg.LineAddress, L1Dcache_entry, TBEs[in_msg.LineAddress]); } else { + + Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); + // Check to see if it is in the OTHER L1 + if (is_valid(L1Icache_entry)) { + // The block is in the wrong L1, put the request on the queue to the shared L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Icache_entry, TBEs[in_msg.LineAddress]); + } if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it trigger(mandatory_request_type_to_event(in_msg.Type), diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index 00e9404c9..226f21374 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -647,20 +647,21 @@ machine(L1Cache, "Token protocol") if (in_msg.Type == CacheRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); - if (is_valid(L1Dcache_entry)) { - // The block is in the wrong L1, try to write it to the L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Dcache_entry, tbe); - } - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); if (is_valid(L1Icache_entry)) { // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Icache_entry, tbe); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); + if (is_valid(L1Dcache_entry)) { + // The block is in the wrong L1, try to write it to the L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Dcache_entry, tbe); + } + if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 trigger(mandatory_request_type_to_event(in_msg.Type), @@ -676,21 +677,21 @@ machine(L1Cache, "Token protocol") } else { // *** DATA ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); - - if (is_valid(L1Icache_entry)) { - // The block is in the wrong L1, try to write it to the L2 - trigger(Event:L1_Replacement, in_msg.LineAddress, - L1Icache_entry, tbe); - } - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); if (is_valid(L1Dcache_entry)) { // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Dcache_entry, tbe); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); + if (is_valid(L1Icache_entry)) { + // The block is in the wrong L1, try to write it to the L2 + trigger(Event:L1_Replacement, in_msg.LineAddress, + L1Icache_entry, tbe); + } + if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 trigger(mandatory_request_type_to_event(in_msg.Type), diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 78bc9e3e7..ab2a6acf4 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -377,26 +377,26 @@ machine(L1Cache, "AMD Hammer-like protocol") if (in_msg.Type == CacheRequestType:IFETCH) { // ** INSTRUCTION ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); - if (is_valid(L1Dcache_entry)) { - // The block is in the wrong L1, try to write it to the L2 - if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { - trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe); - } else { - trigger(Event:L2_Replacement, - L2cacheMemory.cacheProbe(in_msg.LineAddress), - getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), - TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); - } - } - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); if (is_valid(L1Icache_entry)) { // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Icache_entry, tbe); } else { + // Check to see if it is in the OTHER L1 + Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); + if (is_valid(L1Dcache_entry)) { + // The block is in the wrong L1, try to write it to the L2 + if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { + trigger(Event:L1_to_L2, in_msg.LineAddress, L1Dcache_entry, tbe); + } else { + trigger(Event:L2_Replacement, + L2cacheMemory.cacheProbe(in_msg.LineAddress), + getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), + TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); + } + } + if (L1IcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 @@ -430,26 +430,27 @@ machine(L1Cache, "AMD Hammer-like protocol") } else { // *** DATA ACCESS *** - // Check to see if it is in the OTHER L1 - Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); - if (is_valid(L1Icache_entry)) { - // The block is in the wrong L1, try to write it to the L2 - if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { - trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe); - } else { - trigger(Event:L2_Replacement, - L2cacheMemory.cacheProbe(in_msg.LineAddress), - getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), - TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); - } - } - Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress); if (is_valid(L1Dcache_entry)) { // The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, L1Dcache_entry, tbe); } else { + + // Check to see if it is in the OTHER L1 + Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress); + if (is_valid(L1Icache_entry)) { + // The block is in the wrong L1, try to write it to the L2 + if (L2cacheMemory.cacheAvail(in_msg.LineAddress)) { + trigger(Event:L1_to_L2, in_msg.LineAddress, L1Icache_entry, tbe); + } else { + trigger(Event:L2_Replacement, + L2cacheMemory.cacheProbe(in_msg.LineAddress), + getL2CacheEntry(L2cacheMemory.cacheProbe(in_msg.LineAddress)), + TBEs[L2cacheMemory.cacheProbe(in_msg.LineAddress)]); + } + } + if (L1DcacheMemory.cacheAvail(in_msg.LineAddress)) { // L1 does't have the line, but we have space for it in the L1 Entry L2cache_entry := getL2CacheEntry(in_msg.LineAddress); diff --git a/src/mem/ruby/buffers/MessageBuffer.cc b/src/mem/ruby/buffers/MessageBuffer.cc index f6b79c580..225595005 100644 --- a/src/mem/ruby/buffers/MessageBuffer.cc +++ b/src/mem/ruby/buffers/MessageBuffer.cc @@ -58,6 +58,8 @@ MessageBuffer::MessageBuffer(const string &name) m_name = name; m_stall_msg_map.clear(); + m_input_link_id = 0; + m_vnet_id = 0; } int @@ -228,6 +230,7 @@ MessageBuffer::enqueue(MsgPtr message, Time delta) // Schedule the wakeup if (m_consumer_ptr != NULL) { g_eventQueue_ptr->scheduleEventAbsolute(m_consumer_ptr, arrival_time); + m_consumer_ptr->storeEventInfo(m_vnet_id); } else { panic("No consumer: %s name: %s\n", *this, m_name); } diff --git a/src/mem/ruby/buffers/MessageBuffer.hh b/src/mem/ruby/buffers/MessageBuffer.hh index 62cc65670..88df5b788 100644 --- a/src/mem/ruby/buffers/MessageBuffer.hh +++ b/src/mem/ruby/buffers/MessageBuffer.hh @@ -142,6 +142,9 @@ class MessageBuffer void printStats(std::ostream& out); void clearStats() { m_not_avail_count = 0; m_msg_counter = 0; } + void setIncomingLink(int link_id) { m_input_link_id = link_id; } + void setVnet(int net) { m_vnet_id = net; } + private: //added by SS int m_recycle_latency; @@ -184,6 +187,9 @@ class MessageBuffer bool m_ordering_set; bool m_randomization; Time m_last_arrival_time; + + int m_input_link_id; + int m_vnet_id; }; inline std::ostream& diff --git a/src/mem/ruby/common/Consumer.hh b/src/mem/ruby/common/Consumer.hh index c1f8bc42e..a119abb39 100644 --- a/src/mem/ruby/common/Consumer.hh +++ b/src/mem/ruby/common/Consumer.hh @@ -67,6 +67,7 @@ class Consumer virtual void wakeup() = 0; virtual void print(std::ostream& out) const = 0; + virtual void storeEventInfo(int info) {} const Time& getLastScheduledWakeup() const diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc index 7229c724f..5c461c63f 100644 --- a/src/mem/ruby/network/simple/PerfectSwitch.cc +++ b/src/mem/ruby/network/simple/PerfectSwitch.cc @@ -54,6 +54,11 @@ PerfectSwitch::PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr) m_round_robin_start = 0; m_network_ptr = network_ptr; m_wakeups_wo_switch = 0; + + for(int i = 0;i < m_virtual_networks;++i) + { + m_pending_message_count.push_back(0); + } } void @@ -62,12 +67,15 @@ PerfectSwitch::addInPort(const vector<MessageBuffer*>& in) assert(in.size() == m_virtual_networks); NodeID port = m_in.size(); m_in.push_back(in); + for (int j = 0; j < m_virtual_networks; j++) { m_in[port][j]->setConsumer(this); string desc = csprintf("[Queue from port %s %s %s to PerfectSwitch]", NodeIDToString(m_switch_id), NodeIDToString(port), NodeIDToString(j)); m_in[port][j]->setDescription(desc); + m_in[port][j]->setIncomingLink(port); + m_in[port][j]->setVnet(j); } } @@ -154,161 +162,170 @@ PerfectSwitch::wakeup() m_round_robin_start = 0; } - // for all input ports, use round robin scheduling - for (int counter = 0; counter < m_in.size(); counter++) { - // Round robin scheduling - incoming++; - if (incoming >= m_in.size()) { - incoming = 0; - } + if(m_pending_message_count[vnet] > 0) { + // for all input ports, use round robin scheduling + for (int counter = 0; counter < m_in.size(); counter++) { + // Round robin scheduling + incoming++; + if (incoming >= m_in.size()) { + incoming = 0; + } - // temporary vectors to store the routing results - vector<LinkID> output_links; - vector<NetDest> output_link_destinations; - - // Is there a message waiting? - while (m_in[incoming][vnet]->isReady()) { - DPRINTF(RubyNetwork, "incoming: %d\n", incoming); - - // Peek at message - msg_ptr = m_in[incoming][vnet]->peekMsgPtr(); - net_msg_ptr = safe_cast<NetworkMessage*>(msg_ptr.get()); - DPRINTF(RubyNetwork, "Message: %s\n", (*net_msg_ptr)); - - output_links.clear(); - output_link_destinations.clear(); - NetDest msg_dsts = - net_msg_ptr->getInternalDestination(); - - // Unfortunately, the token-protocol sends some - // zero-destination messages, so this assert isn't valid - // assert(msg_dsts.count() > 0); - - assert(m_link_order.size() == m_routing_table.size()); - assert(m_link_order.size() == m_out.size()); - - if (m_network_ptr->getAdaptiveRouting()) { - if (m_network_ptr->isVNetOrdered(vnet)) { - // Don't adaptively route - for (int out = 0; out < m_out.size(); out++) { - m_link_order[out].m_link = out; - m_link_order[out].m_value = 0; - } - } else { - // Find how clogged each link is - for (int out = 0; out < m_out.size(); out++) { - int out_queue_length = 0; - for (int v = 0; v < m_virtual_networks; v++) { - out_queue_length += m_out[out][v]->getSize(); + // temporary vectors to store the routing results + vector<LinkID> output_links; + vector<NetDest> output_link_destinations; + + // Is there a message waiting? + while (m_in[incoming][vnet]->isReady()) { + DPRINTF(RubyNetwork, "incoming: %d\n", incoming); + + // Peek at message + msg_ptr = m_in[incoming][vnet]->peekMsgPtr(); + net_msg_ptr = safe_cast<NetworkMessage*>(msg_ptr.get()); + DPRINTF(RubyNetwork, "Message: %s\n", (*net_msg_ptr)); + + output_links.clear(); + output_link_destinations.clear(); + NetDest msg_dsts = + net_msg_ptr->getInternalDestination(); + + // Unfortunately, the token-protocol sends some + // zero-destination messages, so this assert isn't valid + // assert(msg_dsts.count() > 0); + + assert(m_link_order.size() == m_routing_table.size()); + assert(m_link_order.size() == m_out.size()); + + if (m_network_ptr->getAdaptiveRouting()) { + if (m_network_ptr->isVNetOrdered(vnet)) { + // Don't adaptively route + for (int out = 0; out < m_out.size(); out++) { + m_link_order[out].m_link = out; + m_link_order[out].m_value = 0; + } + } else { + // Find how clogged each link is + for (int out = 0; out < m_out.size(); out++) { + int out_queue_length = 0; + for (int v = 0; v < m_virtual_networks; v++) { + out_queue_length += m_out[out][v]->getSize(); + } + int value = + (out_queue_length << 8) | (random() & 0xff); + m_link_order[out].m_link = out; + m_link_order[out].m_value = value; } - int value = - (out_queue_length << 8) | (random() & 0xff); - m_link_order[out].m_link = out; - m_link_order[out].m_value = value; + + // Look at the most empty link first + sort(m_link_order.begin(), m_link_order.end()); } + } - // Look at the most empty link first - sort(m_link_order.begin(), m_link_order.end()); + for (int i = 0; i < m_routing_table.size(); i++) { + // pick the next link to look at + int link = m_link_order[i].m_link; + NetDest dst = m_routing_table[link]; + DPRINTF(RubyNetwork, "dst: %s\n", dst); + + if (!msg_dsts.intersectionIsNotEmpty(dst)) + continue; + + // Remember what link we're using + output_links.push_back(link); + + // Need to remember which destinations need this + // message in another vector. This Set is the + // intersection of the routing_table entry and the + // current destination set. The intersection must + // not be empty, since we are inside "if" + output_link_destinations.push_back(msg_dsts.AND(dst)); + + // Next, we update the msg_destination not to + // include those nodes that were already handled + // by this link + msg_dsts.removeNetDest(dst); } - } - for (int i = 0; i < m_routing_table.size(); i++) { - // pick the next link to look at - int link = m_link_order[i].m_link; - NetDest dst = m_routing_table[link]; - DPRINTF(RubyNetwork, "dst: %s\n", dst); - - if (!msg_dsts.intersectionIsNotEmpty(dst)) - continue; - - // Remember what link we're using - output_links.push_back(link); - - // Need to remember which destinations need this - // message in another vector. This Set is the - // intersection of the routing_table entry and the - // current destination set. The intersection must - // not be empty, since we are inside "if" - output_link_destinations.push_back(msg_dsts.AND(dst)); - - // Next, we update the msg_destination not to - // include those nodes that were already handled - // by this link - msg_dsts.removeNetDest(dst); - } + assert(msg_dsts.count() == 0); + //assert(output_links.size() > 0); + + // Check for resources - for all outgoing queues + bool enough = true; + for (int i = 0; i < output_links.size(); i++) { + int outgoing = output_links[i]; + if (!m_out[outgoing][vnet]->areNSlotsAvailable(1)) + enough = false; + DPRINTF(RubyNetwork, "Checking if node is blocked\n" + "outgoing: %d, vnet: %d, enough: %d\n", + outgoing, vnet, enough); + } - assert(msg_dsts.count() == 0); - //assert(output_links.size() > 0); - - // Check for resources - for all outgoing queues - bool enough = true; - for (int i = 0; i < output_links.size(); i++) { - int outgoing = output_links[i]; - if (!m_out[outgoing][vnet]->areNSlotsAvailable(1)) - enough = false; - DPRINTF(RubyNetwork, "Checking if node is blocked\n" - "outgoing: %d, vnet: %d, enough: %d\n", - outgoing, vnet, enough); - } + // There were not enough resources + if (!enough) { + g_eventQueue_ptr->scheduleEvent(this, 1); + DPRINTF(RubyNetwork, "Can't deliver message since a node " + "is blocked\n" + "Message: %s\n", (*net_msg_ptr)); + break; // go to next incoming port + } - // There were not enough resources - if (!enough) { - g_eventQueue_ptr->scheduleEvent(this, 1); - DPRINTF(RubyNetwork, "Can't deliver message since a node " - "is blocked\n" - "Message: %s\n", (*net_msg_ptr)); - break; // go to next incoming port - } + MsgPtr unmodified_msg_ptr; - MsgPtr unmodified_msg_ptr; + if (output_links.size() > 1) { + // If we are sending this message down more than + // one link (size>1), we need to make a copy of + // the message so each branch can have a different + // internal destination we need to create an + // unmodified MsgPtr because the MessageBuffer + // enqueue func will modify the message - if (output_links.size() > 1) { - // If we are sending this message down more than - // one link (size>1), we need to make a copy of - // the message so each branch can have a different - // internal destination we need to create an - // unmodified MsgPtr because the MessageBuffer - // enqueue func will modify the message + // This magic line creates a private copy of the + // message + unmodified_msg_ptr = msg_ptr->clone(); + } - // This magic line creates a private copy of the - // message - unmodified_msg_ptr = msg_ptr->clone(); - } + // Enqueue it - for all outgoing queues + for (int i=0; i<output_links.size(); i++) { + int outgoing = output_links[i]; - // Enqueue it - for all outgoing queues - for (int i=0; i<output_links.size(); i++) { - int outgoing = output_links[i]; + if (i > 0) { + // create a private copy of the unmodified + // message + msg_ptr = unmodified_msg_ptr->clone(); + } - if (i > 0) { - // create a private copy of the unmodified - // message - msg_ptr = unmodified_msg_ptr->clone(); - } + // Change the internal destination set of the + // message so it knows which destinations this + // link is responsible for. + net_msg_ptr = safe_cast<NetworkMessage*>(msg_ptr.get()); + net_msg_ptr->getInternalDestination() = + output_link_destinations[i]; - // Change the internal destination set of the - // message so it knows which destinations this - // link is responsible for. - net_msg_ptr = safe_cast<NetworkMessage*>(msg_ptr.get()); - net_msg_ptr->getInternalDestination() = - output_link_destinations[i]; + // Enqeue msg + DPRINTF(RubyNetwork, "Switch: %d enqueuing net msg from " + "inport[%d][%d] to outport [%d][%d] time: %lld.\n", + m_switch_id, incoming, vnet, outgoing, vnet, + g_eventQueue_ptr->getTime()); - // Enqeue msg - DPRINTF(RubyNetwork, "Switch: %d enqueuing net msg from " - "inport[%d][%d] to outport [%d][%d] time: %lld.\n", - m_switch_id, incoming, vnet, outgoing, vnet, - g_eventQueue_ptr->getTime()); + m_out[outgoing][vnet]->enqueue(msg_ptr); + } - m_out[outgoing][vnet]->enqueue(msg_ptr); + // Dequeue msg + m_in[incoming][vnet]->pop(); + m_pending_message_count[vnet]--; } - - // Dequeue msg - m_in[incoming][vnet]->pop(); } } } } void +PerfectSwitch::storeEventInfo(int info) +{ + m_pending_message_count[info]++; +} + +void PerfectSwitch::printStats(std::ostream& out) const { out << "PerfectSwitch printStats" << endl; diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh b/src/mem/ruby/network/simple/PerfectSwitch.hh index a7e577df0..cd0219fd9 100644 --- a/src/mem/ruby/network/simple/PerfectSwitch.hh +++ b/src/mem/ruby/network/simple/PerfectSwitch.hh @@ -69,6 +69,7 @@ class PerfectSwitch : public Consumer int getOutLinks() const { return m_out.size(); } void wakeup(); + void storeEventInfo(int info); void printStats(std::ostream& out) const; void clearStats(); @@ -92,6 +93,7 @@ class PerfectSwitch : public Consumer int m_round_robin_start; int m_wakeups_wo_switch; SimpleNetwork* m_network_ptr; + std::vector<int> m_pending_message_count; }; inline std::ostream& diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh index ff94fdd40..7fcfabe9c 100644 --- a/src/mem/ruby/slicc_interface/Message.hh +++ b/src/mem/ruby/slicc_interface/Message.hh @@ -57,6 +57,8 @@ class Message : public RefCounted virtual Message* clone() const = 0; virtual void print(std::ostream& out) const = 0; + virtual void setIncomingLink(int) {} + virtual void setVnet(int) {} void setDelayedCycles(const int& cycles) { m_DelayedCycles = cycles; } const int& getDelayedCycles() const {return m_DelayedCycles;} diff --git a/src/mem/ruby/slicc_interface/NetworkMessage.hh b/src/mem/ruby/slicc_interface/NetworkMessage.hh index 082481e05..a8f9c625b 100644 --- a/src/mem/ruby/slicc_interface/NetworkMessage.hh +++ b/src/mem/ruby/slicc_interface/NetworkMessage.hh @@ -82,9 +82,16 @@ class NetworkMessage : public Message virtual void print(std::ostream& out) const = 0; + int getIncomingLink() const { return incoming_link; } + void setIncomingLink(int link) { incoming_link = link; } + int getVnet() const { return vnet; } + void setVnet(int net) { vnet = net; } + private: NetDest m_internal_dest; bool m_internal_dest_valid; + int incoming_link; + int vnet; }; inline std::ostream& diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index c336a43bc..003f1c701 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -342,7 +342,6 @@ RubyPort::M5Port::hitCallback(PacketPtr pkt) // the RubyPort itself must convert it to a response. // accessPhysMem = false; - pkt->makeAtomicResponse(); } } else { // diff --git a/src/python/m5/main.py b/src/python/m5/main.py index cd139ccb3..23a012166 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -61,8 +61,6 @@ add_option('-C', "--copyright", action="store_true", default=False, help="Show full copyright information") add_option('-R', "--readme", action="store_true", default=False, help="Show the readme") -add_option('-N', "--release-notes", action="store_true", default=False, - help="Show the release notes") # Options for configuring the base simulator add_option('-d', "--outdir", metavar="DIR", default="m5out", @@ -207,13 +205,6 @@ def main(): print info.README print - if options.release_notes: - done = True - print 'Release Notes:' - print - print info.RELEASE_NOTES - print - if options.trace_help: done = True check_tracing() diff --git a/src/sim/root.cc b/src/sim/root.cc index 1dc9b6058..d51fcbda6 100644 --- a/src/sim/root.cc +++ b/src/sim/root.cc @@ -108,7 +108,18 @@ Root::Root(RootParams *p) : SimObject(p), _enabled(false), assert(_root == NULL); _root = this; lastTime.setTimer(); - timeSyncEnable(p->time_sync_enable); +} + +void +Root::initState() +{ + timeSyncEnable(params()->time_sync_enable); +} + +void +Root::loadState(Checkpoint *cp) +{ + timeSyncEnable(params()->time_sync_enable); } Root * diff --git a/src/sim/root.hh b/src/sim/root.hh index 2beced9d4..76a508c19 100644 --- a/src/sim/root.hh +++ b/src/sim/root.hh @@ -95,7 +95,22 @@ class Root : public SimObject /// Set the threshold for time remaining to spin wait. void timeSyncSpinThreshold(Time newThreshold); - Root(RootParams *p); + typedef RootParams Params; + const Params * + params() const + { + return dynamic_cast<const Params *>(_params); + } + + Root(Params *p); + + /** Schedule the timesync event at loadState() so that curTick is correct + */ + void loadState(Checkpoint *cp); + + /** Schedule the timesync event at initState() when not unserializing + */ + void initState(); }; #endif // __SIM_ROOT_HH__ diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc index d28f335be..44fe7b2e7 100644 --- a/src/sim/serialize.cc +++ b/src/sim/serialize.cc @@ -201,6 +201,23 @@ arrayParamOut(ostream &os, const string &name, const vector<T> ¶m) os << "\n"; } +template <class T> +void +arrayParamOut(ostream &os, const string &name, const list<T> ¶m) +{ + typename list<T>::const_iterator it = param.begin(); + + os << name << "="; + if (param.size() > 0) + showParam(os, *it); + it++; + while (it != param.end()) { + os << " "; + showParam(os, *it); + it++; + } + os << "\n"; +} template <class T> void @@ -326,6 +343,37 @@ arrayParamIn(Checkpoint *cp, const string §ion, } } +template <class T> +void +arrayParamIn(Checkpoint *cp, const string §ion, + const string &name, list<T> ¶m) +{ + string str; + if (!cp->find(section, name, str)) { + fatal("Can't unserialize '%s:%s'\n", section, name); + } + param.clear(); + + vector<string> tokens; + tokenize(tokens, str, ' '); + + for (vector<string>::size_type i = 0; i < tokens.size(); i++) { + T scalar_value = 0; + if (!parseParam(tokens[i], scalar_value)) { + string err("could not parse \""); + + err += str; + err += "\""; + + fatal(err); + } + + // assign parsed value to vector + param.push_back(scalar_value); + } +} + + void objParamIn(Checkpoint *cp, const string §ion, const string &name, SimObject * ¶m) @@ -356,7 +404,13 @@ arrayParamOut(ostream &os, const string &name, \ const vector<type> ¶m); \ template void \ arrayParamIn(Checkpoint *cp, const string §ion, \ - const string &name, vector<type> ¶m); + const string &name, vector<type> ¶m); \ +template void \ +arrayParamOut(ostream &os, const string &name, \ + const list<type> ¶m); \ +template void \ +arrayParamIn(Checkpoint *cp, const string §ion, \ + const string &name, list<type> ¶m); INSTANTIATE_PARAM_TEMPLATES(char) INSTANTIATE_PARAM_TEMPLATES(signed char) diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh index 5ea632ea4..6be8ce3b6 100644 --- a/src/sim/serialize.hh +++ b/src/sim/serialize.hh @@ -70,6 +70,10 @@ void arrayParamOut(std::ostream &os, const std::string &name, const std::vector<T> ¶m); template <class T> +void arrayParamOut(std::ostream &os, const std::string &name, + const std::list<T> ¶m); + +template <class T> void arrayParamIn(Checkpoint *cp, const std::string §ion, const std::string &name, T *param, unsigned size); @@ -77,6 +81,10 @@ template <class T> void arrayParamIn(Checkpoint *cp, const std::string §ion, const std::string &name, std::vector<T> ¶m); +template <class T> +void arrayParamIn(Checkpoint *cp, const std::string §ion, + const std::string &name, std::list<T> ¶m); + void objParamIn(Checkpoint *cp, const std::string §ion, const std::string &name, SimObject * ¶m); diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh index 1512bc0fa..253f12072 100644 --- a/src/sim/tlb.hh +++ b/src/sim/tlb.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2011 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2006 The Regents of The University of Michigan * All rights reserved. * @@ -64,6 +76,12 @@ class BaseTLB : public SimObject virtual ~Translation() {} + /** + * Signal that the translation has been delayed due to a hw page table + * walk. + */ + virtual void markDelayed() = 0; + /* * The memory for this object may be dynamically allocated, and it may * be responsible for cleaning itself up which will happen in this diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index f1bb733dc..eb7a280f4 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -96,6 +96,12 @@ for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports): # cpus[i].test = ruby_port.port cpus[i].functional = system.funcmem.port + + # + # Since the memtester is incredibly bursty, increase the deadlock + # threshold to 1 million cycles + # + ruby_port.deadlock_threshold = 1000000 # ----------------------- # run simulation diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini index 503c61f1c..9a2e60122 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout index 3dbb4b0b4..d3a2b5cda 100755 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -1067,4 +1067,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 772390499500 because target called exit() +Exiting @ tick 766217705000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt index 05b37528b..cc548bebc 100644 --- a/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 168346 # Simulator instruction rate (inst/s) -host_mem_usage 232444 # Number of bytes of host memory used -host_seconds 9631.89 # Real time elapsed on the host -host_tick_rate 80190939 # Simulator tick rate (ticks/s) +host_inst_rate 123498 # Simulator instruction rate (inst/s) +host_mem_usage 236748 # Number of bytes of host memory used +host_seconds 13129.74 # Real time elapsed on the host +host_tick_rate 58357436 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493982 # Number of instructions simulated -sim_seconds 0.772390 # Number of seconds simulated -sim_ticks 772390499500 # Number of ticks simulated +sim_seconds 0.766218 # Number of seconds simulated +sim_ticks 766217705000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 126254885 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 126894033 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 169776992 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 171183773 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5933287 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 126894073 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 126894073 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 8003535 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 180455810 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 180455810 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 107161579 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3710402 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 7534042 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1511501895 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.072770 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.173458 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1432274296 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.132111 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.344268 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 505879323 33.47% 33.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 677452709 44.82% 78.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 153213861 10.14% 88.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 112394621 7.44% 95.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 32585093 2.16% 98.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 19016713 1.26% 99.27% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 5421676 0.36% 99.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 1827497 0.12% 99.75% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3710402 0.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 536173455 37.44% 37.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 547306108 38.21% 75.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 130197340 9.09% 84.74% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 136647601 9.54% 94.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 42821104 2.99% 97.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 22915800 1.60% 98.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 3037283 0.21% 99.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 5641563 0.39% 99.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 7534042 0.53% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1511501895 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1432274296 # Number of insts commited each cycle system.cpu.commit.COM:count 1621493982 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,422 +44,422 @@ system.cpu.commit.COM:loads 419042125 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 607228182 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5933318 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 8003567 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 227874068 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 729601482 # The number of squashed insts skipped by commit system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated -system.cpu.cpi 0.952690 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.952690 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 326327666 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10363.748203 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7391.735933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 326125265 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2097633000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000620 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 202401 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 1725 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1483344000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000615 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 200676 # number of ReadReq MSHR misses +system.cpu.cpi 0.945076 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.945076 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 330979138 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10103.492713 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.561618 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 330761084 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2203107000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000659 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 218054 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 3264 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1536513500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000649 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 214790 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 19667.198248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10021.451346 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 186945733 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 24393698000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006591 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1240324 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 994745 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2461058000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.001305 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 245579 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 19459.417847 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10004.386505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 186948986 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 24072681495 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.006574 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1237071 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 986986 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2501946999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 250085 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 15789.833755 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1149.728625 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 16007.596007 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 1113.654359 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 29234 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 461600000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 473104500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 514513723 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 18362.010085 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 8838.897043 # average overall mshr miss latency -system.cpu.dcache.demand_hits 513070998 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 26491331000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002804 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1442725 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 996470 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3944402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.000867 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 446255 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 519165195 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18057.409841 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency +system.cpu.dcache.demand_hits 517710070 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 26275788495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002803 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1455125 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 990250 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4038460499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000895 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 464875 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.101758 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 514513723 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 18362.010085 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 8838.897043 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999796 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.162912 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 519165195 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18057.409841 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 513070998 # number of overall hits -system.cpu.dcache.overall_miss_latency 26491331000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002804 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1442725 # number of overall misses -system.cpu.dcache.overall_mshr_hits 996470 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3944402000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.000867 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 446255 # number of overall MSHR misses +system.cpu.dcache.overall_hits 517710070 # number of overall hits +system.cpu.dcache.overall_miss_latency 26275788495 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002803 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1455125 # number of overall misses +system.cpu.dcache.overall_mshr_hits 990250 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4038460499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000895 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 464875 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 442158 # number of replacements -system.cpu.dcache.sampled_refs 446254 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 460779 # number of replacements +system.cpu.dcache.sampled_refs 464875 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.101758 # Cycle average of tags in use -system.cpu.dcache.total_refs 513070998 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 331552000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 398281 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 176333648 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 1886463332 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 320369444 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 981528406 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 33063147 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 33270397 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 126894073 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 119630706 # Number of cache lines fetched -system.cpu.fetch.Cycles 1056772647 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 432705 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1026147627 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 9324994 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.082144 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 119630706 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 126254885 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.664267 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1544565042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.230490 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.292215 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.162912 # Cycle average of tags in use +system.cpu.dcache.total_refs 517710070 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 317835000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 411288 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 610366395 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 2477699501 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 436378814 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 330621598 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 99870091 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 54907489 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 180455810 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 168863429 # Number of cache lines fetched +system.cpu.fetch.Cycles 400342229 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 931185 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1404767222 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 14936403 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.117758 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 168863429 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 169776992 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.916689 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1532144387 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.666939 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.038798 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 522111775 33.80% 33.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 496583342 32.15% 65.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 273451194 17.70% 83.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224891951 14.56% 98.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8280335 0.54% 98.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1557581 0.10% 98.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 722 0.00% 98.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8665 0.00% 98.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 17679477 1.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1134818986 74.07% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25831687 1.69% 75.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14383456 0.94% 76.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13631087 0.89% 77.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 30570437 2.00% 79.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 20250642 1.32% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34285955 2.24% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 37728615 2.46% 85.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 220643522 14.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1544565042 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 119630706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37171.926007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35433.712121 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 119629787 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 34161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000008 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 919 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 127 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 28063500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 792 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1532144387 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 12 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 168863429 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 34706.050695 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35310.841984 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 168862206 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42445500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1223 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 356 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 30614500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 867 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 151047.710859 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 194766.096886 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 119630706 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37171.926007 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35433.712121 # average overall mshr miss latency -system.cpu.icache.demand_hits 119629787 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 34161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000008 # miss rate for demand accesses -system.cpu.icache.demand_misses 919 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 127 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 28063500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 792 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 168863429 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 34706.050695 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency +system.cpu.icache.demand_hits 168862206 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42445500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses +system.cpu.icache.demand_misses 1223 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 30614500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 867 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.352078 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 721.055018 # Average occupied blocks per context -system.cpu.icache.overall_accesses 119630706 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37171.926007 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35433.712121 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.386137 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 790.808810 # Average occupied blocks per context +system.cpu.icache.overall_accesses 168863429 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 34706.050695 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 119629787 # number of overall hits -system.cpu.icache.overall_miss_latency 34161000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000008 # miss rate for overall accesses -system.cpu.icache.overall_misses 919 # number of overall misses -system.cpu.icache.overall_mshr_hits 127 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 28063500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 792 # number of overall MSHR misses +system.cpu.icache.overall_hits 168862206 # number of overall hits +system.cpu.icache.overall_miss_latency 42445500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses +system.cpu.icache.overall_misses 1223 # number of overall misses +system.cpu.icache.overall_mshr_hits 356 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 30614500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 867 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.sampled_refs 792 # Sample count of references to valid blocks. +system.cpu.icache.replacements 11 # number of replacements +system.cpu.icache.sampled_refs 867 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 721.055018 # Cycle average of tags in use -system.cpu.icache.total_refs 119629787 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 790.808810 # Cycle average of tags in use +system.cpu.icache.total_refs 168862206 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 215958 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 108586362 # Number of branches executed +system.cpu.idleCycles 291024 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 111314295 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.090888 # Inst execution rate -system.cpu.iew.EXEC:refs 624680336 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 190102881 # Number of stores executed +system.cpu.iew.EXEC:rate 1.203312 # Inst execution rate +system.cpu.iew.EXEC:refs 636104355 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 191312994 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2506292363 # num instructions consuming a value -system.cpu.iew.WB:count 1680860111 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.529936 # average fanout of values written-back +system.cpu.iew.WB:consumers 2089450315 # num instructions consuming a value +system.cpu.iew.WB:count 1839101566 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.684612 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1328173821 # num instructions producing a value -system.cpu.iew.WB:rate 1.088090 # insts written-back per cycle -system.cpu.iew.WB:sent 1681411195 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6122546 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1253236 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 492554241 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 66 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3215387 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 210212351 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1849358863 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 434577455 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8332046 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1685183738 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 18939 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1430463261 # num instructions producing a value +system.cpu.iew.WB:rate 1.200117 # insts written-back per cycle +system.cpu.iew.WB:sent 1842290775 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 8145736 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1415270 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 617903270 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 633937 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 251132554 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2351086206 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 444791361 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11969895 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1843997360 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 60905 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 33063147 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 72665 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 99870091 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 117847 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 29234 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 108234700 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 16690 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 29753 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 113796852 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 8470 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3968261 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 13 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 73512116 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 22026294 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3968261 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 2078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 6120468 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 4148897019 # number of integer regfile reads -system.cpu.int_regfile_writes 1677631671 # number of integer regfile writes -system.cpu.ipc 1.049659 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.049659 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24157467 1.43% 1.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1040578234 61.44% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.87% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 438214492 25.88% 88.75% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 190565591 11.25% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 6921754 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 21 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 198861145 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 62946497 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6921754 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3700861 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4444875 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3233304065 # number of integer regfile reads +system.cpu.int_regfile_writes 1832324218 # number of integer regfile writes +system.cpu.ipc 1.058116 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.058116 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 27128947 1.46% 1.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186880889 63.95% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 450365179 24.27% 89.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 191592240 10.32% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1693515784 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 252744 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000149 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1855967255 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4437489 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002391 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 40 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 250833 99.24% 99.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1871 0.74% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 118316 2.67% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.67% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3486899 78.58% 81.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 832274 18.76% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1544565042 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.096435 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.983023 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1532144387 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211353 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.177271 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 454758636 29.44% 29.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 667103033 43.19% 72.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 281275831 18.21% 90.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 105166888 6.81% 97.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 33264638 2.15% 99.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2679834 0.17% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 311387 0.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 3979 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 816 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 466354124 30.44% 30.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 601647548 39.27% 69.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 244545222 15.96% 85.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 139808763 9.13% 94.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 60228260 3.93% 98.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 13792665 0.90% 99.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 4627487 0.30% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 960857 0.06% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 179461 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1544565042 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.096282 # Inst issue rate -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1669611057 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 4931850619 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1680860109 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 2080058032 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1849358797 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1693515784 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 66 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 226765112 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1273 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 584800312 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 245580 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34276.926221 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.745964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 186864 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2012604000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.239091 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 58716 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1824643500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.239091 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 58716 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 201467 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34133.939861 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31003.577487 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 169042 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1106793000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.160944 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32425 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1005291000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.160944 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32425 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 398281 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 398281 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::total 1532144387 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.211123 # Inst issue rate +system.cpu.iq.fp_alu_accesses 18 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 33 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1833275779 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5248603279 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1839101554 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3087460502 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2351086128 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1855967255 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 729454588 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 86926 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1543114171 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 250094 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.888228 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31092.455043 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 191260 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2021765000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.235248 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 58834 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829293500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235248 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 58834 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 215648 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34134.880348 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.967489 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 182552 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1129728000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.153472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 33096 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1026173500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153472 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 33096 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 411288 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 411288 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.844642 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.099303 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 447047 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34226.056330 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.070769 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 355906 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3119397000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.203873 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 91141 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 465742 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34281.442402 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 373812 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3151493000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.197384 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 91930 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2829934500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.203873 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 91141 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2855467000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.197384 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 91930 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.058867 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.490866 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1928.938344 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16084.711341 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 447047 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34226.056330 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.070769 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.059053 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.491352 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1935.054426 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 16100.609355 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 465742 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34281.442402 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 355906 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3119397000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.203873 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 91141 # number of overall misses +system.cpu.l2cache.overall_hits 373812 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3151493000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.197384 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 91930 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2829934500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.203873 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 91141 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2855467000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.197384 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 91930 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 72873 # number of replacements -system.cpu.l2cache.sampled_refs 88473 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 73661 # number of replacements +system.cpu.l2cache.sampled_refs 89262 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18013.649684 # Cycle average of tags in use -system.cpu.l2cache.total_refs 428620 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18035.663781 # Cycle average of tags in use +system.cpu.l2cache.total_refs 455174 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 58405 # number of writebacks -system.cpu.memDep0.conflictingLoads 289036318 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 113016383 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 492554241 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210212351 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 864820574 # number of misc regfile reads -system.cpu.numCycles 1544781000 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 58542 # number of writebacks +system.cpu.memDep0.conflictingLoads 537232404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 219207458 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 617903270 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 251132554 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 931505074 # number of misc regfile reads +system.cpu.numCycles 1532435411 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 55578139 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 175534951 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 65710608 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 361165681 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 36822801 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 5668050381 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 1874385455 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1871676358 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 968560202 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 33063147 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 126195704 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 253681708 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 5668050349 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 2169 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 67 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 186996608 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 71 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3357159543 # The number of ROB reads -system.cpu.rob.rob_writes 3732197477 # The number of ROB writes -system.cpu.timesIdled 45108 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 318243703 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 499996104 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 107154792 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 44 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5827367622 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2403532061 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2403383901 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 306300874 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 99870091 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 450439326 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 785389251 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5827367526 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 3041 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 87 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 739921776 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3775835718 # The number of ROB reads +system.cpu.rob.rob_writes 4802062478 # The number of ROB writes +system.cpu.timesIdled 45517 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 48 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 1dd3bb0d2..bb6395625 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:38:48 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index ce8635d17..5b839ec88 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1066510 # Simulator instruction rate (inst/s) -host_mem_usage 223440 # Number of bytes of host memory used -host_seconds 1520.37 # Real time elapsed on the host -host_tick_rate 634049597 # Simulator tick rate (ticks/s) +host_inst_rate 2470310 # Simulator instruction rate (inst/s) +host_mem_usage 224012 # Number of bytes of host memory used +host_seconds 656.39 # Real time elapsed on the host +host_tick_rate 1468620897 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 0.963993 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_int_insts 1621354493 # number of integer instructions -system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_mem_refs 607228182 # number of memory refs diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 889c6868b..920574653 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:35 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 46400c920..120240c59 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 685934 # Simulator instruction rate (inst/s) -host_mem_usage 231240 # Number of bytes of host memory used -host_seconds 2363.92 # Real time elapsed on the host -host_tick_rate 762824620 # Simulator tick rate (ticks/s) +host_inst_rate 1667736 # Simulator instruction rate (inst/s) +host_mem_usage 231728 # Number of bytes of host memory used +host_seconds 972.27 # Real time elapsed on the host +host_tick_rate 1854683738 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1621493983 # Number of instructions simulated sim_seconds 1.803259 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1621493983 # Number of instructions executed system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses system.cpu.num_int_insts 1621354493 # number of integer instructions -system.cpu.num_int_register_reads 4883555465 # number of times the integer registers were read +system.cpu.num_int_register_reads 3953866002 # number of times the integer registers were read system.cpu.num_int_register_writes 1617994650 # number of times the integer registers were written system.cpu.num_load_insts 419042125 # Number of load instructions system.cpu.num_mem_refs 607228182 # number of memory refs diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 1d5316147..30d3a70e1 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:04:06 -M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch -M5 started Feb 7 2011 01:04:09 +M5 compiled Feb 8 2011 00:58:27 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:30 M5 executing on burrito -command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-atomic +command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112051463500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 1cabd6a2d..113af673f 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2329852 # Simulator instruction rate (inst/s) -host_mem_usage 370744 # Number of bytes of host memory used -host_seconds 174.53 # Real time elapsed on the host -host_tick_rate 29290692573 # Simulator tick rate (ticks/s) +host_inst_rate 1892986 # Simulator instruction rate (inst/s) +host_mem_usage 370804 # Number of bytes of host memory used +host_seconds 214.81 # Real time elapsed on the host +host_tick_rate 23798444654 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 406624453 # Number of instructions simulated sim_seconds 5.112051 # Number of seconds simulated @@ -341,7 +341,7 @@ system.cpu.num_idle_cycles 9770620811.997942 system.cpu.num_insts 406624453 # Number of instructions executed system.cpu.num_int_alu_accesses 391833833 # Number of integer alu accesses system.cpu.num_int_insts 391833833 # number of integer instructions -system.cpu.num_int_register_reads 1007515486 # number of times the integer registers were read +system.cpu.num_int_register_reads 836347867 # number of times the integer registers were read system.cpu.num_int_register_writes 419160860 # number of times the integer registers were written system.cpu.num_load_insts 29720540 # Number of load instructions system.cpu.num_mem_refs 38133606 # number of memory refs diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 6d191e20f..628b3cd61 100755 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:04:06 -M5 revision 8e058bca28fb 7927 default qtip tip x86fsstats.patch -M5 started Feb 7 2011 01:04:09 +M5 compiled Feb 8 2011 00:58:27 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:30 M5 executing on burrito -command line: build/X86_FS/m5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-simple-timing +command line: build/X86_FS/m5.fast -d build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/fast/long/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5187506658000 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index b4552b7b7..091a2e71c 100644 --- a/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/long/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1700985 # Simulator instruction rate (inst/s) -host_mem_usage 367580 # Number of bytes of host memory used -host_seconds 155.42 # Real time elapsed on the host -host_tick_rate 33377224644 # Simulator tick rate (ticks/s) +host_inst_rate 1227876 # Simulator instruction rate (inst/s) +host_mem_usage 367348 # Number of bytes of host memory used +host_seconds 215.31 # Real time elapsed on the host +host_tick_rate 24093749418 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 264367743 # Number of instructions simulated sim_seconds 5.187507 # Number of seconds simulated @@ -395,7 +395,7 @@ system.cpu.num_idle_cycles 9771315874.126116 system.cpu.num_insts 264367743 # Number of instructions executed system.cpu.num_int_alu_accesses 249584659 # Number of integer alu accesses system.cpu.num_int_insts 249584659 # number of integer instructions -system.cpu.num_int_register_reads 660399505 # number of times the integer registers were read +system.cpu.num_int_register_reads 543556622 # number of times the integer registers were read system.cpu.num_int_register_writes 266062505 # number of times the integer registers were written system.cpu.num_load_insts 14817593 # Number of load instructions system.cpu.num_mem_refs 23178416 # number of memory refs diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini index 8e006cde5..31cbafe2a 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout index bf0cc96de..41587c0af 100755 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 170680631000 because target called exit() +Exiting @ tick 98622214000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt index 3db6ff161..33b45551d 100644 --- a/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 83481 # Simulator instruction rate (inst/s) -host_mem_usage 366872 # Number of bytes of host memory used -host_seconds 3332.41 # Real time elapsed on the host -host_tick_rate 51218385 # Simulator tick rate (ticks/s) +host_inst_rate 133029 # Simulator instruction rate (inst/s) +host_mem_usage 371192 # Number of bytes of host memory used +host_seconds 2091.22 # Real time elapsed on the host +host_tick_rate 47160241 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192519 # Number of instructions simulated -sim_seconds 0.170681 # Number of seconds simulated -sim_ticks 170680631000 # Number of ticks simulated +sim_seconds 0.098622 # Number of seconds simulated +sim_ticks 98622214000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 50810617 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 51416767 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44152407 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 44769192 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4328981 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 51416803 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 51416803 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 3292099 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 50608102 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 50608102 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 29309710 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2488105 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 11603540 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 321793097 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.864507 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.425920 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 176948364 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.572168 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.280995 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 183622049 57.06% 57.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 75902754 23.59% 80.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 27223254 8.46% 89.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 17908154 5.57% 94.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 5463718 1.70% 96.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 3630830 1.13% 97.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 4674698 1.45% 98.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 879535 0.27% 99.23% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2488105 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 83964580 47.45% 47.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 36146762 20.43% 67.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 16087394 9.09% 76.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 14069173 7.95% 84.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 7224288 4.08% 89.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 2649535 1.50% 90.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 3731341 2.11% 92.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1471751 0.83% 93.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 11603540 6.56% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 321793097 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 176948364 # Number of insts commited each cycle system.cpu.commit.COM:count 278192519 # Number of instructions committed system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,421 +44,430 @@ system.cpu.commit.COM:loads 90779388 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 122219139 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4328992 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 3292117 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 111464423 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 130955012 # The number of squashed insts skipped by commit system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated -system.cpu.cpi 1.227068 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.227068 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 82779625 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 5978.815311 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2941.059048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 80764514 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 12047976500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.024343 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 2015111 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 45360 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5793154000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.023795 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1969751 # number of ReadReq MSHR misses +system.cpu.cpi 0.709021 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.709021 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 69458873 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 6142.707591 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3039.983703 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 67343989 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12991114000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.030448 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 2114884 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 142693 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5995428500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.028394 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1972191 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 20696.077989 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 15440.513442 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 31284703 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3208885500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.004932 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 155048 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48629 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1643164000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.003385 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 106419 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_avg_miss_latency 17842.235128 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17696.947420 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 31210017 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 4098968045 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.007307 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 229734 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 123609 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1878088545 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.003376 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 106125 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3358.823529 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 53.969218 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.avg_refs 47.420176 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 285500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 114219376 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 7030.296858 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3581.748123 # average overall mshr miss latency -system.cpu.dcache.demand_hits 112049217 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15256862000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.019000 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2170159 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 93989 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7436318000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.018177 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2076170 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 100898624 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 7289.068857 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency +system.cpu.dcache.demand_hits 98554006 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17090082045 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.023237 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2344618 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 266302 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7873517045 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.020598 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2078316 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995143 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4076.104755 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 114219376 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 7030.296858 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3581.748123 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.994974 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4075.414607 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 100898624 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 7289.068857 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 112049217 # number of overall hits -system.cpu.dcache.overall_miss_latency 15256862000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.019000 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2170159 # number of overall misses -system.cpu.dcache.overall_mshr_hits 93989 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7436318000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.018177 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2076170 # number of overall MSHR misses +system.cpu.dcache.overall_hits 98554006 # number of overall hits +system.cpu.dcache.overall_miss_latency 17090082045 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.023237 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2344618 # number of overall misses +system.cpu.dcache.overall_mshr_hits 266302 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7873517045 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.020598 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2078316 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2072073 # number of replacements -system.cpu.dcache.sampled_refs 2076169 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2074218 # number of replacements +system.cpu.dcache.sampled_refs 2078314 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.104755 # Cycle average of tags in use -system.cpu.dcache.total_refs 112049217 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 66009760000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 1440063 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 922031 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 437195268 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 92021485 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 228705655 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 19453848 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 143926 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 51416803 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 39245397 # Number of cache lines fetched -system.cpu.fetch.Cycles 242939967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 793923 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 249694241 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 9845420 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.150623 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 39245397 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50810617 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.731466 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 341246945 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.321737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.251135 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4075.414607 # Cycle average of tags in use +system.cpu.dcache.total_refs 98554015 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 40655663000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 1442059 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 21837286 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 443283148 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 77587406 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 75762450 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 19022168 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 1761222 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 50608102 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 34652495 # Number of cache lines fetched +system.cpu.fetch.Cycles 82344495 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 326035 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 259681215 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3883025 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.256576 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 34652495 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 44152407 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.316545 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 195970532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.323843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.188074 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 105340577 30.87% 30.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 115413940 33.82% 64.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 47580781 13.94% 78.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 58732555 17.21% 95.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7189604 2.11% 97.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6451059 1.89% 99.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 527277 0.15% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 932 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10220 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 116145210 59.27% 59.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6750085 3.44% 62.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3016102 1.54% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 8362073 4.27% 68.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7646936 3.90% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6348764 3.24% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 9080088 4.63% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8246058 4.21% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 30375216 15.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 341246945 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 44 # number of floating regfile reads -system.cpu.fp_regfile_writes 31 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 39245397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37208.490566 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35316.192560 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 39244337 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 39441000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1060 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 146 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32279000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 914 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 195970532 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 75 # number of floating regfile reads +system.cpu.fp_regfile_writes 41 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 34652495 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35675.242356 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35201.684836 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 34651154 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 47840500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 1341 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 35518500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 1009 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 42936.911379 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 34376.144841 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 39245397 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37208.490566 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35316.192560 # average overall mshr miss latency -system.cpu.icache.demand_hits 39244337 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 39441000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses -system.cpu.icache.demand_misses 1060 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 146 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32279000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000023 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 914 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 34652495 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35675.242356 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency +system.cpu.icache.demand_hits 34651154 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 47840500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000039 # miss rate for demand accesses +system.cpu.icache.demand_misses 1341 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 35518500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 1009 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.360466 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 738.235227 # Average occupied blocks per context -system.cpu.icache.overall_accesses 39245397 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37208.490566 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35316.192560 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.392466 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 803.770978 # Average occupied blocks per context +system.cpu.icache.overall_accesses 34652495 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35675.242356 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 39244337 # number of overall hits -system.cpu.icache.overall_miss_latency 39441000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses -system.cpu.icache.overall_misses 1060 # number of overall misses -system.cpu.icache.overall_mshr_hits 146 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32279000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000023 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 914 # number of overall MSHR misses +system.cpu.icache.overall_hits 34651154 # number of overall hits +system.cpu.icache.overall_miss_latency 47840500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000039 # miss rate for overall accesses +system.cpu.icache.overall_misses 1341 # number of overall misses +system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 35518500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 1009 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 37 # number of replacements -system.cpu.icache.sampled_refs 914 # Sample count of references to valid blocks. +system.cpu.icache.replacements 60 # number of replacements +system.cpu.icache.sampled_refs 1008 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 738.235227 # Cycle average of tags in use -system.cpu.icache.total_refs 39244337 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 803.770978 # Cycle average of tags in use +system.cpu.icache.total_refs 34651154 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 114318 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 31118985 # Number of branches executed +system.cpu.idleCycles 1273897 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 33755681 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.940576 # Inst execution rate -system.cpu.iew.EXEC:refs 137464023 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 32172568 # Number of stores executed +system.cpu.iew.EXEC:rate 1.719732 # Inst execution rate +system.cpu.iew.EXEC:refs 143271490 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 33964004 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 361852587 # num instructions consuming a value -system.cpu.iew.WB:count 317781549 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.623035 # average fanout of values written-back +system.cpu.iew.WB:consumers 356152066 # num instructions consuming a value +system.cpu.iew.WB:count 334303723 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.713943 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 225446782 # num instructions producing a value -system.cpu.iew.WB:rate 0.930924 # insts written-back per cycle -system.cpu.iew.WB:sent 318008427 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 5390321 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 197365 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 131280417 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 455 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3671049 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 41039188 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 389592858 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 105291455 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12266571 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 321076071 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2799 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 254272214 # num instructions producing a value +system.cpu.iew.WB:rate 1.694870 # insts written-back per cycle +system.cpu.iew.WB:sent 336664522 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3987132 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 754395 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 138835558 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 663120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 42750154 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 409142439 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 109307486 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6572046 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 339207523 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 2275 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1704 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 19453848 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 10507 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 78833 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 19022168 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 104797 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 22405068 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 64376 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 14565 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 39666706 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 30063 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5520980 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 2668 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 40501029 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 9599437 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5520980 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 16897 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5373424 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 754340794 # number of integer regfile reads -system.cpu.int_regfile_writes 286169707 # number of integer regfile writes -system.cpu.ipc 0.814950 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.814950 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16700 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 193455065 58.03% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 58.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 107162338 32.15% 90.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 32708524 9.81% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 1469253 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 2742 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 48056170 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 11310403 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1469253 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 865481 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3121651 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 577634708 # number of integer regfile reads +system.cpu.int_regfile_writes 302216415 # number of integer regfile writes +system.cpu.ipc 1.410395 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.410395 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16702 0.00% 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 200471700 57.98% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 57.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 110857049 32.06% 90.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 34434103 9.96% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 333342642 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 98152 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000294 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 345779569 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 4109732 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011885 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 15 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 97651 99.49% 99.50% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 486 0.50% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 26819 0.65% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 3817756 92.90% 93.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 265157 6.45% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 341246945 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.976837 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.032280 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 195970532 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.764447 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.745109 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 143332703 42.00% 42.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 98734149 28.93% 70.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 68142120 19.97% 90.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 26890607 7.88% 98.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 3089152 0.91% 99.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1054470 0.31% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 2951 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 576 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 217 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 63955785 32.64% 32.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 38956843 19.88% 52.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 30997952 15.82% 68.33% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 27554899 14.06% 82.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 19728653 10.07% 92.46% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 8783605 4.48% 96.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 3191043 1.63% 98.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 2230786 1.14% 99.71% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 570966 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 341246945 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.976510 # Inst issue rate -system.cpu.iq.fp_alu_accesses 55 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 110 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 49 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 110 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 333424039 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 1008030271 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 317781500 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 504991584 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 389592403 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 333342642 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 455 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 109882124 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 237362106 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 106419 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34277.831445 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31049.336758 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 63976 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 1454854000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.398829 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 42443 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317827000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398829 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 42443 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1970665 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34310.495712 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31007.530164 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1936270 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1180109500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.017453 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 34395 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1066504000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017453 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 34395 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 1440063 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 1440063 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.iq.ISSUE:issued_per_cycle::total 195970532 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.753051 # Inst issue rate +system.cpu.iq.fp_alu_accesses 110 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 83 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 263 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 349872489 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 891669703 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 334303640 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 540919004 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 409141974 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 345779569 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 130872312 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 30525 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 221868127 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 106126 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34139.167845 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.412541 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 63706 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 1448183500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.399714 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 42420 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317158500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.399714 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 42420 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1973197 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34279.521718 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31013.978995 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1938824 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1178290000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.017420 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 34373 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1066043500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017420 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 34373 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 1442058 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 1442058 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2176.470588 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 42.751383 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 42.835533 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 37000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2077084 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34292.452953 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.622869 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2000246 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2634963500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.036993 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 76838 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 2079323 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34201.991067 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2002530 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 2626473500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.036932 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 76793 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2384331000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.036993 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 76838 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2383202000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.036932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 76793 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.192442 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.349126 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 6305.950681 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 11440.167306 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2077084 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34292.452953 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.622869 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.185144 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.337522 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 6066.784489 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 11059.931141 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2079323 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34201.991067 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2000246 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2634963500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.036993 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 76838 # number of overall misses +system.cpu.l2cache.overall_hits 2002530 # number of overall hits +system.cpu.l2cache.overall_miss_latency 2626473500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.036932 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 76793 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2384331000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.036993 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 76838 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2383202000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.036932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 76793 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 49392 # number of replacements -system.cpu.l2cache.sampled_refs 77392 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 49342 # number of replacements +system.cpu.l2cache.sampled_refs 77347 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17746.117987 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3308615 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17126.715630 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3313200 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 29474 # number of writebacks -system.cpu.memDep0.conflictingLoads 22358679 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3757180 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 131280417 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 41039188 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 204301939 # number of misc regfile reads -system.cpu.numCycles 341361263 # number of cpu cycles simulated +system.cpu.l2cache.writebacks 29450 # number of writebacks +system.cpu.memDep0.conflictingLoads 87882428 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16100005 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 138835558 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42750154 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 218323859 # number of misc regfile reads +system.cpu.numCycles 197244429 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 486743 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 6557218 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 12249 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 98511117 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 368076 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 1292599643 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 423407319 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 377348250 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 222275258 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 19453848 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 514692 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 129004058 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 291 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 1292599352 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 5287 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 454 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 779091 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 708961934 # The number of ROB reads -system.cpu.rob.rob_writes 799263493 # The number of ROB writes -system.cpu.timesIdled 5627 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 228138 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 83203716 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 14824029 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 1059543178 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 431467970 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 388798641 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 71280917 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 19022168 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 15900092 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 140454449 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 574 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 1059542604 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 6421 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 38067869 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 574492355 # The number of ROB reads +system.cpu.rob.rob_writes 837321831 # The number of ROB writes +system.cpu.timesIdled 40675 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 444 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index e76d60819..2aa2852be 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index bcab65c40..aacdb2309 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 722489 # Simulator instruction rate (inst/s) -host_mem_usage 358012 # Number of bytes of host memory used -host_seconds 385.05 # Real time elapsed on the host -host_tick_rate 438776725 # Simulator tick rate (ticks/s) +host_inst_rate 1568972 # Simulator instruction rate (inst/s) +host_mem_usage 358500 # Number of bytes of host memory used +host_seconds 177.31 # Real time elapsed on the host +host_tick_rate 952856596 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.168950 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_int_insts 278186228 # number of integer instructions -system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index 0b92276cc..56b5fe9df 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index cf6f03e98..e90dea7b7 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 424375 # Simulator instruction rate (inst/s) -host_mem_usage 365728 # Number of bytes of host memory used -host_seconds 655.54 # Real time elapsed on the host -host_tick_rate 564440982 # Simulator tick rate (ticks/s) +host_inst_rate 1018906 # Simulator instruction rate (inst/s) +host_mem_usage 366224 # Number of bytes of host memory used +host_seconds 273.03 # Real time elapsed on the host +host_tick_rate 1355197592 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 278192520 # Number of instructions simulated sim_seconds 0.370011 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 278192520 # Number of instructions executed system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses system.cpu.num_int_insts 278186228 # number of integer instructions -system.cpu.num_int_register_reads 855210512 # number of times the integer registers were read +system.cpu.num_int_register_reads 685043114 # number of times the integer registers were read system.cpu.num_int_register_writes 248344166 # number of times the integer registers were written system.cpu.num_load_insts 90779388 # Number of load instructions system.cpu.num_mem_refs 122219139 # number of memory refs diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini index 8363ae747..da344ea4b 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/20.parser/ref/x86/linux/o3-timing/simout index 4d3b5f29b..696087afc 100755 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout @@ -5,16 +5,16 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: *****************************info: Increasing stack size by one page. -******************** + Reading the dictionary files: ***********************info: Increasing stack size by one page. +************************** 58924 words stored in 3784810 bytes @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 817002039000 because target called exit() +Exiting @ tick 610952992000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt index c39e8dfae..070979214 100644 --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,475 +1,475 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 160923 # Simulator instruction rate (inst/s) -host_mem_usage 240360 # Number of bytes of host memory used -host_seconds 9501.35 # Real time elapsed on the host -host_tick_rate 85987979 # Simulator tick rate (ticks/s) +host_inst_rate 130186 # Simulator instruction rate (inst/s) +host_mem_usage 285488 # Number of bytes of host memory used +host_seconds 11733.03 # Real time elapsed on the host +host_tick_rate 52071207 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1528988756 # Number of instructions simulated -sim_seconds 0.817002 # Number of seconds simulated -sim_ticks 817002039000 # Number of ticks simulated +sim_insts 1527476062 # Number of instructions simulated +sim_seconds 0.610953 # Number of seconds simulated +sim_ticks 610952992000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 197674461 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 215147546 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 220273443 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 239822696 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 17901021 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 215739151 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 215739151 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 16691862 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 254901320 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 254901320 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 149758588 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8186576 # number cycles where commit BW limit reached +system.cpu.commit.COM:branches 149616585 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 33918821 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1552269342 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.985002 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.301395 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1083369873 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.409930 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.877801 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 694185983 44.72% 44.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 509617235 32.83% 77.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 176087126 11.34% 88.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 105147186 6.77% 95.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 31137095 2.01% 97.67% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 11224991 0.72% 98.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 11192282 0.72% 99.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 5490868 0.35% 99.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 8186576 0.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 454928288 41.99% 41.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 282557908 26.08% 68.07% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 120287774 11.10% 79.18% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 105365409 9.73% 88.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 40172301 3.71% 92.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 27676804 2.55% 95.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 11415389 1.05% 96.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 7047179 0.65% 96.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 33918821 3.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1552269342 # Number of insts commited each cycle -system.cpu.commit.COM:count 1528988756 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 1083369873 # Number of insts commited each cycle +system.cpu.commit.COM:count 1527476062 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. -system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions. -system.cpu.commit.COM:loads 384102160 # Number of loads committed +system.cpu.commit.COM:int_insts 1526804920 # Number of committed integer instructions. +system.cpu.commit.COM:loads 383724495 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 533262345 # Number of memory references committed +system.cpu.commit.COM:refs 532790180 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 17902344 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions +system.cpu.commit.branchMispredicts 16726957 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1527476062 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 459109010 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1528988756 # Number of Instructions Simulated -system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated -system.cpu.cpi 1.068683 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.068683 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 352008034 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14100.976079 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8499.435037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 350035037 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 27821183500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.005605 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1972997 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 237485 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 14750871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.004930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1735512 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 15942.157352 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12645.445755 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 148213244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 15096537500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.006349 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 946957 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 159966 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 9951852000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005276 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 786991 # number of WriteReq MSHR misses +system.cpu.commit.commitSquashedInsts 841443918 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1527476062 # Number of Instructions Simulated +system.cpu.committedInsts_total 1527476062 # Number of Instructions Simulated +system.cpu.cpi 0.799951 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.799951 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 320046346 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15794.070061 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8150.695480 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 317137092 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 45948961500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.009090 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 2909254 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1183970 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 14062264500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005391 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1725284 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 149065701 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 23554.108597 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18051.470496 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147419835 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 38766906500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.011041 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1645866 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 608291 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 18729754500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006961 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1037575 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 197.709284 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 185.704246 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 501168235 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14698.081203 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency -system.cpu.dcache.demand_hits 498248281 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 42917721000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005826 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2919954 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 397451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 24702723500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2522503 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 469112047 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18597.944291 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency +system.cpu.dcache.demand_hits 464556927 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 84715868000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.009710 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4555120 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1792261 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 32792019000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005890 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2762859 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997749 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4086.780222 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 501168235 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14698.081203 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9792.941178 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.998028 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4087.922333 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 469112047 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18597.944291 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 498248281 # number of overall hits -system.cpu.dcache.overall_miss_latency 42917721000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005826 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2919954 # number of overall misses -system.cpu.dcache.overall_mshr_hits 397451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 24702723500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2522503 # number of overall MSHR misses +system.cpu.dcache.overall_hits 464556927 # number of overall hits +system.cpu.dcache.overall_miss_latency 84715868000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.009710 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4555120 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1792261 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 32792019000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005890 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2762859 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 2516044 # number of replacements -system.cpu.dcache.sampled_refs 2520140 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 2504740 # number of replacements +system.cpu.dcache.sampled_refs 2508836 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4086.780222 # Cycle average of tags in use -system.cpu.dcache.total_refs 498255076 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 3876881000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 2224034 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 25470243 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 2119227193 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 403203369 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 1116867689 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 71636028 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 6728041 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 215739151 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 165973622 # Number of cache lines fetched -system.cpu.fetch.Cycles 1190006834 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 2725815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 1144873460 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 1839 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 29822694 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.132031 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 165973622 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 197674461 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.700655 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1623905370 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.336094 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.273592 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4087.922333 # Cycle average of tags in use +system.cpu.dcache.total_refs 465901497 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2529382000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2229751 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 215366555 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 2516935544 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 437043857 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 404205746 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 113949773 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 26753715 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 254901320 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 190461812 # Number of cache lines fetched +system.cpu.fetch.Cycles 445534669 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3068431 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1374706338 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 85274 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 18549281 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.208610 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 190461812 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 220273443 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.125051 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1197319646 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.144693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.178811 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 477535637 29.41% 29.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 564706157 34.77% 64.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 259330057 15.97% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 261180842 16.08% 96.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 22809127 1.40% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 31399021 1.93% 99.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 502829 0.03% 99.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12 0.00% 99.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6441688 0.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 756027205 63.14% 63.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34054494 2.84% 65.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36745231 3.07% 69.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33767076 2.82% 71.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21459245 1.79% 73.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 40493114 3.38% 77.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 45860411 3.83% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 35731624 2.98% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 193181246 16.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1623905370 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 10 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 165973622 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 22741.617211 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 19372.661290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 165966882 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 153278500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000041 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 6740 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 540 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120110500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000037 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 6200 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 1197319646 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 31 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 190461812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 6527.954910 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3419.281975 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 190192396 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1758735500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001415 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 269416 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1570 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 915841000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 267846 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 49795.025203 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 17699.832480 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 165973622 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 22741.617211 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency -system.cpu.icache.demand_hits 165966882 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 153278500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000041 # miss rate for demand accesses -system.cpu.icache.demand_misses 6740 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 540 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120110500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000037 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 6200 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 190461812 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 6527.954910 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency +system.cpu.icache.demand_hits 190192396 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1758735500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001415 # miss rate for demand accesses +system.cpu.icache.demand_misses 269416 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1570 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 915841000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001406 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 267846 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.436573 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 894.100654 # Average occupied blocks per context -system.cpu.icache.overall_accesses 165973622 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 22741.617211 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 19372.661290 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.466021 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 954.411836 # Average occupied blocks per context +system.cpu.icache.overall_accesses 190461812 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 6527.954910 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 165966882 # number of overall hits -system.cpu.icache.overall_miss_latency 153278500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000041 # miss rate for overall accesses -system.cpu.icache.overall_misses 6740 # number of overall misses -system.cpu.icache.overall_mshr_hits 540 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120110500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 6200 # number of overall MSHR misses +system.cpu.icache.overall_hits 190192396 # number of overall hits +system.cpu.icache.overall_miss_latency 1758735500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001415 # miss rate for overall accesses +system.cpu.icache.overall_misses 269416 # number of overall misses +system.cpu.icache.overall_mshr_hits 1570 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 915841000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001406 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 267846 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1750 # number of replacements -system.cpu.icache.sampled_refs 3333 # Sample count of references to valid blocks. +system.cpu.icache.replacements 9298 # number of replacements +system.cpu.icache.sampled_refs 10745 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 894.100654 # Cycle average of tags in use -system.cpu.icache.total_refs 165966819 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 954.411836 # Cycle average of tags in use +system.cpu.icache.total_refs 190184700 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 10098709 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 158001976 # Number of branches executed +system.cpu.icache.writebacks 3 # number of writebacks +system.cpu.idleCycles 24586339 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 175611349 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.044762 # Inst execution rate -system.cpu.iew.EXEC:refs 586795750 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 160862585 # Number of stores executed +system.cpu.iew.EXEC:rate 1.537639 # Inst execution rate +system.cpu.iew.EXEC:refs 604612823 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 164362000 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 2114014731 # num instructions consuming a value -system.cpu.iew.WB:count 1694146367 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.583880 # average fanout of values written-back +system.cpu.iew.WB:consumers 2150205320 # num instructions consuming a value +system.cpu.iew.WB:count 1865910107 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.666196 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1234331323 # num instructions producing a value -system.cpu.iew.WB:rate 1.036807 # insts written-back per cycle -system.cpu.iew.WB:sent 1697627373 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 18573506 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 6103126 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 508224738 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 579 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 12080656 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 194089353 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 1988097398 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 425933165 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 26013466 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1707144682 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 381189 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1432458045 # num instructions producing a value +system.cpu.iew.WB:rate 1.527049 # insts written-back per cycle +system.cpu.iew.WB:sent 1872952311 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 18187438 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9702727 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 598780500 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 6555 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2427132 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 227725972 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2368916953 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 440250823 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 24902522 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1878850199 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 999062 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 10588 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 71636028 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 847228 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 48995 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 113949773 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1501929 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 72909425 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 277837 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 119150872 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 153037 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 11954619 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 832 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 124122578 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 44929168 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 11954619 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 280770 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 18292736 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 3876226209 # number of integer regfile reads -system.cpu.int_regfile_writes 1582892637 # number of integer regfile writes -system.cpu.ipc 0.935731 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.935731 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1927969 0.11% 0.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1131725915 65.30% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 435582288 25.13% 90.54% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 163921976 9.46% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 1905759 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1230 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 215056005 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 78660287 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 1905759 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2718790 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 15468648 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 3097184079 # number of integer regfile reads +system.cpu.int_regfile_writes 1741804464 # number of integer regfile writes +system.cpu.ipc 1.250077 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.250077 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2283854 0.12% 0.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1286143659 67.56% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 446588315 23.46% 91.14% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 168736893 8.86% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1733158148 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1029171 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000594 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1903752721 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 12019370 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006314 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 182 0.02% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 466697 45.35% 45.36% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 562292 54.64% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1063366 8.85% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 7508013 62.47% 71.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 3447991 28.69% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1623905370 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.067278 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.066518 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1197319646 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.590012 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.576110 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 608633589 37.48% 37.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 503635145 31.01% 68.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 353739534 21.78% 90.28% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 117719188 7.25% 97.53% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 32883027 2.02% 99.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 6737765 0.41% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 234496 0.01% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 322546 0.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 80 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 380569061 31.79% 31.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 297509781 24.85% 56.63% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 210374930 17.57% 74.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 147240855 12.30% 86.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 95168176 7.95% 94.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 42314918 3.53% 97.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 17818883 1.49% 99.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 5974413 0.50% 99.97% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 348629 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1623905370 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.060682 # Inst issue rate -system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 48 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 1732259326 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 5091250901 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 1694146357 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 2453039449 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 1988096819 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1733158148 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 452995728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1010995901 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 789062 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34275.179377 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.682665 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 541538 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 8483929500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.313694 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 247524 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7673660500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313694 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 247524 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1734408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34153.383782 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31001.108327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1401925 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 11355419500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.191698 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 332483 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10307341500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191698 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 332483 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 2863 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 24.346581 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.148228 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_hits 70 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_miss_latency 68000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_rate 0.975550 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 2793 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 86589000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.975550 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 2793 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 2224034 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 2224034 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::total 1197319646 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.558019 # Inst issue rate +system.cpu.iq.fp_alu_accesses 59 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 119 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 7970 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 1913488178 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 5017400189 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 1865910076 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 3209512631 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 2368910398 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1903752721 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 6555 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 838752495 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 555850 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6002 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1472792375 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 786848 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34255.494728 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.453653 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 539884 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 8459874000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.313865 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 246964 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7656243000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 246964 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1732679 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34171.480760 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.917505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 1415970 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 10822415500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.182786 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 316709 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 9818903000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.182786 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 316709 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 256943 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 40.077896 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.030576 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits 1216 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_latency 10249000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate 0.995267 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses 255727 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7928312000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.995267 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses 255727 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 2229754 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 2229754 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.356881 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 5.404070 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 2523470 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34205.361315 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1943463 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 19839349000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.229845 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 580007 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 2519527 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34208.290090 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 1955854 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 19282289500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.223722 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 563673 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17981002000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.229845 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 580007 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 17475146000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.223722 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 563673 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.233067 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.421257 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 7637.149597 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13803.753842 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 2523470 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34205.361315 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.353432 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.213694 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.433705 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 7002.339473 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14211.631717 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 2519527 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34208.290090 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1943463 # number of overall hits -system.cpu.l2cache.overall_miss_latency 19839349000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.229845 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 580007 # number of overall misses +system.cpu.l2cache.overall_hits 1955854 # number of overall hits +system.cpu.l2cache.overall_miss_latency 19282289500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.223722 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 563673 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17981002000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.229845 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 580007 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 17475146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.223722 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 563673 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 569254 # number of replacements -system.cpu.l2cache.sampled_refs 588327 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 553099 # number of replacements +system.cpu.l2cache.sampled_refs 571950 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 21440.903439 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3151598 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 469235659000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 411363 # number of writebacks -system.cpu.memDep0.conflictingLoads 151128770 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 47539398 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 508224738 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194089353 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 947795380 # number of misc regfile reads -system.cpu.numCycles 1634004079 # number of cpu cycles simulated +system.cpu.l2cache.tagsinuse 21213.971190 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3090858 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 329890014000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 404346 # number of writebacks +system.cpu.memDep0.conflictingLoads 432040536 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 167867809 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 598780500 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 227724252 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 1024928879 # number of misc regfile reads +system.cpu.numCycles 1221905985 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 11181498 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 8162354 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 430755417 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1988994 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 37 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 6064799926 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2072679155 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1965930252 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1095363349 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 71636028 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 14962968 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 538631225 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 168 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 6064799758 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 6110 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 566 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 21122292 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 563 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 3532180532 # The number of ROB reads -system.cpu.rob.rob_writes 4048956705 # The number of ROB writes -system.cpu.timesIdled 351337 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:BlockCycles 64472267 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1425688721 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 52544368 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 479786184 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 82632603 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 8428 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 5772028874 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2456264739 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2290118455 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 385614091 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 113949773 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 153477395 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 864429734 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 19762 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 5772009112 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 19936 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2550 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 360051799 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 2561 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 3418371032 # The number of ROB reads +system.cpu.rob.rob_writes 4851844016 # The number of ROB writes +system.cpu.timesIdled 625791 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 551 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini index fdc891c59..adfcd9b98 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -61,7 +61,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index 70ab31a10..e27ac87ea 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 11 2011 23:35:10 +M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip +M5 started Feb 11 2011 23:35:13 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index 836ed1519..afe5ef235 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 904614 # Simulator instruction rate (inst/s) -host_mem_usage 227300 # Number of bytes of host memory used -host_seconds 1690.21 # Real time elapsed on the host -host_tick_rate 523739013 # Simulator tick rate (ticks/s) +host_inst_rate 1866600 # Simulator instruction rate (inst/s) +host_mem_usage 231212 # Number of bytes of host memory used +host_seconds 819.13 # Real time elapsed on the host +host_tick_rate 1080693863 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 0.885229 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini index 4c1fe374d..00b5b00f6 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/config.ini @@ -161,7 +161,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index 9e491e500..1e739aa16 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:36:47 +M5 compiled Feb 11 2011 23:35:10 +M5 revision c3deaa585dd3 7949 default qtip resforflagsstats.patch tip +M5 started Feb 11 2011 23:35:13 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 2cd323573..dbe8c165b 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 738382 # Simulator instruction rate (inst/s) -host_mem_usage 235020 # Number of bytes of host memory used -host_seconds 2070.73 # Real time elapsed on the host -host_tick_rate 801036637 # Simulator tick rate (ticks/s) +host_inst_rate 1188316 # Simulator instruction rate (inst/s) +host_mem_usage 238940 # Number of bytes of host memory used +host_seconds 1286.69 # Real time elapsed on the host +host_tick_rate 1289149200 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1528988757 # Number of instructions simulated sim_seconds 1.658730 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 1528988757 # Number of instructions executed system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses system.cpu.num_int_insts 1528317615 # number of integer instructions -system.cpu.num_int_register_reads 4418676175 # number of times the integer registers were read +system.cpu.num_int_register_reads 3581460239 # number of times the integer registers were read system.cpu.num_int_register_writes 1427299027 # number of times the integer registers were written system.cpu.num_load_insts 384102160 # Number of load instructions system.cpu.num_mem_refs 533262345 # number of memory refs diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index d26ecb349..5d00e7290 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 27953 # Simulator instruction rate (inst/s) -host_mem_usage 1692040 # Number of bytes of host memory used -host_seconds 3160.33 # Real time elapsed on the host -host_tick_rate 13823537 # Simulator tick rate (ticks/s) +host_inst_rate 106274 # Simulator instruction rate (inst/s) +host_mem_usage 1642336 # Number of bytes of host memory used +host_seconds 831.26 # Real time elapsed on the host +host_tick_rate 52555245 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340674 # Number of instructions simulated sim_seconds 0.043687 # Number of seconds simulated diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index 228e6ab0c..403cb4d0b 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index a0361e843..9e70ccdd1 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1421831 # Simulator instruction rate (inst/s) -host_mem_usage 223380 # Number of bytes of host memory used -host_seconds 3296.36 # Real time elapsed on the host -host_tick_rate 863379215 # Simulator tick rate (ticks/s) +host_inst_rate 2540540 # Simulator instruction rate (inst/s) +host_mem_usage 223860 # Number of bytes of host memory used +host_seconds 1844.83 # Real time elapsed on the host +host_tick_rate 1542694185 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 2.846007 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 4686862651 # Number of instructions executed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_int_insts 4686862580 # number of integer instructions -system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index 2ae184132..65c0a8840 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 21d2dce98..59534c87e 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 980837 # Simulator instruction rate (inst/s) -host_mem_usage 231100 # Number of bytes of host memory used -host_seconds 4778.43 # Real time elapsed on the host -host_tick_rate 1239642391 # Simulator tick rate (ticks/s) +host_inst_rate 1546064 # Simulator instruction rate (inst/s) +host_mem_usage 231584 # Number of bytes of host memory used +host_seconds 3031.48 # Real time elapsed on the host +host_tick_rate 1954011316 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4686862651 # Number of instructions simulated sim_seconds 5.923548 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 4686862651 # Number of instructions executed system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses system.cpu.num_int_insts 4686862580 # number of integer instructions -system.cpu.num_int_register_reads 14008880122 # number of times the integer registers were read +system.cpu.num_int_register_reads 11558008181 # number of times the integer registers were read system.cpu.num_int_register_writes 4679057393 # number of times the integer registers were written system.cpu.num_load_insts 1239184749 # Number of load instructions system.cpu.num_mem_refs 1677713086 # number of memory refs diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index bb16b8b96..e197ea18e 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 25888 # Simulator instruction rate (inst/s) -host_mem_usage 1480704 # Number of bytes of host memory used -host_seconds 3550.03 # Real time elapsed on the host -host_tick_rate 11417230 # Simulator tick rate (ticks/s) +host_inst_rate 105929 # Simulator instruction rate (inst/s) +host_mem_usage 1434716 # Number of bytes of host memory used +host_seconds 867.59 # Real time elapsed on the host +host_tick_rate 46717114 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903057 # Number of instructions simulated sim_seconds 0.040531 # Number of seconds simulated diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 78a8cbd6c..f69fd4da6 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -488,7 +488,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index e89403a2f..2ac976df6 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:12 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +27,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 127560542500 because target called exit() +122 123 124 Exiting @ tick 108875474000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 58c1a1259..a77afc849 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 87424 # Simulator instruction rate (inst/s) -host_mem_usage 240332 # Number of bytes of host memory used -host_seconds 2532.06 # Real time elapsed on the host -host_tick_rate 50378144 # Simulator tick rate (ticks/s) +host_inst_rate 92938 # Simulator instruction rate (inst/s) +host_mem_usage 245208 # Number of bytes of host memory used +host_seconds 2381.84 # Real time elapsed on the host +host_tick_rate 45710653 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363017 # Number of instructions simulated -sim_seconds 0.127561 # Number of seconds simulated -sim_ticks 127560542500 # Number of ticks simulated +sim_seconds 0.108875 # Number of seconds simulated +sim_ticks 108875474000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 16939138 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 19067543 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 19725800 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 22620341 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 3582609 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 19223942 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19223942 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 3050205 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 25317132 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 25317132 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 12326943 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 324452 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2257656 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 243992167 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.907255 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.057266 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 193712128 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.142742 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.492040 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 97637775 40.02% 40.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 102801930 42.13% 82.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 24473335 10.03% 92.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 10688182 4.38% 96.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 6438517 2.64% 99.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 836047 0.34% 99.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 523551 0.21% 99.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 268378 0.11% 99.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 324452 0.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 76077426 39.27% 39.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 72463860 37.41% 76.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 18818378 9.71% 86.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 12600057 6.50% 92.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 5960288 3.08% 95.98% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 2688234 1.39% 97.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 1804943 0.93% 98.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 1041286 0.54% 98.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2257656 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 243992167 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 193712128 # Number of insts commited each cycle system.cpu.commit.COM:count 221363017 # Number of instructions committed system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,423 +44,424 @@ system.cpu.commit.COM:loads 56649590 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 77165306 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 3582617 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 3050238 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 70151117 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 180173936 # The number of squashed insts skipped by commit system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 1.152501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.152501 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 51727133 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34247.563353 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34193.055556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 51726620 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 17569000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 513 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 153 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 12309500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses +system.cpu.cpi 0.983683 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.983683 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 50495037 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33300.295858 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34031.250000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 50494361 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 22511000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 676 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 292 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 13068000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26394.870828 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35294.285714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 20510427 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 139972000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 5303 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 3728 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 55588500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1575 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 26250.708416 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35437.100894 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 20508672 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 185277500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000344 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 7058 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 5492 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 55494500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1566 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 37331.807235 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 36411.811795 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 72242863 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 27087.517194 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35089.405685 # average overall mshr miss latency -system.cpu.dcache.demand_hits 72237047 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 157541000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000081 # miss rate for demand accesses -system.cpu.dcache.demand_misses 5816 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 3881 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 67898000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 71010767 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 26866.886475 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency +system.cpu.dcache.demand_hits 71003033 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 207788500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000109 # miss rate for demand accesses +system.cpu.dcache.demand_misses 7734 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5784 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 68562500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1935 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1950 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.336997 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1380.340507 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 72242863 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 27087.517194 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35089.405685 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.340706 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1395.531138 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 71010767 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 26866.886475 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 72237047 # number of overall hits -system.cpu.dcache.overall_miss_latency 157541000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000081 # miss rate for overall accesses -system.cpu.dcache.overall_misses 5816 # number of overall misses -system.cpu.dcache.overall_mshr_hits 3881 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 67898000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 71003033 # number of overall hits +system.cpu.dcache.overall_miss_latency 207788500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000109 # miss rate for overall accesses +system.cpu.dcache.overall_misses 7734 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5784 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 68562500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1935 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1950 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 46 # number of replacements -system.cpu.dcache.sampled_refs 1935 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 48 # number of replacements +system.cpu.dcache.sampled_refs 1950 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1380.340507 # Cycle average of tags in use -system.cpu.dcache.total_refs 72237047 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1395.531138 # Cycle average of tags in use +system.cpu.dcache.total_refs 71003033 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 9 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5656231 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 309852988 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 53029625 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 184220573 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 11003980 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 1085738 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 19223942 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 20440935 # Number of cache lines fetched -system.cpu.fetch.Cycles 196264127 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 182297 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 184675827 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 4455378 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.075352 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 20440935 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 16939138 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.723875 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 254996147 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.239017 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.348981 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.writebacks 10 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 58788191 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 426377378 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 67892396 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 61042516 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 23949638 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 5989025 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 25317132 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 27858568 # Number of cache lines fetched +system.cpu.fetch.Cycles 70494302 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 451015 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 267008364 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 3227425 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.116266 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 27858568 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 19725800 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.226210 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 217661766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.006543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.224025 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66307953 26.00% 26.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 121646972 47.71% 73.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37731127 14.80% 88.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20479784 8.03% 96.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1948325 0.76% 97.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108960 0.43% 97.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1062530 0.42% 98.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1340 0.00% 98.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4709156 1.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 148998369 68.45% 68.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3780164 1.74% 70.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3170889 1.46% 71.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4293321 1.97% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4655999 2.14% 75.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4463846 2.05% 77.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5161555 2.37% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3267808 1.50% 81.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39869815 18.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254996147 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 3212472 # number of floating regfile reads -system.cpu.fp_regfile_writes 2049220 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 20440935 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 25661.556820 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22374.875175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 20435488 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 139778500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000266 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 5447 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 440 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 112031000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000245 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 5007 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 217661766 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 3513078 # number of floating regfile reads +system.cpu.fp_regfile_writes 2177890 # number of floating regfile writes +system.cpu.icache.ReadReq_accesses 27858568 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 25516.664059 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.816190 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 27852177 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 163077000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000229 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 6391 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1005 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120995500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000193 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 5386 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4082.198961 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5171.217416 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 20440935 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 25661.556820 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22374.875175 # average overall mshr miss latency -system.cpu.icache.demand_hits 20435488 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 139778500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000266 # miss rate for demand accesses -system.cpu.icache.demand_misses 5447 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 440 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 112031000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000245 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 5007 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 27858568 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 25516.664059 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency +system.cpu.icache.demand_hits 27852177 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 163077000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000229 # miss rate for demand accesses +system.cpu.icache.demand_misses 6391 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1005 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120995500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000193 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 5386 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.746987 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1529.828433 # Average occupied blocks per context -system.cpu.icache.overall_accesses 20440935 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 25661.556820 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22374.875175 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.783470 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1604.546925 # Average occupied blocks per context +system.cpu.icache.overall_accesses 27858568 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 25516.664059 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 20435488 # number of overall hits -system.cpu.icache.overall_miss_latency 139778500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000266 # miss rate for overall accesses -system.cpu.icache.overall_misses 5447 # number of overall misses -system.cpu.icache.overall_mshr_hits 440 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 112031000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000245 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 5007 # number of overall MSHR misses +system.cpu.icache.overall_hits 27852177 # number of overall hits +system.cpu.icache.overall_miss_latency 163077000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000229 # miss rate for overall accesses +system.cpu.icache.overall_misses 6391 # number of overall misses +system.cpu.icache.overall_mshr_hits 1005 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120995500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000193 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 5386 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 3101 # number of replacements -system.cpu.icache.sampled_refs 5006 # Sample count of references to valid blocks. +system.cpu.icache.replacements 3428 # number of replacements +system.cpu.icache.sampled_refs 5386 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1529.828433 # Cycle average of tags in use -system.cpu.icache.total_refs 20435488 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1604.546925 # Cycle average of tags in use +system.cpu.icache.total_refs 27852177 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 124939 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 13366188 # Number of branches executed +system.cpu.idleCycles 89183 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 15799905 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.954963 # Inst execution rate -system.cpu.iew.EXEC:refs 84717237 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 21535662 # Number of stores executed +system.cpu.iew.EXEC:rate 1.276995 # Inst execution rate +system.cpu.iew.EXEC:refs 89573185 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 22888685 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 389337537 # num instructions consuming a value -system.cpu.iew.WB:count 241459353 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.499412 # average fanout of values written-back +system.cpu.iew.WB:consumers 372933305 # num instructions consuming a value +system.cpu.iew.WB:count 276026292 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.598611 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 194439848 # num instructions producing a value -system.cpu.iew.WB:rate 0.946450 # insts written-back per cycle -system.cpu.iew.WB:sent 242120517 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3656523 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 214895 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 75869162 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1275 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2489008 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 25600521 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 291514094 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 63181575 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4005104 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 243631219 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 25200 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 223241922 # num instructions producing a value +system.cpu.iew.WB:rate 1.267624 # insts written-back per cycle +system.cpu.iew.WB:sent 277033647 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3251135 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 619969 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 106923422 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 171683 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 37463806 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 401512728 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 66684500 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3440679 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 278066855 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 560615 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 11003980 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 40028 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 30447 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 23949638 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 623802 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 11103688 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 71380 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 15985064 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 21414 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 879354 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 44904 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 19219572 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 5084805 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 879354 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 151398 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3505125 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 614135119 # number of integer regfile reads -system.cpu.int_regfile_writes 252115460 # number of integer regfile writes -system.cpu.ipc 0.867678 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.867678 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1180294 0.48% 0.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 158353329 63.95% 64.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 64.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 64.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1520272 0.61% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 64587764 26.08% 91.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 21994664 8.88% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 187512 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 45117 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 50273832 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 16948090 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 187512 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 737658 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2513477 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 514946932 # number of integer regfile reads +system.cpu.int_regfile_writes 284476955 # number of integer regfile writes +system.cpu.ipc 1.016588 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.016588 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1195391 0.42% 0.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 187555358 66.63% 67.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 67.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1589850 0.56% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 67.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 67998663 24.16% 91.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 23168272 8.23% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 247636323 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 40899 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000165 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 281507534 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 2779468 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009874 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 37912 92.70% 92.70% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 2987 7.30% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 58461 2.10% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 2334735 84.00% 86.10% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 386272 13.90% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 254996147 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.971138 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.960460 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 217661766 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.293326 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.357747 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 97493255 38.23% 38.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 86911390 34.08% 72.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 54912481 21.53% 93.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 12234045 4.80% 98.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 3109625 1.22% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 255105 0.10% 99.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 77911 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 2335 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 75328501 34.61% 34.61% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 67045740 30.80% 65.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 37681009 17.31% 82.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 20059185 9.22% 91.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 11722195 5.39% 97.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 3737927 1.72% 99.04% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1378220 0.63% 99.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 597426 0.27% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 111563 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 7 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 254996147 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.970662 # Inst issue rate -system.cpu.iq.fp_alu_accesses 2542426 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 5084249 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2387245 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 3193021 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 243954502 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 745226741 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 239072108 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 358869082 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 291512819 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 247636323 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 1275 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 69673728 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 1298 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 182988092 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34364.012739 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31058.917197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 5 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 53951500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.996825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1570 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48762500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1570 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 5367 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34265.528407 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.178098 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 1970 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 116400000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.632942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3397 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105426500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.632942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3397 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 9 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 9 # number of Writeback hits +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 217661766 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.292796 # Inst issue rate +system.cpu.iq.fp_alu_accesses 2630821 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 5219937 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 2526643 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 5714467 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 280460790 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 778290063 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 273499649 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 575780653 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 401511304 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 281507534 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 179800569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53698 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 375388973 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 1566 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.756410 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 53839500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.996169 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1560 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48902500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996169 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1560 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 5770 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34287.021858 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31043.032787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 2110 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 125490500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.634315 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3660 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 113617500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634315 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3660 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.579412 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.575873 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 6942 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34296.657942 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31042.681699 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1975 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 170351500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.715500 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4967 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 7336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34354.406130 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 2116 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 179330000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.711559 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5220 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 154189000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.715500 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4967 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 162520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.711559 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5220 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.068086 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.074027 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2231.049035 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.015700 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 6942 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34296.657942 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31042.681699 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2425.713909 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.014918 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 7336 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34354.406130 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1975 # number of overall hits -system.cpu.l2cache.overall_miss_latency 170351500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.715500 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4967 # number of overall misses +system.cpu.l2cache.overall_hits 2116 # number of overall hits +system.cpu.l2cache.overall_miss_latency 179330000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.711559 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5220 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 154189000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.715500 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4967 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 162520000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.711559 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5220 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3400 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3664 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2232.064735 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1970 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2426.728827 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2110 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 21807942 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4495847 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 75869162 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 25600521 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 125958118 # number of misc regfile reads +system.cpu.memDep0.conflictingLoads 95035235 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 32152607 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 106923422 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 37463806 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 144601816 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.numCycles 255121086 # number of cpu cycles simulated +system.cpu.numCycles 217750949 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 1303093 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 18951054 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2662460 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 57579297 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 975892 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 963293874 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 304077108 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 331962025 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 180705413 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 11003980 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4387817 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 97598616 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:fp_rename_lookups 7191870 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 956102004 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 16547 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1274 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 8156807 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 1279 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 535181849 # The number of ROB reads -system.cpu.rob.rob_writes 594057529 # The number of ROB writes -system.cpu.timesIdled 2349 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 22087788 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 75841753 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 16619805 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 1071149424 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 415976206 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 437655168 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 58179410 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 23949638 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 40717504 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 203291759 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:fp_rename_lookups 11132052 # Number of floating rename lookups +system.cpu.rename.RENAME:int_rename_lookups 1060017372 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 22407 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1440 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 84366850 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 1310 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 592991425 # The number of ROB reads +system.cpu.rob.rob_writes 827053987 # The number of ROB writes +system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 400 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index 3569c883b..9f05df433 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:36:47 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index da648dcbf..0c54c7d41 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 777141 # Simulator instruction rate (inst/s) -host_mem_usage 230844 # Number of bytes of host memory used -host_seconds 284.84 # Real time elapsed on the host -host_tick_rate 461282227 # Simulator tick rate (ticks/s) +host_inst_rate 1396551 # Simulator instruction rate (inst/s) +host_mem_usage 231332 # Number of bytes of host memory used +host_seconds 158.51 # Real time elapsed on the host +host_tick_rate 828940820 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.131393 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 221363018 # Number of instructions executed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_int_insts 220339607 # number of integer instructions -system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index 31ab1843b..72c0f8f4d 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,13 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index ebc389a3a..bbd74268b 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 446836 # Simulator instruction rate (inst/s) -host_mem_usage 238556 # Number of bytes of host memory used -host_seconds 495.40 # Real time elapsed on the host -host_tick_rate 506580174 # Simulator tick rate (ticks/s) +host_inst_rate 920852 # Simulator instruction rate (inst/s) +host_mem_usage 239052 # Number of bytes of host memory used +host_seconds 240.39 # Real time elapsed on the host +host_tick_rate 1043974445 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 221363018 # Number of instructions simulated sim_seconds 0.250961 # Number of seconds simulated @@ -213,7 +213,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 221363018 # Number of instructions executed system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses system.cpu.num_int_insts 220339607 # number of integer instructions -system.cpu.num_int_register_reads 686620674 # number of times the integer registers were read +system.cpu.num_int_register_reads 567557364 # number of times the integer registers were read system.cpu.num_int_register_writes 232532006 # number of times the integer registers were written system.cpu.num_load_insts 56649590 # Number of load instructions system.cpu.num_mem_refs 77165306 # number of memory refs diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 246665e32..4b7effb4d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 37548 # Simulator instruction rate (inst/s) -host_mem_usage 223436 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 130476959 # Simulator tick rate (ticks/s) +host_inst_rate 76381 # Simulator instruction rate (inst/s) +host_mem_usage 190468 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 264969940 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini index 2d9b77211..c905c3ec3 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -186,6 +195,7 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl0.L1DcacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 1eb50eecd..50b357793 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/13/2011 22:36:30 +Real time: Feb/08/2011 17:31:55 Profiler Stats -------------- -Elapsed_time_in_seconds: 2 -Elapsed_time_in_minutes: 0.0333333 -Elapsed_time_in_hours: 0.000555556 -Elapsed_time_in_days: 2.31481e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 1.2 -Virtual_time_in_minutes: 0.02 -Virtual_time_in_hours: 0.000333333 -Virtual_time_in_days: 1.38889e-05 +Virtual_time_in_seconds: 0.51 +Virtual_time_in_minutes: 0.0085 +Virtual_time_in_hours: 0.000141667 +Virtual_time_in_days: 5.90278e-06 Ruby_current_time: 275313 Ruby_start_time: 0 Ruby_cycles: 275313 -mbytes_resident: 22.0195 -mbytes_total: 156.82 -resident_ratio: 0.140462 +mbytes_resident: 37.0469 +mbytes_total: 210.465 +resident_ratio: 0.176098 ruby_cycles_executed: [ 275314 ] @@ -117,9 +117,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standa Resource Usage -------------- page_size: 4096 -user_time: 1 +user_time: 0 system_time: 0 -page_reclaims: 6300 +page_reclaims: 10681 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout index 4d60ccfef..8e7f8bf86 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 13 2011 22:36:25 -M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip -M5 started Jan 13 2011 22:36:28 -M5 executing on scamorza.cs.wisc.edu +M5 compiled Feb 8 2011 17:31:51 +M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:31:55 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index be34966e1..d0f6b1167 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4080 # Simulator instruction rate (inst/s) -host_mem_usage 160588 # Number of bytes of host memory used -host_seconds 1.57 # Real time elapsed on the host -host_tick_rate 175338 # Simulator tick rate (ticks/s) +host_inst_rate 30108 # Simulator instruction rate (inst/s) +host_mem_usage 215520 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 1293296 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000275 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 275313 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 275313 # Number of busy cycles +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_store_insts 868 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index 756bebd28..cb765942a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -108,32 +117,19 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l1_cntrl0.sequencer.dcache] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=3 @@ -141,7 +137,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -177,14 +173,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -194,13 +189,18 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port [system.ruby.network] type=SimpleNetwork @@ -216,9 +216,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -name=Crossbar num_int_nodes=4 print_config=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index c3c1c36bf..9154f09df 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:35:39 +Real time: Feb/08/2011 17:41:43 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.44 -Virtual_time_in_minutes: 0.00733333 -Virtual_time_in_hours: 0.000122222 -Virtual_time_in_days: 5.09259e-06 +Virtual_time_in_seconds: 0.52 +Virtual_time_in_minutes: 0.00866667 +Virtual_time_in_hours: 0.000144444 +Virtual_time_in_days: 6.01852e-06 Ruby_current_time: 223854 Ruby_start_time: 0 Ruby_cycles: 223854 -mbytes_resident: 34.9609 -mbytes_total: 34.9688 -resident_ratio: 1 +mbytes_resident: 37.1562 +mbytes_total: 210.609 +resident_ratio: 0.176478 ruby_cycles_executed: [ 223855 ] @@ -119,8 +119,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7630 -page_faults: 2184 +page_reclaims: 10696 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.349752 outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 0 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 --- L1Cache --- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index 7e21d792f..c4db03463 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 10:34:54 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:35:39 -M5 executing on svvint09 +M5 compiled Feb 8 2011 17:41:34 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:41:42 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index add084384..e92c6159b 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23717 # Simulator instruction rate (inst/s) -host_mem_usage 212528 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host -host_tick_rate 829037 # Simulator tick rate (ticks/s) +host_inst_rate 26297 # Simulator instruction rate (inst/s) +host_mem_usage 215668 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 918519 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000224 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 223854 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 223854 # Number of busy cycles +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_store_insts 868 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index d5555ef31..d946bdc6f 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -111,9 +120,9 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory N_tokens=2 buffer_size=0 dynamic_timeout_enabled=true @@ -125,24 +134,11 @@ no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l1_cntrl0.sequencer.dcache] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=2 @@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=2 @@ -188,14 +184,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -205,13 +200,18 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port [system.ruby.network] type=SimpleNetwork @@ -227,9 +227,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -name=Crossbar num_int_nodes=4 print_config=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 39236835d..223551577 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, ordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:42:35 +Real time: Feb/08/2011 17:51:05 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.27 -Virtual_time_in_minutes: 0.0045 -Virtual_time_in_hours: 7.5e-05 -Virtual_time_in_days: 3.125e-06 +Virtual_time_in_seconds: 0.4 +Virtual_time_in_minutes: 0.00666667 +Virtual_time_in_hours: 0.000111111 +Virtual_time_in_days: 4.62963e-06 Ruby_current_time: 243131 Ruby_start_time: 0 Ruby_cycles: 243131 -mbytes_resident: 34.8711 -mbytes_total: 34.8789 -resident_ratio: 1 +mbytes_resident: 37.0508 +mbytes_total: 210.492 +resident_ratio: 0.176057 ruby_cycles_executed: [ 243132 ] @@ -70,13 +70,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 286 count: 8464 average: 27.7253 | standard deviation: 60.155 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 215 count: 6414 average: 18.3631 | standard deviation: 49.3028 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 286 count: 1185 average: 71.4084 | standard deviation: 82.7283 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.3029 | standard deviation: 68.2954 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 277 count: 8464 average: 27.7253 | standard deviation: 60.1519 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 205 count: 6414 average: 18.3709 | standard deviation: 49.3264 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 277 count: 1185 average: 71.3747 | standard deviation: 82.6759 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.2913 | standard deviation: 68.2683 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_L1Cache: [binsize: 1 max: 2 count: 7084 average: 2 | standard deviation: 0 | 0 0 7084 ] miss_latency_L2Cache: [binsize: 1 max: 21 count: 79 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 ] -miss_latency_Directory: [binsize: 2 max: 286 count: 1301 average: 168.209 | standard deviation: 14.0495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 2 max: 277 count: 1301 average: 168.209 | standard deviation: 13.9628 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 202 178 134 156 352 4 6 4 3 8 40 31 65 31 60 0 0 0 0 1 2 1 3 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 2 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -89,13 +89,13 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 ave imcomplete_dir_Times: 1300 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 10 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ] -miss_latency_IFETCH_Directory: [binsize: 2 max: 215 count: 636 average: 166.722 | standard deviation: 8.46373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 205 count: 636 average: 166.8 | standard deviation: 8.47154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 60 68 108 171 2 2 1 1 1 19 12 30 22 24 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 38 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 ] -miss_latency_LD_Directory: [binsize: 2 max: 286 count: 487 average: 169.407 | standard deviation: 17.5782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_Directory: [binsize: 2 max: 277 count: 487 average: 169.324 | standard deviation: 17.4353 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 68 53 42 154 2 1 1 2 6 18 12 7 6 29 0 0 0 0 1 1 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 656 average: 2 | standard deviation: 0 | 0 0 656 ] miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 31 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 ] -miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.247 | standard deviation: 18.1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.191 | standard deviation: 18.0345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 50 13 6 27 0 3 2 0 1 3 7 28 3 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -127,8 +127,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7568 -page_faults: 2181 +page_reclaims: 10655 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -197,28 +197,28 @@ links_utilized_percent_switch_3: 0.209297 outgoing_messages_switch_3_link_2_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 646 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 646 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 646 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 646 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100% + system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 646 100% -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 734 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 734 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 734 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 734 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_request_type_LD: 71.5259% - system.l1_cntrl0.sequencer.dcache_request_type_ST: 28.4741% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 71.5259% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 28.4741% - system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 734 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 734 100% --- L1Cache --- - Event Counts - @@ -226,7 +226,7 @@ Load [1185 ] 1185 Ifetch [6414 ] 6414 Store [865 ] 865 Atomic [0 ] 0 -L1_Replacement [1384 ] 1384 +L1_Replacement [1365 ] 1365 Data_Shared [48 ] 48 Data_Owner [0 ] 0 Data_All_Tokens [1332 ] 1332 @@ -356,7 +356,7 @@ M_W Load [102 ] 102 M_W Ifetch [2271 ] 2271 M_W Store [25 ] 25 M_W Atomic [0 ] 0 -M_W L1_Replacement [21 ] 21 +M_W L1_Replacement [8 ] 8 M_W Transient_GETX [0 ] 0 M_W Transient_Local_GETX [0 ] 0 M_W Transient_GETS [0 ] 0 @@ -373,7 +373,7 @@ MM_W Load [21 ] 21 MM_W Ifetch [0 ] 0 MM_W Store [265 ] 265 MM_W Atomic [0 ] 0 -MM_W L1_Replacement [9 ] 9 +MM_W L1_Replacement [3 ] 3 MM_W Transient_GETX [0 ] 0 MM_W Transient_Local_GETX [0 ] 0 MM_W Transient_GETS [0 ] 0 @@ -743,18 +743,18 @@ Memory controller: system.dir_cntrl0.memBuffer: memory_reads: 1301 memory_writes: 241 memory_refreshes: 507 - memory_total_request_delays: 714 - memory_delays_per_request: 0.463035 + memory_total_request_delays: 709 + memory_delays_per_request: 0.459792 memory_delays_in_input_queue: 240 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 474 - memory_stalls_for_bank_busy: 148 + memory_delays_stalled_at_head_of_bank_queue: 469 + memory_stalls_for_bank_busy: 141 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 30 - memory_stalls_for_bus: 278 + memory_stalls_for_arbitration: 33 + memory_stalls_for_bus: 279 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 18 + memory_stalls_for_read_write_turnaround: 16 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 80 17 45 54 54 148 45 17 20 22 33 34 54 53 44 33 40 22 21 28 28 42 73 34 32 25 34 75 101 159 19 56 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index bfe534678..0a28f3bb1 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 10:41:36 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:42:35 -M5 executing on svvint09 +M5 compiled Feb 8 2011 17:50:56 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:51:05 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 4330907be..a8a90f72d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 45740 # Simulator instruction rate (inst/s) -host_mem_usage 212336 # Number of bytes of host memory used +host_inst_rate 46789 # Simulator instruction rate (inst/s) +host_mem_usage 215548 # Number of bytes of host memory used host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 1736538 # Simulator tick rate (ticks/s) +host_tick_rate 1774187 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000243 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 243131 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 243131 # Number of busy cycles +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_store_insts 868 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index a5602ce6c..b25662a67 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -70,6 +79,7 @@ type=Directory_Controller children=directory memBuffer probeFilter buffer_size=0 directory=system.dir_cntrl0.directory +full_bit_dir_enabled=false memBuffer=system.dir_cntrl0.memBuffer memory_controller_latency=2 number_of_TBEs=256 @@ -118,17 +128,18 @@ start_index_bit=6 [system.l1_cntrl0] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L2cacheMemory +L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache +L1IcacheMemory=system.ruby.cpu_ruby_ports.icache L2cacheMemory=system.l1_cntrl0.L2cacheMemory buffer_size=0 cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 @@ -140,12 +151,37 @@ replacement_policy=PSEUDO_LRU size=512 start_index_bit=6 -[system.l1_cntrl0.sequencer] +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.cpu_ruby_ports.physMemPort + +[system.ruby] +type=RubySystem +children=cpu_ruby_ports network profiler tracer +block_size_bytes=64 +clock=1 +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.cpu_ruby_ports] type=RubySequencer children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache +icache=system.ruby.cpu_ruby_ports.icache max_outstanding_requests=16 physmem=system.physmem using_ruby_tester=false @@ -153,7 +189,7 @@ version=0 physMemPort=system.physmem.port[0] port=system.cpu.icache_port system.cpu.dcache_port -[system.l1_cntrl0.sequencer.dcache] +[system.ruby.cpu_ruby_ports.dcache] type=RubyCache assoc=2 latency=2 @@ -161,7 +197,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.ruby.cpu_ruby_ports.icache] type=RubyCache assoc=2 latency=2 @@ -169,39 +205,6 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.l1_cntrl0.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -no_mem_vec=false -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - [system.ruby.network] type=SimpleNetwork children=topology @@ -216,9 +219,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -name=Crossbar num_int_nodes=3 print_config=false diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats index 422144bd2..afe766dd7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 11:09:30 +Real time: Feb/08/2011 17:57:03 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.61 -Virtual_time_in_minutes: 0.0101667 -Virtual_time_in_hours: 0.000169444 -Virtual_time_in_days: 7.06019e-06 +Virtual_time_in_seconds: 0.42 +Virtual_time_in_minutes: 0.007 +Virtual_time_in_hours: 0.000116667 +Virtual_time_in_days: 4.86111e-06 -Ruby_current_time: 207970 +Ruby_current_time: 208400 Ruby_start_time: 0 -Ruby_cycles: 207970 +Ruby_cycles: 208400 -mbytes_resident: 34.3633 -mbytes_total: 206.125 -resident_ratio: 0.166768 +mbytes_resident: 36.6641 +mbytes_total: 209.902 +resident_ratio: 0.174709 -ruby_cycles_executed: [ 207971 ] +ruby_cycles_executed: [ 208401 ] Busy Controller Counts: L1Cache-0:0 @@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.5711 | standard deviation: 54.4023 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8318 | standard deviation: 43.5273 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 320 count: 1185 average: 57.1789 | standard deviation: 73.4856 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9179 | standard deviation: 73.5132 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ] +miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.6219 | standard deviation: 54.4451 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8564 | standard deviation: 43.57 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 327 count: 1185 average: 57.3924 | standard deviation: 73.6654 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9399 | standard deviation: 73.2706 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ] miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ] -miss_latency_L2Cache: [binsize: 1 max: 12 count: 203 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 203 ] -miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.779 | standard deviation: 26.9285 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ] +miss_latency_L2Cache: [binsize: 1 max: 13 count: 203 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 203 ] +miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.975 | standard deviation: 26.6537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 188 166 188 149 272 6 5 3 5 20 2 4 9 1 15 3 1 0 0 1 1 0 3 2 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 3 18 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] imcomplete_dir_Times: 1158 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 65 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 65 ] -miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.578 | standard deviation: 6.13441 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 65 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 65 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.738 | standard deviation: 5.93543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43 102 56 91 98 150 4 2 2 2 14 0 0 5 1 7 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] -miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 105 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 105 ] -miss_latency_LD_Directory: [binsize: 2 max: 320 count: 420 average: 155.183 | standard deviation: 18.008 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 105 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 105 ] +miss_latency_LD_Directory: [binsize: 2 max: 327 count: 420 average: 155.536 | standard deviation: 18.768 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 37 78 73 59 44 91 2 3 1 3 5 2 2 3 0 6 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ] -miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 33 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 33 ] -miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.127 | standard deviation: 61.3036 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 33 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 33 ] +miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.038 | standard deviation: 59.9794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 8 37 38 7 31 0 0 0 0 1 0 2 1 0 2 0 1 0 0 0 1 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 3 17 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -126,7 +126,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 9927 +page_reclaims: 10608 page_faults: 0 swaps: 0 block_inputs: 0 @@ -144,9 +144,9 @@ total_msgs: 20718 total_bytes: 430512 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.111284 - links_utilized_percent_switch_0_link_0: 0.0695653 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.153003 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.111054 + links_utilized_percent_switch_0_link_0: 0.0694218 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.152687 bw: 160000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 @@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.111284 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.158256 - links_utilized_percent_switch_1_link_0: 0.0382507 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.278261 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.157929 + links_utilized_percent_switch_1_link_0: 0.0381718 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.277687 bw: 160000 base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 @@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.158256 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.215632 - links_utilized_percent_switch_2_link_0: 0.278261 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.153003 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.215187 + links_utilized_percent_switch_2_link_0: 0.277687 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.152687 bw: 160000 base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 @@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215632 outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 646 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 646 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.cpu_ruby_ports.icache + system.ruby.cpu_ruby_ports.icache_total_misses: 646 + system.ruby.cpu_ruby_ports.icache_total_demand_misses: 646 + system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% - system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100% + system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 646 100% -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 716 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 716 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 716 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 716 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_request_type_LD: 73.324% - system.l1_cntrl0.sequencer.dcache_request_type_ST: 26.676% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 73.324% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 26.676% - system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 716 100% + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 716 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 1159 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1159 + system.l1_cntrl0.L2cacheMemory_total_misses: 1362 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1362 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 36.2381% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 13.6324% - system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 50.1294% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 38.5463% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 14.0235% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 47.4302% - system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1159 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1362 100% --- L1Cache --- - Event Counts - -Load [1201 ] 1201 -Ifetch [6436 ] 6436 -Store [919 ] 919 +Load [1193 ] 1193 +Ifetch [6425 ] 6425 +Store [892 ] 892 L2_Replacement [1143 ] 1143 L1_to_L2 [1354 ] 1354 Trigger_L2_to_L1D [138 ] 138 @@ -231,6 +231,7 @@ Other_GETX [0 ] 0 Other_GETS [0 ] 0 Merged_GETS [0 ] 0 Other_GETS_No_Mig [0 ] 0 +NC_DMA_GETS [0 ] 0 Invalidate [0 ] 0 Ack [0 ] 0 Shared_Ack [0 ] 0 @@ -253,6 +254,7 @@ I Trigger_L2_to_L1I [0 ] 0 I Other_GETX [0 ] 0 I Other_GETS [0 ] 0 I Other_GETS_No_Mig [0 ] 0 +I NC_DMA_GETS [0 ] 0 I Invalidate [0 ] 0 S Load [0 ] 0 @@ -265,6 +267,7 @@ S Trigger_L2_to_L1I [0 ] 0 S Other_GETX [0 ] 0 S Other_GETS [0 ] 0 S Other_GETS_No_Mig [0 ] 0 +S NC_DMA_GETS [0 ] 0 S Invalidate [0 ] 0 O Load [0 ] 0 @@ -278,6 +281,7 @@ O Other_GETX [0 ] 0 O Other_GETS [0 ] 0 O Merged_GETS [0 ] 0 O Other_GETS_No_Mig [0 ] 0 +O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 M Load [368 ] 368 @@ -291,6 +295,7 @@ M Other_GETX [0 ] 0 M Other_GETS [0 ] 0 M Merged_GETS [0 ] 0 M Other_GETS_No_Mig [0 ] 0 +M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 MM Load [397 ] 397 @@ -304,6 +309,7 @@ MM Other_GETX [0 ] 0 MM Other_GETS [0 ] 0 MM Merged_GETS [0 ] 0 MM Other_GETS_No_Mig [0 ] 0 +MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 IM Load [0 ] 0 @@ -314,6 +320,7 @@ IM L1_to_L2 [0 ] 0 IM Other_GETX [0 ] 0 IM Other_GETS [0 ] 0 IM Other_GETS_No_Mig [0 ] 0 +IM NC_DMA_GETS [0 ] 0 IM Invalidate [0 ] 0 IM Ack [0 ] 0 IM Data [0 ] 0 @@ -327,9 +334,11 @@ SM L1_to_L2 [0 ] 0 SM Other_GETX [0 ] 0 SM Other_GETS [0 ] 0 SM Other_GETS_No_Mig [0 ] 0 +SM NC_DMA_GETS [0 ] 0 SM Invalidate [0 ] 0 SM Ack [0 ] 0 SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 OM Load [0 ] 0 OM Ifetch [0 ] 0 @@ -340,6 +349,7 @@ OM Other_GETX [0 ] 0 OM Other_GETS [0 ] 0 OM Merged_GETS [0 ] 0 OM Other_GETS_No_Mig [0 ] 0 +OM NC_DMA_GETS [0 ] 0 OM Invalidate [0 ] 0 OM Ack [0 ] 0 OM All_acks [0 ] 0 @@ -377,6 +387,7 @@ IS L1_to_L2 [0 ] 0 IS Other_GETX [0 ] 0 IS Other_GETS [0 ] 0 IS Other_GETS_No_Mig [0 ] 0 +IS NC_DMA_GETS [0 ] 0 IS Invalidate [0 ] 0 IS Ack [0 ] 0 IS Shared_Ack [0 ] 0 @@ -403,18 +414,20 @@ OI Other_GETX [0 ] 0 OI Other_GETS [0 ] 0 OI Merged_GETS [0 ] 0 OI Other_GETS_No_Mig [0 ] 0 +OI NC_DMA_GETS [0 ] 0 OI Invalidate [0 ] 0 OI Writeback_Ack [0 ] 0 -MI Load [16 ] 16 -MI Ifetch [22 ] 22 -MI Store [54 ] 54 +MI Load [8 ] 8 +MI Ifetch [11 ] 11 +MI Store [27 ] 27 MI L2_Replacement [0 ] 0 MI L1_to_L2 [0 ] 0 MI Other_GETX [0 ] 0 MI Other_GETS [0 ] 0 MI Merged_GETS [0 ] 0 MI Other_GETS_No_Mig [0 ] 0 +MI NC_DMA_GETS [0 ] 0 MI Invalidate [0 ] 0 MI Writeback_Ack [1143 ] 1143 @@ -426,6 +439,7 @@ II L1_to_L2 [0 ] 0 II Other_GETX [0 ] 0 II Other_GETS [0 ] 0 II Other_GETS_No_Mig [0 ] 0 +II NC_DMA_GETS [0 ] 0 II Invalidate [0 ] 0 II Writeback_Ack [0 ] 0 II Writeback_Nack [0 ] 0 @@ -440,6 +454,7 @@ IT Other_GETX [0 ] 0 IT Other_GETS [0 ] 0 IT Merged_GETS [0 ] 0 IT Other_GETS_No_Mig [0 ] 0 +IT NC_DMA_GETS [0 ] 0 IT Invalidate [0 ] 0 ST Load [0 ] 0 @@ -452,6 +467,7 @@ ST Other_GETX [0 ] 0 ST Other_GETS [0 ] 0 ST Merged_GETS [0 ] 0 ST Other_GETS_No_Mig [0 ] 0 +ST NC_DMA_GETS [0 ] 0 ST Invalidate [0 ] 0 OT Load [0 ] 0 @@ -464,6 +480,7 @@ OT Other_GETX [0 ] 0 OT Other_GETS [0 ] 0 OT Merged_GETS [0 ] 0 OT Other_GETS_No_Mig [0 ] 0 +OT NC_DMA_GETS [0 ] 0 OT Invalidate [0 ] 0 MT Load [0 ] 0 @@ -476,6 +493,7 @@ MT Other_GETX [0 ] 0 MT Other_GETS [0 ] 0 MT Merged_GETS [0 ] 0 MT Other_GETS_No_Mig [0 ] 0 +MT NC_DMA_GETS [0 ] 0 MT Invalidate [0 ] 0 MMT Load [0 ] 0 @@ -488,6 +506,7 @@ MMT Other_GETX [0 ] 0 MMT Other_GETS [0 ] 0 MMT Merged_GETS [0 ] 0 MMT Other_GETS_No_Mig [0 ] 0 +MMT NC_DMA_GETS [0 ] 0 MMT Invalidate [0 ] 0 Cache Stats: system.dir_cntrl0.probeFilter @@ -502,19 +521,19 @@ Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1379 memory_reads: 1159 memory_writes: 220 - memory_refreshes: 434 - memory_total_request_delays: 471 - memory_delays_per_request: 0.341552 - memory_delays_in_input_queue: 15 + memory_refreshes: 435 + memory_total_request_delays: 495 + memory_delays_per_request: 0.358956 + memory_delays_in_input_queue: 3 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 456 - memory_stalls_for_bank_busy: 86 + memory_delays_stalled_at_head_of_bank_queue: 492 + memory_stalls_for_bank_busy: 124 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 30 + memory_stalls_for_arbitration: 23 memory_stalls_for_bus: 78 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 262 + memory_stalls_for_read_write_turnaround: 267 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52 @@ -625,6 +644,8 @@ NO_B_X PUT [0 ] 0 NO_B_X UnblockS [0 ] 0 NO_B_X UnblockM [0 ] 0 NO_B_X Pf_Replacement [0 ] 0 +NO_B_X DMA_READ [0 ] 0 +NO_B_X DMA_WRITE [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 @@ -648,6 +669,7 @@ O_B GETX [0 ] 0 O_B GETS [0 ] 0 O_B PUT [0 ] 0 O_B UnblockS [0 ] 0 +O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 01467c4b7..968d521e0 100755 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout -Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 11:09:13 -M5 revision c5f5b5533e96 7536 default qtip tip brad/regress_updates -M5 started Aug 5 2010 11:09:30 +M5 compiled Feb 8 2011 17:56:59 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:57:03 M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 207970 because target called exit() +Exiting @ tick 208400 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 8112f9791..5f06bc32c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 31390 # Simulator instruction rate (inst/s) -host_mem_usage 211076 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -host_tick_rate 1018487 # Simulator tick rate (ticks/s) +host_inst_rate 50833 # Simulator instruction rate (inst/s) +host_mem_usage 214944 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 1651975 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000208 # Number of seconds simulated -sim_ticks 207970 # Number of ticks simulated +sim_ticks 208400 # Number of ticks simulated system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2050 # DTB hits @@ -42,9 +42,25 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 207970 # number of cpu cycles simulated +system.cpu.numCycles 208400 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 208400 # Number of busy cycles +system.cpu.num_conditional_control_insts 750 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 6404 # Number of instructions executed -system.cpu.num_refs 2060 # Number of memory references +system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses +system.cpu.num_int_insts 6331 # number of integer instructions +system.cpu.num_int_register_reads 8304 # number of times the integer registers were read +system.cpu.num_int_register_writes 4581 # number of times the integer registers were written +system.cpu.num_load_insts 1192 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_store_insts 868 # Number of store instructions system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index a4ed53868..b7bfb0aae 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -186,6 +195,7 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl0.L1DcacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 4efa8de79..594f80de9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/13/2011 22:36:30 +Real time: Feb/08/2011 17:31:55 Profiler Stats -------------- -Elapsed_time_in_seconds: 2 -Elapsed_time_in_minutes: 0.0333333 -Elapsed_time_in_hours: 0.000555556 -Elapsed_time_in_days: 2.31481e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.79 -Virtual_time_in_minutes: 0.0131667 -Virtual_time_in_hours: 0.000219444 -Virtual_time_in_days: 9.14352e-06 +Virtual_time_in_seconds: 0.39 +Virtual_time_in_minutes: 0.0065 +Virtual_time_in_hours: 0.000108333 +Virtual_time_in_days: 4.51389e-06 Ruby_current_time: 103637 Ruby_start_time: 0 Ruby_cycles: 103637 -mbytes_resident: 20.9219 -mbytes_total: 156.062 -resident_ratio: 0.134111 +mbytes_resident: 35.7188 +mbytes_total: 209.473 +resident_ratio: 0.170592 ruby_cycles_executed: [ 103638 ] @@ -119,7 +119,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 6028 +page_reclaims: 10341 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index 5c8b35b72..38e786bad 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 13 2011 22:36:25 -M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip -M5 started Jan 13 2011 22:36:28 -M5 executing on scamorza.cs.wisc.edu +M5 compiled Feb 8 2011 17:31:51 +M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:31:55 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index 5b40ee1fb..591cdf9bb 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2534 # Simulator instruction rate (inst/s) -host_mem_usage 159812 # Number of bytes of host memory used -host_seconds 1.02 # Real time elapsed on the host -host_tick_rate 101843 # Simulator tick rate (ticks/s) +host_inst_rate 31237 # Simulator instruction rate (inst/s) +host_mem_usage 214504 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 1253532 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000104 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 103637 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 103637 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 59f975e1e..dae855509 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -108,32 +117,19 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l1_cntrl0.sequencer.dcache] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=3 @@ -141,7 +137,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -177,14 +173,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -194,13 +189,18 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port [system.ruby.network] type=SimpleNetwork @@ -216,9 +216,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -name=Crossbar num_int_nodes=4 print_config=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 86aa94fb6..b0eff5788 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:37:10 +Real time: Feb/08/2011 17:41:43 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.41 -Virtual_time_in_minutes: 0.00683333 -Virtual_time_in_hours: 0.000113889 -Virtual_time_in_days: 4.74537e-06 +Virtual_time_in_seconds: 0.4 +Virtual_time_in_minutes: 0.00666667 +Virtual_time_in_hours: 0.000111111 +Virtual_time_in_days: 4.62963e-06 Ruby_current_time: 85988 Ruby_start_time: 0 Ruby_cycles: 85988 -mbytes_resident: 33.6484 -mbytes_total: 33.6562 -resident_ratio: 1 +mbytes_resident: 35.8359 +mbytes_total: 209.617 +resident_ratio: 0.171015 ruby_cycles_executed: [ 85989 ] @@ -119,8 +119,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7386 -page_faults: 2090 +page_reclaims: 10362 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.342645 outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 0 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 --- L1Cache --- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index c8e6b0646..2588731f1 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 10:34:54 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:37:10 -M5 executing on svvint09 +M5 compiled Feb 8 2011 17:41:34 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:41:42 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index bc9801bf7..dd02fbf60 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 19822 # Simulator instruction rate (inst/s) -host_mem_usage 211548 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 661411 # Simulator tick rate (ticks/s) +host_inst_rate 26760 # Simulator instruction rate (inst/s) +host_mem_usage 214652 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 891261 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000086 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 85988 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 85988 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 1971d2a44..537819260 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -111,9 +120,9 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory N_tokens=2 buffer_size=0 dynamic_timeout_enabled=true @@ -125,24 +134,11 @@ no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.l1_cntrl0.sequencer.dcache] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=2 @@ -150,7 +146,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=2 @@ -188,14 +184,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -205,13 +200,18 @@ randomization=false stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port [system.ruby.network] type=SimpleNetwork @@ -227,9 +227,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -name=Crossbar num_int_nodes=4 print_config=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats index dbdcc6601..23d0a1d6f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, ordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:43:25 +Real time: Feb/08/2011 17:51:05 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.25 -Virtual_time_in_minutes: 0.00416667 -Virtual_time_in_hours: 6.94444e-05 -Virtual_time_in_days: 2.89352e-06 +Virtual_time_in_seconds: 0.33 +Virtual_time_in_minutes: 0.0055 +Virtual_time_in_hours: 9.16667e-05 +Virtual_time_in_days: 3.81944e-06 Ruby_current_time: 92099 Ruby_start_time: 0 Ruby_cycles: 92099 -mbytes_resident: 33.5859 -mbytes_total: 33.5938 -resident_ratio: 1 +mbytes_resident: 35.7695 +mbytes_total: 209.457 +resident_ratio: 0.17081 ruby_cycles_executed: [ 92100 ] @@ -127,8 +127,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7341 -page_faults: 2084 +page_reclaims: 10334 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -193,28 +193,28 @@ links_utilized_percent_switch_3: 0.205739 outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 270 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 270 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 270 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 270 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100% + system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 270 100% -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 243 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 243 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 243 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971% - system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 74.8971% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 25.1029% - system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 243 100% --- L1Cache --- - Event Counts - @@ -222,7 +222,7 @@ Load [415 ] 415 Ifetch [2585 ] 2585 Store [294 ] 294 Atomic [0 ] 0 -L1_Replacement [506 ] 506 +L1_Replacement [503 ] 503 Data_Shared [18 ] 18 Data_Owner [0 ] 0 Data_All_Tokens [495 ] 495 @@ -352,7 +352,7 @@ M_W Load [47 ] 47 M_W Ifetch [1038 ] 1038 M_W Store [6 ] 6 M_W Atomic [0 ] 0 -M_W L1_Replacement [4 ] 4 +M_W L1_Replacement [1 ] 1 M_W Transient_GETX [0 ] 0 M_W Transient_Local_GETX [0 ] 0 M_W Transient_GETS [0 ] 0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index 9cf458143..f29df4a71 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 10:41:36 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:43:25 -M5 executing on svvint09 +M5 compiled Feb 8 2011 17:50:56 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:51:05 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index e8b218502..caef5b8f0 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 42948 # Simulator instruction rate (inst/s) -host_mem_usage 211392 # Number of bytes of host memory used +host_inst_rate 44139 # Simulator instruction rate (inst/s) +host_mem_usage 214488 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 1534907 # Simulator tick rate (ticks/s) +host_tick_rate 1572917 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000092 # Number of seconds simulated @@ -43,8 +43,24 @@ system.cpu.itb.write_hits 0 # DT system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 92099 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 92099 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 4d36728d7..08f882272 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu] type=TimingSimpleCPU @@ -32,8 +41,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.ruby.cpu_ruby_ports.port[1] +icache_port=system.ruby.cpu_ruby_ports.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +63,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -70,6 +79,7 @@ type=Directory_Controller children=directory memBuffer probeFilter buffer_size=0 directory=system.dir_cntrl0.directory +full_bit_dir_enabled=false memBuffer=system.dir_cntrl0.memBuffer memory_controller_latency=2 number_of_TBEs=256 @@ -118,17 +128,18 @@ start_index_bit=6 [system.l1_cntrl0] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L2cacheMemory +L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache +L1IcacheMemory=system.ruby.cpu_ruby_ports.icache L2cacheMemory=system.l1_cntrl0.L2cacheMemory buffer_size=0 cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 @@ -140,12 +151,37 @@ replacement_policy=PSEUDO_LRU size=512 start_index_bit=6 -[system.l1_cntrl0.sequencer] +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.ruby.cpu_ruby_ports.physMemPort + +[system.ruby] +type=RubySystem +children=cpu_ruby_ports network profiler tracer +block_size_bytes=64 +clock=1 +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.cpu_ruby_ports] type=RubySequencer children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache +icache=system.ruby.cpu_ruby_ports.icache max_outstanding_requests=16 physmem=system.physmem using_ruby_tester=false @@ -153,7 +189,7 @@ version=0 physMemPort=system.physmem.port[0] port=system.cpu.icache_port system.cpu.dcache_port -[system.l1_cntrl0.sequencer.dcache] +[system.ruby.cpu_ruby_ports.dcache] type=RubyCache assoc=2 latency=2 @@ -161,7 +197,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.ruby.cpu_ruby_ports.icache] type=RubyCache assoc=2 latency=2 @@ -169,39 +205,6 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.l1_cntrl0.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -no_mem_vec=false -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - [system.ruby.network] type=SimpleNetwork children=topology @@ -216,9 +219,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -name=Crossbar num_int_nodes=3 print_config=false diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 6e53a933a..3e0d391db 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 14:44:19 +Real time: Feb/08/2011 17:57:03 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.21 -Virtual_time_in_minutes: 0.0035 -Virtual_time_in_hours: 5.83333e-05 -Virtual_time_in_days: 2.43056e-06 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 -Ruby_current_time: 78408 +Ruby_current_time: 78448 Ruby_start_time: 0 -Ruby_cycles: 78408 +Ruby_cycles: 78448 -mbytes_resident: 33.3242 -mbytes_total: 33.332 -resident_ratio: 1 +mbytes_resident: 35.3906 +mbytes_total: 208.879 +resident_ratio: 0.169469 -ruby_cycles_executed: [ 78409 ] +ruby_cycles_executed: [ 78449 ] Busy Controller Counts: L1Cache-0:0 @@ -69,13 +69,13 @@ sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8033 | standard deviation: 52.924 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5544 | standard deviation: 44.4412 | 0 0 2315 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ] -miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.4602 | standard deviation: 75.1127 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.8265 | standard deviation: 63.3064 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] +miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ] -miss_latency_L2Cache: [binsize: 1 max: 12 count: 69 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 69 ] -miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.823 | standard deviation: 21.7136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ] +miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -87,14 +87,14 @@ miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 averag miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] imcomplete_dir_Times: 440 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 22 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 22 ] -miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.819 | standard deviation: 5.60689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ] +miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ] miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] -miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 36 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 36 ] -miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 157.178 | standard deviation: 25.3138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ] +miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ] -miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 11 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 11 ] -miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 167.468 | standard deviation: 46.1312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ] +miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -126,8 +126,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7298 -page_faults: 2071 +page_reclaims: 10290 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -144,9 +144,9 @@ total_msgs: 7791 total_bytes: 162552 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.110878 - links_utilized_percent_switch_0_link_0: 0.0700502 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.151706 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.110822 + links_utilized_percent_switch_0_link_0: 0.0700145 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.151629 bw: 160000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 @@ -157,9 +157,9 @@ links_utilized_percent_switch_0: 0.110878 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.159064 - links_utilized_percent_switch_1_link_0: 0.0379266 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.280201 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.158983 + links_utilized_percent_switch_1_link_0: 0.0379073 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.280058 bw: 160000 base_latency: 1 outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 @@ -170,9 +170,9 @@ links_utilized_percent_switch_1: 0.159064 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.215954 - links_utilized_percent_switch_2_link_0: 0.280201 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.151706 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.215844 + links_utilized_percent_switch_2_link_0: 0.280058 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.151629 bw: 160000 base_latency: 1 outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 @@ -181,47 +181,47 @@ links_utilized_percent_switch_2: 0.215954 outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 270 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 270 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.cpu_ruby_ports.icache + system.ruby.cpu_ruby_ports.icache_total_misses: 270 + system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270 + system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% - system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100% + system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 270 100% -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 240 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 240 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 240 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_request_type_LD: 75.8333% - system.l1_cntrl0.sequencer.dcache_request_type_ST: 24.1667% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667% - system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 240 100% + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 240 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 441 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 441 + system.l1_cntrl0.L2cacheMemory_total_misses: 510 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 510 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 33.1066% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 10.6576% - system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 56.2358% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 35.6863% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412% - system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 441 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 510 100% --- L1Cache --- - Event Counts - -Load [428 ] 428 -Ifetch [2597 ] 2597 -Store [302 ] 302 +Load [422 ] 422 +Ifetch [2591 ] 2591 +Store [298 ] 298 L2_Replacement [425 ] 425 L1_to_L2 [502 ] 502 Trigger_L2_to_L1D [47 ] 47 @@ -231,6 +231,7 @@ Other_GETX [0 ] 0 Other_GETS [0 ] 0 Merged_GETS [0 ] 0 Other_GETS_No_Mig [0 ] 0 +NC_DMA_GETS [0 ] 0 Invalidate [0 ] 0 Ack [0 ] 0 Shared_Ack [0 ] 0 @@ -253,6 +254,7 @@ I Trigger_L2_to_L1I [0 ] 0 I Other_GETX [0 ] 0 I Other_GETS [0 ] 0 I Other_GETS_No_Mig [0 ] 0 +I NC_DMA_GETS [0 ] 0 I Invalidate [0 ] 0 S Load [0 ] 0 @@ -265,6 +267,7 @@ S Trigger_L2_to_L1I [0 ] 0 S Other_GETX [0 ] 0 S Other_GETS [0 ] 0 S Other_GETS_No_Mig [0 ] 0 +S NC_DMA_GETS [0 ] 0 S Invalidate [0 ] 0 O Load [0 ] 0 @@ -278,6 +281,7 @@ O Other_GETX [0 ] 0 O Other_GETS [0 ] 0 O Merged_GETS [0 ] 0 O Other_GETS_No_Mig [0 ] 0 +O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 M Load [131 ] 131 @@ -291,6 +295,7 @@ M Other_GETX [0 ] 0 M Other_GETS [0 ] 0 M Merged_GETS [0 ] 0 M Other_GETS_No_Mig [0 ] 0 +M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 MM Load [138 ] 138 @@ -304,6 +309,7 @@ MM Other_GETX [0 ] 0 MM Other_GETS [0 ] 0 MM Merged_GETS [0 ] 0 MM Other_GETS_No_Mig [0 ] 0 +MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 IM Load [0 ] 0 @@ -314,6 +320,7 @@ IM L1_to_L2 [0 ] 0 IM Other_GETX [0 ] 0 IM Other_GETS [0 ] 0 IM Other_GETS_No_Mig [0 ] 0 +IM NC_DMA_GETS [0 ] 0 IM Invalidate [0 ] 0 IM Ack [0 ] 0 IM Data [0 ] 0 @@ -327,9 +334,11 @@ SM L1_to_L2 [0 ] 0 SM Other_GETX [0 ] 0 SM Other_GETS [0 ] 0 SM Other_GETS_No_Mig [0 ] 0 +SM NC_DMA_GETS [0 ] 0 SM Invalidate [0 ] 0 SM Ack [0 ] 0 SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 OM Load [0 ] 0 OM Ifetch [0 ] 0 @@ -340,6 +349,7 @@ OM Other_GETX [0 ] 0 OM Other_GETS [0 ] 0 OM Merged_GETS [0 ] 0 OM Other_GETS_No_Mig [0 ] 0 +OM NC_DMA_GETS [0 ] 0 OM Invalidate [0 ] 0 OM Ack [0 ] 0 OM All_acks [0 ] 0 @@ -377,6 +387,7 @@ IS L1_to_L2 [0 ] 0 IS Other_GETX [0 ] 0 IS Other_GETS [0 ] 0 IS Other_GETS_No_Mig [0 ] 0 +IS NC_DMA_GETS [0 ] 0 IS Invalidate [0 ] 0 IS Ack [0 ] 0 IS Shared_Ack [0 ] 0 @@ -403,18 +414,20 @@ OI Other_GETX [0 ] 0 OI Other_GETS [0 ] 0 OI Merged_GETS [0 ] 0 OI Other_GETS_No_Mig [0 ] 0 +OI NC_DMA_GETS [0 ] 0 OI Invalidate [0 ] 0 OI Writeback_Ack [0 ] 0 -MI Load [13 ] 13 -MI Ifetch [12 ] 12 -MI Store [8 ] 8 +MI Load [7 ] 7 +MI Ifetch [6 ] 6 +MI Store [4 ] 4 MI L2_Replacement [0 ] 0 MI L1_to_L2 [0 ] 0 MI Other_GETX [0 ] 0 MI Other_GETS [0 ] 0 MI Merged_GETS [0 ] 0 MI Other_GETS_No_Mig [0 ] 0 +MI NC_DMA_GETS [0 ] 0 MI Invalidate [0 ] 0 MI Writeback_Ack [425 ] 425 @@ -426,6 +439,7 @@ II L1_to_L2 [0 ] 0 II Other_GETX [0 ] 0 II Other_GETS [0 ] 0 II Other_GETS_No_Mig [0 ] 0 +II NC_DMA_GETS [0 ] 0 II Invalidate [0 ] 0 II Writeback_Ack [0 ] 0 II Writeback_Nack [0 ] 0 @@ -440,6 +454,7 @@ IT Other_GETX [0 ] 0 IT Other_GETS [0 ] 0 IT Merged_GETS [0 ] 0 IT Other_GETS_No_Mig [0 ] 0 +IT NC_DMA_GETS [0 ] 0 IT Invalidate [0 ] 0 ST Load [0 ] 0 @@ -452,6 +467,7 @@ ST Other_GETX [0 ] 0 ST Other_GETS [0 ] 0 ST Merged_GETS [0 ] 0 ST Other_GETS_No_Mig [0 ] 0 +ST NC_DMA_GETS [0 ] 0 ST Invalidate [0 ] 0 OT Load [0 ] 0 @@ -464,6 +480,7 @@ OT Other_GETX [0 ] 0 OT Other_GETS [0 ] 0 OT Merged_GETS [0 ] 0 OT Other_GETS_No_Mig [0 ] 0 +OT NC_DMA_GETS [0 ] 0 OT Invalidate [0 ] 0 MT Load [0 ] 0 @@ -476,6 +493,7 @@ MT Other_GETX [0 ] 0 MT Other_GETS [0 ] 0 MT Merged_GETS [0 ] 0 MT Other_GETS_No_Mig [0 ] 0 +MT NC_DMA_GETS [0 ] 0 MT Invalidate [0 ] 0 MMT Load [0 ] 0 @@ -488,6 +506,7 @@ MMT Other_GETX [0 ] 0 MMT Other_GETS [0 ] 0 MMT Merged_GETS [0 ] 0 MMT Other_GETS_No_Mig [0 ] 0 +MMT NC_DMA_GETS [0 ] 0 MMT Invalidate [0 ] 0 Cache Stats: system.dir_cntrl0.probeFilter @@ -503,18 +522,18 @@ Memory controller: system.dir_cntrl0.memBuffer: memory_reads: 441 memory_writes: 81 memory_refreshes: 164 - memory_total_request_delays: 147 - memory_delays_per_request: 0.281609 + memory_total_request_delays: 151 + memory_delays_per_request: 0.289272 memory_delays_in_input_queue: 2 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 145 - memory_stalls_for_bank_busy: 27 + memory_delays_stalled_at_head_of_bank_queue: 149 + memory_stalls_for_bank_busy: 22 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 6 - memory_stalls_for_bus: 23 + memory_stalls_for_arbitration: 7 + memory_stalls_for_bus: 26 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 89 + memory_stalls_for_read_write_turnaround: 94 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62 @@ -625,6 +644,8 @@ NO_B_X PUT [0 ] 0 NO_B_X UnblockS [0 ] 0 NO_B_X UnblockM [0 ] 0 NO_B_X Pf_Replacement [0 ] 0 +NO_B_X DMA_READ [0 ] 0 +NO_B_X DMA_WRITE [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 @@ -648,6 +669,7 @@ O_B GETX [0 ] 0 O_B GETS [0 ] 0 O_B PUT [0 ] 0 O_B UnblockS [0 ] 0 +O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 76a97a409..06957aba3 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 14:43:33 -M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates -M5 started Aug 5 2010 14:44:19 -M5 executing on svvint09 +M5 compiled Feb 8 2011 17:56:59 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:57:03 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 78408 because target called exit() +Exiting @ tick 78448 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 58de899ed..73743c0c5 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 42947 # Simulator instruction rate (inst/s) -host_mem_usage 211060 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 1306713 # Simulator tick rate (ticks/s) +host_inst_rate 49095 # Simulator instruction rate (inst/s) +host_mem_usage 213896 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 1489708 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000078 # Number of seconds simulated -sim_ticks 78408 # Number of ticks simulated +sim_ticks 78448 # Number of ticks simulated system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 709 # DTB hits @@ -42,9 +42,25 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 78408 # number of cpu cycles simulated +system.cpu.numCycles 78448 # number of cpu cycles simulated +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.num_busy_cycles 78448 # Number of busy cycles +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 2577 # Number of instructions executed -system.cpu.num_refs 717 # Number of memory references +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_store_insts 298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1e86aa862..87307e90b 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32668 # Simulator instruction rate (inst/s) -host_mem_usage 224608 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 120542676 # Simulator tick rate (ticks/s) +host_inst_rate 1339 # Simulator instruction rate (inst/s) +host_mem_usage 191872 # Number of bytes of host memory used +host_seconds 4.35 # Real time elapsed on the host +host_tick_rate 4946645 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 0767b9777..1943466e8 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! -Exiting @ tick 13766000 because target called exit() +Exiting @ tick 11421500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 182e72d25..c2dfaa3ff 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 47133 # Simulator instruction rate (inst/s) -host_mem_usage 227692 # Number of bytes of host memory used +host_inst_rate 47598 # Simulator instruction rate (inst/s) +host_mem_usage 231896 # Number of bytes of host memory used host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 66053082 # Simulator tick rate (ticks/s) +host_tick_rate 55349277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13766000 # Number of ticks simulated +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11421500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1892 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 944 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 2550 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1920 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 1920 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 2777 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2777 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1214 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 37 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 139 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 15124 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.648572 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.100130 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 11906 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.823870 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.588166 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9612 63.55% 63.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 3088 20.42% 83.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1220 8.07% 92.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 836 5.53% 97.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 232 1.53% 99.10% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 57 0.38% 99.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 30 0.20% 99.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 12 0.08% 99.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 37 0.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 8274 69.49% 69.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1230 10.33% 79.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 588 4.94% 84.76% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 963 8.09% 92.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 395 3.32% 96.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 136 1.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 125 1.05% 98.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 56 0.47% 98.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 139 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 11906 # Number of insts commited each cycle system.cpu.commit.COM:count 9809 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,415 +44,417 @@ system.cpu.commit.COM:loads 1056 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1990 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3832 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9374 # The number of squashed insts skipped by commit system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.806912 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.806912 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1244 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37105.263158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35048.387097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1168 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2820000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061093 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 76 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2173000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.049839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 62 # number of ReadReq MSHR misses +system.cpu.cpi 2.328882 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.328882 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1541 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34473.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35119.402985 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1427 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3930000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.073978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.043478 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35775.641026 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34089.456869 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36012.987013 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10670000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2790500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.870504 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.321678 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2178 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33913.881748 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1789 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13192500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.178604 # miss rate for demand accesses -system.cpu.dcache.demand_misses 389 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 249 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4963500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.064279 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2475 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34192.037471 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14600000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.172525 # miss rate for demand accesses +system.cpu.dcache.demand_misses 427 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5126000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.058182 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.020744 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 84.965644 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2178 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33913.881748 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 85.892970 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2475 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34192.037471 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1789 # number of overall hits -system.cpu.dcache.overall_miss_latency 13192500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.178604 # miss rate for overall accesses -system.cpu.dcache.overall_misses 389 # number of overall misses -system.cpu.dcache.overall_mshr_hits 249 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4963500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.064279 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 140 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 14600000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.172525 # miss rate for overall accesses +system.cpu.dcache.overall_misses 427 # number of overall misses +system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5126000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.058182 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 139 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.965644 # Cycle average of tags in use -system.cpu.dcache.total_refs 1789 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.892970 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 464 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 15304 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 6233 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 8371 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 721 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 56 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1920 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1255 # Number of cache lines fetched -system.cpu.fetch.Cycles 9031 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 8830 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.069735 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1255 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.320706 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15845 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.178869 # Number of instructions fetched each cycle (Total) +system.cpu.decode.DECODE:BlockedCycles 1367 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 22275 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7155 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3308 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1504 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 76 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2777 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1732 # Number of cache lines fetched +system.cpu.fetch.Cycles 3623 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 245 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.121564 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1732 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 944 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.568027 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.734526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.109133 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 7129 44.99% 44.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4489 28.33% 73.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1878 11.85% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2046 12.91% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 57 0.36% 98.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 227 1.43% 99.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9877 73.65% 73.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 162 1.21% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 123 0.92% 75.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.69% 77.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 192 1.43% 78.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 174 1.30% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 266 1.98% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2214 16.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 970 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.227092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 285 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 9040500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.205578 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 258 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 13410 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 4 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 1732 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36454.794521 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35105.084746 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13306000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.210739 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 365 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10356000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.170323 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.759690 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.633898 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1255 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37417.543860 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency -system.cpu.icache.demand_hits 970 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.227092 # miss rate for demand accesses -system.cpu.icache.demand_misses 285 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9040500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.205578 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 258 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1732 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36454.794521 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency +system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13306000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.210739 # miss rate for demand accesses +system.cpu.icache.demand_misses 365 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10356000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.170323 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.061525 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 126.002915 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1255 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37417.543860 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.070726 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 144.846093 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1732 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36454.794521 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 970 # number of overall hits -system.cpu.icache.overall_miss_latency 10664000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.227092 # miss rate for overall accesses -system.cpu.icache.overall_misses 285 # number of overall misses -system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9040500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.205578 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 258 # number of overall MSHR misses +system.cpu.icache.overall_hits 1367 # number of overall hits +system.cpu.icache.overall_miss_latency 13306000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.210739 # miss rate for overall accesses +system.cpu.icache.overall_misses 365 # number of overall misses +system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10356000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.170323 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 258 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 126.002915 # Cycle average of tags in use -system.cpu.icache.total_refs 970 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.846093 # Cycle average of tags in use +system.cpu.icache.total_refs 1367 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11688 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1318 # Number of branches executed +system.cpu.idleCycles 9434 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1551 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.434678 # Inst execution rate -system.cpu.iew.EXEC:refs 2353 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1060 # Number of stores executed +system.cpu.iew.EXEC:rate 0.676151 # Inst execution rate +system.cpu.iew.EXEC:refs 2971 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1306 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10358 # num instructions consuming a value -system.cpu.iew.WB:count 11818 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.702935 # average fanout of values written-back +system.cpu.iew.WB:consumers 14704 # num instructions consuming a value +system.cpu.iew.WB:count 15138 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.679747 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7281 # num instructions producing a value -system.cpu.iew.WB:rate 0.429230 # insts written-back per cycle -system.cpu.iew.WB:sent 11866 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 487 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 58 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1535 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 418 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1238 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 13635 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1293 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 536 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 11968 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 9995 # num instructions producing a value +system.cpu.iew.WB:rate 0.662669 # insts written-back per cycle +system.cpu.iew.WB:sent 15263 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 565 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2105 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19184 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1665 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15446 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1504 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 21 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 479 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 304 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 25083 # number of integer regfile reads -system.cpu.int_regfile_writes 11189 # number of integer regfile writes -system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 10018 80.12% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1360 10.88% 91.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1123 8.98% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 31 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1049 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 705 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 496 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 23051 # number of integer regfile reads +system.cpu.int_regfile_writes 14062 # number of integer regfile writes +system.cpu.ipc 0.429391 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.429391 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 12967 80.26% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1786 11.05% 91.34% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1399 8.66% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 12504 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000320 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 16156 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008789 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3 75.00% 75.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1 25.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 97 68.31% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 26 18.31% 86.62% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 19 13.38% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.789145 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.977935 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13410 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.204773 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.912582 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8160 51.50% 51.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 4079 25.74% 77.24% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 2594 16.37% 93.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 834 5.26% 98.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 157 0.99% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 19 0.12% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 2 0.01% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8282 61.76% 61.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1307 9.75% 71.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.35% 78.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 745 5.56% 84.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 787 5.87% 90.28% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 588 4.38% 94.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 498 3.71% 98.38% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 170 1.27% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 12501 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 40849 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 11816 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 16975 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3342 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5066 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.589744 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.923077 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2690500 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 13410 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.707232 # Inst issue rate +system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 16289 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 45908 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 15134 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 27963 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 19154 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16156 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8758 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 11067 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34616.883117 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31389.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2443500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 320 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34188.679245 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34245.833333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 10872000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.993750 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 318 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9859500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993750 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 318 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 12328500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006309 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 398 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34248.737374 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34311.212815 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.994975 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 396 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14994000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12303000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.994975 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 396 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.004816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 157.820330 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 398 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34248.737374 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005436 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 178.138745 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34311.212815 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.994975 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 396 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14994000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 437 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12303000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.994975 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 396 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 317 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 157.820330 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.138745 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 5334 # number of misc regfile reads -system.cpu.numCycles 27533 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2105 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 6857 # number of misc regfile reads +system.cpu.numCycles 22844 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 565 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 6603 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 38664 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 14745 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 13787 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8027 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 51 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 7399 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 247 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 44700 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21187 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19905 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3124 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1504 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 378 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10537 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 38648 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 28728 # The number of ROB reads -system.cpu.rob.rob_writes 28005 # The number of ROB writes -system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 44684 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 440 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1476 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 30950 # The number of ROB reads +system.cpu.rob.rob_writes 39896 # The number of ROB writes +system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 09f4d0b50..8fb08388b 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 1dca11ec5..cddb4c7b6 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 180423 # Simulator instruction rate (inst/s) -host_mem_usage 219128 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 103433649 # Simulator tick rate (ticks/s) +host_inst_rate 992012 # Simulator instruction rate (inst/s) +host_mem_usage 219616 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 556721453 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index a12716c02..569662936 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/07/2011 02:32:13 +Real time: Feb/08/2011 00:58:34 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 38.6094 -mbytes_total: 231.508 -resident_ratio: 0.16679 +mbytes_resident: 38.6797 +mbytes_total: 231.98 +resident_ratio: 0.166754 ruby_cycles_executed: [ 276485 ] @@ -125,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10950 +page_reclaims: 11003 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index 877c8d9b9..ab908eedc 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index b88df01c5..491eaf1d1 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32378 # Simulator instruction rate (inst/s) -host_mem_usage 237068 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 911908 # Simulator tick rate (ticks/s) +host_inst_rate 81703 # Simulator instruction rate (inst/s) +host_mem_usage 237552 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 2292859 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000276 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index d6afbecf0..43766d7be 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index 0c21882f5..fc7acffe1 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 594010 # Simulator instruction rate (inst/s) -host_mem_usage 226844 # Number of bytes of host memory used +host_inst_rate 525864 # Simulator instruction rate (inst/s) +host_mem_usage 227336 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1712507148 # Simulator tick rate (ticks/s) +host_tick_rate 1518719132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -208,7 +208,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 79021a958..859778cbe 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -7,11 +7,11 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus +children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -167,7 +167,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false @@ -187,7 +187,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.clcd.dma +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma [system.iocache] type=BaseCache @@ -217,7 +217,7 @@ tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.iobus.port[24] +cpu_side=system.iobus.port[25] mem_side=system.membus.port[5] [system.l2c] @@ -291,7 +291,7 @@ port=system.membus.port[1] [system.realview] type=RealView -children=aaci_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -305,6 +305,22 @@ platform=system.realview system=system pio=system.iobus.port[20] +[system.realview.cf0_fake] +type=IsaFake +pio_addr=402653184 +pio_latency=1000 +pio_size=4095 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[24] + [system.realview.clcd] type=Pl111 amba_id=1315089 @@ -317,7 +333,8 @@ pio_addr=268566528 pio_latency=10000 platform=system.realview system=system -dma=system.iobus.port[25] +vnc=system.vncserver +dma=system.iobus.port[26] pio=system.iobus.port[5] [system.realview.dmac_fake] @@ -391,24 +408,28 @@ pio=system.iobus.port[17] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=52 +is_mouse=false pio_addr=268460032 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[6] [system.realview.kmi1] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=53 +is_mouse=true pio_addr=268464128 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[7] [system.realview.l2x0_fake] @@ -594,3 +615,8 @@ use_default_range=false width=64 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.vncserver] +type=VncServer +number=0 +port=5900 + diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr index 122561307..63ac398c9 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -1,3 +1,5 @@ +warn: Sockets disabled, not accepting vnc client connections +For more information see: http://www.m5sim.org/warn/af6a84f6 warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index ba4c6742c..180619cc1 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:53:13 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:53:26 -M5 executing on burrito +M5 compiled Feb 11 2011 17:53:57 +M5 revision 6c65f7ee86c1 7949 default qtip tip ext/vnc_stats_updates.patch +M5 started Feb 11 2011 17:54:00 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 25821310500 because m5_exit instruction encountered +Exiting @ tick 26073617500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 0a7542a7c..9854d94df 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 739167 # Simulator instruction rate (inst/s) -host_mem_usage 360776 # Number of bytes of host memory used -host_seconds 68.93 # Real time elapsed on the host -host_tick_rate 374609475 # Simulator tick rate (ticks/s) +host_inst_rate 2481190 # Simulator instruction rate (inst/s) +host_mem_usage 374936 # Number of bytes of host memory used +host_seconds 20.74 # Real time elapsed on the host +host_tick_rate 1257294139 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50949504 # Number of instructions simulated -sim_seconds 0.025821 # Number of seconds simulated -sim_ticks 25821310500 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 96794 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 96794 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::0 91895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 91895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050613 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 4899 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4899 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses::0 7714516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7714516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits::0 7482193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7482193 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate::0 0.030115 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 232323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 232323 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses::0 96793 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 96793 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 96793 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 96793 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6604860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6604860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 6433311 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6433311 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.025973 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 171549 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 171549 # number of WriteReq misses +sim_insts 51454118 # Number of instructions simulated +sim_seconds 0.026074 # Number of seconds simulated +sim_ticks 26073617500 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::0 95292 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95292 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051387 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5162 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::0 7830681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7830681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7594158 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7594158 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.030205 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 236523 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 236523 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses::0 100453 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100453 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100453 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100453 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6676067 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6676067 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 6503881 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6503881 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.025792 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172186 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172186 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.663994 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.695419 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14319376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14506748 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14319376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 14506748 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13915504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 14098039 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13915504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 14098039 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028205 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.028174 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 403872 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 408709 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 403872 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 408709 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -67,26 +67,26 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999475 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.731250 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14319376 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.999480 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.733850 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14506748 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14319376 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 14506748 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13915504 # number of overall hits +system.cpu.dcache.overall_hits::0 14098039 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13915504 # number of overall hits +system.cpu.dcache.overall_hits::total 14098039 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.028174 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 403872 # number of overall misses +system.cpu.dcache.overall_misses::0 408709 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 403872 # number of overall misses +system.cpu.dcache.overall_misses::total 408709 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -95,66 +95,66 @@ system.cpu.dcache.overall_mshr_miss_rate::total no_value system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 406424 # number of replacements -system.cpu.dcache.sampled_refs 406936 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 411520 # number of replacements +system.cpu.dcache.sampled_refs 412032 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.731250 # Cycle average of tags in use -system.cpu.dcache.total_refs 14106027 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.733850 # Cycle average of tags in use +system.cpu.dcache.total_refs 14295623 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21760000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 379025 # number of writebacks -system.cpu.dtb.accesses 15336291 # DTB accesses +system.cpu.dcache.writebacks 381867 # number of writebacks +system.cpu.dtb.accesses 15531286 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2242 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2267 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15330762 # DTB hits +system.cpu.dtb.hits 15525735 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5529 # DTB misses +system.cpu.dtb.misses 5551 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 768 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8622893 # DTB read accesses -system.cpu.dtb.read_hits 8618361 # DTB read hits -system.cpu.dtb.read_misses 4532 # DTB read misses -system.cpu.dtb.write_accesses 6713398 # DTB write accesses -system.cpu.dtb.write_hits 6712401 # DTB write hits -system.cpu.dtb.write_misses 997 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41172623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41172623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits::0 40741841 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40741841 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate::0 0.010463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 430782 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 430782 # number of ReadReq misses +system.cpu.dtb.prefetch_faults 775 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8743013 # DTB read accesses +system.cpu.dtb.read_hits 8738461 # DTB read hits +system.cpu.dtb.read_misses 4552 # DTB read misses +system.cpu.dtb.write_accesses 6788273 # DTB write accesses +system.cpu.dtb.write_hits 6787274 # DTB write hits +system.cpu.dtb.write_misses 999 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41564629 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41564629 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 41131432 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41131432 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.010422 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 433197 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433197 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.576690 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.948781 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41172623 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41564629 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41172623 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41564629 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits::0 40741841 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 41131432 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40741841 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41131432 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::0 0.010422 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 430782 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 433197 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 430782 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433197 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -164,26 +164,26 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.929162 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 475.731149 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41172623 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.930040 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 476.180679 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41564629 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41172623 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41564629 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 40741841 # number of overall hits +system.cpu.icache.overall_hits::0 41131432 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 40741841 # number of overall hits +system.cpu.icache.overall_hits::total 41131432 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.010422 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 430782 # number of overall misses +system.cpu.icache.overall_misses::0 433197 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 430782 # number of overall misses +system.cpu.icache.overall_misses::total 433197 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -192,15 +192,15 @@ system.cpu.icache.overall_mshr_miss_rate::total no_value system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 430269 # number of replacements -system.cpu.icache.sampled_refs 430781 # Sample count of references to valid blocks. +system.cpu.icache.replacements 432684 # number of replacements +system.cpu.icache.sampled_refs 433196 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 475.731149 # Cycle average of tags in use -system.cpu.icache.total_refs 40741841 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 476.180679 # Cycle average of tags in use +system.cpu.icache.total_refs 41131432 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 4544230000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33727 # number of writebacks +system.cpu.icache.writebacks 33708 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41173750 # DTB accesses +system.cpu.itb.accesses 41565756 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -208,9 +208,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41170928 # DTB hits -system.cpu.itb.inst_accesses 41173750 # ITB inst accesses -system.cpu.itb.inst_hits 41170928 # ITB inst hits +system.cpu.itb.hits 41562934 # DTB hits +system.cpu.itb.inst_accesses 41565756 # ITB inst accesses +system.cpu.itb.inst_hits 41562934 # ITB inst hits system.cpu.itb.inst_misses 2822 # ITB inst misses system.cpu.itb.misses 2822 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -224,10 +224,10 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 51642622 # number of cpu cycles simulated +system.cpu.numCycles 52147236 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 51642622 # Number of busy cycles +system.cpu.num_busy_cycles 52147236 # Number of busy cycles system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6059 # Number of float alu accesses system.cpu.num_fp_insts 6059 # number of float instructions @@ -235,14 +235,14 @@ system.cpu.num_fp_register_reads 4227 # nu system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 50949504 # Number of instructions executed -system.cpu.num_int_alu_accesses 41395090 # Number of integer alu accesses -system.cpu.num_int_insts 41395090 # number of integer instructions -system.cpu.num_int_register_reads 128438705 # number of times the integer registers were read -system.cpu.num_int_register_writes 33973128 # number of times the integer registers were written -system.cpu.num_load_insts 9082722 # Number of load instructions -system.cpu.num_mem_refs 16092645 # number of memory refs -system.cpu.num_store_insts 7009923 # Number of store instructions +system.cpu.num_insts 51454118 # Number of instructions executed +system.cpu.num_int_alu_accesses 41848094 # Number of integer alu accesses +system.cpu.num_int_insts 41848094 # number of integer instructions +system.cpu.num_int_register_reads 129780130 # number of times the integer registers were read +system.cpu.num_int_register_writes 34330061 # number of times the integer registers were written +system.cpu.num_load_insts 9213901 # Number of load instructions +system.cpu.num_mem_refs 16300106 # number of memory refs +system.cpu.num_store_insts 7086205 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -310,61 +310,61 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 169714 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169714 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits::0 60310 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60310 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate::0 0.644637 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 109404 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 109404 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 665898 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 6073 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 671971 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 648226 # number of ReadReq hits -system.l2c.ReadReq_hits::1 6049 # number of ReadReq hits -system.l2c.ReadReq_hits::total 654275 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.026539 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.003952 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.030491 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 17672 # number of ReadReq misses -system.l2c.ReadReq_misses::1 24 # number of ReadReq misses -system.l2c.ReadReq_misses::total 17696 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 1835 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 170347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits::0 60613 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60613 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.644179 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 109734 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 109734 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 672769 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 6110 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 678879 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 651602 # number of ReadReq hits +system.l2c.ReadReq_hits::1 6087 # number of ReadReq hits +system.l2c.ReadReq_hits::total 657689 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.031463 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.003764 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.035227 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 21167 # number of ReadReq misses +system.l2c.ReadReq_misses::1 23 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21190 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_rate::0 0.990736 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1818 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1818 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 412752 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 412752 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 412752 # number of Writeback hits -system.l2c.Writeback_hits::total 412752 # number of Writeback hits +system.l2c.UpgradeReq_miss_rate::0 0.990756 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 415575 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415575 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415575 # number of Writeback hits +system.l2c.Writeback_hits::total 415575 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.885433 # Average number of references to valid blocks. +system.l2c.avg_refs 6.741439 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 835612 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 6073 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 841685 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 843116 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 6110 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 849226 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 708536 # number of demand (read+write) hits -system.l2c.demand_hits::1 6049 # number of demand (read+write) hits -system.l2c.demand_hits::total 714585 # number of demand (read+write) hits +system.l2c.demand_hits::0 712215 # number of demand (read+write) hits +system.l2c.demand_hits::1 6087 # number of demand (read+write) hits +system.l2c.demand_hits::total 718302 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.152075 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.003952 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.156027 # miss rate for demand accesses -system.l2c.demand_misses::0 127076 # number of demand (read+write) misses -system.l2c.demand_misses::1 24 # number of demand (read+write) misses -system.l2c.demand_misses::total 127100 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.155259 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.003764 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.159023 # miss rate for demand accesses +system.l2c.demand_misses::0 130901 # number of demand (read+write) misses +system.l2c.demand_misses::1 23 # number of demand (read+write) misses +system.l2c.demand_misses::total 130924 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -374,28 +374,28 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.072507 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.478199 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 4751.792305 # Average occupied blocks per context -system.l2c.occ_blocks::1 31339.221407 # Average occupied blocks per context -system.l2c.overall_accesses::0 835612 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 6073 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 841685 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.076407 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.476934 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5007.401793 # Average occupied blocks per context +system.l2c.occ_blocks::1 31256.365097 # Average occupied blocks per context +system.l2c.overall_accesses::0 843116 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 6110 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 849226 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 708536 # number of overall hits -system.l2c.overall_hits::1 6049 # number of overall hits -system.l2c.overall_hits::total 714585 # number of overall hits +system.l2c.overall_hits::0 712215 # number of overall hits +system.l2c.overall_hits::1 6087 # number of overall hits +system.l2c.overall_hits::total 718302 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.152075 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.003952 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.156027 # miss rate for overall accesses -system.l2c.overall_misses::0 127076 # number of overall misses -system.l2c.overall_misses::1 24 # number of overall misses -system.l2c.overall_misses::total 127100 # number of overall misses +system.l2c.overall_miss_rate::0 0.155259 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.003764 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.159023 # miss rate for overall accesses +system.l2c.overall_misses::0 130901 # number of overall misses +system.l2c.overall_misses::1 23 # number of overall misses +system.l2c.overall_misses::total 130924 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -404,12 +404,12 @@ system.l2c.overall_mshr_miss_rate::total 0 # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 95922 # number of replacements -system.l2c.sampled_refs 125830 # Sample count of references to valid blocks. +system.l2c.replacements 97028 # number of replacements +system.l2c.sampled_refs 129660 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36091.013712 # Cycle average of tags in use -system.l2c.total_refs 866394 # Total number of references to valid blocks. +system.l2c.tagsinuse 36263.766890 # Cycle average of tags in use +system.l2c.total_refs 874095 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 90126 # number of writebacks +system.l2c.writebacks 90970 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 4fad32362..49b04d190 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -7,11 +7,11 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus +children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -164,7 +164,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false @@ -184,7 +184,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.clcd.dma +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma [system.iocache] type=BaseCache @@ -214,7 +214,7 @@ tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.iobus.port[24] +cpu_side=system.iobus.port[25] mem_side=system.membus.port[5] [system.l2c] @@ -288,7 +288,7 @@ port=system.membus.port[1] [system.realview] type=RealView -children=aaci_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -302,6 +302,22 @@ platform=system.realview system=system pio=system.iobus.port[20] +[system.realview.cf0_fake] +type=IsaFake +pio_addr=402653184 +pio_latency=1000 +pio_size=4095 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[24] + [system.realview.clcd] type=Pl111 amba_id=1315089 @@ -314,7 +330,8 @@ pio_addr=268566528 pio_latency=10000 platform=system.realview system=system -dma=system.iobus.port[25] +vnc=system.vncserver +dma=system.iobus.port[26] pio=system.iobus.port[5] [system.realview.dmac_fake] @@ -388,24 +405,28 @@ pio=system.iobus.port[17] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=52 +is_mouse=false pio_addr=268460032 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[6] [system.realview.kmi1] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=53 +is_mouse=true pio_addr=268464128 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[7] [system.realview.l2x0_fake] @@ -591,3 +612,8 @@ use_default_range=false width=64 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.vncserver] +type=VncServer +number=0 +port=5900 + diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index e76a50eec..1cff4671c 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -1,3 +1,5 @@ +warn: Sockets disabled, not accepting vnc client connections +For more information see: http://www.m5sim.org/warn/af6a84f6 warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 994dfb6a2..2a456e7be 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:53:13 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:53:26 -M5 executing on burrito +M5 compiled Feb 11 2011 17:53:57 +M5 revision 6c65f7ee86c1 7949 default qtip tip ext/vnc_stats_updates.patch +M5 started Feb 11 2011 17:54:00 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 114721074000 because m5_exit instruction encountered +Exiting @ tick 114726567000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 85fb99220..c96422cfa 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,254 +1,254 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 433208 # Simulator instruction rate (inst/s) -host_mem_usage 360908 # Number of bytes of host memory used -host_seconds 116.74 # Real time elapsed on the host -host_tick_rate 982709659 # Simulator tick rate (ticks/s) +host_inst_rate 1425483 # Simulator instruction rate (inst/s) +host_mem_usage 374960 # Number of bytes of host memory used +host_seconds 35.49 # Real time elapsed on the host +host_tick_rate 3232752918 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50572425 # Number of instructions simulated -sim_seconds 0.114721 # Number of seconds simulated -sim_ticks 114721074000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100214 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100214 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385 # average LoadLockedReq miss latency +sim_insts 50588397 # Number of instructions simulated +sim_seconds 0.114727 # Number of seconds simulated +sim_ticks 114726567000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100290 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100290 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14562.978560 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11562.978560 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 95014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 78765000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051889 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5200 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5200 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63165000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_hits::0 95066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 76077000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052089 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052089 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5200 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 7824780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7824780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5224 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310532000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_accesses::0 7828656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7828656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15679.539912 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12679.195749 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7588163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7588163 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3738156500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030239 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 236617 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 236617 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3028228000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030239 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7590397 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7590397 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3735791500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030434 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 238259 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 238259 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3020932500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030434 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 236617 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38190415500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 100213 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100213 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100213 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100213 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6671860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6671860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 238259 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191771500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 100289 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100289 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100289 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100289 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6674369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6674369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40728.962545 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37728.712808 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6499787 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499787 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7026784000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172073 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172073 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6510516500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6502188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6502188 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7012753500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172181 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172181 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6496167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025797 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172073 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 172181 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927436000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.660375 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.529769 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14496640 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14503025 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14496640 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26340.112310 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14503025 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26187.859370 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14087950 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14092585 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14087950 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10764940500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028192 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14092585 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10748545000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028300 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 408690 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 410440 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 408690 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 410440 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9538744500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9517100000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028300 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 408690 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 410440 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 509.199113 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14496640 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 509.199247 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14503025 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14496640 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26340.112310 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14503025 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26187.859370 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14087950 # number of overall hits +system.cpu.dcache.overall_hits::0 14092585 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14087950 # number of overall hits -system.cpu.dcache.overall_miss_latency 10764940500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028192 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14092585 # number of overall hits +system.cpu.dcache.overall_miss_latency 10748545000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028300 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 408690 # number of overall misses +system.cpu.dcache.overall_misses::0 410440 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 408690 # number of overall misses +system.cpu.dcache.overall_misses::total 410440 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9538744500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9517100000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028300 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 408690 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39116462000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 410440 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39119207500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 411628 # number of replacements -system.cpu.dcache.sampled_refs 412140 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 413327 # number of replacements +system.cpu.dcache.sampled_refs 413839 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.199113 # Cycle average of tags in use -system.cpu.dcache.total_refs 14284927 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.199247 # Cycle average of tags in use +system.cpu.dcache.total_refs 14289765 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 382676 # number of writebacks -system.cpu.dtb.accesses 15524935 # DTB accesses +system.cpu.dcache.writebacks 381698 # number of writebacks +system.cpu.dtb.accesses 15531532 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2199 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2220 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15519414 # DTB hits +system.cpu.dtb.hits 15525999 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5521 # DTB misses +system.cpu.dtb.misses 5533 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8740303 # DTB read accesses -system.cpu.dtb.read_hits 8735762 # DTB read hits -system.cpu.dtb.read_misses 4541 # DTB read misses -system.cpu.dtb.write_accesses 6784632 # DTB write accesses -system.cpu.dtb.write_hits 6783652 # DTB write hits -system.cpu.dtb.write_misses 980 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41543801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41543801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885 # average ReadReq miss latency +system.cpu.dtb.prefetch_faults 757 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8744287 # DTB read accesses +system.cpu.dtb.read_hits 8739733 # DTB read hits +system.cpu.dtb.read_misses 4554 # DTB read misses +system.cpu.dtb.write_accesses 6787245 # DTB write accesses +system.cpu.dtb.write_hits 6786266 # DTB write hits +system.cpu.dtb.write_misses 979 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41555414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41555414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14790.398445 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11789.103925 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41110405 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41110405 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6414604000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010432 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 433396 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433396 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5113853000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010432 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41121276 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41121276 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6421074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 434138 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 434138 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5118098000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010447 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 433396 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 434138 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.856667 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.719366 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41543801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41555414 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41543801 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14800.791885 # average overall miss latency +system.cpu.icache.demand_accesses::total 41555414 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14790.398445 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41110405 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41121276 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41110405 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6414604000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010432 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41121276 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6421074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010447 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 433396 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 434138 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433396 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 434138 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5113853000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010432 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5118098000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010447 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 433396 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 434138 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.945788 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 484.243503 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41543801 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.946115 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 484.411008 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41555414 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41543801 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14800.791885 # average overall miss latency +system.cpu.icache.overall_accesses::total 41555414 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14790.398445 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41110405 # number of overall hits +system.cpu.icache.overall_hits::0 41121276 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41110405 # number of overall hits -system.cpu.icache.overall_miss_latency 6414604000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010432 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41121276 # number of overall hits +system.cpu.icache.overall_miss_latency 6421074000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010447 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 433396 # number of overall misses +system.cpu.icache.overall_misses::0 434138 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 433396 # number of overall misses +system.cpu.icache.overall_misses::total 434138 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5113853000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010432 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5118098000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010447 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 433396 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 434138 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 432883 # number of replacements -system.cpu.icache.sampled_refs 433395 # Sample count of references to valid blocks. +system.cpu.icache.replacements 433626 # number of replacements +system.cpu.icache.sampled_refs 434138 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 484.243503 # Cycle average of tags in use -system.cpu.icache.total_refs 41110405 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 484.411008 # Cycle average of tags in use +system.cpu.icache.total_refs 41121276 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33555 # number of writebacks +system.cpu.icache.writebacks 34007 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41546620 # DTB accesses +system.cpu.itb.accesses 41558233 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -256,9 +256,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41543801 # DTB hits -system.cpu.itb.inst_accesses 41546620 # ITB inst accesses -system.cpu.itb.inst_hits 41543801 # ITB inst hits +system.cpu.itb.hits 41555414 # DTB hits +system.cpu.itb.inst_accesses 41558233 # ITB inst accesses +system.cpu.itb.inst_hits 41555414 # ITB inst hits system.cpu.itb.inst_misses 2819 # ITB inst misses system.cpu.itb.misses 2819 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -272,10 +272,10 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 229442148 # number of cpu cycles simulated +system.cpu.numCycles 229453134 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 229442148 # Number of busy cycles +system.cpu.num_busy_cycles 229453134 # Number of busy cycles system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses system.cpu.num_fp_insts 6058 # number of float instructions @@ -283,14 +283,14 @@ system.cpu.num_fp_register_reads 4226 # nu system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 50572425 # Number of instructions executed -system.cpu.num_int_alu_accesses 41827211 # Number of integer alu accesses -system.cpu.num_int_insts 41827211 # number of integer instructions -system.cpu.num_int_register_reads 137988684 # number of times the integer registers were read -system.cpu.num_int_register_writes 34313952 # number of times the integer registers were written -system.cpu.num_load_insts 9208240 # Number of load instructions -system.cpu.num_mem_refs 16289993 # number of memory refs -system.cpu.num_store_insts 7081753 # Number of store instructions +system.cpu.num_insts 50588397 # Number of instructions executed +system.cpu.num_int_alu_accesses 41841366 # Number of integer alu accesses +system.cpu.num_int_insts 41841366 # number of integer instructions +system.cpu.num_int_register_reads 138034734 # number of times the integer registers were read +system.cpu.num_int_register_writes 34325875 # number of times the integer registers were written +system.cpu.num_load_insts 9211791 # Number of load instructions +system.cpu.num_mem_refs 16296219 # number of memory refs +system.cpu.num_store_insts 7084428 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -359,141 +359,141 @@ system.iocache.total_refs 0 # To system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 170323 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170323 # number of ReadExReq accesses(hits+misses) +system.l2c.LoadLockedReq_mshr_uncacheable_latency 234360000 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.ReadExReq_accesses::0 170356 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170356 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62071 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62071 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.635569 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.635569 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_hits::0 62546 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62546 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5606120000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.632851 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107810 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107810 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4312400000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.632851 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 673101 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 5652 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 678753 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52096.523258 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 28127657.142857 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 28179753.666115 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 107810 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 675489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 5600 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 681089 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52080.437900 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 33725803.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 33777884.009328 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 654204 # number of ReadReq hits -system.l2c.ReadReq_hits::1 5617 # number of ReadReq hits -system.l2c.ReadReq_hits::total 659821 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 984468000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.028075 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.006192 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.034267 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18897 # number of ReadReq misses -system.l2c.ReadReq_misses::1 35 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18932 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 757280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028127 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 3.349611 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.377737 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18932 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 29199338000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1750 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1750 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 660.126947 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 657357 # number of ReadReq hits +system.l2c.ReadReq_hits::1 5572 # number of ReadReq hits +system.l2c.ReadReq_hits::total 662929 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 944322500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.026843 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.005000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.031843 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18132 # number of ReadReq misses +system.l2c.ReadReq_misses::1 28 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18160 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 726400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026884 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 3.242857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.269741 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18160 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 29200446000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1825 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 489.208633 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 1144000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.990286 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 69320000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.990286 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.990137 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1807 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1807 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 72280000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.990137 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1733 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1807 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 416231 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 416231 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 416231 # number of Writeback hits -system.l2c.Writeback_hits::total 416231 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 740884000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 415705 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415705 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415705 # number of Writeback hits +system.l2c.Writeback_hits::total 415705 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.975292 # Average number of references to valid blocks. +system.l2c.avg_refs 7.060757 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 843424 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 5652 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 849076 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52014.345374 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 188959200 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 189011214.345374 # average overall miss latency +system.l2c.demand_accesses::0 845845 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 5600 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 851445 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52011.580728 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 233944375 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 233996386.580728 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 716275 # number of demand (read+write) hits -system.l2c.demand_hits::1 5617 # number of demand (read+write) hits -system.l2c.demand_hits::total 721892 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6613572000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.150753 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.006192 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.156946 # miss rate for demand accesses -system.l2c.demand_misses::0 127149 # number of demand (read+write) misses -system.l2c.demand_misses::1 35 # number of demand (read+write) misses -system.l2c.demand_misses::total 127184 # number of demand (read+write) misses +system.l2c.demand_hits::0 719903 # number of demand (read+write) hits +system.l2c.demand_hits::1 5572 # number of demand (read+write) hits +system.l2c.demand_hits::total 725475 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6550442500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.148895 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.005000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.153895 # miss rate for demand accesses +system.l2c.demand_misses::0 125942 # number of demand (read+write) misses +system.l2c.demand_misses::1 28 # number of demand (read+write) misses +system.l2c.demand_misses::total 125970 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5087360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.150795 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 22.502477 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 22.653272 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 127184 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5038800000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.148928 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 22.494643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 22.643571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 125970 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.086431 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.477933 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5664.361976 # Average occupied blocks per context -system.l2c.occ_blocks::1 31321.847814 # Average occupied blocks per context -system.l2c.overall_accesses::0 843424 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 5652 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 849076 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52014.345374 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 188959200 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 189011214.345374 # average overall miss latency +system.l2c.occ_%::0 0.081481 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.477898 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5339.953820 # Average occupied blocks per context +system.l2c.occ_blocks::1 31319.548737 # Average occupied blocks per context +system.l2c.overall_accesses::0 845845 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 5600 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 851445 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52011.580728 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 233944375 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 233996386.580728 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 716275 # number of overall hits -system.l2c.overall_hits::1 5617 # number of overall hits -system.l2c.overall_hits::total 721892 # number of overall hits -system.l2c.overall_miss_latency 6613572000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.150753 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.006192 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.156946 # miss rate for overall accesses -system.l2c.overall_misses::0 127149 # number of overall misses -system.l2c.overall_misses::1 35 # number of overall misses -system.l2c.overall_misses::total 127184 # number of overall misses +system.l2c.overall_hits::0 719903 # number of overall hits +system.l2c.overall_hits::1 5572 # number of overall hits +system.l2c.overall_hits::total 725475 # number of overall hits +system.l2c.overall_miss_latency 6550442500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.148895 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.005000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.153895 # miss rate for overall accesses +system.l2c.overall_misses::0 125942 # number of overall misses +system.l2c.overall_misses::1 28 # number of overall misses +system.l2c.overall_misses::total 125970 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5087360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.150795 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 22.502477 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 22.653272 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 127184 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29939182000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5038800000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.148928 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 22.494643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 22.643571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 125970 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29941330000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94170 # number of replacements -system.l2c.sampled_refs 125831 # Sample count of references to valid blocks. +system.l2c.replacements 93233 # number of replacements +system.l2c.sampled_refs 124676 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36986.209790 # Cycle average of tags in use -system.l2c.total_refs 877708 # Total number of references to valid blocks. +system.l2c.tagsinuse 36659.502556 # Cycle average of tags in use +system.l2c.total_refs 880307 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87626 # number of writebacks +system.l2c.writebacks 87349 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differindex f3053783c..3921585df 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini index 75b04f0f3..296040009 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=MemTest @@ -492,8 +501,9 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports0] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl0.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl0.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -504,8 +514,9 @@ port=system.cpu0.test [system.ruby.cpu_ruby_ports1] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl1.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl1.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -516,8 +527,9 @@ port=system.cpu1.test [system.ruby.cpu_ruby_ports2] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl2.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl2.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -528,8 +540,9 @@ port=system.cpu2.test [system.ruby.cpu_ruby_ports3] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl3.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl3.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -540,8 +553,9 @@ port=system.cpu3.test [system.ruby.cpu_ruby_ports4] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl4.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl4.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -552,8 +566,9 @@ port=system.cpu4.test [system.ruby.cpu_ruby_ports5] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl5.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl5.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -564,8 +579,9 @@ port=system.cpu5.test [system.ruby.cpu_ruby_ports6] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl6.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl6.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -576,8 +592,9 @@ port=system.cpu6.test [system.ruby.cpu_ruby_ports7] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl7.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl7.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index 307193acf..4d13c8032 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -34,47 +34,47 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/13/2011 22:37:51 +Real time: Feb/08/2011 17:40:23 Profiler Stats -------------- -Elapsed_time_in_seconds: 83 -Elapsed_time_in_minutes: 1.38333 -Elapsed_time_in_hours: 0.0230556 -Elapsed_time_in_days: 0.000960648 +Elapsed_time_in_seconds: 508 +Elapsed_time_in_minutes: 8.46667 +Elapsed_time_in_hours: 0.141111 +Elapsed_time_in_days: 0.00587963 -Virtual_time_in_seconds: 82.77 -Virtual_time_in_minutes: 1.3795 -Virtual_time_in_hours: 0.0229917 -Virtual_time_in_days: 0.000957986 +Virtual_time_in_seconds: 508.81 +Virtual_time_in_minutes: 8.48017 +Virtual_time_in_hours: 0.141336 +Virtual_time_in_days: 0.005889 -Ruby_current_time: 3750455 +Ruby_current_time: 44606455 Ruby_start_time: 0 -Ruby_cycles: 3750455 +Ruby_cycles: 44606455 -mbytes_resident: 19.9609 -mbytes_total: 283.734 -resident_ratio: 0.0703783 +mbytes_resident: 36.0898 +mbytes_total: 338.191 +resident_ratio: 0.106749 -ruby_cycles_executed: [ 3750456 3750456 3750456 3750456 3750456 3750456 3750456 3750456 ] +ruby_cycles_executed: [ 44606456 44606456 44606456 44606456 44606456 44606456 44606456 44606456 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 -L2Cache-0:0 +L2Cache-0:26511 Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1214418 average: 1.94809 | standard deviation: 0.221842 | 0 63038 1151380 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1209678 average: 15.9992 | standard deviation: 0.0905568 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1209558 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 8 max: 1079 count: 1214403 average: 47.4054 | standard deviation: 87.7695 | 824470 0 0 12894 11412 8998 17892 40950 24916 42594 9338 3572 16827 9457 11007 15772 161 11564 19818 8986 12734 954 6802 7943 7905 3848 2258 8875 5128 7988 3446 884 5476 4184 3638 4117 237 2891 3956 2527 2729 391 2362 2183 2145 1154 411 1893 1351 1651 981 176 1151 1053 857 816 98 701 743 586 441 76 471 414 382 247 44 339 264 232 184 31 182 166 137 112 12 94 106 81 59 4 52 56 59 34 6 40 35 26 16 2 25 14 13 6 1 10 9 6 8 1 7 5 4 4 0 4 2 7 3 0 0 2 2 1 0 1 3 2 2 0 0 2 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 8 max: 1079 count: 789143 average: 30.7712 | standard deviation: 72.2185 | 629519 0 0 2836 2474 366 17891 15571 10278 19362 276 3568 7258 2108 5077 5648 153 5491 8389 3430 5065 953 2091 3542 2692 420 2258 3543 2000 3479 615 881 2404 1400 1542 1468 237 1126 1600 920 950 391 872 942 824 224 411 784 516 695 265 176 475 413 347 267 98 275 311 226 127 76 179 178 132 65 44 138 108 90 47 31 73 65 50 34 12 26 40 25 14 4 23 18 26 7 6 15 13 12 7 2 17 6 5 0 1 7 4 1 2 1 2 2 1 1 0 2 1 4 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 8 max: 1006 count: 425260 average: 78.2731 | standard deviation: 104.183 | 194951 0 0 10058 8938 8632 1 25379 14638 23232 9062 4 9569 7349 5930 10124 8 6073 11429 5556 7669 1 4711 4401 5213 3428 0 5332 3128 4509 2831 3 3072 2784 2096 2649 0 1765 2356 1607 1779 0 1490 1241 1321 930 0 1109 835 956 716 0 676 640 510 549 0 426 432 360 314 0 292 236 250 182 0 201 156 142 137 0 109 101 87 78 0 68 66 56 45 0 29 38 33 27 0 25 22 14 9 0 8 8 8 6 0 3 5 5 6 0 5 3 3 3 0 2 1 3 1 0 0 1 2 1 0 1 2 2 1 0 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_NULL: [binsize: 8 max: 1079 count: 1214403 average: 47.4054 | standard deviation: 87.7695 | 824470 0 0 12894 11412 8998 17892 40950 24916 42594 9338 3572 16827 9457 11007 15772 161 11564 19818 8986 12734 954 6802 7943 7905 3848 2258 8875 5128 7988 3446 884 5476 4184 3638 4117 237 2891 3956 2527 2729 391 2362 2183 2145 1154 411 1893 1351 1651 981 176 1151 1053 857 816 98 701 743 586 441 76 471 414 382 247 44 339 264 232 184 31 182 166 137 112 12 94 106 81 59 4 52 56 59 34 6 40 35 26 16 2 25 14 13 6 1 10 9 6 8 1 7 5 4 4 0 4 2 7 3 0 0 2 2 1 0 1 3 2 2 0 0 2 2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 4096 max: 668164 count: 1209550 average: 4719.92 | standard deviation: 8274.07 | 638780 444277 77264 20058 11632 6634 3721 2287 1498 951 565 385 192 142 161 87 51 58 50 36 40 36 47 26 23 19 17 23 21 23 19 17 18 10 12 15 16 14 17 11 13 10 18 10 10 15 7 8 5 10 13 8 6 4 7 3 3 7 7 11 4 5 2 3 4 2 3 1 2 9 3 3 0 3 1 5 2 4 3 0 0 3 2 2 2 2 2 2 2 1 1 1 1 3 2 2 1 1 1 2 1 0 2 2 2 0 0 1 1 2 1 2 4 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 4096 max: 668164 count: 786272 average: 4719.14 | standard deviation: 8618.14 | 415711 288653 50021 12927 7526 4347 2411 1503 957 613 346 254 128 93 117 61 33 39 28 17 27 20 28 16 16 10 14 18 16 18 16 13 9 9 7 9 11 8 12 7 10 6 11 7 7 8 5 8 3 6 9 3 5 2 6 3 2 6 6 9 3 4 1 2 4 1 0 1 2 6 0 3 0 2 1 2 1 3 2 0 0 2 1 2 1 2 1 2 0 1 1 1 1 2 1 1 0 1 0 2 1 0 2 1 0 0 0 1 1 2 1 1 3 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 4096 max: 528524 count: 423278 average: 4721.37 | standard deviation: 6405.47 | 223069 155624 27243 7131 4106 2287 1310 784 541 338 219 131 64 49 44 26 18 19 22 19 13 16 19 10 7 9 3 5 5 5 3 4 9 1 5 6 5 6 5 4 3 4 7 3 3 7 2 0 2 4 4 5 1 2 1 0 1 1 1 2 1 1 1 1 0 1 3 0 0 3 3 0 0 1 0 3 1 1 1 0 0 1 1 0 1 0 1 0 2 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 2 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 4096 max: 668164 count: 1209550 average: 4719.92 | standard deviation: 8274.07 | 638780 444277 77264 20058 11632 6634 3721 2287 1498 951 565 385 192 142 161 87 51 58 50 36 40 36 47 26 23 19 17 23 21 23 19 17 18 10 12 15 16 14 17 11 13 10 18 10 10 15 7 8 5 10 13 8 6 4 7 3 3 7 7 11 4 5 2 3 4 2 3 1 2 9 3 3 0 3 1 5 2 4 3 0 0 3 2 2 2 2 2 2 2 1 1 1 1 3 2 2 1 1 1 2 1 0 2 2 2 0 0 1 1 2 1 2 4 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,8 +85,8 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 8 max: 1079 count: 789143 average: 30.7712 | standard deviation: 72.2185 | 629519 0 0 2836 2474 366 17891 15571 10278 19362 276 3568 7258 2108 5077 5648 153 5491 8389 3430 5065 953 2091 3542 2692 420 2258 3543 2000 3479 615 881 2404 1400 1542 1468 237 1126 1600 920 950 391 872 942 824 224 411 784 516 695 265 176 475 413 347 267 98 275 311 226 127 76 179 178 132 65 44 138 108 90 47 31 73 65 50 34 12 26 40 25 14 4 23 18 26 7 6 15 13 12 7 2 17 6 5 0 1 7 4 1 2 1 2 2 1 1 0 2 1 4 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 8 max: 1006 count: 425260 average: 78.2731 | standard deviation: 104.183 | 194951 0 0 10058 8938 8632 1 25379 14638 23232 9062 4 9569 7349 5930 10124 8 6073 11429 5556 7669 1 4711 4401 5213 3428 0 5332 3128 4509 2831 3 3072 2784 2096 2649 0 1765 2356 1607 1779 0 1490 1241 1321 930 0 1109 835 956 716 0 676 640 510 549 0 426 432 360 314 0 292 236 250 182 0 201 156 142 137 0 109 101 87 78 0 68 66 56 45 0 29 38 33 27 0 25 22 14 9 0 8 8 8 6 0 3 5 5 6 0 5 3 3 3 0 2 1 3 1 0 0 1 2 1 0 1 2 2 1 0 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 4096 max: 668164 count: 786272 average: 4719.14 | standard deviation: 8618.14 | 415711 288653 50021 12927 7526 4347 2411 1503 957 613 346 254 128 93 117 61 33 39 28 17 27 20 28 16 16 10 14 18 16 18 16 13 9 9 7 9 11 8 12 7 10 6 11 7 7 8 5 8 3 6 9 3 5 2 6 3 2 6 6 9 3 4 1 2 4 1 0 1 2 6 0 3 0 2 1 2 1 3 2 0 0 2 1 2 1 2 1 2 0 1 1 1 1 2 1 1 0 1 0 2 1 0 2 1 0 0 0 1 1 2 1 1 3 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 4096 max: 528524 count: 423278 average: 4721.37 | standard deviation: 6405.47 | 223069 155624 27243 7131 4106 2287 1310 784 541 338 219 131 64 49 44 26 18 19 22 19 13 16 19 10 7 9 3 5 5 5 3 4 9 1 5 6 5 6 5 4 3 4 7 3 3 7 2 0 2 4 4 5 1 2 1 0 1 1 1 2 1 1 1 1 0 1 3 0 0 3 3 0 0 1 0 3 1 1 1 0 0 1 1 0 1 0 1 0 2 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 2 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -100,12 +100,12 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 32 max: 1060 count: 1913633 average: 23.7314 | standard deviation: 66.6438 | 1615818 76894 36728 51093 28828 31559 16836 13214 11846 8004 7926 4154 3044 2472 1588 1447 724 490 338 202 198 80 52 27 22 16 14 4 5 4 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1199123 average: 0.00254603 | standard deviation: 0.057655 | 1196518 2179 404 22 ] - virtual_network_0_delay_cycles: [binsize: 32 max: 1060 count: 714510 average: 63.5543 | standard deviation: 96.7696 | 416695 76894 36728 51093 28828 31559 16836 13214 11846 8004 7926 4154 3044 2472 1588 1447 724 490 338 202 198 80 52 27 22 16 14 4 5 4 5 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_delay_cycles: [binsize: 2048 max: 81271 count: 9469233 average: 110.621 | standard deviation: 505.81 | 9455869 3415 2382 1953 1397 1072 815 622 431 313 232 152 153 103 80 56 46 40 17 18 15 12 4 8 2 6 7 3 2 2 0 1 0 0 3 0 0 0 0 2 0 0 0 0 0 0 0 0 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 1 count: 6455267 average: 5.1276e-05 | standard deviation: 0.00716072 | 6454936 331 ] + virtual_network_0_delay_cycles: [binsize: 2048 max: 81271 count: 3013966 average: 347.548 | standard deviation: 849.39 | 3000602 3415 2382 1953 1397 1072 815 622 431 313 232 152 153 103 80 56 46 40 17 18 15 12 4 8 2 6 7 3 2 2 0 1 0 0 3 0 0 0 0 2 0 0 0 0 0 0 0 0 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 3 count: 472614 average: 0.0053257 | standard deviation: 0.0852408 | 470540 1653 399 22 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 726509 average: 0.000737775 | standard deviation: 0.0274142 | 725978 526 5 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 1 count: 1119608 average: 6.25219e-06 | standard deviation: 0.00250044 | 1119601 7 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 1 count: 5335659 average: 6.07235e-05 | standard deviation: 0.00779253 | 5335335 324 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -116,9 +116,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1199123 average: 0.00254603 Resource Usage -------------- page_size: 4096 -user_time: 82 +user_time: 508 system_time: 0 -page_reclaims: 5799 +page_reclaims: 10505 page_faults: 0 swaps: 0 block_inputs: 0 @@ -127,181 +127,208 @@ block_outputs: 0 Network Stats ------------- -total_msg_count_Control: 1169847 9358776 -total_msg_count_Request_Control: 1269806 10158448 -total_msg_count_Response_Data: 1417845 102084840 -total_msg_count_Response_Control: 1735406 13883248 -total_msgs: 5592904 total_bytes: 135485312 +total_msg_count_Control: 7234287 57874296 +total_msg_count_Request_Control: 3352867 26822936 +total_msg_count_Response_Data: 8501093 612078696 +total_msg_count_Response_Control: 12544428 100355424 +total_msg_count_Writeback_Data: 2803846 201876912 +total_msg_count_Writeback_Control: 1171668 9373344 +total_msgs: 35608189 total_bytes: 1008381608 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.416004 - links_utilized_percent_switch_0_link_0: 0.17421 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.657799 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 59976 479808 [ 59976 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 47892 3448224 [ 0 47892 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 31689 253512 [ 0 31689 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 49369 394952 [ 49369 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 41367 2978424 [ 0 41367 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 71737 573896 [ 0 30695 41042 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.104449 + links_utilized_percent_switch_0_link_0: 0.0444403 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.164457 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 141029 1128232 [ 141029 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 152090 10950480 [ 0 152090 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 76021 608168 [ 0 76021 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 152092 1216736 [ 152092 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 484 34848 [ 0 484 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 200672 1605376 [ 0 49763 150909 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 117888 8487936 [ 26963 90925 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 49059 392472 [ 49059 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.412969 - links_utilized_percent_switch_1_link_0: 0.173819 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.65212 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 59702 477616 [ 59702 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 47820 3443040 [ 0 47820 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 31438 251504 [ 0 31438 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 49257 394056 [ 49257 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 40912 2945664 [ 0 40912 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 71684 573472 [ 0 30672 41012 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.105352 + links_utilized_percent_switch_1_link_0: 0.0448859 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.165818 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 142261 1138088 [ 142261 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 153623 11060856 [ 0 153623 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 76891 615128 [ 0 76891 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 153625 1229000 [ 153625 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 491 35352 [ 0 491 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 202705 1621640 [ 0 50260 152445 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 118753 8550216 [ 27097 91656 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 49789 398312 [ 49789 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.4136 - links_utilized_percent_switch_2_link_0: 0.173041 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.654158 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 59557 476456 [ 59557 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 47536 3422592 [ 0 47536 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 31806 254448 [ 0 31806 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 49047 392376 [ 49047 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 41125 2961000 [ 0 41125 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 71506 572048 [ 0 30453 41053 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.1034 + links_utilized_percent_switch_2_link_0: 0.0441434 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.162657 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 139745 1117960 [ 139745 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 151126 10881072 [ 0 151126 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 75386 603088 [ 0 75386 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 151129 1209032 [ 151129 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 485 34920 [ 0 485 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 199681 1597448 [ 0 49774 149907 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 116365 8378280 [ 26738 89627 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 48648 389184 [ 48648 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.410067 - links_utilized_percent_switch_3_link_0: 0.172661 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.647473 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 59126 473008 [ 59126 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 47416 3413952 [ 0 47416 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 32177 257416 [ 0 32177 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 48856 390848 [ 48856 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 40642 2926224 [ 0 40642 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 71030 568240 [ 0 30194 40836 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.104799 + links_utilized_percent_switch_3_link_0: 0.0446279 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.16497 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 141577 1132616 [ 141577 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 152754 10998288 [ 0 152754 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 76191 609528 [ 0 76191 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 152758 1222064 [ 152758 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 515 37080 [ 0 515 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 201709 1613672 [ 0 50165 151544 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 118175 8508600 [ 27125 91050 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 49066 392528 [ 49066 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.407326 - links_utilized_percent_switch_4_link_0: 0.17208 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.642573 bw: 160000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Request_Control: 58944 471552 [ 58944 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 47294 3405168 [ 0 47294 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 31713 253704 [ 0 31713 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 48686 389488 [ 48686 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 40277 2899944 [ 0 40277 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 70809 566472 [ 0 30317 40492 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 0.10421 + links_utilized_percent_switch_4_link_0: 0.0443719 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.164048 bw: 160000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Request_Control: 140569 1124552 [ 140569 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 151893 10936296 [ 0 151893 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 75812 606496 [ 0 75812 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 151895 1215160 [ 151895 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 513 36936 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 200376 1603008 [ 0 49681 150695 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 117536 8462592 [ 27004 90532 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 48808 390464 [ 48808 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.408786 - links_utilized_percent_switch_5_link_0: 0.171315 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.646256 bw: 160000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Request_Control: 58908 471264 [ 58908 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 47044 3387168 [ 0 47044 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 31703 253624 [ 0 31703 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 48502 388016 [ 48502 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 40634 2925648 [ 0 40634 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 70543 564344 [ 0 30139 40404 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 0.101404 + links_utilized_percent_switch_5_link_0: 0.0432323 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.159576 bw: 160000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Request_Control: 137030 1096240 [ 137030 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 147989 10655208 [ 0 147989 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 73821 590568 [ 0 73821 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 147993 1183944 [ 147993 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 504 36288 [ 0 504 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 195355 1562840 [ 0 48520 146835 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 114221 8223912 [ 26070 88151 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 47750 382000 [ 47750 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.405763 - links_utilized_percent_switch_6_link_0: 0.170848 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.640678 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Request_Control: 58592 468736 [ 58592 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 46924 3378528 [ 0 46924 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 31699 253592 [ 0 31699 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 48385 387080 [ 48385 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 40226 2896272 [ 0 40226 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 70148 561184 [ 0 30034 40114 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.102366 + links_utilized_percent_switch_6_link_0: 0.0437156 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.161015 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Request_Control: 138259 1106072 [ 138259 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 149657 10775304 [ 0 149657 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 74826 598608 [ 0 74826 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 149660 1197280 [ 149660 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 453 32616 [ 0 453 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 197444 1579552 [ 0 48952 148492 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 115184 8293248 [ 26197 88987 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Control: 48629 389032 [ 48629 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.399042 - links_utilized_percent_switch_7_link_0: 0.169071 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.629013 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Request_Control: 57809 462472 [ 57809 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 46422 3342384 [ 0 46422 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 31667 253336 [ 0 31667 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 47845 382760 [ 47845 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 39394 2836368 [ 0 39394 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 69426 555408 [ 0 29802 39624 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.103268 + links_utilized_percent_switch_7_link_0: 0.0439489 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.162587 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Request_Control: 139138 1113104 [ 139138 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 150412 10829664 [ 0 150412 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 75477 603816 [ 0 75477 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 150413 1203304 [ 150413 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 521 37512 [ 0 521 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 198127 1585016 [ 0 48950 149177 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 116494 8387568 [ 26667 89827 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Control: 48807 390456 [ 48807 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 1.37261 - links_utilized_percent_switch_8_link_0: 0.520924 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 2.22429 bw: 160000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Control: 389947 3119576 [ 389947 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Data: 94271 6787512 [ 0 94271 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 324576 2596608 [ 0 0 324576 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 324578 2596624 [ 324578 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 148028 10658016 [ 0 148028 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 11586 92688 [ 0 11586 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 1.35802 + links_utilized_percent_switch_8_link_0: 0.662373 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 2.05366 bw: 160000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Control: 1209565 9676520 [ 1209565 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Data: 1203036 86618592 [ 0 1203036 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 2797904 22383232 [ 0 1597900 1200004 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 934615 67292280 [ 213861 720754 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Control: 390556 3124448 [ 390556 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Control: 1201864 9614912 [ 1201864 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 1113651 8909208 [ 1113651 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 1624693 116977896 [ 0 1624693 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 1383558 11068464 [ 0 1383558 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 1.23318e-05 - links_utilized_percent_switch_9_link_0: 6.66586e-07 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.39971e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 0.754651 + links_utilized_percent_switch_9_link_0: 0.162123 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 1.34718 bw: 160000 base_latency: 1 - outgoing_messages_switch_9_link_0_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Control: 1201864 9614912 [ 1201864 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 422708 30434976 [ 0 422708 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 779147 6233176 [ 0 779147 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 1201858 86533776 [ 0 1201858 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 1201849 9614792 [ 0 1201849 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.759188 - links_utilized_percent_switch_10_link_0: 0.696839 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.695276 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.692165 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.690646 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.68832 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.68526 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.683393 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.676283 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 2.0837 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 2.66634e-06 bw: 160000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Request_Control: 59976 479808 [ 59976 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 47892 3448224 [ 0 47892 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 31689 253512 [ 0 31689 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Request_Control: 59702 477616 [ 59702 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 47820 3443040 [ 0 47820 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 31438 251504 [ 0 31438 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Request_Control: 59557 476456 [ 59557 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 47536 3422592 [ 0 47536 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 31806 254448 [ 0 31806 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Request_Control: 59126 473008 [ 59126 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 47416 3413952 [ 0 47416 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 32177 257416 [ 0 32177 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Request_Control: 58944 471552 [ 58944 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 47294 3405168 [ 0 47294 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 31713 253704 [ 0 31713 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Request_Control: 58908 471264 [ 58908 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 47044 3387168 [ 0 47044 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 31703 253624 [ 0 31703 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Request_Control: 58592 468736 [ 58592 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 46924 3378528 [ 0 46924 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 31699 253592 [ 0 31699 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Request_Control: 57809 462472 [ 57809 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 46422 3342384 [ 0 46422 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 31667 253336 [ 0 31667 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 389947 3119576 [ 389947 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Data: 94271 6787512 [ 0 94271 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 324577 2596616 [ 0 0 324577 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_10: 0.471145 + links_utilized_percent_switch_10_link_0: 0.177761 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.179543 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.176574 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.178512 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.177488 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.172929 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.174862 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.175796 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 2.64949 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 0.648492 bw: 160000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Request_Control: 141029 1128232 [ 141029 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 152090 10950480 [ 0 152090 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 76021 608168 [ 0 76021 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Request_Control: 142261 1138088 [ 142261 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 153623 11060856 [ 0 153623 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 76891 615128 [ 0 76891 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Request_Control: 139745 1117960 [ 139745 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 151126 10881072 [ 0 151126 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 75386 603088 [ 0 75386 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Request_Control: 141577 1132616 [ 141577 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 152754 10998288 [ 0 152754 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 76191 609528 [ 0 76191 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Request_Control: 140569 1124552 [ 140569 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 151893 10936296 [ 0 151893 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 75812 606496 [ 0 75812 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Request_Control: 137030 1096240 [ 137030 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 147989 10655208 [ 0 147989 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 73821 590568 [ 0 73821 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Request_Control: 138259 1106072 [ 138259 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 149657 10775304 [ 0 149657 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 74826 598608 [ 0 74826 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Request_Control: 139138 1113104 [ 139138 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 150412 10829664 [ 0 150412 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 75477 603816 [ 0 75477 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 1209565 9676520 [ 1209565 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Data: 1203036 86618592 [ 0 1203036 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 2797904 22383232 [ 0 1597900 1200004 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Writeback_Data: 934615 67292280 [ 213861 720754 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Writeback_Control: 390556 3124448 [ 390556 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Control: 1201864 9614912 [ 1201864 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Response_Data: 422708 30434976 [ 0 422708 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Response_Control: 779147 6233176 [ 0 779147 0 0 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -321,84 +348,84 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory --- L1Cache --- - Event Counts - -Load [98631 98244 97407 96638 100000 99918 99521 98787 ] 789146 +Load [98886 96243 97583 97728 98791 100101 98555 99215 ] 787102 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [52748 52924 52660 51759 54108 53759 53950 53363 ] 425271 -Inv [30317 30139 30034 29802 30695 30672 30453 30194 ] 242306 -L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -Fwd_GETX [16977 16904 16890 16620 17195 17148 17083 17222 ] 136039 -Fwd_GETS [11650 11865 11668 11387 12086 11882 12021 11710 ] 94269 +Store [53456 51755 52117 53064 54558 53626 53073 53642 ] 425291 +Inv [140213 136671 137939 138777 140688 141916 139401 141215 ] 1116820 +L1_Replacement [59176647 59366144 59287548 59249710 59221304 59185380 59232447 59146573 ] 473865753 +Fwd_GETX [199 214 187 201 198 199 203 209 ] 1610 +Fwd_GETS [157 145 133 160 143 146 141 153 ] 1178 Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -Data [10466 10303 10281 10332 10345 10249 10257 10451 ] 82684 -Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 -DataS_fromL1 [11865 11635 11556 11617 11760 11982 11949 11904 ] 94268 -Data_all_Acks [24963 25105 25087 24473 25787 25589 25330 25061 ] 201395 -Ack [19857 19943 19959 19914 19867 19754 20040 20288 ] 159622 -Ack_all [11856 11760 11740 11753 11822 11684 11766 11889 ] 94270 -WB_Ack [0 0 0 0 0 0 0 0 ] 0 +Data [0 1 0 2 0 3 0 1 ] 7 +Data_Exclusive [97101 94947 96224 96338 97462 98657 97005 97817 ] 775551 +DataS_fromL1 [145 139 155 134 142 164 149 150 ] 1178 +Data_all_Acks [54647 52902 53278 53938 54486 54799 53972 54786 ] 432808 +Ack [0 1 0 2 0 3 0 1 ] 7 +Ack_all [0 1 0 2 0 3 0 1 ] 7 +WB_Ack [75812 73819 74826 75473 76021 76885 75386 76189 ] 604411 - Transitions - -NP Load [2 2 1 2 2 2 2 1 ] 14 +NP Load [98431 96234 97525 97692 98769 99980 98359 99167 ] 786157 NP Ifetch [0 0 0 0 0 0 0 0 ] 0 -NP Store [0 0 1 0 0 0 0 1 ] 2 -NP Inv [0 0 0 0 0 0 0 0 ] 0 +NP Store [53441 51747 52107 52691 53297 53619 52748 53573 ] 423223 +NP Inv [659 638 628 693 652 649 657 685 ] 5261 NP L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -I Load [20055 19731 19824 19834 20085 20223 19939 19922 ] 159613 +I Load [15 7 22 16 17 20 15 14 ] 126 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [10642 10737 10713 10485 10952 10852 10710 10852 ] 85943 +I Store [8 5 6 14 9 6 7 4 ] 59 I Inv [0 0 0 0 0 0 0 0 ] 0 -I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I L1_Replacement [75454 73571 74216 74266 75441 76105 75113 75916 ] 600082 -S Load [33152 33048 32637 32620 33721 34023 33841 33185 ] 266227 +S Load [0 0 0 0 0 0 0 0 ] 0 S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [17987 18032 17846 17524 18330 18180 18396 18080 ] 144375 -S Inv [11616 11475 11582 11602 11637 11749 11468 11453 ] 92582 -S L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +S Store [0 0 0 0 0 0 0 0 ] 0 +S Inv [841 800 825 835 814 838 852 828 ] 6633 +S L1_Replacement [602 586 586 639 599 604 604 629 ] 4849 -E Load [0 0 0 0 0 0 0 0 ] 0 +E Load [0 0 2 0 0 1 0 0 ] 3 E Ifetch [0 0 0 0 0 0 0 0 ] 0 -E Store [0 0 0 0 0 0 0 0 ] 0 -E Inv [0 0 0 0 0 0 0 0 ] 0 -E L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -E Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -E Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +E Store [0 0 0 1 0 0 1 0 ] 2 +E Inv [48181 47082 47499 47422 48297 48773 48265 48652 ] 384171 +E L1_Replacement [48812 47751 48633 48809 49061 49789 48649 49067 ] 390571 +E Fwd_GETX [80 95 72 85 85 77 76 85 ] 655 +E Fwd_GETS [28 19 19 21 19 18 14 13 ] 151 E Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -M Load [45422 45463 44945 44182 46192 45670 45739 45679 ] 363292 +M Load [0 0 0 0 0 0 0 0 ] 0 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [24119 24155 24100 23750 24826 24727 24844 24430 ] 194951 -M Inv [0 0 0 0 0 0 0 0 ] 0 -M L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -M Fwd_GETX [16977 16904 16890 16620 17195 17148 17083 17222 ] 136039 -M Fwd_GETS [11650 11865 11668 11387 12086 11882 12021 11710 ] 94269 +M Store [0 0 0 0 0 1 0 0 ] 1 +M Inv [26338 25564 25813 25909 26233 26398 25893 26331 ] 208479 +M L1_Replacement [27000 26069 26193 26665 26961 27097 26737 27124 ] 213846 +M Fwd_GETX [39 42 35 47 40 46 50 38 ] 337 +M Fwd_GETS [72 74 72 85 71 83 74 84 ] 615 M Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 -IS Inv [2104 2089 2065 2097 2205 2178 2098 2099 ] 16935 -IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -IS Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 -IS DataS_fromL1 [11865 11635 11556 11617 11760 11982 11949 11904 ] 94268 -IS Data_all_Acks [6088 6007 6204 6122 6122 6065 5894 5919 ] 48421 +IS Inv [0 0 0 0 0 0 0 0 ] 0 +IS L1_Replacement [38113203 38318741 38190806 37721962 37990776 37966622 37976621 38191379 ] 304470110 +IS Data_Exclusive [97101 94947 96224 96338 97462 98657 97005 97817 ] 775551 +IS DataS_fromL1 [145 139 155 134 142 164 149 150 ] 1178 +IS Data_all_Acks [1198 1154 1165 1235 1181 1178 1219 1210 ] 9540 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM Inv [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -IM Data [10466 10303 10281 10332 10345 10249 10257 10451 ] 82684 -IM Data_all_Acks [16771 17009 16818 16254 17460 17346 17338 17043 ] 136039 +IM L1_Replacement [20911576 20899418 20947114 21377361 21078466 21065137 21104723 20802458 ] 168186253 +IM Data [0 1 0 2 0 3 0 1 ] 7 +IM Data_all_Acks [53449 51748 52113 52703 53305 53621 52753 53576 ] 423268 IM Ack [0 0 0 0 0 0 0 0 ] 0 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 -SM Inv [16597 16575 16387 16103 16853 16745 16887 16642 ] 132789 -SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM Ack [19857 19943 19959 19914 19867 19754 20040 20288 ] 159622 -SM Ack_all [11856 11760 11740 11753 11822 11684 11766 11889 ] 94270 +SM Inv [0 0 0 0 0 0 0 0 ] 0 +SM L1_Replacement [0 8 0 8 0 26 0 0 ] 42 +SM Ack [0 1 0 2 0 3 0 1 ] 7 +SM Ack_all [0 1 0 2 0 3 0 1 ] 7 IS_I Load [0 0 0 0 0 0 0 0 ] 0 IS_I Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -407,29 +434,29 @@ IS_I Inv [0 0 0 0 0 0 0 0 ] 0 IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0 -IS_I Data_all_Acks [2104 2089 2065 2097 2205 2178 2098 2099 ] 16935 +IS_I Data_all_Acks [0 0 0 0 0 0 0 0 ] 0 M_I Load [0 0 0 0 0 0 0 0 ] 0 M_I Ifetch [0 0 0 0 0 0 0 0 ] 0 M_I Store [0 0 0 0 0 0 0 0 ] 0 -M_I Inv [0 0 0 0 0 0 0 0 ] 0 +M_I Inv [64194 62587 63174 63918 64692 65258 63734 64719 ] 512276 M_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_I Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -M_I Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +M_I Fwd_GETX [80 77 80 69 73 76 77 86 ] 618 +M_I Fwd_GETS [57 52 42 54 53 45 53 56 ] 412 M_I Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -M_I WB_Ack [0 0 0 0 0 0 0 0 ] 0 +M_I WB_Ack [11481 11104 11530 11433 11204 11507 11522 11330 ] 91111 E_I Load [0 0 0 0 0 0 0 0 ] 0 E_I Ifetch [0 0 0 0 0 0 0 0 ] 0 E_I Store [0 0 0 0 0 0 0 0 ] 0 E_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK Load [0 0 0 0 0 0 0 0 ] 0 +SINK_WB_ACK Load [440 2 34 20 5 100 181 34 ] 816 SINK_WB_ACK Ifetch [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK Store [0 0 0 0 0 0 0 0 ] 0 +SINK_WB_ACK Store [7 3 4 358 1252 0 317 65 ] 2006 SINK_WB_ACK Inv [0 0 0 0 0 0 0 0 ] 0 SINK_WB_ACK L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK WB_Ack [0 0 0 0 0 0 0 0 ] 0 +SINK_WB_ACK WB_Ack [64331 62715 63296 64040 64817 65378 63864 64859 ] 513300 Cache Stats: system.l1_cntrl1.L1IcacheMemory system.l1_cntrl1.L1IcacheMemory_total_misses: 0 @@ -554,69 +581,69 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory --- L2Cache --- - Event Counts - L1_GET_INSTR [0 ] 0 -L1_GETS [2029346 ] 2029346 -L1_GETX [2583035 ] 2583035 -L1_UPGRADE [318717 ] 318717 -L1_PUTX [0 ] 0 -L1_PUTX_old [0 ] 0 +L1_GETS [848065 ] 848065 +L1_GETX [519919 ] 519919 +L1_UPGRADE [0 ] 0 +L1_PUTX [94198 ] 94198 +L1_PUTX_old [525501 ] 525501 Fwd_L1_GETX [0 ] 0 Fwd_L1_GETS [0 ] 0 Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [0 ] 0 -L2_Replacement_clean [0 ] 0 -Mem_Data [2 ] 2 -Mem_Ack [0 ] 0 -WB_Data [94268 ] 94268 -WB_Data_clean [0 ] 0 -Ack [0 ] 0 -Ack_all [0 ] 0 -Unblock [94268 ] 94268 +L2_Replacement [34658 ] 34658 +L2_Replacement_clean [105741810 ] 105741810 +Mem_Data [1201858 ] 1201858 +Mem_Ack [1201849 ] 1201849 +WB_Data [390262 ] 390262 +WB_Data_clean [331670 ] 331670 +Ack [5950 ] 5950 +Ack_all [390101 ] 390101 +Unblock [1178 ] 1178 Unblock_Cancel [0 ] 0 -Exclusive_Unblock [230308 ] 230308 +Exclusive_Unblock [1198826 ] 1198826 MEM_Inv [0 ] 0 - Transitions - NP L1_GET_INSTR [0 ] 0 -NP L1_GETS [2 ] 2 -NP L1_GETX [0 ] 0 +NP L1_GETS [780251 ] 780251 +NP L1_GETX [421614 ] 421614 NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [0 ] 0 +NP L1_PUTX_old [454090 ] 454090 SS L1_GET_INSTR [0 ] 0 -SS L1_GETS [65342 ] 65342 -SS L1_GETX [82684 ] 82684 -SS L1_UPGRADE [11586 ] 11586 +SS L1_GETS [9 ] 9 +SS L1_GETX [7 ] 7 +SS L1_UPGRADE [0 ] 0 SS L1_PUTX [0 ] 0 SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L2_Replacement_clean [0 ] 0 +SS L2_Replacement [1026 ] 1026 +SS L2_Replacement_clean [4905 ] 4905 SS MEM_Inv [0 ] 0 M L1_GET_INSTR [0 ] 0 -M L1_GETS [0 ] 0 -M L1_GETX [0 ] 0 +M L1_GETS [66 ] 66 +M L1_GETX [45 ] 45 M L1_PUTX [0 ] 0 -M L1_PUTX_old [0 ] 0 -M L2_Replacement [0 ] 0 -M L2_Replacement_clean [0 ] 0 +M L1_PUTX_old [15 ] 15 +M L2_Replacement [32427 ] 32427 +M L2_Replacement_clean [58573 ] 58573 M MEM_Inv [0 ] 0 MT L1_GET_INSTR [0 ] 0 -MT L1_GETS [94269 ] 94269 -MT L1_GETX [136039 ] 136039 -MT L1_PUTX [0 ] 0 -MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [0 ] 0 -MT L2_Replacement_clean [0 ] 0 +MT L1_GETS [1178 ] 1178 +MT L1_GETX [1610 ] 1610 +MT L1_PUTX [91111 ] 91111 +MT L1_PUTX_old [386 ] 386 +MT L2_Replacement [28 ] 28 +MT L2_Replacement_clean [1104898 ] 1104898 MT MEM_Inv [0 ] 0 M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [0 ] 0 -M_I L1_GETX [0 ] 0 +M_I L1_GETS [6331 ] 6331 +M_I L1_GETX [3188 ] 3188 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [0 ] 0 -M_I Mem_Ack [0 ] 0 +M_I L1_PUTX_old [56154 ] 56154 +M_I Mem_Ack [1201849 ] 1201849 M_I MEM_Inv [0 ] 0 MT_I L1_GET_INSTR [0 ] 0 @@ -625,29 +652,29 @@ MT_I L1_GETX [0 ] 0 MT_I L1_UPGRADE [0 ] 0 MT_I L1_PUTX [0 ] 0 MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [0 ] 0 +MT_I WB_Data [8 ] 8 MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [0 ] 0 +MT_I Ack_all [20 ] 20 MT_I MEM_Inv [0 ] 0 MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [0 ] 0 -MCT_I L1_GETX [0 ] 0 +MCT_I L1_GETS [266 ] 266 +MCT_I L1_GETX [392 ] 392 MCT_I L1_UPGRADE [0 ] 0 MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [0 ] 0 -MCT_I WB_Data [0 ] 0 -MCT_I WB_Data_clean [0 ] 0 -MCT_I Ack_all [0 ] 0 +MCT_I L1_PUTX_old [12610 ] 12610 +MCT_I WB_Data [389227 ] 389227 +MCT_I WB_Data_clean [331519 ] 331519 +MCT_I Ack_all [384151 ] 384151 I_I L1_GET_INSTR [0 ] 0 I_I L1_GETS [0 ] 0 -I_I L1_GETX [0 ] 0 +I_I L1_GETX [2 ] 2 I_I L1_UPGRADE [0 ] 0 I_I L1_PUTX [0 ] 0 I_I L1_PUTX_old [0 ] 0 -I_I Ack [0 ] 0 -I_I Ack_all [0 ] 0 +I_I Ack [4915 ] 4915 +I_I Ack_all [4904 ] 4904 S_I L1_GET_INSTR [0 ] 0 S_I L1_GETS [0 ] 0 @@ -655,62 +682,62 @@ S_I L1_GETX [0 ] 0 S_I L1_UPGRADE [0 ] 0 S_I L1_PUTX [0 ] 0 S_I L1_PUTX_old [0 ] 0 -S_I Ack [0 ] 0 -S_I Ack_all [0 ] 0 +S_I Ack [1035 ] 1035 +S_I Ack_all [1026 ] 1026 S_I MEM_Inv [0 ] 0 ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [2 ] 2 -ISS L1_GETX [1 ] 1 +ISS L1_GETS [4760 ] 4760 +ISS L1_GETX [57052 ] 57052 ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [0 ] 0 +ISS L1_PUTX_old [869 ] 869 ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [0 ] 0 -ISS Mem_Data [0 ] 0 +ISS L2_Replacement_clean [63408696 ] 63408696 +ISS Mem_Data [775485 ] 775485 ISS MEM_Inv [0 ] 0 IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [10 ] 10 -IS L1_GETX [60 ] 60 +IS L1_GETS [11 ] 11 +IS L1_GETX [353 ] 353 IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [0 ] 0 +IS L1_PUTX_old [3 ] 3 IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [0 ] 0 -IS Mem_Data [2 ] 2 +IS L2_Replacement_clean [465689 ] 465689 +IS Mem_Data [4760 ] 4760 IS MEM_Inv [0 ] 0 IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [0 ] 0 -IM L1_GETX [0 ] 0 +IM L1_GETS [52721 ] 52721 +IM L1_GETX [31631 ] 31631 IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [0 ] 0 +IM L1_PUTX_old [1371 ] 1371 IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [0 ] 0 -IM Mem_Data [0 ] 0 +IM L2_Replacement_clean [34417195 ] 34417195 +IM Mem_Data [421613 ] 421613 IM MEM_Inv [0 ] 0 SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [471755 ] 471755 -SS_MB L1_GETX [572825 ] 572825 -SS_MB L1_UPGRADE [265946 ] 265946 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 SS_MB L1_PUTX [0 ] 0 SS_MB L1_PUTX_old [0 ] 0 SS_MB L2_Replacement [0 ] 0 -SS_MB L2_Replacement_clean [0 ] 0 +SS_MB L2_Replacement_clean [23 ] 23 SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [94269 ] 94269 +SS_MB Exclusive_Unblock [7 ] 7 SS_MB MEM_Inv [0 ] 0 MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [858796 ] 858796 -MT_MB L1_GETX [1078050 ] 1078050 +MT_MB L1_GETS [2451 ] 2451 +MT_MB L1_GETX [4019 ] 4019 MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [0 ] 0 -MT_MB L1_PUTX_old [0 ] 0 +MT_MB L1_PUTX [1851 ] 1851 +MT_MB L1_PUTX_old [3 ] 3 MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [0 ] 0 +MT_MB L2_Replacement_clean [6280543 ] 6280543 MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [136039 ] 136039 +MT_MB Exclusive_Unblock [1198819 ] 1198819 MT_MB MEM_Inv [0 ] 0 M_MB L1_GET_INSTR [0 ] 0 @@ -725,15 +752,15 @@ M_MB Exclusive_Unblock [0 ] 0 M_MB MEM_Inv [0 ] 0 MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [384618 ] 384618 -MT_IIB L1_GETX [506028 ] 506028 +MT_IIB L1_GETS [14 ] 14 +MT_IIB L1_GETX [4 ] 4 MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX [824 ] 824 MT_IIB L1_PUTX_old [0 ] 0 MT_IIB L2_Replacement [0 ] 0 -MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [94268 ] 94268 -MT_IIB WB_Data_clean [0 ] 0 +MT_IIB L2_Replacement_clean [1252 ] 1252 +MT_IIB WB_Data [1027 ] 1027 +MT_IIB WB_Data_clean [151 ] 151 MT_IIB Unblock [0 ] 0 MT_IIB MEM_Inv [0 ] 0 @@ -751,48 +778,48 @@ MT_IB Unblock_Cancel [0 ] 0 MT_IB MEM_Inv [0 ] 0 MT_SB L1_GET_INSTR [0 ] 0 -MT_SB L1_GETS [154552 ] 154552 -MT_SB L1_GETX [207348 ] 207348 -MT_SB L1_UPGRADE [41185 ] 41185 -MT_SB L1_PUTX [0 ] 0 +MT_SB L1_GETS [7 ] 7 +MT_SB L1_GETX [2 ] 2 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [412 ] 412 MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [0 ] 0 -MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [94268 ] 94268 +MT_SB L2_Replacement [1177 ] 1177 +MT_SB L2_Replacement_clean [36 ] 36 +MT_SB Unblock [1178 ] 1178 MT_SB MEM_Inv [0 ] 0 Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 2 - memory_reads: 2 - memory_writes: 0 - memory_refreshes: 22 - memory_total_request_delays: 31 - memory_delays_per_request: 15.5 - memory_delays_in_input_queue: 1 - memory_delays_behind_head_of_bank_queue: 10 - memory_delays_stalled_at_head_of_bank_queue: 20 - memory_stalls_for_bank_busy: 20 + memory_total_requests: 1624572 + memory_reads: 1201859 + memory_writes: 422705 + memory_refreshes: 92931 + memory_total_request_delays: 21562515 + memory_delays_per_request: 13.2727 + memory_delays_in_input_queue: 799404 + memory_delays_behind_head_of_bank_queue: 2824712 + memory_delays_stalled_at_head_of_bank_queue: 17938399 + memory_stalls_for_bank_busy: 3122651 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 0 - memory_stalls_for_bus: 0 + memory_stalls_for_anti_starvation: 1448376 + memory_stalls_for_arbitration: 3657027 + memory_stalls_for_bus: 5644479 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 0 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + memory_stalls_for_read_write_turnaround: 2899436 + memory_stalls_for_read_read_turnaround: 1166430 + accesses_per_bank: 51109 50797 50614 50783 50782 51123 51111 50505 50976 50836 51125 50801 50737 50827 50674 50360 50870 50536 51039 50708 50638 50708 50669 50566 50891 50471 50548 50407 50890 50755 51098 50618 --- Directory --- - Event Counts - -Fetch [2 ] 2 -Data [0 ] 0 -Memory_Data [2 ] 2 -Memory_Ack [0 ] 0 +Fetch [1201864 ] 1201864 +Data [422708 ] 422708 +Memory_Data [1201858 ] 1201858 +Memory_Ack [422702 ] 422702 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -CleanReplacement [0 ] 0 +CleanReplacement [779147 ] 779147 - Transitions - -I Fetch [2 ] 2 +I Fetch [1201864 ] 1201864 I DMA_READ [0 ] 0 I DMA_WRITE [0 ] 0 @@ -808,20 +835,20 @@ ID_W Memory_Ack [0 ] 0 ID_W DMA_READ [0 ] 0 ID_W DMA_WRITE [0 ] 0 -M Data [0 ] 0 +M Data [422708 ] 422708 M DMA_READ [0 ] 0 M DMA_WRITE [0 ] 0 -M CleanReplacement [0 ] 0 +M CleanReplacement [779147 ] 779147 IM Fetch [0 ] 0 IM Data [0 ] 0 -IM Memory_Data [2 ] 2 +IM Memory_Data [1201858 ] 1201858 IM DMA_READ [0 ] 0 IM DMA_WRITE [0 ] 0 MI Fetch [0 ] 0 MI Data [0 ] 0 -MI Memory_Ack [0 ] 0 +MI Memory_Ack [422702 ] 422702 MI DMA_READ [0 ] 0 MI DMA_WRITE [0 ] 0 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr index e36729355..c575e5183 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr @@ -1,74 +1,74 @@ -system.cpu0: completed 10000 read accesses @371396 -system.cpu2: completed 10000 read accesses @374647 -system.cpu7: completed 10000 read accesses @377314 -system.cpu1: completed 10000 read accesses @379478 -system.cpu3: completed 10000 read accesses @380787 -system.cpu5: completed 10000 read accesses @386046 -system.cpu4: completed 10000 read accesses @386470 -system.cpu6: completed 10000 read accesses @394077 -system.cpu0: completed 20000 read accesses @748308 -system.cpu2: completed 20000 read accesses @750148 -system.cpu1: completed 20000 read accesses @752701 -system.cpu3: completed 20000 read accesses @761044 -system.cpu5: completed 20000 read accesses @762156 -system.cpu4: completed 20000 read accesses @766351 -system.cpu6: completed 20000 read accesses @775961 -system.cpu7: completed 20000 read accesses @776472 -system.cpu2: completed 30000 read accesses @1125160 -system.cpu1: completed 30000 read accesses @1125369 -system.cpu0: completed 30000 read accesses @1130636 -system.cpu3: completed 30000 read accesses @1139985 -system.cpu5: completed 30000 read accesses @1141453 -system.cpu4: completed 30000 read accesses @1142264 -system.cpu6: completed 30000 read accesses @1154957 -system.cpu7: completed 30000 read accesses @1163543 -system.cpu2: completed 40000 read accesses @1501376 -system.cpu1: completed 40000 read accesses @1506717 -system.cpu0: completed 40000 read accesses @1507617 -system.cpu3: completed 40000 read accesses @1521033 -system.cpu4: completed 40000 read accesses @1523666 -system.cpu5: completed 40000 read accesses @1527373 -system.cpu6: completed 40000 read accesses @1547890 -system.cpu7: completed 40000 read accesses @1551332 -system.cpu2: completed 50000 read accesses @1879261 -system.cpu0: completed 50000 read accesses @1879360 -system.cpu1: completed 50000 read accesses @1885794 -system.cpu3: completed 50000 read accesses @1900931 -system.cpu4: completed 50000 read accesses @1902181 -system.cpu5: completed 50000 read accesses @1910820 -system.cpu6: completed 50000 read accesses @1931247 -system.cpu7: completed 50000 read accesses @1940656 -system.cpu0: completed 60000 read accesses @2246405 -system.cpu1: completed 60000 read accesses @2255112 -system.cpu2: completed 60000 read accesses @2258276 -system.cpu3: completed 60000 read accesses @2284120 -system.cpu4: completed 60000 read accesses @2284604 -system.cpu5: completed 60000 read accesses @2293116 -system.cpu6: completed 60000 read accesses @2311203 -system.cpu7: completed 60000 read accesses @2336896 -system.cpu0: completed 70000 read accesses @2626542 -system.cpu1: completed 70000 read accesses @2633209 -system.cpu2: completed 70000 read accesses @2638509 -system.cpu4: completed 70000 read accesses @2659805 -system.cpu3: completed 70000 read accesses @2663605 -system.cpu5: completed 70000 read accesses @2671213 -system.cpu6: completed 70000 read accesses @2693680 -system.cpu7: completed 70000 read accesses @2725734 -system.cpu0: completed 80000 read accesses @2999116 -system.cpu1: completed 80000 read accesses @3008858 -system.cpu2: completed 80000 read accesses @3014566 -system.cpu3: completed 80000 read accesses @3028069 -system.cpu4: completed 80000 read accesses @3040014 -system.cpu5: completed 80000 read accesses @3055346 -system.cpu6: completed 80000 read accesses @3080851 -system.cpu7: completed 80000 read accesses @3115153 -system.cpu0: completed 90000 read accesses @3374370 -system.cpu1: completed 90000 read accesses @3384044 -system.cpu2: completed 90000 read accesses @3385035 -system.cpu3: completed 90000 read accesses @3412877 -system.cpu4: completed 90000 read accesses @3422171 -system.cpu5: completed 90000 read accesses @3435207 -system.cpu6: completed 90000 read accesses @3466955 -system.cpu7: completed 90000 read accesses @3499833 -system.cpu0: completed 100000 read accesses @3750455 +system.cpu1: completed 10000 read accesses @4267815 +system.cpu0: completed 10000 read accesses @4386665 +system.cpu7: completed 10000 read accesses @4430875 +system.cpu5: completed 10000 read accesses @4607545 +system.cpu2: completed 10000 read accesses @4619185 +system.cpu6: completed 10000 read accesses @4647575 +system.cpu4: completed 10000 read accesses @4703325 +system.cpu3: completed 10000 read accesses @4708885 +system.cpu7: completed 20000 read accesses @8917485 +system.cpu1: completed 20000 read accesses @8927935 +system.cpu0: completed 20000 read accesses @8978605 +system.cpu2: completed 20000 read accesses @9011105 +system.cpu6: completed 20000 read accesses @9036385 +system.cpu3: completed 20000 read accesses @9124815 +system.cpu4: completed 20000 read accesses @9252305 +system.cpu5: completed 20000 read accesses @9314285 +system.cpu2: completed 30000 read accesses @13433315 +system.cpu6: completed 30000 read accesses @13458245 +system.cpu3: completed 30000 read accesses @13464345 +system.cpu7: completed 30000 read accesses @13518155 +system.cpu1: completed 30000 read accesses @13598825 +system.cpu0: completed 30000 read accesses @13662375 +system.cpu4: completed 30000 read accesses @13823135 +system.cpu5: completed 30000 read accesses @14030995 +system.cpu1: completed 40000 read accesses @17924245 +system.cpu3: completed 40000 read accesses @17944405 +system.cpu2: completed 40000 read accesses @17991615 +system.cpu7: completed 40000 read accesses @18065995 +system.cpu6: completed 40000 read accesses @18146535 +system.cpu4: completed 40000 read accesses @18360575 +system.cpu0: completed 40000 read accesses @18363865 +system.cpu5: completed 40000 read accesses @18573915 +system.cpu6: completed 50000 read accesses @22483915 +system.cpu1: completed 50000 read accesses @22585525 +system.cpu2: completed 50000 read accesses @22658905 +system.cpu3: completed 50000 read accesses @22664345 +system.cpu7: completed 50000 read accesses @22693455 +system.cpu0: completed 50000 read accesses @22708375 +system.cpu4: completed 50000 read accesses @22882115 +system.cpu5: completed 50000 read accesses @23249715 +system.cpu1: completed 60000 read accesses @27015465 +system.cpu3: completed 60000 read accesses @27113125 +system.cpu6: completed 60000 read accesses @27149645 +system.cpu0: completed 60000 read accesses @27234945 +system.cpu4: completed 60000 read accesses @27270805 +system.cpu7: completed 60000 read accesses @27282045 +system.cpu2: completed 60000 read accesses @27287805 +system.cpu5: completed 60000 read accesses @27813435 +system.cpu1: completed 70000 read accesses @31507655 +system.cpu3: completed 70000 read accesses @31524465 +system.cpu4: completed 70000 read accesses @31736945 +system.cpu6: completed 70000 read accesses @31758665 +system.cpu2: completed 70000 read accesses @31768595 +system.cpu7: completed 70000 read accesses @31845335 +system.cpu0: completed 70000 read accesses @31923925 +system.cpu5: completed 70000 read accesses @32335665 +system.cpu1: completed 80000 read accesses @35877115 +system.cpu3: completed 80000 read accesses @35924075 +system.cpu2: completed 80000 read accesses @36219765 +system.cpu4: completed 80000 read accesses @36272265 +system.cpu0: completed 80000 read accesses @36290615 +system.cpu7: completed 80000 read accesses @36433305 +system.cpu6: completed 80000 read accesses @36513795 +system.cpu5: completed 80000 read accesses @37012615 +system.cpu1: completed 90000 read accesses @40229765 +system.cpu3: completed 90000 read accesses @40530675 +system.cpu0: completed 90000 read accesses @40687495 +system.cpu4: completed 90000 read accesses @40754715 +system.cpu2: completed 90000 read accesses @40778275 +system.cpu6: completed 90000 read accesses @41067465 +system.cpu7: completed 90000 read accesses @41097375 +system.cpu5: completed 90000 read accesses @41743025 +system.cpu1: completed 100000 read accesses @44606455 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index edd524f60..959d8910e 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 13 2011 22:36:25 -M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip -M5 started Jan 13 2011 22:36:28 -M5 executing on scamorza.cs.wisc.edu +M5 compiled Feb 8 2011 17:31:51 +M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:31:55 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3750455 because maximum number of loads reached +Exiting @ tick 44606455 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index ce3cfcb57..393bd8a0f 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 290548 # Number of bytes of host memory used -host_seconds 82.41 # Real time elapsed on the host -host_tick_rate 45509 # Simulator tick rate (ticks/s) +host_mem_usage 346312 # Number of bytes of host memory used +host_seconds 508.61 # Real time elapsed on the host +host_tick_rate 87702 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003750 # Number of seconds simulated -sim_ticks 3750455 # Number of ticks simulated +sim_seconds 0.044606 # Number of seconds simulated +sim_ticks 44606455 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 54108 # number of write accesses completed +system.cpu0.num_reads 98785 # number of read accesses completed +system.cpu0.num_writes 53305 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99918 # number of read accesses completed -system.cpu1.num_writes 53757 # number of write accesses completed +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 53625 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99521 # number of read accesses completed -system.cpu2.num_writes 53948 # number of write accesses completed +system.cpu2.num_reads 98373 # number of read accesses completed +system.cpu2.num_writes 52754 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98786 # number of read accesses completed -system.cpu3.num_writes 53362 # number of write accesses completed +system.cpu3.num_reads 99177 # number of read accesses completed +system.cpu3.num_writes 53577 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98631 # number of read accesses completed -system.cpu4.num_writes 52746 # number of write accesses completed +system.cpu4.num_reads 98444 # number of read accesses completed +system.cpu4.num_writes 53449 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 98242 # number of read accesses completed -system.cpu5.num_writes 52924 # number of write accesses completed +system.cpu5.num_reads 96240 # number of read accesses completed +system.cpu5.num_writes 51749 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 97407 # number of read accesses completed -system.cpu6.num_writes 52658 # number of write accesses completed +system.cpu6.num_reads 97546 # number of read accesses completed +system.cpu6.num_writes 52113 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 96638 # number of read accesses completed -system.cpu7.num_writes 51757 # number of write accesses completed +system.cpu7.num_reads 97707 # number of read accesses completed +system.cpu7.num_writes 52706 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index 2086e11ae..d4f28799b 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=MemTest @@ -460,10 +469,9 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem [system.ruby] type=RubySystem -children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -475,8 +483,9 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports0] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl0.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl0.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -487,8 +496,9 @@ port=system.cpu0.test [system.ruby.cpu_ruby_ports1] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl1.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl1.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -499,8 +509,9 @@ port=system.cpu1.test [system.ruby.cpu_ruby_ports2] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl2.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl2.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -511,8 +522,9 @@ port=system.cpu2.test [system.ruby.cpu_ruby_ports3] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl3.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl3.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -523,8 +535,9 @@ port=system.cpu3.test [system.ruby.cpu_ruby_ports4] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl4.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl4.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -535,8 +548,9 @@ port=system.cpu4.test [system.ruby.cpu_ruby_ports5] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl5.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl5.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -547,8 +561,9 @@ port=system.cpu5.test [system.ruby.cpu_ruby_ports6] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl6.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl6.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -559,8 +574,9 @@ port=system.cpu6.test [system.ruby.cpu_ruby_ports7] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl7.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl7.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -569,14 +585,6 @@ version=7 physMemPort=system.physmem.port[7] port=system.cpu7.test -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - [system.ruby.network] type=SimpleNetwork children=topology diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats index f165c60b3..76098d4be 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/20/2010 12:11:08 +Real time: Feb/08/2011 17:50:03 Profiler Stats -------------- -Elapsed_time_in_seconds: 30 -Elapsed_time_in_minutes: 0.5 -Elapsed_time_in_hours: 0.00833333 -Elapsed_time_in_days: 0.000347222 +Elapsed_time_in_seconds: 500 +Elapsed_time_in_minutes: 8.33333 +Elapsed_time_in_hours: 0.138889 +Elapsed_time_in_days: 0.00578704 -Virtual_time_in_seconds: 29.75 -Virtual_time_in_minutes: 0.495833 -Virtual_time_in_hours: 0.00826389 -Virtual_time_in_days: 0.000344329 +Virtual_time_in_seconds: 500.11 +Virtual_time_in_minutes: 8.33517 +Virtual_time_in_hours: 0.138919 +Virtual_time_in_days: 0.00578831 -Ruby_current_time: 3377485 +Ruby_current_time: 38939096 Ruby_start_time: 0 -Ruby_cycles: 3377485 +Ruby_cycles: 38939096 -mbytes_resident: 32.793 -mbytes_total: 333.84 -resident_ratio: 0.0982413 +mbytes_resident: 36.1992 +mbytes_total: 338.434 +resident_ratio: 0.106984 -ruby_cycles_executed: [ 3377486 3377486 3377486 3377486 3377486 3377486 3377486 3377486 ] +ruby_cycles_executed: [ 38939097 38939097 38939097 38939097 38939097 38939097 38939097 38939097 ] Busy Controller Counts: L2Cache-0:0 @@ -67,14 +67,14 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1222069 average: 1.94291 | standard deviation: 0.23202 | 0 69771 1152298 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1227844 average: 15.9992 | standard deviation: 0.0898844 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1227724 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 32 max: 4208 count: 1222054 average: 42.2144 | standard deviation: 177.639 | 1118155 105 18532 286 3706 237 19816 120 4820 316 9753 144 6122 225 4331 189 5362 145 2953 440 3702 168 1691 1186 2271 308 1234 1136 1280 666 862 897 527 990 627 643 435 761 434 563 339 533 242 520 273 405 165 382 209 333 127 267 107 240 108 187 88 134 91 133 60 101 60 112 52 67 38 53 46 61 23 39 27 37 19 21 22 15 10 23 14 13 16 8 12 11 5 2 5 5 5 4 5 4 2 0 2 0 6 3 2 3 4 2 1 0 1 1 1 0 1 1 1 0 0 0 1 2 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 32 max: 4117 count: 794230 average: 41.6343 | standard deviation: 176.091 | 727408 2 12034 217 2312 126 12876 50 3128 152 6319 79 3980 161 2804 92 3427 65 2070 99 2386 94 1090 805 1432 189 791 748 1019 231 541 562 349 637 396 401 264 513 339 295 198 328 158 351 152 263 112 246 162 179 77 176 65 154 55 125 52 78 63 79 34 65 43 84 31 39 28 38 31 39 16 18 15 28 15 13 15 9 7 16 7 8 7 7 5 9 2 0 4 4 4 2 3 3 2 0 2 0 5 2 2 1 3 2 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 32 max: 4208 count: 427824 average: 43.2911 | standard deviation: 180.475 | 390747 103 6498 69 1394 111 6940 70 1692 164 3434 65 2142 64 1527 97 1935 80 883 341 1316 74 601 381 839 119 443 388 261 435 321 335 178 353 231 242 171 248 95 268 141 205 84 169 121 142 53 136 47 154 50 91 42 86 53 62 36 56 28 54 26 36 17 28 21 28 10 15 15 22 7 21 12 9 4 8 7 6 3 7 7 5 9 1 7 2 3 2 1 1 1 2 2 1 0 0 0 0 1 1 0 2 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 2 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_NULL: [binsize: 32 max: 4208 count: 1222054 average: 42.2144 | standard deviation: 177.639 | 1118155 105 18532 286 3706 237 19816 120 4820 316 9753 144 6122 225 4331 189 5362 145 2953 440 3702 168 1691 1186 2271 308 1234 1136 1280 666 862 897 527 990 627 643 435 761 434 563 339 533 242 520 273 405 165 382 209 333 127 267 107 240 108 187 88 134 91 133 60 101 60 112 52 67 38 53 46 61 23 39 27 37 19 21 22 15 10 23 14 13 16 8 12 11 5 2 5 5 5 4 5 4 2 0 2 0 6 3 2 3 4 2 1 0 1 1 1 0 1 1 1 0 0 0 1 2 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 4096 max: 586358 count: 1227716 average: 4059.12 | standard deviation: 6630.54 | 915382 91625 85198 72179 41849 15993 4230 871 157 19 15 10 11 13 13 11 7 8 6 6 5 6 1 6 7 6 3 2 6 6 2 6 3 2 4 4 1 3 3 0 1 0 3 4 0 2 2 2 0 0 3 2 1 0 1 1 2 0 0 1 0 0 0 1 0 0 1 2 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 4096 max: 458107 count: 798039 average: 4060.36 | standard deviation: 7800.42 | 595041 59542 55380 46865 27273 10341 2768 557 110 12 14 9 7 8 7 7 4 8 4 4 2 5 1 1 7 6 2 1 4 5 1 4 2 1 2 3 1 2 2 0 0 0 2 3 0 2 1 1 0 0 2 1 0 0 1 1 2 0 0 1 0 0 0 1 0 0 0 2 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 4096 max: 586358 count: 429677 average: 4056.81 | standard deviation: 5606.8 | 320341 32083 29818 25314 14576 5652 1462 314 47 7 1 1 4 5 6 4 3 0 2 2 3 1 0 5 0 0 1 1 2 1 1 2 1 1 2 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 4096 max: 586358 count: 1227716 average: 4059.12 | standard deviation: 6630.54 | 915382 91625 85198 72179 41849 15993 4230 871 157 19 15 10 11 13 13 11 7 8 6 6 5 6 1 6 7 6 3 2 6 6 2 6 3 2 4 4 1 3 3 0 1 0 3 4 0 2 2 2 0 0 3 2 1 0 1 1 2 0 0 1 0 0 0 1 0 0 1 2 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,8 +85,8 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 32 max: 4117 count: 794230 average: 41.6343 | standard deviation: 176.091 | 727408 2 12034 217 2312 126 12876 50 3128 152 6319 79 3980 161 2804 92 3427 65 2070 99 2386 94 1090 805 1432 189 791 748 1019 231 541 562 349 637 396 401 264 513 339 295 198 328 158 351 152 263 112 246 162 179 77 176 65 154 55 125 52 78 63 79 34 65 43 84 31 39 28 38 31 39 16 18 15 28 15 13 15 9 7 16 7 8 7 7 5 9 2 0 4 4 4 2 3 3 2 0 2 0 5 2 2 1 3 2 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 32 max: 4208 count: 427824 average: 43.2911 | standard deviation: 180.475 | 390747 103 6498 69 1394 111 6940 70 1692 164 3434 65 2142 64 1527 97 1935 80 883 341 1316 74 601 381 839 119 443 388 261 435 321 335 178 353 231 242 171 248 95 268 141 205 84 169 121 142 53 136 47 154 50 91 42 86 53 62 36 56 28 54 26 36 17 28 21 28 10 15 15 22 7 21 12 9 4 8 7 6 3 7 7 5 9 1 7 2 3 2 1 1 1 2 2 1 0 0 0 0 1 1 0 2 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 2 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 4096 max: 458107 count: 798039 average: 4060.36 | standard deviation: 7800.42 | 595041 59542 55380 46865 27273 10341 2768 557 110 12 14 9 7 8 7 7 4 8 4 4 2 5 1 1 7 6 2 1 4 5 1 4 2 1 2 3 1 2 2 0 0 0 2 3 0 2 1 1 0 0 2 1 0 0 1 1 2 0 0 1 0 0 0 1 0 0 0 2 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 4096 max: 586358 count: 429677 average: 4056.81 | standard deviation: 5606.8 | 320341 32083 29818 25314 14576 5652 1462 314 47 7 1 1 4 5 6 4 3 0 2 2 3 1 0 5 0 0 1 1 2 1 1 2 1 1 2 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,227 +116,302 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 29 +user_time: 499 system_time: 0 -page_reclaims: 9510 +page_reclaims: 10514 page_faults: 0 swaps: 0 -block_inputs: 16 +block_inputs: 0 block_outputs: 0 Network Stats ------------- -total_msg_count_Request_Control: 311844 2494752 -total_msg_count_Response_Data: 12 864 -total_msg_count_ResponseLocal_Data: 311478 22426416 -total_msg_count_Response_Control: 113679 909432 -total_msg_count_Forwarded_Control: 311796 2494368 -total_msg_count_Invalidate_Control: 1988 15904 -total_msg_count_Unblock_Control: 311802 2494416 -total_msgs: 1362599 total_bytes: 30836152 +total_msg_count_Request_Control: 7302717 58421736 +total_msg_count_Response_Data: 7240224 521296128 +total_msg_count_ResponseL2hit_Data: 12633 909576 +total_msg_count_ResponseLocal_Data: 49758 3582576 +total_msg_count_Response_Control: 17919 143352 +total_msg_count_Writeback_Data: 4922002 354384144 +total_msg_count_Writeback_Control: 16868172 134945376 +total_msg_count_Forwarded_Control: 49758 398064 +total_msg_count_Invalidate_Control: 153 1224 +total_msg_count_Unblock_Control: 7327287 58618296 +total_msgs: 43790623 total_bytes: 1132700472 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.130402 - links_utilized_percent_switch_0_link_0: 0.0495676 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.211237 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseLocal_Data: 12906 929232 [ 0 0 12906 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 4705 37640 [ 0 0 4705 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Invalidate_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 12920 103360 [ 12920 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseLocal_Data: 12975 934200 [ 0 0 12975 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 77 616 [ 0 0 77 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 12918 103344 [ 0 0 12918 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.142732 + links_utilized_percent_switch_0_link_0: 0.0492106 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.236253 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 150484 10834848 [ 0 0 150484 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 517 37224 [ 0 0 517 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseLocal_Data: 2084 150048 [ 0 0 2084 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 733 5864 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 152428 1219424 [ 152428 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Forwarded_Control: 2038 16304 [ 2038 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Invalidate_Control: 8 64 [ 8 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 153088 1224704 [ 153088 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseLocal_Data: 2038 146736 [ 0 0 2038 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 8 64 [ 0 0 8 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 151322 10895184 [ 0 0 151322 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 152428 1219424 [ 152428 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 154131 1233048 [ 0 0 154131 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.130527 - links_utilized_percent_switch_1_link_0: 0.0497582 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.211296 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 12961 933192 [ 0 0 12961 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 4701 37608 [ 0 0 4701 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Forwarded_Control: 12983 103864 [ 12983 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 12985 103880 [ 12985 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 12962 933264 [ 0 0 12962 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 104 832 [ 0 0 104 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 12983 103864 [ 0 0 12983 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.143413 + links_utilized_percent_switch_1_link_0: 0.0494321 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.237394 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 151179 10884888 [ 0 0 151179 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 522 37584 [ 0 0 522 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseLocal_Data: 2067 148824 [ 0 0 2067 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 724 5792 [ 0 0 724 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 153110 1224880 [ 153110 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Forwarded_Control: 2120 16960 [ 2120 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 153771 1230168 [ 153771 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseLocal_Data: 2120 152640 [ 0 0 2120 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 6 48 [ 0 0 6 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 151999 10943928 [ 0 0 151999 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 153110 1224880 [ 153110 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 154820 1238560 [ 0 0 154820 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.130904 - links_utilized_percent_switch_2_link_0: 0.0499306 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.211878 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 13014 937008 [ 0 0 13014 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 4676 37408 [ 0 0 4676 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Forwarded_Control: 13007 104056 [ 13007 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 13024 104192 [ 13024 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 12997 935784 [ 0 0 12997 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 103 824 [ 0 0 103 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 13023 104184 [ 0 0 13023 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.143021 + links_utilized_percent_switch_2_link_0: 0.0493064 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.236736 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 150709 10851048 [ 0 0 150709 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 552 39744 [ 0 0 552 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 2118 152496 [ 0 0 2118 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 783 6264 [ 0 0 783 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 152718 1221744 [ 152718 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Forwarded_Control: 2035 16280 [ 2035 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Invalidate_Control: 9 72 [ 9 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 153382 1227056 [ 153382 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 2035 146520 [ 0 0 2035 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 9 72 [ 0 0 9 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 151649 10918728 [ 0 0 151649 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 152718 1221744 [ 152718 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 154390 1235120 [ 0 0 154390 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.131152 - links_utilized_percent_switch_3_link_0: 0.0500739 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.21223 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 13048 939456 [ 0 0 13048 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 4729 37832 [ 0 0 4729 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Forwarded_Control: 13027 104216 [ 13027 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Invalidate_Control: 111 888 [ 111 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 13063 104504 [ 13063 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseLocal_Data: 13014 937008 [ 0 0 13014 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 111 888 [ 0 0 111 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 13061 104488 [ 0 0 13061 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.14278 + links_utilized_percent_switch_3_link_0: 0.0492124 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.236348 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 150596 10842912 [ 0 0 150596 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 483 34776 [ 0 0 483 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 2010 144720 [ 0 0 2010 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 718 5744 [ 0 0 718 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 152418 1219344 [ 152418 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Forwarded_Control: 2087 16696 [ 2087 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 153091 1224728 [ 153091 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseLocal_Data: 2087 150264 [ 0 0 2087 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 6 48 [ 0 0 6 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 151360 10897920 [ 0 0 151360 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 152418 1219344 [ 152418 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 154100 1232800 [ 0 0 154100 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.130608 - links_utilized_percent_switch_4_link_0: 0.0498674 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.21135 bw: 160000 base_latency: 1 - - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 12981 934632 [ 0 0 12981 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 4834 38672 [ 0 0 4834 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Forwarded_Control: 12976 103808 [ 12976 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 12995 103960 [ 12995 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 12964 933408 [ 0 0 12964 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 102 816 [ 0 0 102 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 12993 103944 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 0.142856 + links_utilized_percent_switch_4_link_0: 0.0492357 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.236477 bw: 160000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Response_Data: 150629 10845288 [ 0 0 150629 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 518 37296 [ 0 0 518 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 2015 145080 [ 0 0 2015 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 709 5672 [ 0 0 709 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 152528 1220224 [ 152528 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Forwarded_Control: 2056 16448 [ 2056 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Invalidate_Control: 5 40 [ 5 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 153164 1225312 [ 153164 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 2056 148032 [ 0 0 2056 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 5 40 [ 0 0 5 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 151475 10906200 [ 0 0 151475 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 152528 1220224 [ 152528 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 154166 1233328 [ 0 0 154166 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.129687 - links_utilized_percent_switch_5_link_0: 0.0495006 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.209874 bw: 160000 base_latency: 1 - - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 12892 928224 [ 0 0 12892 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Forwarded_Control: 12887 103096 [ 12887 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 12908 103264 [ 12908 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_ResponseLocal_Data: 12873 926856 [ 0 0 12873 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 98 784 [ 0 0 98 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 12906 103248 [ 0 0 12906 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 0.143084 + links_utilized_percent_switch_5_link_0: 0.0493135 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.236854 bw: 160000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Response_Data: 150874 10862928 [ 0 0 150874 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 528 38016 [ 0 0 528 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseLocal_Data: 2002 144144 [ 0 0 2002 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 715 5720 [ 0 0 715 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 152731 1221848 [ 152731 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Forwarded_Control: 2090 16720 [ 2090 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Invalidate_Control: 8 64 [ 8 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 153405 1227240 [ 153405 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseLocal_Data: 2090 150480 [ 0 0 2090 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 8 64 [ 0 0 8 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 151692 10921824 [ 0 0 151692 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 152731 1221848 [ 152731 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 154393 1235144 [ 0 0 154393 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.130865 - links_utilized_percent_switch_6_link_0: 0.0499036 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.211826 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_ResponseLocal_Data: 12996 935712 [ 0 0 12996 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 4774 38192 [ 0 0 4774 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Forwarded_Control: 13010 104080 [ 13010 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 13008 104064 [ 13008 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 12998 935856 [ 0 0 12998 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 91 728 [ 0 0 91 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 13007 104056 [ 0 0 13007 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.143721 + links_utilized_percent_switch_6_link_0: 0.0495395 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.237903 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Response_Data: 151359 10897848 [ 0 0 151359 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 565 40680 [ 0 0 565 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseLocal_Data: 2164 155808 [ 0 0 2164 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 807 6456 [ 0 0 807 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 153471 1227768 [ 153471 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Forwarded_Control: 2143 17144 [ 2143 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Invalidate_Control: 7 56 [ 7 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 154090 1232720 [ 154090 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 2143 154296 [ 0 0 2143 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 7 56 [ 0 0 7 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 152300 10965600 [ 0 0 152300 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Control: 153471 1227768 [ 153471 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 155187 1241496 [ 0 0 155187 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.131276 - links_utilized_percent_switch_7_link_0: 0.0500158 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.212537 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 13028 938016 [ 0 0 13028 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Forwarded_Control: 13056 104448 [ 13056 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 13043 104344 [ 13043 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 13043 939096 [ 0 0 13043 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 97 776 [ 0 0 97 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 13041 104328 [ 0 0 13041 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.143169 + links_utilized_percent_switch_7_link_0: 0.0493539 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.236983 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Response_Data: 150874 10862928 [ 0 0 150874 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 526 37872 [ 0 0 526 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 2126 153072 [ 0 0 2126 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 784 6272 [ 0 0 784 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 152900 1223200 [ 152900 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Forwarded_Control: 2017 16136 [ 2017 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 153527 1228216 [ 153527 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 2017 145224 [ 0 0 2017 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 151829 10931688 [ 0 0 151829 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Control: 152900 1223200 [ 152900 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 154539 1236312 [ 0 0 154539 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.143198 - links_utilized_percent_switch_8_link_0: 0.0769419 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.209455 bw: 160000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Request_Control: 103946 831568 [ 103946 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 103932 831456 [ 0 0 103932 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 37110 296880 [ 0 0 37110 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Forwarded_Control: 103932 831456 [ 103932 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Invalidate_Control: 422 3376 [ 422 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 1.73629 + links_utilized_percent_switch_8_link_0: 0.856152 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 2.61643 bw: 160000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Request_Control: 1227518 9820144 [ 1227518 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Data: 1206704 86882688 [ 0 0 1206704 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 1213626 87381072 [ 0 0 1213626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Control: 2424023 19392184 [ 1222304 1201719 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 1235726 9885808 [ 0 0 1235726 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 1206721 9653768 [ 0 1206721 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 1206704 86882688 [ 0 0 1206704 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 4211 303192 [ 0 0 4211 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 5922 47376 [ 0 0 5922 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Data: 427042 30747024 [ 0 0 427042 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 3198701 25589608 [ 1222304 1201720 774677 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Forwarded_Control: 16586 132688 [ 16586 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Invalidate_Control: 51 408 [ 51 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Unblock_Control: 1206703 9653624 [ 0 0 1206703 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 1.40637e-05 - links_utilized_percent_switch_9_link_0: 1.48039e-06 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.6647e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 0.906567 + links_utilized_percent_switch_9_link_0: 0.264297 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 1.54884 bw: 160000 base_latency: 1 - outgoing_messages_switch_9_link_0_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Request_Control: 1206721 9653768 [ 0 1206721 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Data: 427041 30746952 [ 0 0 427041 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 1976397 15811176 [ 0 1201720 774677 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Unblock_Control: 1206703 9653624 [ 0 0 1206703 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 1206704 86882688 [ 0 0 1206704 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 1201719 9613752 [ 0 1201719 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.190224 - links_utilized_percent_switch_10_link_0: 0.19827 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.199033 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.199723 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.200295 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.199469 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.198002 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.199615 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.200063 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.307767 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 5.92157e-06 bw: 160000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseLocal_Data: 12906 929232 [ 0 0 12906 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 4705 37640 [ 0 0 4705 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Invalidate_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 12961 933192 [ 0 0 12961 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 4701 37608 [ 0 0 4701 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Forwarded_Control: 12983 103864 [ 12983 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 13014 937008 [ 0 0 13014 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 4676 37408 [ 0 0 4676 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Forwarded_Control: 13007 104056 [ 13007 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 13048 939456 [ 0 0 13048 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 4729 37832 [ 0 0 4729 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Forwarded_Control: 13027 104216 [ 13027 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Invalidate_Control: 111 888 [ 111 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 12981 934632 [ 0 0 12981 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 4834 38672 [ 0 0 4834 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Forwarded_Control: 12976 103808 [ 12976 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 12892 928224 [ 0 0 12892 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Forwarded_Control: 12887 103096 [ 12887 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseLocal_Data: 12996 935712 [ 0 0 12996 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 4774 38192 [ 0 0 4774 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Forwarded_Control: 13010 104080 [ 13010 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Invalidate_Control: 91 728 [ 91 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 13028 938016 [ 0 0 13028 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 4737 37896 [ 0 0 4737 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Forwarded_Control: 13056 104448 [ 13056 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Request_Control: 103946 831568 [ 103946 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Unblock_Control: 103932 831456 [ 0 0 103932 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_10: 0.606021 + links_utilized_percent_switch_10_link_0: 0.196842 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.197728 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.197225 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.19685 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.196943 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.197254 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.198158 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.197416 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 3.42461 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 1.05719 bw: 160000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Response_Data: 150484 10834848 [ 0 0 150484 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 517 37224 [ 0 0 517 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseLocal_Data: 2084 150048 [ 0 0 2084 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 733 5864 [ 0 0 733 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Control: 152428 1219424 [ 152428 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Forwarded_Control: 2038 16304 [ 2038 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Invalidate_Control: 8 64 [ 8 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 151179 10884888 [ 0 0 151179 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 522 37584 [ 0 0 522 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseLocal_Data: 2067 148824 [ 0 0 2067 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 724 5792 [ 0 0 724 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Writeback_Control: 153110 1224880 [ 153110 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Forwarded_Control: 2120 16960 [ 2120 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 150709 10851048 [ 0 0 150709 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 552 39744 [ 0 0 552 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 2118 152496 [ 0 0 2118 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 783 6264 [ 0 0 783 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Writeback_Control: 152718 1221744 [ 152718 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Forwarded_Control: 2035 16280 [ 2035 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Invalidate_Control: 9 72 [ 9 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 150596 10842912 [ 0 0 150596 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 483 34776 [ 0 0 483 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 2010 144720 [ 0 0 2010 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 718 5744 [ 0 0 718 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Writeback_Control: 152418 1219344 [ 152418 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Forwarded_Control: 2087 16696 [ 2087 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 150629 10845288 [ 0 0 150629 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 518 37296 [ 0 0 518 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 2015 145080 [ 0 0 2015 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 709 5672 [ 0 0 709 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Writeback_Control: 152528 1220224 [ 152528 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Forwarded_Control: 2056 16448 [ 2056 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Invalidate_Control: 5 40 [ 5 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 150874 10862928 [ 0 0 150874 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 528 38016 [ 0 0 528 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseLocal_Data: 2002 144144 [ 0 0 2002 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 715 5720 [ 0 0 715 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Writeback_Control: 152731 1221848 [ 152731 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Forwarded_Control: 2090 16720 [ 2090 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Invalidate_Control: 8 64 [ 8 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 151359 10897848 [ 0 0 151359 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 565 40680 [ 0 0 565 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseLocal_Data: 2164 155808 [ 0 0 2164 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 807 6456 [ 0 0 807 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Writeback_Control: 153471 1227768 [ 153471 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Forwarded_Control: 2143 17144 [ 2143 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Invalidate_Control: 7 56 [ 7 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 150874 10862928 [ 0 0 150874 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 526 37872 [ 0 0 526 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 2126 153072 [ 0 0 2126 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 784 6272 [ 0 0 784 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Writeback_Control: 152900 1223200 [ 152900 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Forwarded_Control: 2017 16136 [ 2017 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Request_Control: 1227518 9820144 [ 1227518 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Data: 1206704 86882688 [ 0 0 1206704 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Writeback_Data: 1213626 87381072 [ 0 0 1213626 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Writeback_Control: 2424023 19392184 [ 1222304 1201719 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Unblock_Control: 1235726 9885808 [ 0 0 1235726 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Request_Control: 1206721 9653768 [ 0 1206721 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Writeback_Data: 427041 30746952 [ 0 0 427041 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Writeback_Control: 1976397 15811176 [ 0 1201720 774677 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Unblock_Control: 1206703 9653624 [ 0 0 1206703 0 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -356,155 +431,155 @@ Cache Stats: system.l1_cntrl0.L1DcacheMemory --- L1Cache --- - Event Counts - -Load [99188 98347 99157 99646 99118 99153 100001 99634 ] 794244 +Load [99346 99989 100000 99701 99652 99889 99730 99744 ] 798051 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [53590 53268 53749 53528 53019 53486 53183 54001 ] 427824 -L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -Own_GETX [12 14 11 13 11 21 9 13 ] 104 -Fwd_GETX [22780 22543 22706 22494 22314 22746 22504 22308 ] 180395 -Fwd_GETS [40560 40358 40695 41058 40851 40579 40962 41289 ] 326352 +Store [53842 53434 54117 53855 53466 53908 53685 53375 ] 429682 +L1_Replacement [51679234 51650729 51653770 51670696 51699067 51665651 51674373 51657971 ] 413351491 +Own_GETX [0 0 0 0 0 0 0 0 ] 0 +Fwd_GETX [2699 2710 2705 2541 2634 2694 2642 2703 ] 21328 +Fwd_GETS [4842 4709 5137 4829 4716 5047 4647 4835 ] 38762 Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -Inv [102 98 91 97 77 104 103 111 ] 783 -Ack [4834 4737 4774 4737 4705 4701 4676 4729 ] 37893 -Data [117 113 98 108 88 113 112 122 ] 871 -Exclusive_Data [12864 12779 12898 12920 12819 12849 12902 12926 ] 102957 -Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 -Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -All_acks [4733 4635 4671 4642 4608 4591 4583 4647 ] 37110 -Use_Timeout [12876 12793 12908 12933 12830 12870 12910 12939 ] 103059 +Inv [5 8 7 2 8 6 9 6 ] 51 +Ack [709 715 807 784 733 724 783 718 ] 5973 +Data [1692 1677 1758 1730 1717 1744 1731 1702 ] 13751 +Exclusive_Data [151470 151727 152330 151796 151368 152024 151648 151387 ] 1213750 +Writeback_Ack [729 713 785 732 775 770 747 723 ] 5974 +Writeback_Ack_Data [151750 151968 152615 152110 151593 152281 151913 151648 ] 1215878 +Writeback_Nack [49 50 71 58 60 59 58 47 ] 452 +All_acks [53831 53426 54104 53846 53454 53898 53671 53363 ] 429593 +Use_Timeout [151470 151727 152329 151795 151368 152024 151648 151387 ] 1213748 - Transitions - -I Load [8262 8273 8337 8401 8312 8394 8441 8416 ] 66836 +I Load [99333 99979 99984 99680 99633 99873 99711 99727 ] 797920 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [4573 4492 4542 4491 4468 4437 4447 4499 ] 35949 -I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I Store [53831 53425 54106 53847 53455 53898 53671 53363 ] 429596 +I L1_Replacement [678 714 682 680 711 712 713 712 ] 5602 I Inv [0 0 0 0 0 0 0 0 ] 0 -S Load [136 189 149 161 147 187 176 221 ] 1366 +S Load [0 0 0 0 0 0 1 0 ] 1 S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [109 97 80 91 76 95 93 104 ] 745 -S L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -S Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +S Store [0 1 0 0 0 0 0 1 ] 2 +S L1_Replacement [1690 1673 1755 1729 1714 1742 1727 1698 ] 13728 +S Fwd_GETS [4 5 7 7 2 6 3 5 ] 39 S Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -S Inv [8 16 18 17 12 18 19 18 ] 126 +S Inv [2 3 3 1 3 2 4 3 ] 21 -O Load [93 105 85 75 124 102 80 82 ] 746 +O Load [0 0 0 0 0 0 0 0 ] 0 O Ifetch [0 0 0 0 0 0 0 0 ] 0 -O Store [51 46 49 60 64 59 43 44 ] 416 -O L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -O Fwd_GETX [2 4 2 1 1 1 3 1 ] 15 -O Fwd_GETS [3 5 4 2 6 8 4 3 ] 35 +O Store [0 0 0 0 0 0 0 0 ] 0 +O L1_Replacement [584 611 588 525 551 566 556 589 ] 4570 +O Fwd_GETX [2 3 0 1 0 1 0 1 ] 8 +O Fwd_GETS [2 3 3 1 3 4 6 4 ] 26 O Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -M Load [116 128 118 133 159 134 127 113 ] 1028 +M Load [7 2 11 9 11 11 13 10 ] 74 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [57 72 73 65 45 58 84 64 ] 518 -M L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -M Fwd_GETX [28 33 30 32 33 36 34 34 ] 260 -M Fwd_GETS [53 50 51 61 65 60 46 45 ] 431 +M Store [6 4 8 4 5 7 8 6 ] 48 +M L1_Replacement [96750 97343 97329 97135 97016 97229 97061 97091 ] 776954 +M Fwd_GETX [295 337 299 283 341 322 351 335 ] 2563 +M Fwd_GETS [586 614 588 526 551 567 556 590 ] 4578 M Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -M_W Load [14625 14739 14872 15279 15066 15137 15392 14864 ] 119974 +M_W Load [0 1 0 0 0 0 0 0 ] 1 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -M_W Store [8005 8003 8084 8133 8079 8125 8164 8149 ] 64742 -M_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_W Store [0 0 0 0 0 0 0 0 ] 0 +M_W L1_Replacement [1731154 1738479 1732095 1738299 1737770 1736109 1737116 1740218 ] 13891240 M_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 -M_W Fwd_GETX [1364 1363 1417 1394 1416 1389 1476 1364 ] 11183 -M_W Fwd_GETS [2392 2478 2488 2651 2563 2494 2590 2473 ] 20129 +M_W Fwd_GETX [1239 1175 1217 1063 1241 1209 1241 1280 ] 9665 +M_W Fwd_GETS [2253 2137 2289 2249 2093 2363 2012 2169 ] 17565 M_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 M_W Inv [0 0 0 0 0 0 0 0 ] 0 -M_W Use_Timeout [138 155 154 158 143 154 164 143 ] 1209 +M_W Use_Timeout [97639 98301 98225 97949 97914 98126 97977 98024 ] 784155 -MM Load [11570 11359 11558 11408 11540 11529 11698 11455 ] 92117 +MM Load [6 7 5 12 8 5 5 7 ] 55 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [6129 6213 6160 6217 6122 6256 6194 6383 ] 49674 -MM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -MM Fwd_GETX [4600 4549 4589 4547 4500 4586 4546 4502 ] 36419 -MM Fwd_GETS [8195 8161 8238 8293 8232 8188 8284 8358 ] 65949 +MM Store [5 4 3 3 6 3 4 5 ] 33 +MM L1_Replacement [53458 53059 53732 53454 53092 53518 53321 52996 ] 426630 +MM Fwd_GETX [153 142 131 147 140 143 121 122 ] 1099 +MM Fwd_GETS [226 229 249 248 227 244 237 251 ] 1911 MM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -MM_W Load [64386 63554 64038 64189 63770 63670 64087 64483 ] 512177 +MM_W Load [0 0 0 0 0 0 0 0 ] 0 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM_W Store [34666 34345 34761 34471 34165 34456 34158 34758 ] 275780 -MM_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM_W Store [0 0 0 1 0 0 2 0 ] 3 +MM_W L1_Replacement [950252 943134 957418 948048 944969 950631 948207 941544 ] 7584203 MM_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 -MM_W Fwd_GETX [16747 16562 16630 16473 16311 16696 16411 16376 ] 132206 -MM_W Fwd_GETS [29873 29625 29868 29991 29900 29784 29992 30370 ] 239403 +MM_W Fwd_GETX [735 777 743 766 641 737 665 677 ] 5741 +MM_W Fwd_GETS [1258 1240 1450 1275 1337 1312 1336 1325 ] 10533 MM_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 MM_W Inv [0 0 0 0 0 0 0 0 ] 0 -MM_W Use_Timeout [12738 12638 12754 12775 12687 12716 12746 12796 ] 101850 +MM_W Use_Timeout [53831 53426 54104 53846 53454 53898 53671 53363 ] 429593 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM L1_Replacement [17050741 16944001 17146281 17026088 16990015 16910076 17042850 17066004 ] 136176056 IM Inv [0 0 0 0 0 0 0 0 ] 0 -IM Ack [4717 4630 4681 4635 4610 4584 4595 4636 ] 37088 +IM Ack [705 712 801 777 729 720 777 709 ] 5930 IM Data [0 0 0 0 0 0 0 0 ] 0 -IM Exclusive_Data [4706 4606 4653 4618 4586 4561 4565 4623 ] 36918 +IM Exclusive_Data [53831 53425 54104 53846 53454 53898 53671 53362 ] 429591 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 -SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM L1_Replacement [0 66 0 0 0 0 0 0 ] 66 SM Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 SM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -SM Inv [94 82 73 80 65 86 84 93 ] 657 -SM Ack [33 31 14 16 20 21 15 20 ] 170 +SM Inv [0 0 0 0 0 0 0 0 ] 0 +SM Ack [0 0 0 0 0 0 0 0 ] 0 SM Data [0 0 0 0 0 0 0 0 ] 0 -SM Exclusive_Data [15 15 7 11 11 9 9 11 ] 88 +SM Exclusive_Data [0 1 0 0 0 0 0 1 ] 2 OM Load [0 0 0 0 0 0 0 0 ] 0 OM Ifetch [0 0 0 0 0 0 0 0 ] 0 OM Store [0 0 0 0 0 0 0 0 ] 0 -OM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -OM Own_GETX [12 14 11 13 11 21 9 13 ] 104 -OM Fwd_GETX [39 32 38 47 53 38 34 31 ] 312 -OM Fwd_GETS [44 39 46 60 85 45 46 40 ] 405 +OM L1_Replacement [210 239 245 295 296 192 259 272 ] 2008 +OM Own_GETX [0 0 0 0 0 0 0 0 ] 0 +OM Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +OM Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 OM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -OM Ack [84 76 79 86 75 96 66 73 ] 635 -OM All_acks [4733 4635 4671 4642 4608 4591 4583 4647 ] 37110 +OM Ack [4 3 6 7 4 4 6 9 ] 43 +OM All_acks [53831 53426 54104 53846 53454 53898 53671 53363 ] 429593 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 -IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS L1_Replacement [31793717 31871410 31663645 31804443 31872933 31914876 31792563 31756847 ] 254470434 IS Inv [0 0 0 0 0 0 0 0 ] 0 -IS Data [117 113 98 108 88 113 112 122 ] 871 -IS Exclusive_Data [8143 8158 8238 8291 8222 8279 8328 8292 ] 65951 +IS Data [1692 1677 1758 1730 1717 1744 1731 1702 ] 13751 +IS Exclusive_Data [97639 98301 98226 97950 97914 98126 97977 98024 ] 784157 SI Load [0 0 0 0 0 0 0 0 ] 0 SI Ifetch [0 0 0 0 0 0 0 0 ] 0 SI Store [0 0 0 0 0 0 0 0 ] 0 SI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SI Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +SI Fwd_GETS [5 3 2 1 2 3 1 4 ] 21 SI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -SI Inv [0 0 0 0 0 0 0 0 ] 0 -SI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -SI Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +SI Inv [3 5 4 1 5 4 5 3 ] 30 +SI Writeback_Ack [729 713 785 732 775 770 747 723 ] 5974 +SI Writeback_Ack_Data [958 955 966 996 934 968 975 972 ] 7724 SI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 OI Load [0 0 0 0 0 0 0 0 ] 0 OI Ifetch [0 0 0 0 0 0 0 0 ] 0 OI Store [0 0 0 0 0 0 0 0 ] 0 OI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -OI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -OI Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +OI Fwd_GETX [0 0 2 2 0 0 0 1 ] 5 +OI Fwd_GETS [3 0 2 0 5 4 0 2 ] 16 OI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 OI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Ack_Data [1089 1089 1133 1045 1047 1110 1052 1073 ] 8638 +OI Writeback_Nack [46 45 67 57 55 55 53 44 ] 422 MI Load [0 0 0 0 0 0 0 0 ] 0 MI Ifetch [0 0 0 0 0 0 0 0 ] 0 MI Store [0 0 0 0 0 0 0 0 ] 0 MI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -MI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -MI Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +MI Fwd_GETX [275 276 313 279 271 282 264 287 ] 2247 +MI Fwd_GETS [505 478 547 522 496 544 496 485 ] 4073 MI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack_Data [149428 149648 150201 149788 149341 149921 149622 149315 ] 1197264 MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 II Load [0 0 0 0 0 0 0 0 ] 0 @@ -513,8 +588,8 @@ II Store [0 0 0 0 0 0 0 0 ] 0 II L1_Replacement [0 0 0 0 0 0 0 0 ] 0 II Inv [0 0 0 0 0 0 0 0 ] 0 II Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Ack_Data [275 276 315 281 271 282 264 288 ] 2252 +II Writeback_Nack [3 5 4 1 5 4 5 3 ] 30 Cache Stats: system.l1_cntrl1.L1IcacheMemory system.l1_cntrl1.L1IcacheMemory_total_misses: 0 @@ -638,12 +713,12 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory --- L2Cache --- - Event Counts - -L1_GETS [2715881 ] 2715881 -L1_GETX [1524697 ] 1524697 -L1_PUTO [0 ] 0 -L1_PUTX [0 ] 0 -L1_PUTS_only [0 ] 0 -L1_PUTS [0 ] 0 +L1_GETS [1156724 ] 1156724 +L1_GETX [632843 ] 632843 +L1_PUTO [6387 ] 6387 +L1_PUTX [1217214 ] 1217214 +L1_PUTS_only [19414 ] 19414 +L1_PUTS [180 ] 180 Fwd_GETX [0 ] 0 Fwd_GETS [0 ] 0 Fwd_DMA [0 ] 0 @@ -651,20 +726,20 @@ Own_GETX [0 ] 0 Inv [0 ] 0 IntAck [0 ] 0 ExtAck [0 ] 0 -All_Acks [0 ] 0 -Data [0 ] 0 -Data_Exclusive [2 ] 2 -L1_WBCLEANDATA [0 ] 0 -L1_WBDIRTYDATA [0 ] 0 -Writeback_Ack [0 ] 0 +All_Acks [422217 ] 422217 +Data [427178 ] 427178 +Data_Exclusive [779526 ] 779526 +L1_WBCLEANDATA [785130 ] 785130 +L1_WBDIRTYDATA [428496 ] 428496 +Writeback_Ack [1201719 ] 1201719 Writeback_Nack [0 ] 0 -Unblock [871 ] 871 -Exclusive_Unblock [103061 ] 103061 -L2_Replacement [0 ] 0 +Unblock [21977 ] 21977 +Exclusive_Unblock [1213749 ] 1213749 +L2_Replacement [1209622 ] 1209622 - Transitions - -NP L1_GETS [2 ] 2 -NP L1_GETX [0 ] 0 +NP L1_GETS [784499 ] 784499 +NP L1_GETX [422171 ] 422171 NP L1_PUTO [0 ] 0 NP L1_PUTX [0 ] 0 NP L1_PUTS [0 ] 0 @@ -678,21 +753,21 @@ I L1_PUTS [0 ] 0 I Inv [0 ] 0 I L2_Replacement [0 ] 0 -ILS L1_GETS [0 ] 0 -ILS L1_GETX [0 ] 0 +ILS L1_GETS [60 ] 60 +ILS L1_GETX [37 ] 37 ILS L1_PUTO [0 ] 0 ILS L1_PUTX [0 ] 0 -ILS L1_PUTS_only [0 ] 0 -ILS L1_PUTS [0 ] 0 +ILS L1_PUTS_only [7655 ] 7655 +ILS L1_PUTS [69 ] 69 ILS Inv [0 ] 0 ILS L2_Replacement [0 ] 0 -ILX L1_GETS [66382 ] 66382 -ILX L1_GETX [36679 ] 36679 +ILX L1_GETS [10562 ] 10562 +ILX L1_GETX [5909 ] 5909 ILX L1_PUTO [0 ] 0 -ILX L1_PUTX [0 ] 0 +ILX L1_PUTX [1199516 ] 1199516 ILX L1_PUTS_only [0 ] 0 -ILX L1_PUTS [0 ] 0 +ILX L1_PUTS [30 ] 30 ILX Fwd_GETX [0 ] 0 ILX Fwd_GETS [0 ] 0 ILX Fwd_DMA [0 ] 0 @@ -712,10 +787,10 @@ ILO Inv [0 ] 0 ILO Data [0 ] 0 ILO L2_Replacement [0 ] 0 -ILOX L1_GETS [0 ] 0 -ILOX L1_GETX [0 ] 0 -ILOX L1_PUTO [0 ] 0 -ILOX L1_PUTX [0 ] 0 +ILOX L1_GETS [15 ] 15 +ILOX L1_GETX [4 ] 4 +ILOX L1_PUTO [2554 ] 2554 +ILOX L1_PUTX [422 ] 422 ILOX L1_PUTS [0 ] 0 ILOX Fwd_GETX [0 ] 0 ILOX Fwd_GETS [0 ] 0 @@ -734,23 +809,23 @@ ILOS Fwd_DMA [0 ] 0 ILOS Data [0 ] 0 ILOS L2_Replacement [0 ] 0 -ILOSX L1_GETS [440 ] 440 -ILOSX L1_GETX [431 ] 431 -ILOSX L1_PUTO [0 ] 0 -ILOSX L1_PUTX [0 ] 0 -ILOSX L1_PUTS_only [0 ] 0 -ILOSX L1_PUTS [0 ] 0 +ILOSX L1_GETS [27 ] 27 +ILOSX L1_GETX [9 ] 9 +ILOSX L1_PUTO [2438 ] 2438 +ILOSX L1_PUTX [3646 ] 3646 +ILOSX L1_PUTS_only [2573 ] 2573 +ILOSX L1_PUTS [11 ] 11 ILOSX Fwd_GETX [0 ] 0 ILOSX Fwd_GETS [0 ] 0 ILOSX Fwd_DMA [0 ] 0 ILOSX Data [0 ] 0 -S L1_GETS [0 ] 0 -S L1_GETX [0 ] 0 +S L1_GETS [24 ] 24 +S L1_GETX [14 ] 14 S L1_PUTX [0 ] 0 S L1_PUTS [0 ] 0 S Inv [0 ] 0 -S L2_Replacement [0 ] 0 +S L2_Replacement [7658 ] 7658 O L1_GETS [0 ] 0 O L1_GETX [0 ] 0 @@ -770,34 +845,34 @@ OLS Fwd_GETS [0 ] 0 OLS Fwd_DMA [0 ] 0 OLS L2_Replacement [0 ] 0 -OLSX L1_GETS [0 ] 0 -OLSX L1_GETX [0 ] 0 +OLSX L1_GETS [13 ] 13 +OLSX L1_GETX [7 ] 7 OLSX L1_PUTO [0 ] 0 OLSX L1_PUTX [0 ] 0 -OLSX L1_PUTS_only [0 ] 0 -OLSX L1_PUTS [0 ] 0 +OLSX L1_PUTS_only [3329 ] 3329 +OLSX L1_PUTS [20 ] 20 OLSX Fwd_GETX [0 ] 0 OLSX Fwd_GETS [0 ] 0 OLSX Fwd_DMA [0 ] 0 -OLSX L2_Replacement [0 ] 0 +OLSX L2_Replacement [2748 ] 2748 SLS L1_GETS [0 ] 0 SLS L1_GETX [0 ] 0 SLS L1_PUTX [0 ] 0 -SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS_only [41 ] 41 SLS L1_PUTS [0 ] 0 SLS Inv [0 ] 0 -SLS L2_Replacement [0 ] 0 +SLS L2_Replacement [52 ] 52 -M L1_GETS [0 ] 0 -M L1_GETX [0 ] 0 +M L1_GETS [2720 ] 2720 +M L1_GETX [1447 ] 1447 M L1_PUTO [0 ] 0 M L1_PUTX [0 ] 0 M L1_PUTS [0 ] 0 M Fwd_GETX [0 ] 0 M Fwd_GETS [0 ] 0 M Fwd_DMA [0 ] 0 -M L2_Replacement [0 ] 0 +M L2_Replacement [1198972 ] 1198972 IFGX L1_GETS [0 ] 0 IFGX L1_GETX [0 ] 0 @@ -896,19 +971,19 @@ ILOW L1_WBDIRTYDATA [0 ] 0 ILOW Unblock [0 ] 0 ILOW L2_Replacement [0 ] 0 -ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETS [2 ] 2 ILOXW L1_GETX [0 ] 0 -ILOXW L1_PUTO [0 ] 0 -ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTO [185 ] 185 +ILOXW L1_PUTX [839 ] 839 ILOXW L1_PUTS_only [0 ] 0 ILOXW L1_PUTS [0 ] 0 ILOXW Fwd_GETX [0 ] 0 ILOXW Fwd_GETS [0 ] 0 ILOXW Fwd_DMA [0 ] 0 ILOXW Inv [0 ] 0 -ILOXW L1_WBCLEANDATA [0 ] 0 -ILOXW L1_WBDIRTYDATA [0 ] 0 -ILOXW Unblock [0 ] 0 +ILOXW L1_WBCLEANDATA [2332 ] 2332 +ILOXW L1_WBDIRTYDATA [222 ] 222 +ILOXW Unblock [2573 ] 2573 ILOXW L2_Replacement [0 ] 0 ILOSW L1_GETS [0 ] 0 @@ -926,19 +1001,19 @@ ILOSW L1_WBDIRTYDATA [0 ] 0 ILOSW Unblock [0 ] 0 ILOSW L2_Replacement [0 ] 0 -ILOSXW L1_GETS [0 ] 0 -ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_GETS [16 ] 16 +ILOSXW L1_GETX [8 ] 8 ILOSXW L1_PUTO [0 ] 0 -ILOSXW L1_PUTX [0 ] 0 -ILOSXW L1_PUTS_only [0 ] 0 -ILOSXW L1_PUTS [0 ] 0 +ILOSXW L1_PUTX [6 ] 6 +ILOSXW L1_PUTS_only [3219 ] 3219 +ILOSXW L1_PUTS [18 ] 18 ILOSXW Fwd_GETX [0 ] 0 ILOSXW Fwd_GETS [0 ] 0 ILOSXW Fwd_DMA [0 ] 0 ILOSXW Inv [0 ] 0 -ILOSXW L1_WBCLEANDATA [0 ] 0 -ILOSXW L1_WBDIRTYDATA [0 ] 0 -ILOSXW Unblock [0 ] 0 +ILOSXW L1_WBCLEANDATA [4446 ] 4446 +ILOSXW L1_WBDIRTYDATA [1638 ] 1638 +ILOSXW Unblock [11 ] 11 ILOSXW L2_Replacement [0 ] 0 SLSW L1_GETS [0 ] 0 @@ -972,16 +1047,16 @@ ILSW L1_GETX [0 ] 0 ILSW L1_PUTO [0 ] 0 ILSW L1_PUTX [0 ] 0 ILSW L1_PUTS_only [0 ] 0 -ILSW L1_PUTS [0 ] 0 +ILSW L1_PUTS [17 ] 17 ILSW Fwd_GETX [0 ] 0 ILSW Fwd_GETS [0 ] 0 ILSW Fwd_DMA [0 ] 0 ILSW Inv [0 ] 0 -ILSW L1_WBCLEANDATA [0 ] 0 +ILSW L1_WBCLEANDATA [69 ] 69 ILSW Unblock [0 ] 0 ILSW L2_Replacement [0 ] 0 -IW L1_GETS [0 ] 0 +IW L1_GETS [9 ] 9 IW L1_GETX [0 ] 0 IW L1_PUTO [0 ] 0 IW L1_PUTX [0 ] 0 @@ -991,7 +1066,7 @@ IW Fwd_GETX [0 ] 0 IW Fwd_GETS [0 ] 0 IW Fwd_DMA [0 ] 0 IW Inv [0 ] 0 -IW L1_WBCLEANDATA [0 ] 0 +IW L1_WBCLEANDATA [7655 ] 7655 IW L2_Replacement [0 ] 0 OW L1_GETS [0 ] 0 @@ -1017,11 +1092,11 @@ SW Fwd_GETX [0 ] 0 SW Fwd_GETS [0 ] 0 SW Fwd_DMA [0 ] 0 SW Inv [0 ] 0 -SW Unblock [0 ] 0 -SW L2_Replacement [0 ] 0 +SW Unblock [41 ] 41 +SW L2_Replacement [4 ] 4 -OXW L1_GETS [0 ] 0 -OXW L1_GETX [0 ] 0 +OXW L1_GETS [7 ] 7 +OXW L1_GETX [4 ] 4 OXW L1_PUTO [0 ] 0 OXW L1_PUTX [0 ] 0 OXW L1_PUTS_only [0 ] 0 @@ -1030,8 +1105,8 @@ OXW Fwd_GETX [0 ] 0 OXW Fwd_GETS [0 ] 0 OXW Fwd_DMA [0 ] 0 OXW Inv [0 ] 0 -OXW Unblock [0 ] 0 -OXW L2_Replacement [0 ] 0 +OXW Unblock [3329 ] 3329 +OXW L2_Replacement [97 ] 97 OLSXW L1_GETS [0 ] 0 OLSXW L1_GETX [0 ] 0 @@ -1043,36 +1118,36 @@ OLSXW Fwd_GETX [0 ] 0 OLSXW Fwd_GETS [0 ] 0 OLSXW Fwd_DMA [0 ] 0 OLSXW Inv [0 ] 0 -OLSXW Unblock [0 ] 0 +OLSXW Unblock [20 ] 20 OLSXW L2_Replacement [0 ] 0 -ILXW L1_GETS [0 ] 0 -ILXW L1_GETX [0 ] 0 +ILXW L1_GETS [145 ] 145 +ILXW L1_GETX [71 ] 71 ILXW L1_PUTO [0 ] 0 ILXW L1_PUTX [0 ] 0 ILXW L1_PUTS_only [0 ] 0 -ILXW L1_PUTS [0 ] 0 +ILXW L1_PUTS [4 ] 4 ILXW Fwd_GETX [0 ] 0 ILXW Fwd_GETS [0 ] 0 ILXW Fwd_DMA [0 ] 0 ILXW Inv [0 ] 0 ILXW Data [0 ] 0 -ILXW L1_WBCLEANDATA [0 ] 0 -ILXW L1_WBDIRTYDATA [0 ] 0 -ILXW Unblock [0 ] 0 +ILXW L1_WBCLEANDATA [770628 ] 770628 +ILXW L1_WBDIRTYDATA [426636 ] 426636 +ILXW Unblock [2252 ] 2252 ILXW L2_Replacement [0 ] 0 IFLS L1_GETS [0 ] 0 IFLS L1_GETX [0 ] 0 IFLS L1_PUTO [0 ] 0 IFLS L1_PUTX [0 ] 0 -IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS_only [64 ] 64 IFLS L1_PUTS [0 ] 0 IFLS Fwd_GETX [0 ] 0 IFLS Fwd_GETS [0 ] 0 IFLS Fwd_DMA [0 ] 0 IFLS Inv [0 ] 0 -IFLS Unblock [0 ] 0 +IFLS Unblock [60 ] 60 IFLS L2_Replacement [0 ] 0 IFLO L1_GETS [0 ] 0 @@ -1090,78 +1165,78 @@ IFLO L2_Replacement [0 ] 0 IFLOX L1_GETS [0 ] 0 IFLOX L1_GETX [0 ] 0 -IFLOX L1_PUTO [0 ] 0 -IFLOX L1_PUTX [0 ] 0 -IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTO [1 ] 1 +IFLOX L1_PUTX [3 ] 3 +IFLOX L1_PUTS_only [3 ] 3 IFLOX L1_PUTS [0 ] 0 IFLOX Fwd_GETX [0 ] 0 IFLOX Fwd_GETS [0 ] 0 IFLOX Fwd_DMA [0 ] 0 IFLOX Inv [0 ] 0 -IFLOX Unblock [0 ] 0 -IFLOX Exclusive_Unblock [0 ] 0 +IFLOX Unblock [15 ] 15 +IFLOX Exclusive_Unblock [7 ] 7 IFLOX L2_Replacement [0 ] 0 -IFLOXX L1_GETS [2641993 ] 2641993 -IFLOXX L1_GETX [1479034 ] 1479034 -IFLOXX L1_PUTO [0 ] 0 -IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_GETS [360 ] 360 +IFLOXX L1_GETX [116 ] 116 +IFLOXX L1_PUTO [1204 ] 1204 +IFLOXX L1_PUTX [12725 ] 12725 IFLOXX L1_PUTS_only [0 ] 0 -IFLOXX L1_PUTS [0 ] 0 +IFLOXX L1_PUTS [6 ] 6 IFLOXX Fwd_GETX [0 ] 0 IFLOXX Fwd_GETS [0 ] 0 IFLOXX Fwd_DMA [0 ] 0 IFLOXX Inv [0 ] 0 -IFLOXX Unblock [431 ] 431 -IFLOXX Exclusive_Unblock [102628 ] 102628 +IFLOXX Unblock [8651 ] 8651 +IFLOXX Exclusive_Unblock [7824 ] 7824 IFLOXX L2_Replacement [0 ] 0 -IFLOSX L1_GETS [3247 ] 3247 -IFLOSX L1_GETX [4201 ] 4201 -IFLOSX L1_PUTO [0 ] 0 -IFLOSX L1_PUTX [0 ] 0 -IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [5 ] 5 +IFLOSX L1_PUTX [42 ] 42 +IFLOSX L1_PUTS_only [26 ] 26 IFLOSX L1_PUTS [0 ] 0 IFLOSX Fwd_GETX [0 ] 0 IFLOSX Fwd_GETS [0 ] 0 IFLOSX Fwd_DMA [0 ] 0 IFLOSX Inv [0 ] 0 -IFLOSX Unblock [440 ] 440 +IFLOSX Unblock [27 ] 27 IFLOSX Exclusive_Unblock [0 ] 0 IFLOSX L2_Replacement [0 ] 0 -IFLXO L1_GETS [3428 ] 3428 -IFLXO L1_GETX [4287 ] 4287 +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 IFLXO L1_PUTO [0 ] 0 -IFLXO L1_PUTX [0 ] 0 -IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTX [15 ] 15 +IFLXO L1_PUTS_only [6 ] 6 IFLXO L1_PUTS [0 ] 0 IFLXO Fwd_GETX [0 ] 0 IFLXO Fwd_GETS [0 ] 0 IFLXO Fwd_DMA [0 ] 0 IFLXO Inv [0 ] 0 -IFLXO Exclusive_Unblock [431 ] 431 +IFLXO Exclusive_Unblock [9 ] 9 IFLXO L2_Replacement [0 ] 0 -IGS L1_GETS [389 ] 389 -IGS L1_GETX [65 ] 65 +IGS L1_GETS [232650 ] 232650 +IGS L1_GETX [132978 ] 132978 IGS L1_PUTO [0 ] 0 IGS L1_PUTX [0 ] 0 IGS L1_PUTS_only [0 ] 0 -IGS L1_PUTS [0 ] 0 +IGS L1_PUTS [1 ] 1 IGS Fwd_GETX [0 ] 0 IGS Fwd_GETS [0 ] 0 IGS Fwd_DMA [0 ] 0 IGS Own_GETX [0 ] 0 IGS Inv [0 ] 0 -IGS Data [0 ] 0 -IGS Data_Exclusive [2 ] 2 -IGS Unblock [0 ] 0 -IGS Exclusive_Unblock [2 ] 2 +IGS Data [4961 ] 4961 +IGS Data_Exclusive [779526 ] 779526 +IGS Unblock [4961 ] 4961 +IGS Exclusive_Unblock [779525 ] 779525 IGS L2_Replacement [0 ] 0 -IGM L1_GETS [0 ] 0 -IGM L1_GETX [0 ] 0 +IGM L1_GETS [121622 ] 121622 +IGM L1_GETX [67947 ] 67947 IGM L1_PUTO [0 ] 0 IGM L1_PUTX [0 ] 0 IGM L1_PUTS_only [0 ] 0 @@ -1172,37 +1247,37 @@ IGM Fwd_DMA [0 ] 0 IGM Own_GETX [0 ] 0 IGM Inv [0 ] 0 IGM ExtAck [0 ] 0 -IGM Data [0 ] 0 +IGM Data [422180 ] 422180 IGM Data_Exclusive [0 ] 0 IGM L2_Replacement [0 ] 0 IGMLS L1_GETS [0 ] 0 -IGMLS L1_GETX [0 ] 0 +IGMLS L1_GETX [11 ] 11 IGMLS L1_PUTO [0 ] 0 IGMLS L1_PUTX [0 ] 0 -IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS_only [2219 ] 2219 IGMLS L1_PUTS [0 ] 0 IGMLS Inv [0 ] 0 IGMLS IntAck [0 ] 0 IGMLS ExtAck [0 ] 0 IGMLS All_Acks [0 ] 0 -IGMLS Data [0 ] 0 +IGMLS Data [37 ] 37 IGMLS Data_Exclusive [0 ] 0 IGMLS L2_Replacement [0 ] 0 -IGMO L1_GETS [0 ] 0 -IGMO L1_GETX [0 ] 0 +IGMO L1_GETS [3469 ] 3469 +IGMO L1_GETX [1846 ] 1846 IGMO L1_PUTO [0 ] 0 IGMO L1_PUTX [0 ] 0 -IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS_only [57 ] 57 IGMO L1_PUTS [0 ] 0 IGMO Fwd_GETX [0 ] 0 IGMO Fwd_GETS [0 ] 0 IGMO Fwd_DMA [0 ] 0 IGMO Own_GETX [0 ] 0 IGMO ExtAck [0 ] 0 -IGMO All_Acks [0 ] 0 -IGMO Exclusive_Unblock [0 ] 0 +IGMO All_Acks [422217 ] 422217 +IGMO Exclusive_Unblock [422217 ] 422217 IGMO L2_Replacement [0 ] 0 IGMIO L1_GETS [0 ] 0 @@ -1282,7 +1357,7 @@ MM Fwd_GETX [0 ] 0 MM Fwd_GETS [0 ] 0 MM Fwd_DMA [0 ] 0 MM Inv [0 ] 0 -MM Exclusive_Unblock [0 ] 0 +MM Exclusive_Unblock [1447 ] 1447 MM L2_Replacement [0 ] 0 SS L1_GETS [0 ] 0 @@ -1295,8 +1370,8 @@ SS Fwd_GETX [0 ] 0 SS Fwd_GETS [0 ] 0 SS Fwd_DMA [0 ] 0 SS Inv [0 ] 0 -SS Unblock [0 ] 0 -SS L2_Replacement [0 ] 0 +SS Unblock [24 ] 24 +SS L2_Replacement [1 ] 1 OO L1_GETS [0 ] 0 OO L1_GETX [0 ] 0 @@ -1309,8 +1384,8 @@ OO Fwd_GETS [0 ] 0 OO Fwd_DMA [0 ] 0 OO Inv [0 ] 0 OO Unblock [0 ] 0 -OO Exclusive_Unblock [0 ] 0 -OO L2_Replacement [0 ] 0 +OO Exclusive_Unblock [2720 ] 2720 +OO L2_Replacement [90 ] 90 OLSS L1_GETS [0 ] 0 OLSS L1_GETX [0 ] 0 @@ -1335,7 +1410,7 @@ OLSXS Fwd_GETX [0 ] 0 OLSXS Fwd_GETS [0 ] 0 OLSXS Fwd_DMA [0 ] 0 OLSXS Inv [0 ] 0 -OLSXS Unblock [0 ] 0 +OLSXS Unblock [13 ] 13 OLSXS L2_Replacement [0 ] 0 SLSS L1_GETS [0 ] 0 @@ -1364,8 +1439,8 @@ OI Writeback_Ack [0 ] 0 OI Writeback_Nack [0 ] 0 OI L2_Replacement [0 ] 0 -MI L1_GETS [0 ] 0 -MI L1_GETX [0 ] 0 +MI L1_GETS [524 ] 524 +MI L1_GETX [264 ] 264 MI L1_PUTO [0 ] 0 MI L1_PUTX [0 ] 0 MI L1_PUTS_only [0 ] 0 @@ -1373,7 +1448,7 @@ MI L1_PUTS [0 ] 0 MI Fwd_GETX [0 ] 0 MI Fwd_GETS [0 ] 0 MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [0 ] 0 +MI Writeback_Ack [1198971 ] 1198971 MI L2_Replacement [0 ] 0 MII L1_GETS [0 ] 0 @@ -1390,12 +1465,12 @@ OLSI L1_GETS [0 ] 0 OLSI L1_GETX [0 ] 0 OLSI L1_PUTO [0 ] 0 OLSI L1_PUTX [0 ] 0 -OLSI L1_PUTS_only [0 ] 0 -OLSI L1_PUTS [0 ] 0 +OLSI L1_PUTS_only [222 ] 222 +OLSI L1_PUTS [4 ] 4 OLSI Fwd_GETX [0 ] 0 OLSI Fwd_GETS [0 ] 0 OLSI Fwd_DMA [0 ] 0 -OLSI Writeback_Ack [0 ] 0 +OLSI Writeback_Ack [2748 ] 2748 OLSI L2_Replacement [0 ] 0 ILSI L1_GETS [0 ] 0 @@ -1410,59 +1485,59 @@ ILSI Writeback_Ack [0 ] 0 ILSI L2_Replacement [0 ] 0 Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 2 - memory_reads: 2 - memory_writes: 0 - memory_refreshes: 22 - memory_total_request_delays: 31 - memory_delays_per_request: 15.5 - memory_delays_in_input_queue: 1 - memory_delays_behind_head_of_bank_queue: 10 - memory_delays_stalled_at_head_of_bank_queue: 20 - memory_stalls_for_bank_busy: 20 + memory_total_requests: 1633762 + memory_reads: 1206708 + memory_writes: 427032 + memory_refreshes: 81124 + memory_total_request_delays: 100270801 + memory_delays_per_request: 61.3742 + memory_delays_in_input_queue: 671540 + memory_delays_behind_head_of_bank_queue: 41440167 + memory_delays_stalled_at_head_of_bank_queue: 58159094 + memory_stalls_for_bank_busy: 8934136 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 0 - memory_stalls_for_bus: 0 + memory_stalls_for_anti_starvation: 14073572 + memory_stalls_for_arbitration: 11978655 + memory_stalls_for_bus: 16268659 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 0 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + memory_stalls_for_read_write_turnaround: 4121967 + memory_stalls_for_read_read_turnaround: 2782105 + accesses_per_bank: 51374 51312 51085 51181 51268 51561 51508 50825 51409 51217 51548 51127 51070 51087 50968 50678 51156 50861 51389 50919 50839 50944 50908 50859 51006 50629 50693 50438 51078 50705 51300 50820 --- Directory --- - Event Counts - -GETX [0 ] 0 -GETS [2 ] 2 -PUTX [0 ] 0 +GETX [422222 ] 422222 +GETS [784499 ] 784499 +PUTX [1198972 ] 1198972 PUTO [0 ] 0 -PUTO_SHARERS [0 ] 0 +PUTO_SHARERS [2748 ] 2748 Unblock [0 ] 0 -Last_Unblock [0 ] 0 -Exclusive_Unblock [2 ] 2 -Clean_Writeback [0 ] 0 -Dirty_Writeback [0 ] 0 -Memory_Data [2 ] 2 -Memory_Ack [0 ] 0 +Last_Unblock [4961 ] 4961 +Exclusive_Unblock [1201742 ] 1201742 +Clean_Writeback [774677 ] 774677 +Dirty_Writeback [427041 ] 427041 +Memory_Data [1206704 ] 1206704 +Memory_Ack [427031 ] 427031 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 Data [0 ] 0 - Transitions - -I GETX [0 ] 0 -I GETS [2 ] 2 +I GETX [419482 ] 419482 +I GETS [779538 ] 779538 I PUTX [0 ] 0 I PUTO [0 ] 0 I Memory_Data [0 ] 0 -I Memory_Ack [0 ] 0 +I Memory_Ack [420246 ] 420246 I DMA_READ [0 ] 0 I DMA_WRITE [0 ] 0 -S GETX [0 ] 0 -S GETS [0 ] 0 +S GETX [2740 ] 2740 +S GETS [4961 ] 4961 S PUTX [0 ] 0 S PUTO [0 ] 0 S Memory_Data [0 ] 0 -S Memory_Ack [0 ] 0 +S Memory_Ack [640 ] 640 S DMA_READ [0 ] 0 S DMA_WRITE [0 ] 0 @@ -1478,9 +1553,9 @@ O DMA_WRITE [0 ] 0 M GETX [0 ] 0 M GETS [0 ] 0 -M PUTX [0 ] 0 +M PUTX [1198972 ] 1198972 M PUTO [0 ] 0 -M PUTO_SHARERS [0 ] 0 +M PUTO_SHARERS [2748 ] 2748 M Memory_Data [0 ] 0 M Memory_Ack [0 ] 0 M DMA_READ [0 ] 0 @@ -1492,9 +1567,9 @@ IS PUTX [0 ] 0 IS PUTO [0 ] 0 IS PUTO_SHARERS [0 ] 0 IS Unblock [0 ] 0 -IS Exclusive_Unblock [2 ] 2 -IS Memory_Data [2 ] 2 -IS Memory_Ack [0 ] 0 +IS Exclusive_Unblock [779525 ] 779525 +IS Memory_Data [779526 ] 779526 +IS Memory_Ack [4016 ] 4016 IS DMA_READ [0 ] 0 IS DMA_WRITE [0 ] 0 @@ -1504,9 +1579,9 @@ SS PUTX [0 ] 0 SS PUTO [0 ] 0 SS PUTO_SHARERS [0 ] 0 SS Unblock [0 ] 0 -SS Last_Unblock [0 ] 0 -SS Memory_Data [0 ] 0 -SS Memory_Ack [0 ] 0 +SS Last_Unblock [4961 ] 4961 +SS Memory_Data [4961 ] 4961 +SS Memory_Ack [3 ] 3 SS DMA_READ [0 ] 0 SS DMA_WRITE [0 ] 0 @@ -1539,9 +1614,9 @@ MM GETS [0 ] 0 MM PUTX [0 ] 0 MM PUTO [0 ] 0 MM PUTO_SHARERS [0 ] 0 -MM Exclusive_Unblock [0 ] 0 -MM Memory_Data [0 ] 0 -MM Memory_Ack [0 ] 0 +MM Exclusive_Unblock [422217 ] 422217 +MM Memory_Data [422217 ] 422217 +MM Memory_Ack [2126 ] 2126 MM DMA_READ [0 ] 0 MM DMA_WRITE [0 ] 0 @@ -1552,8 +1627,8 @@ MI PUTX [0 ] 0 MI PUTO [0 ] 0 MI PUTO_SHARERS [0 ] 0 MI Unblock [0 ] 0 -MI Clean_Writeback [0 ] 0 -MI Dirty_Writeback [0 ] 0 +MI Clean_Writeback [772580 ] 772580 +MI Dirty_Writeback [426390 ] 426390 MI Memory_Data [0 ] 0 MI Memory_Ack [0 ] 0 MI DMA_READ [0 ] 0 @@ -1565,8 +1640,8 @@ MIS PUTX [0 ] 0 MIS PUTO [0 ] 0 MIS PUTO_SHARERS [0 ] 0 MIS Unblock [0 ] 0 -MIS Clean_Writeback [0 ] 0 -MIS Dirty_Writeback [0 ] 0 +MIS Clean_Writeback [2097 ] 2097 +MIS Dirty_Writeback [651 ] 651 MIS Memory_Data [0 ] 0 MIS Memory_Ack [0 ] 0 MIS DMA_READ [0 ] 0 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr index ac46137f1..5944f2026 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr @@ -1,74 +1,74 @@ -system.cpu3: completed 10000 read accesses @323743 -system.cpu2: completed 10000 read accesses @336402 -system.cpu1: completed 10000 read accesses @338132 -system.cpu0: completed 10000 read accesses @340751 -system.cpu5: completed 10000 read accesses @341263 -system.cpu4: completed 10000 read accesses @346558 -system.cpu7: completed 10000 read accesses @346738 -system.cpu6: completed 10000 read accesses @348135 -system.cpu3: completed 20000 read accesses @670303 -system.cpu0: completed 20000 read accesses @670934 -system.cpu2: completed 20000 read accesses @675651 -system.cpu1: completed 20000 read accesses @679374 -system.cpu6: completed 20000 read accesses @683883 -system.cpu7: completed 20000 read accesses @684999 -system.cpu4: completed 20000 read accesses @688475 -system.cpu5: completed 20000 read accesses @691089 -system.cpu3: completed 30000 read accesses @1012754 -system.cpu2: completed 30000 read accesses @1013014 -system.cpu5: completed 30000 read accesses @1015303 -system.cpu0: completed 30000 read accesses @1018359 -system.cpu1: completed 30000 read accesses @1021563 -system.cpu4: completed 30000 read accesses @1024489 -system.cpu6: completed 30000 read accesses @1024945 -system.cpu7: completed 30000 read accesses @1026805 -system.cpu3: completed 40000 read accesses @1337640 -system.cpu4: completed 40000 read accesses @1353749 -system.cpu5: completed 40000 read accesses @1355921 -system.cpu2: completed 40000 read accesses @1358297 -system.cpu0: completed 40000 read accesses @1365879 -system.cpu7: completed 40000 read accesses @1368402 -system.cpu6: completed 40000 read accesses @1369510 -system.cpu1: completed 40000 read accesses @1372174 -system.cpu3: completed 50000 read accesses @1687319 -system.cpu4: completed 50000 read accesses @1694511 -system.cpu7: completed 50000 read accesses @1696243 -system.cpu2: completed 50000 read accesses @1699794 -system.cpu5: completed 50000 read accesses @1700188 -system.cpu6: completed 50000 read accesses @1703368 -system.cpu0: completed 50000 read accesses @1704599 -system.cpu1: completed 50000 read accesses @1716501 -system.cpu4: completed 60000 read accesses @2030412 -system.cpu3: completed 60000 read accesses @2034929 -system.cpu2: completed 60000 read accesses @2036378 -system.cpu7: completed 60000 read accesses @2036726 -system.cpu0: completed 60000 read accesses @2038738 -system.cpu5: completed 60000 read accesses @2046852 -system.cpu1: completed 60000 read accesses @2050784 -system.cpu6: completed 60000 read accesses @2058109 -system.cpu3: completed 70000 read accesses @2359493 -system.cpu4: completed 70000 read accesses @2365063 -system.cpu2: completed 70000 read accesses @2371739 -system.cpu0: completed 70000 read accesses @2373666 -system.cpu7: completed 70000 read accesses @2373767 -system.cpu5: completed 70000 read accesses @2395804 -system.cpu1: completed 70000 read accesses @2404686 -system.cpu6: completed 70000 read accesses @2406335 -system.cpu2: completed 80000 read accesses @2701352 -system.cpu7: completed 80000 read accesses @2705729 -system.cpu3: completed 80000 read accesses @2707362 -system.cpu4: completed 80000 read accesses @2711169 -system.cpu0: completed 80000 read accesses @2718197 -system.cpu1: completed 80000 read accesses @2736476 -system.cpu6: completed 80000 read accesses @2746379 -system.cpu5: completed 80000 read accesses @2751740 -system.cpu2: completed 90000 read accesses @3041770 -system.cpu3: completed 90000 read accesses @3048359 -system.cpu7: completed 90000 read accesses @3049406 -system.cpu0: completed 90000 read accesses @3052026 -system.cpu4: completed 90000 read accesses @3061142 -system.cpu1: completed 90000 read accesses @3064341 -system.cpu6: completed 90000 read accesses @3079121 -system.cpu5: completed 90000 read accesses @3089679 -system.cpu2: completed 100000 read accesses @3377485 +system.cpu7: completed 10000 read accesses @3869056 +system.cpu6: completed 10000 read accesses @3886426 +system.cpu4: completed 10000 read accesses @3898396 +system.cpu5: completed 10000 read accesses @3918286 +system.cpu0: completed 10000 read accesses @3919696 +system.cpu1: completed 10000 read accesses @3927286 +system.cpu2: completed 10000 read accesses @3929616 +system.cpu3: completed 10000 read accesses @3936396 +system.cpu5: completed 20000 read accesses @7713766 +system.cpu7: completed 20000 read accesses @7774726 +system.cpu4: completed 20000 read accesses @7795816 +system.cpu6: completed 20000 read accesses @7798926 +system.cpu1: completed 20000 read accesses @7805792 +system.cpu0: completed 20000 read accesses @7819976 +system.cpu2: completed 20000 read accesses @7850656 +system.cpu3: completed 20000 read accesses @7872096 +system.cpu5: completed 30000 read accesses @11623576 +system.cpu6: completed 30000 read accesses @11668436 +system.cpu0: completed 30000 read accesses @11699446 +system.cpu7: completed 30000 read accesses @11704516 +system.cpu4: completed 30000 read accesses @11718806 +system.cpu1: completed 30000 read accesses @11741606 +system.cpu3: completed 30000 read accesses @11767816 +system.cpu2: completed 30000 read accesses @11813276 +system.cpu5: completed 40000 read accesses @15522846 +system.cpu0: completed 40000 read accesses @15592626 +system.cpu6: completed 40000 read accesses @15619436 +system.cpu1: completed 40000 read accesses @15624516 +system.cpu4: completed 40000 read accesses @15630786 +system.cpu7: completed 40000 read accesses @15640616 +system.cpu3: completed 40000 read accesses @15655796 +system.cpu2: completed 40000 read accesses @15680896 +system.cpu5: completed 50000 read accesses @19438476 +system.cpu0: completed 50000 read accesses @19458866 +system.cpu1: completed 50000 read accesses @19542456 +system.cpu6: completed 50000 read accesses @19543746 +system.cpu4: completed 50000 read accesses @19568206 +system.cpu7: completed 50000 read accesses @19569526 +system.cpu3: completed 50000 read accesses @19594416 +system.cpu2: completed 50000 read accesses @19626796 +system.cpu5: completed 60000 read accesses @23331176 +system.cpu0: completed 60000 read accesses @23345146 +system.cpu6: completed 60000 read accesses @23379766 +system.cpu1: completed 60000 read accesses @23400806 +system.cpu4: completed 60000 read accesses @23475225 +system.cpu3: completed 60000 read accesses @23504027 +system.cpu7: completed 60000 read accesses @23511286 +system.cpu2: completed 60000 read accesses @23548006 +system.cpu5: completed 70000 read accesses @27140516 +system.cpu0: completed 70000 read accesses @27275896 +system.cpu1: completed 70000 read accesses @27288996 +system.cpu6: completed 70000 read accesses @27292846 +system.cpu7: completed 70000 read accesses @27386426 +system.cpu3: completed 70000 read accesses @27389056 +system.cpu4: completed 70000 read accesses @27433216 +system.cpu2: completed 70000 read accesses @27451236 +system.cpu5: completed 80000 read accesses @31034206 +system.cpu6: completed 80000 read accesses @31104766 +system.cpu1: completed 80000 read accesses @31179446 +system.cpu0: completed 80000 read accesses @31203676 +system.cpu3: completed 80000 read accesses @31246486 +system.cpu7: completed 80000 read accesses @31258446 +system.cpu2: completed 80000 read accesses @31320306 +system.cpu4: completed 80000 read accesses @31334426 +system.cpu5: completed 90000 read accesses @34995346 +system.cpu6: completed 90000 read accesses @35062566 +system.cpu3: completed 90000 read accesses @35112636 +system.cpu1: completed 90000 read accesses @35134786 +system.cpu7: completed 90000 read accesses @35159686 +system.cpu2: completed 90000 read accesses @35168476 +system.cpu0: completed 90000 read accesses @35169596 +system.cpu4: completed 90000 read accesses @35260086 +system.cpu6: completed 100000 read accesses @38939096 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index be3549bde..3251b74fa 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 20 2010 12:10:28 -M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates -M5 started Aug 20 2010 12:10:38 -M5 executing on SC2B0629 +M5 compiled Feb 8 2011 17:41:34 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:41:42 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3377485 because maximum number of loads reached +Exiting @ tick 38939096 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index b18cfb37f..fd4797192 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 341856 # Number of bytes of host memory used -host_seconds 29.56 # Real time elapsed on the host -host_tick_rate 114257 # Simulator tick rate (ticks/s) +host_mem_usage 346560 # Number of bytes of host memory used +host_seconds 500.03 # Real time elapsed on the host +host_tick_rate 77873 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003377 # Number of seconds simulated -sim_ticks 3377485 # Number of ticks simulated +sim_seconds 0.038939 # Number of seconds simulated +sim_ticks 38939096 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99116 # number of read accesses completed -system.cpu0.num_writes 53019 # number of write accesses completed +system.cpu0.num_reads 99650 # number of read accesses completed +system.cpu0.num_writes 53465 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99151 # number of read accesses completed -system.cpu1.num_writes 53486 # number of write accesses completed +system.cpu1.num_reads 99886 # number of read accesses completed +system.cpu1.num_writes 53908 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53183 # number of write accesses completed +system.cpu2.num_reads 99727 # number of read accesses completed +system.cpu2.num_writes 53685 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99632 # number of read accesses completed -system.cpu3.num_writes 54001 # number of write accesses completed +system.cpu3.num_reads 99743 # number of read accesses completed +system.cpu3.num_writes 53374 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99186 # number of read accesses completed -system.cpu4.num_writes 53590 # number of write accesses completed +system.cpu4.num_reads 99344 # number of read accesses completed +system.cpu4.num_writes 53842 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 98345 # number of read accesses completed -system.cpu5.num_writes 53268 # number of write accesses completed +system.cpu5.num_reads 99988 # number of read accesses completed +system.cpu5.num_writes 53434 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99155 # number of read accesses completed -system.cpu6.num_writes 53749 # number of write accesses completed +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 54115 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99644 # number of read accesses completed -system.cpu7.num_writes 53528 # number of write accesses completed +system.cpu7.num_reads 99701 # number of read accesses completed +system.cpu7.num_writes 53854 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini index cffe74459..00f219b6b 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=MemTest @@ -513,10 +522,9 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem [system.ruby] type=RubySystem -children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -528,8 +536,9 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports0] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl0.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl0.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -540,8 +549,9 @@ port=system.cpu0.test [system.ruby.cpu_ruby_ports1] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl1.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl1.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -552,8 +562,9 @@ port=system.cpu1.test [system.ruby.cpu_ruby_ports2] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl2.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl2.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -564,8 +575,9 @@ port=system.cpu2.test [system.ruby.cpu_ruby_ports3] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl3.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl3.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -576,8 +588,9 @@ port=system.cpu3.test [system.ruby.cpu_ruby_ports4] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl4.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl4.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -588,8 +601,9 @@ port=system.cpu4.test [system.ruby.cpu_ruby_ports5] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl5.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl5.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -600,8 +614,9 @@ port=system.cpu5.test [system.ruby.cpu_ruby_ports6] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl6.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl6.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -612,8 +627,9 @@ port=system.cpu6.test [system.ruby.cpu_ruby_ports7] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl7.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl7.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -622,14 +638,6 @@ version=7 physMemPort=system.physmem.port[7] port=system.cpu7.test -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - [system.ruby.network] type=SimpleNetwork children=topology diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats index 7b2bdba27..6f3eb0cc7 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/20/2010 12:14:59 +Real time: Feb/08/2011 17:56:11 Profiler Stats -------------- -Elapsed_time_in_seconds: 26 -Elapsed_time_in_minutes: 0.433333 -Elapsed_time_in_hours: 0.00722222 -Elapsed_time_in_days: 0.000300926 +Elapsed_time_in_seconds: 306 +Elapsed_time_in_minutes: 5.1 +Elapsed_time_in_hours: 0.085 +Elapsed_time_in_days: 0.00354167 -Virtual_time_in_seconds: 25.78 -Virtual_time_in_minutes: 0.429667 -Virtual_time_in_hours: 0.00716111 -Virtual_time_in_days: 0.00029838 +Virtual_time_in_seconds: 306.37 +Virtual_time_in_minutes: 5.10617 +Virtual_time_in_hours: 0.0851028 +Virtual_time_in_days: 0.00354595 -Ruby_current_time: 2583072 +Ruby_current_time: 39098820 Ruby_start_time: 0 -Ruby_cycles: 2583072 +Ruby_cycles: 39098820 -mbytes_resident: 32.8789 -mbytes_total: 333.961 -resident_ratio: 0.0984747 +mbytes_resident: 35.8438 +mbytes_total: 338.02 +resident_ratio: 0.106052 -ruby_cycles_executed: [ 2583073 2583073 2583073 2583073 2583073 2583073 2583073 2583073 ] +ruby_cycles_executed: [ 39098821 39098821 39098821 39098821 39098821 39098821 39098821 39098821 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -67,31 +67,35 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1202451 average: 1.98763 | standard deviation: 0.110552 | 0 14880 1187571 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1222292 average: 15.9992 | standard deviation: 0.0900883 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1222172 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 8 max: 1010 count: 1202436 average: 32.3679 | standard deviation: 136.165 | 1145435 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56101 498 85 84 67 29 60 30 1 5 1 0 0 0 0 4 2 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 8 max: 1010 count: 782221 average: 32.3974 | standard deviation: 136.229 | 745119 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36551 320 49 51 39 20 34 21 1 3 1 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 8 max: 825 count: 420215 average: 32.313 | standard deviation: 136.046 | 400316 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19550 178 36 33 28 9 26 9 0 2 0 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 2 count: 1145435 average: 2 | standard deviation: 0 | 0 0 1145435 ] -miss_latency_Directory: [binsize: 2 max: 369 count: 2 average: 314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_L1Cache_wCC: [binsize: 8 max: 1010 count: 56999 average: 642.622 | standard deviation: 13.675 | 0 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56101 498 85 84 67 29 60 30 1 5 1 0 0 0 0 4 2 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] -miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] -miss_latency_wCC_first_response_to_completion: [binsize: 8 max: 887 count: 6 average: 764.333 | standard deviation: 101.837 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -imcomplete_wCC_Times: 56993 -miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] -miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] -miss_latency_dir_first_response_to_completion: [binsize: 2 max: 369 count: 2 average: 314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -imcomplete_dir_Times: 0 -miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 745119 average: 2 | standard deviation: 0 | 0 0 745119 ] -miss_latency_LD_Directory: [binsize: 2 max: 369 count: 2 average: 314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_L1Cache_wCC: [binsize: 8 max: 1010 count: 37100 average: 642.885 | standard deviation: 5.20071 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36551 320 49 51 39 20 34 21 1 3 1 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 400316 average: 2 | standard deviation: 0 | 0 0 400316 ] -miss_latency_ST_L1Cache_wCC: [binsize: 8 max: 825 count: 19899 average: 642.132 | standard deviation: 22.02 | 0 0 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19550 178 36 33 28 9 26 9 0 2 0 0 0 0 0 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 19010 count: 1222164 average: 4094.58 | standard deviation: 4593.48 | 880 14265 26585 29256 28185 35200 38945 38659 33785 30463 32498 30366 25971 24412 21952 21617 19095 18024 17874 15039 15394 14747 15001 13923 12605 13752 13676 13169 13327 12339 13422 12918 12919 13474 12199 13007 13169 13505 13304 11996 13422 13587 13234 13635 13004 14282 13902 14329 14720 13221 14049 14170 14758 14115 12697 14009 13907 13300 13036 12016 12717 11721 11409 11153 9488 9656 9446 9016 8223 7027 7249 6997 6100 5734 4930 5022 4406 3930 3733 3114 2971 2616 2611 2119 1803 1802 1613 1355 1170 1067 944 845 751 691 552 470 444 408 329 301 262 258 185 172 148 120 124 92 81 69 53 55 44 44 30 28 27 14 17 12 18 15 11 2 4 4 2 4 3 3 1 2 5 2 3 0 2 0 0 1 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 19010 count: 794491 average: 4097.54 | standard deviation: 6162.87 | 574 9241 17391 18989 18344 22795 25252 25174 21924 19783 21202 19508 16884 15814 14312 14027 12415 11711 11609 9835 10025 9594 9689 8982 8157 8925 8922 8521 8688 7983 8759 8333 8336 8819 7995 8480 8556 8845 8615 7796 8730 8855 8537 8853 8467 9277 9000 9350 9661 8645 9005 9134 9600 9253 8268 9089 9151 8760 8479 7801 8302 7675 7466 7212 6197 6318 6086 5880 5353 4602 4740 4503 3963 3713 3209 3232 2853 2538 2406 2050 1897 1727 1714 1378 1169 1186 1040 885 771 692 593 561 512 447 356 315 291 270 228 178 173 164 112 110 107 78 80 64 60 45 32 33 25 32 19 17 17 10 10 9 15 10 9 1 0 4 2 3 3 3 1 2 4 2 2 0 1 0 0 1 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 128 max: 17500 count: 427673 average: 4089.1 | standard deviation: 2956.01 | 306 5024 9194 10267 9841 12405 13693 13485 11861 10680 11296 10858 9087 8598 7640 7590 6680 6313 6265 5204 5369 5153 5312 4941 4448 4827 4754 4648 4639 4356 4663 4585 4583 4655 4204 4527 4613 4660 4689 4200 4692 4732 4697 4782 4537 5005 4902 4979 5059 4576 5044 5036 5158 4862 4429 4920 4756 4540 4557 4215 4415 4046 3943 3941 3291 3338 3360 3136 2870 2425 2509 2494 2137 2021 1721 1790 1553 1392 1327 1064 1074 889 897 741 634 616 573 470 399 375 351 284 239 244 196 155 153 138 101 123 89 94 73 62 41 42 44 28 21 24 21 22 19 12 11 11 10 4 7 3 3 5 2 1 4 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 182 average: 2 | standard deviation: 0 | 0 0 182 ] +miss_latency_L2Cache: [binsize: 128 max: 14636 count: 3318 average: 4304.23 | standard deviation: 3025.46 | 103 34 41 46 41 81 42 74 81 73 78 75 61 77 70 75 60 60 65 39 55 43 40 38 39 32 32 48 28 32 32 36 39 45 44 33 36 26 37 48 36 41 30 24 38 43 29 40 38 35 40 31 38 37 31 37 33 39 44 32 40 44 29 34 28 25 23 25 29 16 21 30 15 15 27 16 21 11 14 9 12 7 9 5 9 3 8 4 3 5 3 2 4 1 2 2 2 3 0 0 2 0 0 1 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 128 max: 19010 count: 1212227 average: 4096.98 | standard deviation: 4615.1 | 1 14081 26393 29048 27995 34881 38752 38403 33550 30252 32309 30196 25812 24248 21814 21475 18947 17878 17734 14925 15278 14631 14881 13820 12515 13647 13587 13028 13222 12241 13320 12827 12817 13368 12081 12904 13058 13415 13183 11879 13322 13475 13134 13541 12888 14167 13803 14219 14601 13102 13935 14061 14647 13997 12600 13894 13816 13186 12931 11939 12620 11639 11321 11073 9422 9602 9381 8954 8158 6979 7199 6945 6056 5700 4877 4986 4372 3908 3705 3092 2944 2601 2590 2102 1788 1793 1593 1347 1162 1060 938 838 747 688 548 466 442 405 327 298 258 258 185 170 147 119 122 90 81 69 53 55 44 44 29 28 27 14 16 12 18 15 11 2 4 4 2 4 3 3 1 2 5 2 3 0 2 0 0 1 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 128 max: 15204 count: 6437 average: 3651.95 | standard deviation: 2983.45 | 594 150 151 162 149 238 151 182 154 138 111 95 98 87 68 67 88 86 75 75 61 73 80 65 51 73 57 93 77 66 70 55 63 61 74 70 75 64 84 69 64 71 70 70 78 72 70 70 81 84 74 78 73 81 66 78 58 75 61 45 57 38 59 46 38 29 42 37 36 32 29 22 29 19 26 20 13 11 14 13 15 8 12 12 6 6 12 4 5 2 3 5 0 2 2 2 0 0 2 3 2 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 6437 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 8 average: 0 | standard deviation: 0 | 8 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 8 average: 0 | standard deviation: 0 | 8 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 8 average: 0 | standard deviation: 0 | 8 ] +miss_latency_dir_first_response_to_completion: [binsize: 4 max: 579 count: 8 average: 340.25 | standard deviation: 178.281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_dir_Times: 1212219 +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 120 average: 2 | standard deviation: 0 | 0 0 120 ] +miss_latency_LD_L2Cache: [binsize: 128 max: 13736 count: 2082 average: 4302.16 | standard deviation: 3042.21 | 68 21 23 26 19 57 29 48 59 48 48 54 33 52 45 47 40 32 38 26 31 29 29 20 20 14 22 33 16 20 17 21 22 25 28 22 25 17 22 27 22 28 18 17 21 25 20 25 26 24 21 19 24 25 25 22 21 25 31 17 18 28 17 25 16 15 13 18 18 10 16 16 13 10 16 14 13 6 8 4 9 5 7 5 2 1 3 4 3 3 2 1 3 1 2 2 1 2 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_Directory: [binsize: 128 max: 19010 count: 788140 average: 4099.76 | standard deviation: 6200.71 | 0 9117 17280 18869 18227 22592 25126 25009 21768 19647 21089 19389 16788 15698 14217 13930 12324 11625 11524 9759 9953 9516 9610 8921 8109 8862 8864 8436 8621 7916 8703 8275 8280 8751 7918 8410 8481 8787 8526 7730 8661 8781 8481 8793 8398 9211 8939 9284 9582 8567 8942 9064 9531 9173 8203 9011 9100 8685 8403 7754 8242 7617 7411 7165 6158 6282 6047 5837 5310 4567 4708 4472 3926 3691 3172 3205 2830 2524 2387 2037 1875 1716 1702 1365 1164 1181 1029 878 763 687 589 557 509 445 352 312 290 268 226 176 171 164 112 110 106 77 79 63 60 45 32 33 25 32 19 17 17 10 10 9 15 10 9 1 0 4 2 3 3 3 1 2 4 2 2 0 1 0 0 1 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 13609 count: 4149 average: 3690.67 | standard deviation: 3008.16 | 386 103 88 94 98 146 97 117 97 88 65 65 63 64 50 50 51 54 47 50 41 49 50 41 28 49 36 52 51 47 39 37 34 43 49 48 50 41 67 39 47 46 38 43 48 41 41 41 53 54 42 51 45 55 40 56 30 50 45 30 42 30 38 22 23 21 26 25 25 25 16 15 24 12 21 13 10 8 11 9 13 6 5 8 3 4 8 3 5 2 2 3 0 1 2 1 0 0 2 2 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 62 average: 2 | standard deviation: 0 | 0 0 62 ] +miss_latency_ST_L2Cache: [binsize: 128 max: 14636 count: 1236 average: 4307.73 | standard deviation: 2998.25 | 35 13 18 20 22 24 13 26 22 25 30 21 28 25 25 28 20 28 27 13 24 14 11 18 19 18 10 15 12 12 15 15 17 20 16 11 11 9 15 21 14 13 12 7 17 18 9 15 12 11 19 12 14 12 6 15 12 14 13 15 22 16 12 9 12 10 10 7 11 6 5 14 2 5 11 2 8 5 6 5 3 2 2 0 7 2 5 0 0 2 1 1 1 0 0 0 1 1 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 128 max: 17500 count: 424087 average: 4091.79 | standard deviation: 2955.53 | 1 4964 9113 10179 9768 12289 13626 13394 11782 10605 11220 10807 9024 8550 7597 7545 6623 6253 6210 5166 5325 5115 5271 4899 4406 4785 4723 4592 4601 4325 4617 4552 4537 4617 4163 4494 4577 4628 4657 4149 4661 4694 4653 4748 4490 4956 4864 4935 5019 4535 4993 4997 5116 4824 4397 4883 4716 4501 4528 4185 4378 4022 3910 3908 3264 3320 3334 3117 2848 2412 2491 2473 2130 2009 1705 1781 1542 1384 1318 1055 1069 885 888 737 624 612 564 469 399 373 349 281 238 243 196 154 152 137 101 122 87 94 73 60 41 42 43 27 21 24 21 22 19 12 10 11 10 4 6 3 3 5 2 1 4 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15204 count: 2288 average: 3581.73 | standard deviation: 2937.45 | 208 47 63 68 51 92 54 65 57 50 46 30 35 23 18 17 37 32 28 25 20 24 30 24 23 24 21 41 26 19 31 18 29 18 25 22 25 23 17 30 17 25 32 27 30 31 29 29 28 30 32 27 28 26 26 22 28 25 16 15 15 8 21 24 15 8 16 12 11 7 13 7 5 7 5 7 3 3 3 4 2 2 7 4 3 2 4 1 0 0 1 2 0 1 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -121,244 +125,322 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 25 +user_time: 306 system_time: 0 -page_reclaims: 9519 +page_reclaims: 10416 page_faults: 0 swaps: 0 -block_inputs: 16 +block_inputs: 0 block_outputs: 0 Network Stats ------------- -total_msg_count_Request_Control: 342090 2736720 -total_msg_count_Response_Data: 170931 12307032 -total_msg_count_ResponseLocal_Data: 48 3456 -total_msg_count_Response_Control: 170943 1367544 -total_msg_count_Broadcast_Control: 855225 6841800 -total_msg_count_Persistent_Control: 2279000 18232000 -total_msgs: 3818237 total_bytes: 41488552 +total_msg_count_Request_Control: 7329210 58633680 +total_msg_count_Response_Data: 3644058 262372176 +total_msg_count_ResponseL2hit_Data: 2832 203904 +total_msg_count_ResponseLocal_Data: 13539 974808 +total_msg_count_Response_Control: 11253 90024 +total_msg_count_Writeback_Data: 4939377 355635144 +total_msg_count_Writeback_Control: 2366358 18930864 +total_msg_count_Broadcast_Control: 18330105 146640840 +total_msg_count_Persistent_Control: 16213440 129707520 +total_msgs: 52850172 total_bytes: 973188960 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.151672 - links_utilized_percent_switch_0_link_0: 0.110312 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.193032 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 7123 512856 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Broadcast_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.166841 + links_utilized_percent_switch_0_link_0: 0.104259 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.229422 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 152823 11003256 [ 0 0 0 0 152823 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 130 9360 [ 0 0 0 0 130 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseLocal_Data: 597 42984 [ 0 0 0 0 597 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 1068453 8547624 [ 0 1068453 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 153554 1228432 [ 0 153554 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 261 18792 [ 0 0 0 0 261 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseLocal_Data: 583 41976 [ 0 0 0 0 583 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 490 3920 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 153061 11020392 [ 0 0 0 0 153061 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Broadcast_Control: 153554 1228432 [ 0 153554 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 101285 810280 [ 0 0 0 101285 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.151704 - links_utilized_percent_switch_1_link_0: 0.11032 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.193088 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 7124 512928 [ 0 0 0 0 7124 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Broadcast_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Persistent_Control: 14242 113936 [ 0 0 0 14242 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.166478 + links_utilized_percent_switch_1_link_0: 0.104145 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.228811 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 152394 10972368 [ 0 0 0 0 152394 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 119 8568 [ 0 0 0 0 119 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseLocal_Data: 533 38376 [ 0 0 0 0 533 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 64 4608 [ 0 0 0 0 64 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 1068894 8551152 [ 0 1068894 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 153113 1224904 [ 0 153113 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 251 18072 [ 0 0 0 0 251 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseLocal_Data: 535 38520 [ 0 0 0 0 535 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 457 3656 [ 0 0 0 0 457 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 152654 10991088 [ 0 0 0 0 152654 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Broadcast_Control: 153113 1224904 [ 0 153113 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Persistent_Control: 101607 812856 [ 0 0 0 101607 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.151685 - links_utilized_percent_switch_2_link_0: 0.110312 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.193057 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 7120 512640 [ 0 0 0 0 7120 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Broadcast_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.16592 + links_utilized_percent_switch_2_link_0: 0.103987 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.227854 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 151660 10919520 [ 0 0 0 0 151660 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 104 7488 [ 0 0 0 0 104 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 582 41904 [ 0 0 0 0 582 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 145 10440 [ 0 0 0 0 145 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 1069512 8556096 [ 0 1069512 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 152495 1219960 [ 0 152495 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 242 17424 [ 0 0 0 0 242 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 562 40464 [ 0 0 0 0 562 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 469 3752 [ 0 0 0 0 469 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 152024 10945728 [ 0 0 0 0 152024 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Broadcast_Control: 152495 1219960 [ 0 152495 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Persistent_Control: 100853 806824 [ 0 0 0 100853 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.151691 - links_utilized_percent_switch_3_link_0: 0.110313 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.193069 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 6 48 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Broadcast_Control: 49885 399080 [ 0 49885 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 7130 57040 [ 0 7130 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 7124 512928 [ 0 0 0 0 7124 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Broadcast_Control: 7130 57040 [ 0 7130 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.165833 + links_utilized_percent_switch_3_link_0: 0.103949 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.227717 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 151505 10908360 [ 0 0 0 0 151505 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 99 7128 [ 0 0 0 0 99 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 554 39888 [ 0 0 0 0 554 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Data: 185 13320 [ 0 0 0 0 185 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 1069661 8557288 [ 0 1069661 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 152346 1218768 [ 0 152346 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 249 17928 [ 0 0 0 0 249 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseLocal_Data: 591 42552 [ 0 0 0 0 591 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 505 4040 [ 0 0 0 0 505 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 151837 10932264 [ 0 0 0 0 151837 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Broadcast_Control: 152346 1218768 [ 0 152346 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 101401 811208 [ 0 0 0 101401 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.1517 - links_utilized_percent_switch_4_link_0: 0.110316 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.193084 bw: 160000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Broadcast_Control: 49886 399088 [ 0 49886 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 7129 57032 [ 0 7129 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 7123 512856 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 7123 56984 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Broadcast_Control: 7129 57032 [ 0 7129 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 0.165882 + links_utilized_percent_switch_4_link_0: 0.103963 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.227802 bw: 160000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Response_Data: 151444 10903968 [ 0 0 0 0 151444 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 132 9504 [ 0 0 0 0 132 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 564 40608 [ 0 0 0 0 564 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Data: 257 18504 [ 0 0 0 0 257 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 1069606 8556848 [ 0 1069606 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 152401 1219208 [ 0 152401 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 254 18288 [ 0 0 0 0 254 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 561 40392 [ 0 0 0 0 561 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 468 3744 [ 0 0 0 0 468 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 151929 10938888 [ 0 0 0 0 151929 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Broadcast_Control: 152401 1219208 [ 0 152401 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Persistent_Control: 101391 811128 [ 0 0 0 101391 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.151686 - links_utilized_percent_switch_5_link_0: 0.110312 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.193059 bw: 160000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 7119 512568 [ 0 0 0 0 7119 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_ResponseLocal_Data: 5 360 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 7123 56984 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Broadcast_Control: 7127 57016 [ 0 7127 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 0.166348 + links_utilized_percent_switch_5_link_0: 0.104099 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.228597 bw: 160000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Response_Data: 151938 10939536 [ 0 0 0 0 151938 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 115 8280 [ 0 0 0 0 115 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseLocal_Data: 568 40896 [ 0 0 0 0 568 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Data: 311 22392 [ 0 0 0 0 311 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 1069072 8552576 [ 0 1069072 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 152935 1223480 [ 0 152935 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 245 17640 [ 0 0 0 0 245 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseLocal_Data: 560 40320 [ 0 0 0 0 560 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 466 3728 [ 0 0 0 0 466 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 152466 10977552 [ 0 0 0 0 152466 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Broadcast_Control: 152935 1223480 [ 0 152935 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Persistent_Control: 101798 814384 [ 0 0 0 101798 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.151673 - links_utilized_percent_switch_6_link_0: 0.110309 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.193038 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 7125 57000 [ 0 0 0 0 7125 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Broadcast_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.166154 + links_utilized_percent_switch_6_link_0: 0.104058 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.22825 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Response_Data: 151673 10920456 [ 0 0 0 0 151673 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 120 8640 [ 0 0 0 0 120 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseLocal_Data: 559 40248 [ 0 0 0 0 559 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Data: 418 30096 [ 0 0 0 0 418 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 1069234 8553872 [ 0 1069234 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 152773 1222184 [ 0 152773 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 215 15480 [ 0 0 0 0 215 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 570 41040 [ 0 0 0 0 570 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 469 3752 [ 0 0 0 0 469 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 152302 10965744 [ 0 0 0 0 152302 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Broadcast_Control: 152773 1222184 [ 0 152773 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Persistent_Control: 101062 808496 [ 0 0 0 101062 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.151662 - links_utilized_percent_switch_7_link_0: 0.110309 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.193014 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 7121 512712 [ 0 0 0 0 7121 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 7122 56976 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Broadcast_Control: 7125 57000 [ 0 7125 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Persistent_Control: 14244 113952 [ 0 0 0 14244 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.165861 + links_utilized_percent_switch_7_link_0: 0.10396 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.227762 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Response_Data: 151248 10889856 [ 0 0 0 0 151248 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 125 9000 [ 0 0 0 0 125 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 556 40032 [ 0 0 0 0 556 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Data: 459 33048 [ 0 0 0 0 459 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 1069617 8556936 [ 0 1069617 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 152390 1219120 [ 0 152390 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 212 15264 [ 0 0 0 0 212 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 551 39672 [ 0 0 0 0 551 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 420 3360 [ 0 0 0 0 420 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 151967 10941624 [ 0 0 0 0 151967 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Broadcast_Control: 152390 1219120 [ 0 152390 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Persistent_Control: 101275 810200 [ 0 0 0 101275 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.110331 - links_utilized_percent_switch_8_link_0: 0.110299 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.110363 bw: 160000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Request_Control: 57015 456120 [ 0 57015 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 56964 455712 [ 0 0 0 0 56964 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 57015 456120 [ 0 0 57015 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 0.5836 + links_utilized_percent_switch_8_link_0: 0.415632 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.751568 bw: 160000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Request_Control: 1222007 9776056 [ 0 1222007 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 3735 29880 [ 0 0 0 0 3735 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 1218239 87713208 [ 0 0 0 0 1218239 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 1221063 9768504 [ 0 0 1221063 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 566 40752 [ 0 0 0 0 566 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 944 67968 [ 0 0 0 0 944 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Data: 428184 30829248 [ 0 0 0 0 428184 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 788775 6310200 [ 0 0 0 0 788775 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 0.0413841 - links_utilized_percent_switch_9_link_0: 0.0827334 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 3.48422e-05 bw: 160000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Request_Control: 57015 456120 [ 0 0 57015 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_9: 0.804022 + links_utilized_percent_switch_9_link_0: 0.212855 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 1.39519 bw: 160000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Request_Control: 1221063 9768504 [ 0 0 1221063 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Data: 426377 30699144 [ 0 0 0 0 426377 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 788780 6310240 [ 0 0 0 0 788780 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 1212191 87277752 [ 0 0 0 0 1212191 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Data: 35 2520 [ 0 0 0 0 35 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 6 48 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.408158 - links_utilized_percent_switch_10_link_0: 0.413678 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.413713 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.413678 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.41368 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.413693 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.413678 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.413664 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.413664 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.441198 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 0.330933 bw: 160000 base_latency: 1 - - outgoing_messages_switch_10_link_0_Response_Data: 7123 512856 [ 0 0 0 0 7123 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Persistent_Control: 99708 797664 [ 0 0 0 99708 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 6 48 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Broadcast_Control: 49885 399080 [ 0 49885 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Broadcast_Control: 49886 399088 [ 0 49886 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Broadcast_Control: 49888 399104 [ 0 49888 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 7122 512784 [ 0 0 0 0 7122 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Broadcast_Control: 49890 399120 [ 0 49890 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Persistent_Control: 99706 797648 [ 0 0 0 99706 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Request_Control: 57015 456120 [ 0 57015 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 56964 455712 [ 0 0 0 0 56964 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Request_Control: 57015 456120 [ 0 0 57015 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Persistent_Control: 113950 911600 [ 0 0 0 113950 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_10: 0.573996 + links_utilized_percent_switch_10_link_0: 0.404083 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.403587 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.40305 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.402828 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.402885 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.40338 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.403308 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.40289 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 1.66253 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 0.851422 bw: 160000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Response_Data: 152823 11003256 [ 0 0 0 0 152823 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 130 9360 [ 0 0 0 0 130 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseLocal_Data: 597 42984 [ 0 0 0 0 597 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Broadcast_Control: 1068453 8547624 [ 0 1068453 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Persistent_Control: 709387 5675096 [ 0 0 0 709387 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 152394 10972368 [ 0 0 0 0 152394 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 119 8568 [ 0 0 0 0 119 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseLocal_Data: 533 38376 [ 0 0 0 0 533 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Writeback_Data: 64 4608 [ 0 0 0 0 64 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Broadcast_Control: 1068894 8551152 [ 0 1068894 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Persistent_Control: 709065 5672520 [ 0 0 0 709065 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 151660 10919520 [ 0 0 0 0 151660 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 104 7488 [ 0 0 0 0 104 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 582 41904 [ 0 0 0 0 582 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Writeback_Data: 145 10440 [ 0 0 0 0 145 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Broadcast_Control: 1069512 8556096 [ 0 1069512 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Persistent_Control: 709819 5678552 [ 0 0 0 709819 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 151505 10908360 [ 0 0 0 0 151505 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 99 7128 [ 0 0 0 0 99 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 554 39888 [ 0 0 0 0 554 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Writeback_Data: 185 13320 [ 0 0 0 0 185 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Broadcast_Control: 1069661 8557288 [ 0 1069661 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Persistent_Control: 709271 5674168 [ 0 0 0 709271 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 151444 10903968 [ 0 0 0 0 151444 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 132 9504 [ 0 0 0 0 132 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 564 40608 [ 0 0 0 0 564 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Writeback_Data: 257 18504 [ 0 0 0 0 257 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Broadcast_Control: 1069606 8556848 [ 0 1069606 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Persistent_Control: 709281 5674248 [ 0 0 0 709281 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 151938 10939536 [ 0 0 0 0 151938 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 115 8280 [ 0 0 0 0 115 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseLocal_Data: 568 40896 [ 0 0 0 0 568 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Writeback_Data: 311 22392 [ 0 0 0 0 311 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Broadcast_Control: 1069072 8552576 [ 0 1069072 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Persistent_Control: 708874 5670992 [ 0 0 0 708874 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 151673 10920456 [ 0 0 0 0 151673 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 120 8640 [ 0 0 0 0 120 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseLocal_Data: 559 40248 [ 0 0 0 0 559 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Writeback_Data: 418 30096 [ 0 0 0 0 418 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Broadcast_Control: 1069234 8553872 [ 0 1069234 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Persistent_Control: 709610 5676880 [ 0 0 0 709610 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 151248 10889856 [ 0 0 0 0 151248 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 125 9000 [ 0 0 0 0 125 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 556 40032 [ 0 0 0 0 556 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Writeback_Data: 459 33048 [ 0 0 0 0 459 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Broadcast_Control: 1069617 8556936 [ 0 1069617 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Persistent_Control: 709397 5675176 [ 0 0 0 709397 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Request_Control: 1222007 9776056 [ 0 1222007 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 3735 29880 [ 0 0 0 0 3735 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Writeback_Data: 1218239 87713208 [ 0 0 0 0 1218239 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Request_Control: 1221063 9768504 [ 0 0 1221063 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Response_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Writeback_Data: 426377 30699144 [ 0 0 0 0 426377 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Writeback_Control: 788780 6310240 [ 0 0 0 0 788780 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Persistent_Control: 810672 6485376 [ 0 0 0 810672 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -369,203 +451,203 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 7125 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 7125 + system.l1_cntrl0.L1DcacheMemory_total_misses: 153555 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 153555 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 64.9965% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 35.0035% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 65.1174% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 34.8826% - system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 7125 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 153555 100% --- L1Cache --- - Event Counts - -Load [97598 97330 96960 97500 100000 98829 96777 97237 ] 782231 +Load [99079 99634 99062 99037 100002 99633 99065 99000 ] 794512 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [52430 52106 52281 52110 53664 53487 51846 52295 ] 420219 +Store [53348 53317 53734 53376 53574 53502 53455 53372 ] 427678 Atomic [0 0 0 0 0 0 0 0 ] 0 -L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -Data_Shared [0 0 0 0 0 0 0 0 ] 0 -Data_Owner [6 6 3 2 1 3 5 4 ] 30 -Data_All_Tokens [7119 7118 7120 7121 7123 7123 7119 7120 ] 56963 -Ack [0 1 1 1 0 0 1 2 ] 6 -Ack_All_Tokens [3 1 1 1 0 0 1 4 ] 11 +L1_Replacement [2549788 2558433 2553840 2548163 2566926 2559538 2551293 2548476 ] 20436457 +Data_Shared [325 321 306 321 323 299 309 317 ] 2521 +Data_Owner [97 90 104 115 101 92 97 120 ] 816 +Data_All_Tokens [151975 152521 152360 151952 153130 152719 152085 151906 ] 1218648 +Ack [1 1 3 1 3 3 2 1 ] 15 +Ack_All_Tokens [1 1 0 0 1 2 1 0 ] 6 Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -Transient_Local_GETX [17379 17433 17386 17429 17409 17431 17418 17436 ] 139321 +Transient_Local_GETX [374278 374305 373891 374249 374052 374120 374165 374252 ] 2993312 Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -Transient_Local_GETS [32507 32455 32504 32461 32481 32457 32470 32449 ] 259784 +Transient_Local_GETS [695328 694766 695342 695367 694400 694774 695344 695409 ] 5560730 Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -Persistent_GETX [19681 19967 19851 19972 19399 19393 19734 19360 ] 157357 -Persistent_GETS [36732 37056 37006 37152 36090 36049 36638 36016 ] 292739 -Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -Own_Lock_or_Unlock [57537 56927 57093 56826 58461 58508 57578 58574 ] 461504 -Request_Timeout [7147 7226 7147 7140 7122 7468 7539 7333 ] 58122 -Use_TimeoutStarverX [6 19 10 28 0 6 54 0 ] 123 -Use_TimeoutStarverS [11 27 13 48 0 8 69 1 ] 177 -Use_TimeoutNoStarvers [7105 7073 7098 7046 7123 7109 6997 7123 ] 56674 +Transient_Local_GETS_Last_Token [0 1 1 1 1 0 3 0 ] 7 +Persistent_GETX [124790 124771 124739 124760 124868 124800 124686 124679 ] 998093 +Persistent_GETS [231798 231640 232019 231915 231752 231656 232127 231872 ] 1854779 +Persistent_GETS_Last_Token [1 0 0 0 0 0 1 2 ] 4 +Own_Lock_or_Unlock [454083 454261 453914 453997 454052 454216 453858 454119 ] 3632500 +Request_Timeout [987948 1003569 995376 995086 995661 991836 987483 990404 ] 7947363 +Use_TimeoutStarverX [13 14 10 10 3 1 10 6 ] 67 +Use_TimeoutStarverS [29 30 20 25 5 9 20 17 ] 155 +Use_TimeoutNoStarvers [151934 152478 152330 151916 153120 152711 152056 151882 ] 1218427 Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 - Transitions - -NP Load [2 2 1 2 2 2 2 1 ] 14 +NP Load [98846 99418 98841 98814 99785 99416 98856 98777 ] 792753 NP Ifetch [0 0 0 0 0 0 0 0 ] 0 -NP Store [0 0 1 0 0 0 0 1 ] 2 +NP Store [53244 53182 53579 53256 53436 53391 53317 53247 ] 426652 NP Atomic [0 0 0 0 0 0 0 0 ] 0 NP Data_Shared [0 0 0 0 0 0 0 0 ] 0 -NP Data_Owner [0 0 0 0 0 0 0 0 ] 0 -NP Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 -NP Ack [0 0 0 0 0 0 0 0 ] 0 +NP Data_Owner [0 1 0 0 0 0 0 0 ] 1 +NP Data_All_Tokens [0 0 0 1 0 0 0 0 ] 1 +NP Ack [0 1 2 0 1 2 0 0 ] 6 NP Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -NP Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +NP Transient_Local_GETX [372830 372866 372426 372762 372623 372681 372738 372818 ] 2981744 NP Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -NP Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +NP Transient_Local_GETS [692740 692196 692800 692831 691905 692270 692717 692830 ] 5540289 NP Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 NP Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 NP Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -NP Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 +NP Own_Lock_or_Unlock [393214 393338 393622 393536 393429 393566 393547 393223 ] 3147475 -I Load [1 4 1 0 0 2 4 0 ] 12 +I Load [0 0 0 0 0 0 0 0 ] 0 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [1 1 1 1 1 0 0 0 ] 5 +I Store [0 0 0 1 0 0 0 1 ] 2 I Atomic [0 0 0 0 0 0 0 0 ] 0 -I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I L1_Replacement [468 465 467 419 489 454 467 504 ] 3733 I Data_Shared [0 0 0 0 0 0 0 0 ] 0 I Data_Owner [0 0 0 0 0 0 0 0 ] 0 I Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 I Ack [0 0 0 0 0 0 0 0 ] 0 I Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -I Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +I Transient_Local_GETX [2 0 3 3 0 1 1 2 ] 12 I Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -I Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +I Transient_Local_GETS [2 1 6 2 0 1 2 3 ] 17 I Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 I Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -I Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +I Persistent_GETX [1 0 0 0 1 0 0 1 ] 3 +I Persistent_GETS [1 0 3 2 0 1 0 1 ] 8 I Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I Own_Lock_or_Unlock [0 1 0 0 0 1 0 0 ] 2 +I Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 -S Load [0 0 4 0 0 2 0 2 ] 8 +S Load [0 0 0 0 0 0 0 0 ] 0 S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [0 0 0 0 1 2 0 1 ] 4 +S Store [0 0 0 0 0 0 0 0 ] 0 S Atomic [0 0 0 0 0 0 0 0 ] 0 -S L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -S Data_Shared [0 0 0 0 0 0 0 0 ] 0 -S Data_Owner [0 0 0 0 0 0 0 0 ] 0 +S L1_Replacement [440 427 388 415 425 398 404 415 ] 3312 +S Data_Shared [0 0 0 0 1 0 0 0 ] 1 +S Data_Owner [0 0 0 1 0 0 0 0 ] 1 S Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 S Ack [0 0 0 0 0 0 0 0 ] 0 S Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -S Transient_Local_GETX [0 0 1 0 0 0 0 0 ] 1 +S Transient_Local_GETX [0 0 1 0 0 1 1 0 ] 3 S Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -S Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +S Transient_Local_GETS [1 1 0 0 1 0 0 0 ] 3 S Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -S Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -S Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -S Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 -S Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S Transient_Local_GETS_Last_Token [0 1 1 1 1 0 3 0 ] 7 +S Persistent_GETX [0 1 1 0 1 1 0 0 ] 4 +S Persistent_GETS [0 0 0 0 0 0 1 0 ] 1 +S Persistent_GETS_Last_Token [1 0 0 0 0 0 1 2 ] 4 S Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 -O Load [7 3 2 5 1 0 9 0 ] 27 +O Load [0 0 0 0 0 0 1 0 ] 1 O Ifetch [0 0 0 0 0 0 0 0 ] 0 -O Store [3 1 1 1 0 0 1 4 ] 11 +O Store [0 0 0 0 0 1 0 0 ] 1 O Atomic [0 0 0 0 0 0 0 0 ] 0 -O L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +O L1_Replacement [326 317 337 361 348 321 336 353 ] 2699 O Data_Shared [0 0 0 0 0 0 0 0 ] 0 O Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 -O Ack [0 0 0 0 0 0 1 1 ] 2 -O Ack_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +O Ack [0 0 1 0 0 0 0 1 ] 2 +O Ack_All_Tokens [0 0 0 0 1 0 0 0 ] 1 O Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -O Transient_Local_GETX [2 5 1 1 1 2 4 0 ] 16 +O Transient_Local_GETX [0 1 1 1 0 0 0 2 ] 5 O Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -O Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +O Transient_Local_GETS [0 2 0 0 1 2 1 2 ] 8 O Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 O Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -O Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -O Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +O Persistent_GETX [0 0 0 0 1 0 0 0 ] 1 +O Persistent_GETS [1 0 2 1 1 0 1 0 ] 6 O Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -O Own_Lock_or_Unlock [4 4 1 2 1 1 4 1 ] 18 +O Own_Lock_or_Unlock [26 20 23 35 37 26 26 43 ] 236 -M Load [28 73 44 39 51 47 48 45 ] 375 +M Load [11 7 9 11 8 11 11 13 ] 81 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [22 27 20 30 34 31 25 34 ] 223 +M Store [2 5 5 6 6 4 3 3 ] 34 M Atomic [0 0 0 0 0 0 0 0 ] 0 -M L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M L1_Replacement [98109 98682 98114 98075 99009 98717 98125 98021 ] 786852 M Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -M Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +M Transient_Local_GETX [130 131 140 116 140 108 116 130 ] 1011 M Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -M Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 -M Persistent_GETX [2 2 4 1 2 1 3 3 ] 18 -M Persistent_GETS [4 4 3 1 3 5 2 3 ] 25 -M Own_Lock_or_Unlock [19 24 20 17 24 22 19 23 ] 168 +M Transient_Local_GETS [231 230 236 248 250 231 241 235 ] 1902 +M Persistent_GETX [45 48 51 39 56 63 50 53 ] 405 +M Persistent_GETS [92 89 69 81 99 97 85 88 ] 700 +M Own_Lock_or_Unlock [5953 5846 5581 5706 5728 5637 5674 5916 ] 46041 -MM Load [37560 37440 37171 37275 39797 38949 36895 37075 ] 302162 +MM Load [5 3 4 3 3 5 8 5 ] 36 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [20087 19886 19931 20132 21523 20999 19589 20207 ] 162354 +MM Store [8 1 4 3 3 2 1 5 ] 27 MM Atomic [0 0 0 0 0 0 0 0 ] 0 -MM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM L1_Replacement [53054 53040 53463 53115 53280 53218 53159 53048 ] 425377 MM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -MM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +MM Transient_Local_GETX [86 67 59 74 74 77 70 74 ] 581 MM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -MM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 -MM Persistent_GETX [2470 2470 2418 2451 2479 2469 2466 2510 ] 19733 -MM Persistent_GETS [4629 4597 4673 4592 4638 4634 4526 4607 ] 36896 -MM Own_Lock_or_Unlock [6898 6682 6801 6585 7078 6942 6691 7047 ] 54724 +MM Transient_Local_GETS [113 128 134 112 117 117 134 148 ] 1003 +MM Persistent_GETX [17 26 26 24 34 28 32 35 ] 222 +MM Persistent_GETS [57 37 37 32 62 53 44 50 ] 372 +MM Own_Lock_or_Unlock [3131 3110 3076 3014 3065 3089 3077 3111 ] 24673 -M_W Load [8494 8681 8359 8508 8736 8655 8348 8688 ] 68469 +M_W Load [0 0 1 0 0 0 1 0 ] 2 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -M_W Store [4571 4617 4577 4617 4591 4614 4605 4617 ] 36809 +M_W Store [0 0 0 0 0 0 0 0 ] 0 M_W Atomic [0 0 0 0 0 0 0 0 ] 0 -M_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_W L1_Replacement [438628 439522 436751 434652 442927 440817 438811 440017 ] 3512125 M_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -M_W Transient_Local_GETX [1166 1154 1141 1143 1201 1194 1152 1185 ] 9336 +M_W Transient_Local_GETX [21 25 21 19 20 20 17 27 ] 170 M_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -M_W Transient_Local_GETS [2166 2212 2154 2181 2163 2167 2179 2189 ] 17411 -M_W Persistent_GETX [0 1 0 1 0 0 4 0 ] 6 -M_W Persistent_GETS [0 1 0 0 0 0 2 0 ] 3 -M_W Own_Lock_or_Unlock [1 0 0 0 2 3 0 1 ] 7 -M_W Use_TimeoutStarverX [0 0 0 0 0 0 0 0 ] 0 -M_W Use_TimeoutStarverS [0 0 0 0 0 0 0 0 ] 0 -M_W Use_TimeoutNoStarvers [28 33 27 32 39 37 30 40 ] 266 +M_W Transient_Local_GETS [39 41 30 39 29 50 32 30 ] 290 +M_W Persistent_GETX [5 7 7 5 1 0 4 2 ] 31 +M_W Persistent_GETS [18 17 11 13 3 3 9 8 ] 82 +M_W Own_Lock_or_Unlock [208 253 255 216 229 259 227 245 ] 1892 +M_W Use_TimeoutStarverX [8 9 7 6 1 0 5 3 ] 39 +M_W Use_TimeoutStarverS [22 18 13 13 4 4 10 10 ] 94 +M_W Use_TimeoutNoStarvers [98609 99185 98616 98565 99559 99221 98620 98530 ] 790905 M_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 -MM_W Load [46901 46467 46766 47022 46777 46509 46835 46760 ] 374037 +MM_W Load [0 0 0 0 0 0 0 0 ] 0 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM_W Store [25226 25106 25236 24857 25022 25371 25142 24970 ] 200930 +MM_W Store [0 0 0 0 1 0 0 0 ] 1 MM_W Atomic [0 0 0 0 0 0 0 0 ] 0 -MM_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM_W L1_Replacement [238286 236813 235991 235628 235275 235170 238358 238844 ] 1894365 MM_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -MM_W Transient_Local_GETX [726 705 680 664 692 661 707 713 ] 5548 +MM_W Transient_Local_GETX [12 5 12 9 11 14 10 15 ] 88 MM_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -MM_W Transient_Local_GETS [1308 1301 1347 1301 1330 1295 1309 1253 ] 10444 -MM_W Persistent_GETX [6 17 10 26 0 6 48 0 ] 113 -MM_W Persistent_GETS [11 26 13 47 0 8 62 1 ] 168 -MM_W Own_Lock_or_Unlock [56 8 48 0 16 91 27 45 ] 291 -MM_W Use_TimeoutStarverX [6 19 10 28 0 6 54 0 ] 123 -MM_W Use_TimeoutStarverS [11 27 13 48 0 8 69 1 ] 177 -MM_W Use_TimeoutNoStarvers [7077 7040 7071 7014 7084 7072 6967 7083 ] 56408 +MM_W Transient_Local_GETS [18 20 19 24 8 14 28 19 ] 150 +MM_W Persistent_GETX [5 5 3 3 2 1 5 3 ] 27 +MM_W Persistent_GETS [6 10 7 10 1 5 10 6 ] 55 +MM_W Own_Lock_or_Unlock [124 123 114 122 121 124 142 111 ] 981 +MM_W Use_TimeoutStarverX [5 5 3 4 2 1 5 3 ] 28 +MM_W Use_TimeoutStarverS [7 12 7 12 1 5 10 7 ] 61 +MM_W Use_TimeoutNoStarvers [53325 53293 53714 53351 53561 53490 53436 53352 ] 427522 MM_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM Atomic [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM L1_Replacement [597681 600323 603709 602923 602449 597924 604184 599055 ] 4808248 IM Data_Shared [0 0 0 0 0 0 0 0 ] 0 -IM Data_Owner [1 0 1 0 0 1 0 0 ] 3 -IM Data_All_Tokens [2518 2465 2516 2471 2492 2469 2479 2461 ] 19871 -IM Ack [0 1 1 1 0 0 0 1 ] 4 +IM Data_Owner [1 1 0 0 0 1 1 0 ] 4 +IM Data_All_Tokens [53335 53307 53724 53364 53564 53494 53450 53361 ] 427599 +IM Ack [1 0 0 1 2 1 2 0 ] 7 IM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IM Transient_Local_GETX [222 216 237 258 221 212 225 232 ] 1823 +IM Transient_Local_GETX [169 190 183 191 148 179 202 176 ] 1438 IM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IM Transient_Local_GETS [400 402 434 422 408 454 399 431 ] 3350 +IM Transient_Local_GETS [354 326 324 298 288 304 326 315 ] 2535 IM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IM Persistent_GETX [4521 4513 4646 4487 4479 4548 4472 4529 ] 36195 -IM Persistent_GETS [8641 8405 8595 8462 8549 8387 8536 8357 ] 67932 +IM Persistent_GETX [79 76 100 115 61 76 80 82 ] 669 +IM Persistent_GETS [156 163 192 187 120 109 131 129 ] 1187 IM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IM Own_Lock_or_Unlock [2182 1996 2007 1984 2492 2470 2235 2406 ] 17772 -IM Request_Timeout [1799 1793 1784 1765 1766 1755 1871 1763 ] 14296 +IM Own_Lock_or_Unlock [17531 17525 17519 17502 17492 17556 17639 17671 ] 140435 +IM Request_Timeout [343584 348506 347037 343579 342498 342141 341175 341787 ] 2750307 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -574,12 +656,12 @@ SM Atomic [0 0 0 0 0 0 0 0 ] 0 SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 SM Data_Shared [0 0 0 0 0 0 0 0 ] 0 SM Data_Owner [0 0 0 0 0 0 0 0 ] 0 -SM Data_All_Tokens [2 2 0 1 1 3 2 2 ] 13 +SM Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 SM Ack [0 0 0 0 0 0 0 0 ] 0 SM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -SM Transient_Local_GETX [3 2 3 0 2 2 0 1 ] 13 +SM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 SM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -SM Transient_Local_GETS [0 0 0 0 0 2 0 0 ] 2 +SM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 SM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 SM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 SM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 @@ -596,65 +678,65 @@ OM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 OM Data_Shared [0 0 0 0 0 0 0 0 ] 0 OM Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 OM Ack [0 0 0 0 0 0 0 0 ] 0 -OM Ack_All_Tokens [3 1 1 1 0 0 1 4 ] 11 +OM Ack_All_Tokens [1 1 0 0 0 2 1 0 ] 5 OM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -OM Transient_Local_GETX [3 1 1 0 0 0 0 3 ] 8 +OM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 OM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -OM Transient_Local_GETS [0 0 0 1 0 0 0 0 ] 1 +OM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 OM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 OM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -OM Persistent_GETX [0 0 0 0 0 1 0 0 ] 1 -OM Persistent_GETS [1 0 1 0 0 0 0 0 ] 2 +OM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +OM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 OM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -OM Own_Lock_or_Unlock [0 1 0 0 0 0 0 3 ] 4 +OM Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 OM Request_Timeout [0 0 0 0 0 0 0 0 ] 0 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 IS Atomic [0 0 0 0 0 0 0 0 ] 0 -IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -IS Data_Shared [0 0 0 0 0 0 0 0 ] 0 -IS Data_Owner [5 6 2 2 1 2 5 4 ] 27 -IS Data_All_Tokens [4599 4650 4604 4647 4630 4651 4631 4657 ] 37069 +IS L1_Replacement [1116012 1121454 1116280 1115024 1127150 1126599 1111548 1112279 ] 8946346 +IS Data_Shared [325 321 306 321 322 299 309 317 ] 2520 +IS Data_Owner [96 88 104 114 101 91 96 120 ] 810 +IS Data_All_Tokens [98632 99209 98634 98583 99565 99224 98633 98541 ] 791021 IS Ack [0 0 0 0 0 0 0 0 ] 0 IS Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IS Transient_Local_GETX [400 408 389 443 408 431 429 415 ] 3323 +IS Transient_Local_GETX [289 321 356 346 311 328 306 315 ] 2572 IS Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IS Transient_Local_GETS [769 757 780 755 748 754 760 742 ] 6065 +IS Transient_Local_GETS [600 617 562 557 566 572 629 590 ] 4693 IS Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IS Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IS Persistent_GETX [8371 8439 8397 8510 8389 8397 8431 8464 ] 67398 -IS Persistent_GETS [15722 16004 15772 15880 15673 15863 15872 16008 ] 126794 +IS Persistent_GETX [144 154 162 195 131 126 125 128 ] 1165 +IS Persistent_GETS [267 274 314 319 246 229 247 263 ] 2159 IS Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IS Own_Lock_or_Unlock [3999 3732 3684 3780 4636 4659 4178 4566 ] 33234 -IS Request_Timeout [3330 3318 3254 3362 3293 3408 3544 3379 ] 26888 +IS Own_Lock_or_Unlock [32690 32804 32386 32521 32797 32862 32379 32627 ] 261066 +IS Request_Timeout [638170 648266 640666 644805 646272 643689 640188 643189 ] 5145245 -I_L Load [4602 4651 4606 4649 4629 4651 4636 4662 ] 37086 +I_L Load [217 206 207 209 206 201 188 205 ] 1639 I_L Ifetch [0 0 0 0 0 0 0 0 ] 0 -I_L Store [2516 2464 2512 2471 2490 2467 2482 2459 ] 19861 +I_L Store [94 129 146 110 128 104 134 116 ] 961 I_L Atomic [0 0 0 0 0 0 0 0 ] 0 -I_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I_L L1_Replacement [197 153 81 114 157 189 117 56 ] 1064 I_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 I_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 I_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 I_L Ack [0 0 0 0 0 0 0 0 ] 0 I_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -I_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_Local_GETX [738 698 688 726 723 711 702 691 ] 5677 I_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -I_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_Local_GETS [1228 1204 1229 1255 1231 1211 1231 1233 ] 9822 I_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 I_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I_L Persistent_GETX [29 83 67 101 1 11 63 0 ] 355 -I_L Persistent_GETS [52 140 100 186 1 27 119 0 ] 625 +I_L Persistent_GETX [124437 124391 124284 124271 124578 124495 124364 124342 ] 995162 +I_L Persistent_GETS [231075 230903 231210 231076 231220 231143 231542 231236 ] 1849405 I_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -I_L Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 +I_L Own_Lock_or_Unlock [141 138 135 119 159 152 146 153 ] 1143 -S_L Load [3 9 6 0 7 12 0 4 ] 41 +S_L Load [0 0 0 0 0 0 0 0 ] 0 S_L Ifetch [0 0 0 0 0 0 0 0 ] 0 -S_L Store [4 4 2 1 2 3 2 2 ] 20 +S_L Store [0 0 0 0 0 0 0 0 ] 0 S_L Atomic [0 0 0 0 0 0 0 0 ] 0 -S_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +S_L L1_Replacement [50 48 15 7 15 17 32 21 ] 205 S_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 S_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 S_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 @@ -666,29 +748,29 @@ S_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 S_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 S_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 S_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -S_L Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +S_L Persistent_GETS [16 14 5 13 0 0 7 6 ] 61 S_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -S_L Own_Lock_or_Unlock [0 0 1 0 1 2 0 1 ] 5 +S_L Own_Lock_or_Unlock [116 107 84 95 104 101 98 100 ] 805 IM_L Load [0 0 0 0 0 0 0 0 ] 0 IM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 IM_L Store [0 0 0 0 0 0 0 0 ] 0 IM_L Atomic [0 0 0 0 0 0 0 0 ] 0 -IM_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM_L L1_Replacement [2155 2601 3319 2489 1925 2105 2183 2242 ] 19019 IM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 IM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 -IM_L Data_All_Tokens [0 1 0 0 0 0 3 0 ] 4 +IM_L Data_All_Tokens [1 2 0 3 0 0 0 1 ] 7 IM_L Ack [0 0 0 0 0 0 0 0 ] 0 IM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IM_L Transient_Local_GETX [5265 5143 5258 5229 5111 5141 5302 5088 ] 41537 +IM_L Transient_Local_GETX [1 0 0 0 2 0 1 0 ] 4 IM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IM_L Transient_Local_GETS [9843 9650 9830 9596 9842 9666 9585 9672 ] 77684 +IM_L Transient_Local_GETS [1 0 1 1 0 2 2 2 ] 9 IM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IM_L Persistent_GETX [1517 1566 1504 1478 1373 1311 1418 1290 ] 11457 -IM_L Persistent_GETS [2742 2736 2735 2863 2483 2456 2680 2521 ] 21216 -IM_L Own_Lock_or_Unlock [15678 15381 15753 15420 15518 15403 15487 15345 ] 123985 -IM_L Request_Timeout [719 701 732 708 726 823 763 775 ] 5947 +IM_L Persistent_GETX [21 18 35 42 1 3 15 11 ] 146 +IM_L Persistent_GETS [33 57 68 63 0 6 22 29 ] 278 +IM_L Own_Lock_or_Unlock [328 366 438 409 309 289 345 326 ] 2810 +IM_L Request_Timeout [2931 3158 2730 1836 2012 1948 2127 2455 ] 19197 SM_L Load [0 0 0 0 0 0 0 0 ] 0 SM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -706,30 +788,30 @@ SM_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 SM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 SM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 SM_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 -SM_L Persistent_GETS [0 0 0 0 0 0 1 0 ] 1 +SM_L Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 SM_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -SM_L Own_Lock_or_Unlock [5 4 3 1 2 3 2 2 ] 22 +SM_L Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 SM_L Request_Timeout [0 0 0 0 0 0 0 0 ] 0 IS_L Load [0 0 0 0 0 0 0 0 ] 0 IS_L Ifetch [0 0 0 0 0 0 0 0 ] 0 IS_L Store [0 0 0 0 0 0 0 0 ] 0 IS_L Atomic [0 0 0 0 0 0 0 0 ] 0 -IS_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS_L L1_Replacement [4382 4588 4925 4941 3477 3609 3569 3621 ] 33112 IS_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 IS_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 -IS_L Data_All_Tokens [0 0 0 2 0 0 4 0 ] 6 +IS_L Data_All_Tokens [7 3 2 1 1 1 2 3 ] 20 IS_L Ack [0 0 0 0 0 0 0 0 ] 0 IS_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 -IS_L Transient_Local_GETX [9592 9799 9675 9691 9773 9788 9599 9799 ] 77716 +IS_L Transient_Local_GETX [0 1 1 2 0 0 1 2 ] 7 IS_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 -IS_L Transient_Local_GETS [18021 18133 17959 18205 17990 18119 18238 18162 ] 144827 +IS_L Transient_Local_GETS [1 0 1 0 4 0 1 2 ] 9 IS_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 IS_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 -IS_L Persistent_GETX [2765 2876 2805 2917 2676 2649 2829 2564 ] 22081 -IS_L Persistent_GETS [4930 5143 5114 5121 4743 4669 4838 4519 ] 39077 -IS_L Own_Lock_or_Unlock [28695 29094 28775 29037 28691 28911 28935 29134 ] 231272 -IS_L Request_Timeout [1299 1414 1377 1305 1337 1482 1361 1416 ] 10991 +IS_L Persistent_GETX [36 45 70 66 1 7 11 22 ] 258 +IS_L Persistent_GETS [76 76 101 118 0 10 28 56 ] 465 +IS_L Own_Lock_or_Unlock [621 631 681 722 582 555 558 593 ] 4943 +IS_L Request_Timeout [3263 3639 4943 4866 4879 4058 3993 2973 ] 32614 Cache Stats: system.l1_cntrl1.L1IcacheMemory system.l1_cntrl1.L1IcacheMemory_total_misses: 0 @@ -740,16 +822,16 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory Cache Stats: system.l1_cntrl1.L1DcacheMemory - system.l1_cntrl1.L1DcacheMemory_total_misses: 7127 - system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 7127 + system.l1_cntrl1.L1DcacheMemory_total_misses: 153113 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 153113 system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L1DcacheMemory_request_type_LD: 65.315% - system.l1_cntrl1.L1DcacheMemory_request_type_ST: 34.685% + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 65.0611% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 34.9389% - system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode: 7127 100% + system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode: 153113 100% Cache Stats: system.l1_cntrl2.L1IcacheMemory system.l1_cntrl2.L1IcacheMemory_total_misses: 0 @@ -760,16 +842,16 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory Cache Stats: system.l1_cntrl2.L1DcacheMemory - system.l1_cntrl2.L1DcacheMemory_total_misses: 7127 - system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 7127 + system.l1_cntrl2.L1DcacheMemory_total_misses: 152495 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 152495 system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L1DcacheMemory_request_type_LD: 65.1326% - system.l1_cntrl2.L1DcacheMemory_request_type_ST: 34.8674% + system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.949% + system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.051% - system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode: 7127 100% + system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode: 152495 100% Cache Stats: system.l1_cntrl3.L1IcacheMemory system.l1_cntrl3.L1IcacheMemory_total_misses: 0 @@ -780,16 +862,16 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory Cache Stats: system.l1_cntrl3.L1DcacheMemory - system.l1_cntrl3.L1DcacheMemory_total_misses: 7130 - system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 7130 + system.l1_cntrl3.L1DcacheMemory_total_misses: 152346 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 152346 system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L1DcacheMemory_request_type_LD: 65.3997% - system.l1_cntrl3.L1DcacheMemory_request_type_ST: 34.6003% + system.l1_cntrl3.L1DcacheMemory_request_type_LD: 64.9718% + system.l1_cntrl3.L1DcacheMemory_request_type_ST: 35.0282% - system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode: 7130 100% + system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode: 152346 100% Cache Stats: system.l1_cntrl4.L1IcacheMemory system.l1_cntrl4.L1IcacheMemory_total_misses: 0 @@ -800,16 +882,16 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory Cache Stats: system.l1_cntrl4.L1DcacheMemory - system.l1_cntrl4.L1DcacheMemory_total_misses: 7129 - system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 7129 + system.l1_cntrl4.L1DcacheMemory_total_misses: 152401 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 152401 system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.5953% - system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.4047% + system.l1_cntrl4.L1DcacheMemory_request_type_LD: 65.0015% + system.l1_cntrl4.L1DcacheMemory_request_type_ST: 34.9985% - system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode: 7129 100% + system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode: 152401 100% Cache Stats: system.l1_cntrl5.L1IcacheMemory system.l1_cntrl5.L1IcacheMemory_total_misses: 0 @@ -820,16 +902,16 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory Cache Stats: system.l1_cntrl5.L1DcacheMemory - system.l1_cntrl5.L1DcacheMemory_total_misses: 7127 - system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 7127 + system.l1_cntrl5.L1DcacheMemory_total_misses: 152935 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 152935 system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L1DcacheMemory_request_type_LD: 65.3431% - system.l1_cntrl5.L1DcacheMemory_request_type_ST: 34.6569% + system.l1_cntrl5.L1DcacheMemory_request_type_LD: 65.1414% + system.l1_cntrl5.L1DcacheMemory_request_type_ST: 34.8586% - system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode: 7127 100% + system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode: 152935 100% Cache Stats: system.l1_cntrl6.L1IcacheMemory system.l1_cntrl6.L1IcacheMemory_total_misses: 0 @@ -840,16 +922,16 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory Cache Stats: system.l1_cntrl6.L1DcacheMemory - system.l1_cntrl6.L1DcacheMemory_total_misses: 7125 - system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 7125 + system.l1_cntrl6.L1DcacheMemory_total_misses: 152773 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 152773 system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.6737% - system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.3263% + system.l1_cntrl6.L1DcacheMemory_request_type_LD: 64.8334% + system.l1_cntrl6.L1DcacheMemory_request_type_ST: 35.1666% - system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode: 7125 100% + system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode: 152773 100% Cache Stats: system.l1_cntrl7.L1IcacheMemory system.l1_cntrl7.L1IcacheMemory_total_misses: 0 @@ -860,63 +942,63 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory Cache Stats: system.l1_cntrl7.L1DcacheMemory - system.l1_cntrl7.L1DcacheMemory_total_misses: 7125 - system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 7125 + system.l1_cntrl7.L1DcacheMemory_total_misses: 152390 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 152390 system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L1DcacheMemory_request_type_LD: 65.2772% - system.l1_cntrl7.L1DcacheMemory_request_type_ST: 34.7228% + system.l1_cntrl7.L1DcacheMemory_request_type_LD: 64.98% + system.l1_cntrl7.L1DcacheMemory_request_type_ST: 35.02% - system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode: 7125 100% + system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode: 152390 100% Cache Stats: system.l2_cntrl0.L2cacheMemory - system.l2_cntrl0.L2cacheMemory_total_misses: 57015 - system.l2_cntrl0.L2cacheMemory_total_demand_misses: 57015 + system.l2_cntrl0.L2cacheMemory_total_misses: 1221063 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1221063 system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_request_type_GETS: 65.0916% - system.l2_cntrl0.L2cacheMemory_request_type_GETX: 34.9084% + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 65.0075% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 34.9925% - system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 57015 100% + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1221063 100% --- L2Cache --- - Event Counts - -L1_GETS [37112 ] 37112 +L1_GETS [794391 ] 794391 L1_GETS_Last_Token [0 ] 0 -L1_GETX [19903 ] 19903 -L1_INV [56964 ] 56964 +L1_GETX [427616 ] 427616 +L1_INV [3735 ] 3735 Transient_GETX [0 ] 0 Transient_GETS [0 ] 0 Transient_GETS_Last_Token [0 ] 0 -L2_Replacement [0 ] 0 +L2_Replacement [1216001 ] 1216001 Writeback_Tokens [0 ] 0 -Writeback_Shared_Data [0 ] 0 -Writeback_All_Tokens [0 ] 0 -Writeback_Owned [0 ] 0 +Writeback_Shared_Data [3090 ] 3090 +Writeback_All_Tokens [1212600 ] 1212600 +Writeback_Owned [2549 ] 2549 Data_Shared [0 ] 0 Data_Owner [0 ] 0 Data_All_Tokens [0 ] 0 Ack [0 ] 0 Ack_All_Tokens [0 ] 0 -Persistent_GETX [22460 ] 22460 -Persistent_GETS [41771 ] 41771 -Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [49719 ] 49719 +Persistent_GETX [142586 ] 142586 +Persistent_GETS [264969 ] 264969 +Persistent_GETS_Last_Token [1 ] 1 +Own_Lock_or_Unlock [403116 ] 403116 - Transitions - -NP L1_GETS [26 ] 26 -NP L1_GETX [27 ] 27 -NP L1_INV [17 ] 17 +NP L1_GETS [792143 ] 792143 +NP L1_GETX [426330 ] 426330 +NP L1_INV [2602 ] 2602 NP Transient_GETX [0 ] 0 NP Transient_GETS [0 ] 0 NP Writeback_Tokens [0 ] 0 -NP Writeback_Shared_Data [0 ] 0 -NP Writeback_All_Tokens [0 ] 0 -NP Writeback_Owned [0 ] 0 +NP Writeback_Shared_Data [3088 ] 3088 +NP Writeback_All_Tokens [1210366 ] 1210366 +NP Writeback_Owned [2549 ] 2549 NP Data_Shared [0 ] 0 NP Data_Owner [0 ] 0 NP Data_All_Tokens [0 ] 0 @@ -924,19 +1006,19 @@ NP Ack [0 ] 0 NP Persistent_GETX [0 ] 0 NP Persistent_GETS [0 ] 0 NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [49719 ] 49719 +NP Own_Lock_or_Unlock [403006 ] 403006 I L1_GETS [0 ] 0 I L1_GETS_Last_Token [0 ] 0 I L1_GETX [0 ] 0 -I L1_INV [0 ] 0 +I L1_INV [1 ] 1 I Transient_GETX [0 ] 0 I Transient_GETS [0 ] 0 I Transient_GETS_Last_Token [0 ] 0 -I L2_Replacement [0 ] 0 +I L2_Replacement [394 ] 394 I Writeback_Tokens [0 ] 0 I Writeback_Shared_Data [0 ] 0 -I Writeback_All_Tokens [0 ] 0 +I Writeback_All_Tokens [54 ] 54 I Writeback_Owned [0 ] 0 I Data_Shared [0 ] 0 I Data_Owner [0 ] 0 @@ -949,15 +1031,15 @@ I Own_Lock_or_Unlock [0 ] 0 S L1_GETS [0 ] 0 S L1_GETS_Last_Token [0 ] 0 -S L1_GETX [0 ] 0 +S L1_GETX [2 ] 2 S L1_INV [0 ] 0 S Transient_GETX [0 ] 0 S Transient_GETS [0 ] 0 S Transient_GETS_Last_Token [0 ] 0 -S L2_Replacement [0 ] 0 +S L2_Replacement [2935 ] 2935 S Writeback_Tokens [0 ] 0 -S Writeback_Shared_Data [0 ] 0 -S Writeback_All_Tokens [0 ] 0 +S Writeback_Shared_Data [1 ] 1 +S Writeback_All_Tokens [150 ] 150 S Writeback_Owned [0 ] 0 S Data_Shared [0 ] 0 S Data_Owner [0 ] 0 @@ -965,20 +1047,20 @@ S Data_All_Tokens [0 ] 0 S Ack [0 ] 0 S Persistent_GETX [0 ] 0 S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [0 ] 0 +S Persistent_GETS_Last_Token [1 ] 1 S Own_Lock_or_Unlock [0 ] 0 -O L1_GETS [0 ] 0 +O L1_GETS [1 ] 1 O L1_GETS_Last_Token [0 ] 0 O L1_GETX [0 ] 0 O L1_INV [0 ] 0 O Transient_GETX [0 ] 0 O Transient_GETS [0 ] 0 O Transient_GETS_Last_Token [0 ] 0 -O L2_Replacement [0 ] 0 +O L2_Replacement [2934 ] 2934 O Writeback_Tokens [0 ] 0 -O Writeback_Shared_Data [0 ] 0 -O Writeback_All_Tokens [0 ] 0 +O Writeback_Shared_Data [1 ] 1 +O Writeback_All_Tokens [222 ] 222 O Data_Shared [0 ] 0 O Data_All_Tokens [0 ] 0 O Ack [0 ] 0 @@ -988,34 +1070,34 @@ O Persistent_GETS [0 ] 0 O Persistent_GETS_Last_Token [0 ] 0 O Own_Lock_or_Unlock [0 ] 0 -M L1_GETS [0 ] 0 -M L1_GETX [0 ] 0 +M L1_GETS [607 ] 607 +M L1_GETX [336 ] 336 M L1_INV [0 ] 0 M Transient_GETX [0 ] 0 M Transient_GETS [0 ] 0 -M L2_Replacement [0 ] 0 -M Persistent_GETX [0 ] 0 -M Persistent_GETS [0 ] 0 +M L2_Replacement [1209281 ] 1209281 +M Persistent_GETX [208 ] 208 +M Persistent_GETS [358 ] 358 M Own_Lock_or_Unlock [0 ] 0 -I_L L1_GETS [37086 ] 37086 -I_L L1_GETX [19876 ] 19876 -I_L L1_INV [56947 ] 56947 +I_L L1_GETS [1640 ] 1640 +I_L L1_GETX [948 ] 948 +I_L L1_INV [1132 ] 1132 I_L Transient_GETX [0 ] 0 I_L Transient_GETS [0 ] 0 I_L Transient_GETS_Last_Token [0 ] 0 -I_L L2_Replacement [0 ] 0 +I_L L2_Replacement [456 ] 456 I_L Writeback_Tokens [0 ] 0 I_L Writeback_Shared_Data [0 ] 0 -I_L Writeback_All_Tokens [0 ] 0 +I_L Writeback_All_Tokens [1808 ] 1808 I_L Writeback_Owned [0 ] 0 I_L Data_Shared [0 ] 0 I_L Data_Owner [0 ] 0 I_L Data_All_Tokens [0 ] 0 I_L Ack [0 ] 0 -I_L Persistent_GETX [22460 ] 22460 -I_L Persistent_GETS [41771 ] 41771 -I_L Own_Lock_or_Unlock [0 ] 0 +I_L Persistent_GETX [142378 ] 142378 +I_L Persistent_GETS [264611 ] 264611 +I_L Own_Lock_or_Unlock [110 ] 110 S_L L1_GETS [0 ] 0 S_L L1_GETS_Last_Token [0 ] 0 @@ -1024,7 +1106,7 @@ S_L L1_INV [0 ] 0 S_L Transient_GETX [0 ] 0 S_L Transient_GETS [0 ] 0 S_L Transient_GETS_Last_Token [0 ] 0 -S_L L2_Replacement [0 ] 0 +S_L L2_Replacement [1 ] 1 S_L Writeback_Tokens [0 ] 0 S_L Writeback_Shared_Data [0 ] 0 S_L Writeback_All_Tokens [0 ] 0 @@ -1039,93 +1121,93 @@ S_L Persistent_GETS_Last_Token [0 ] 0 S_L Own_Lock_or_Unlock [0 ] 0 Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 2 - memory_reads: 2 - memory_writes: 0 - memory_refreshes: 22 - memory_total_request_delays: 31 - memory_delays_per_request: 15.5 - memory_delays_in_input_queue: 1 - memory_delays_behind_head_of_bank_queue: 10 - memory_delays_stalled_at_head_of_bank_queue: 20 - memory_stalls_for_bank_busy: 20 + memory_total_requests: 1638489 + memory_reads: 1212126 + memory_writes: 426322 + memory_refreshes: 81456 + memory_total_request_delays: 99459030 + memory_delays_per_request: 60.7017 + memory_delays_in_input_queue: 1167381 + memory_delays_behind_head_of_bank_queue: 40964968 + memory_delays_stalled_at_head_of_bank_queue: 57326681 + memory_stalls_for_bank_busy: 8863977 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 0 - memory_stalls_for_bus: 0 + memory_stalls_for_anti_starvation: 13706459 + memory_stalls_for_arbitration: 11848502 + memory_stalls_for_bus: 16081023 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 0 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + memory_stalls_for_read_write_turnaround: 4050192 + memory_stalls_for_read_read_turnaround: 2776528 + accesses_per_bank: 51563 51247 51111 51262 51307 51641 51526 50922 51422 51315 51572 51160 51192 51249 51125 50854 51329 50999 51574 51128 51109 51142 51061 51073 51213 50871 50957 50802 51227 51032 51458 51046 --- Directory --- - Event Counts - -GETX [19962 ] 19962 -GETS [37458 ] 37458 -Lockdown [64231 ] 64231 -Unlockdown [49719 ] 49719 +GETX [781168 ] 781168 +GETS [1437822 ] 1437822 +Lockdown [407556 ] 407556 +Unlockdown [403116 ] 403116 Own_Lock_or_Unlock [0 ] 0 Own_Lock_or_Unlock_Tokens [0 ] 0 -Data_Owner [0 ] 0 -Data_All_Tokens [0 ] 0 -Ack_Owner [0 ] 0 -Ack_Owner_All_Tokens [0 ] 0 -Tokens [0 ] 0 -Ack_All_Tokens [0 ] 0 +Data_Owner [217 ] 217 +Data_All_Tokens [426161 ] 426161 +Ack_Owner [1520 ] 1520 +Ack_Owner_All_Tokens [784319 ] 784319 +Tokens [1303 ] 1303 +Ack_All_Tokens [15697 ] 15697 Request_Timeout [0 ] 0 -Memory_Data [2 ] 2 -Memory_Ack [0 ] 0 +Memory_Data [1212121 ] 1212121 +Memory_Ack [426322 ] 426322 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX [0 ] 0 -O GETS [2 ] 2 -O Lockdown [0 ] 0 +O GETX [420963 ] 420963 +O GETS [782334 ] 782334 +O Lockdown [5301 ] 5301 O Unlockdown [0 ] 0 O Own_Lock_or_Unlock [0 ] 0 O Own_Lock_or_Unlock_Tokens [0 ] 0 O Data_Owner [0 ] 0 O Data_All_Tokens [0 ] 0 -O Tokens [0 ] 0 -O Ack_All_Tokens [0 ] 0 +O Tokens [5 ] 5 +O Ack_All_Tokens [1720 ] 1720 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 O DMA_WRITE_All_Tokens [0 ] 0 -NO GETX [42 ] 42 -NO GETS [24 ] 24 -NO Lockdown [49719 ] 49719 +NO GETX [3484 ] 3484 +NO GETS [6315 ] 6315 +NO Lockdown [13581 ] 13581 NO Unlockdown [0 ] 0 NO Own_Lock_or_Unlock [0 ] 0 NO Own_Lock_or_Unlock_Tokens [0 ] 0 -NO Data_Owner [0 ] 0 -NO Data_All_Tokens [0 ] 0 -NO Ack_Owner [0 ] 0 -NO Ack_Owner_All_Tokens [0 ] 0 -NO Tokens [0 ] 0 +NO Data_Owner [217 ] 217 +NO Data_All_Tokens [426126 ] 426126 +NO Ack_Owner [1518 ] 1518 +NO Ack_Owner_All_Tokens [784251 ] 784251 +NO Tokens [1211 ] 1211 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 -L GETX [19861 ] 19861 -L GETS [37086 ] 37086 -L Lockdown [14512 ] 14512 -L Unlockdown [49719 ] 49719 +L GETX [2833 ] 2833 +L GETS [5134 ] 5134 +L Lockdown [2527 ] 2527 +L Unlockdown [403116 ] 403116 L Own_Lock_or_Unlock [0 ] 0 L Own_Lock_or_Unlock_Tokens [0 ] 0 L Data_Owner [0 ] 0 -L Data_All_Tokens [0 ] 0 -L Ack_Owner [0 ] 0 -L Ack_Owner_All_Tokens [0 ] 0 -L Tokens [0 ] 0 +L Data_All_Tokens [35 ] 35 +L Ack_Owner [2 ] 2 +L Ack_Owner_All_Tokens [68 ] 68 +L Tokens [6 ] 6 L DMA_READ [0 ] 0 L DMA_WRITE [0 ] 0 L DMA_WRITE_All_Tokens [0 ] 0 -O_W GETX [0 ] 0 -O_W GETS [0 ] 0 -O_W Lockdown [0 ] 0 +O_W GETX [88763 ] 88763 +O_W GETS [164639 ] 164639 +O_W Lockdown [3548 ] 3548 O_W Unlockdown [0 ] 0 O_W Own_Lock_or_Unlock [0 ] 0 O_W Own_Lock_or_Unlock_Tokens [0 ] 0 @@ -1133,16 +1215,16 @@ O_W Data_Owner [0 ] 0 O_W Data_All_Tokens [0 ] 0 O_W Ack_Owner [0 ] 0 O_W Tokens [0 ] 0 -O_W Ack_All_Tokens [0 ] 0 +O_W Ack_All_Tokens [13339 ] 13339 O_W Memory_Data [0 ] 0 -O_W Memory_Ack [0 ] 0 +O_W Memory_Ack [422774 ] 422774 O_W DMA_READ [0 ] 0 O_W DMA_WRITE [0 ] 0 O_W DMA_WRITE_All_Tokens [0 ] 0 -L_O_W GETX [0 ] 0 -L_O_W GETS [0 ] 0 -L_O_W Lockdown [0 ] 0 +L_O_W GETX [78820 ] 78820 +L_O_W GETS [141705 ] 141705 +L_O_W Lockdown [91 ] 91 L_O_W Unlockdown [0 ] 0 L_O_W Own_Lock_or_Unlock [0 ] 0 L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 @@ -1150,16 +1232,16 @@ L_O_W Data_Owner [0 ] 0 L_O_W Data_All_Tokens [0 ] 0 L_O_W Ack_Owner [0 ] 0 L_O_W Tokens [0 ] 0 -L_O_W Ack_All_Tokens [0 ] 0 -L_O_W Memory_Data [0 ] 0 -L_O_W Memory_Ack [0 ] 0 +L_O_W Ack_All_Tokens [349 ] 349 +L_O_W Memory_Data [8849 ] 8849 +L_O_W Memory_Ack [3548 ] 3548 L_O_W DMA_READ [0 ] 0 L_O_W DMA_WRITE [0 ] 0 L_O_W DMA_WRITE_All_Tokens [0 ] 0 -L_NO_W GETX [0 ] 0 -L_NO_W GETS [0 ] 0 -L_NO_W Lockdown [0 ] 0 +L_NO_W GETX [88353 ] 88353 +L_NO_W GETS [158940 ] 158940 +L_NO_W Lockdown [1816 ] 1816 L_NO_W Unlockdown [0 ] 0 L_NO_W Own_Lock_or_Unlock [0 ] 0 L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 @@ -1167,8 +1249,8 @@ L_NO_W Data_Owner [0 ] 0 L_NO_W Data_All_Tokens [0 ] 0 L_NO_W Ack_Owner [0 ] 0 L_NO_W Tokens [0 ] 0 -L_NO_W Ack_All_Tokens [0 ] 0 -L_NO_W Memory_Data [0 ] 0 +L_NO_W Ack_All_Tokens [54 ] 54 +L_NO_W Memory_Data [380687 ] 380687 L_NO_W DMA_READ [0 ] 0 L_NO_W DMA_WRITE [0 ] 0 L_NO_W DMA_WRITE_All_Tokens [0 ] 0 @@ -1207,18 +1289,18 @@ DW_L_W DMA_READ [0 ] 0 DW_L_W DMA_WRITE [0 ] 0 DW_L_W DMA_WRITE_All_Tokens [0 ] 0 -NO_W GETX [59 ] 59 -NO_W GETS [346 ] 346 -NO_W Lockdown [0 ] 0 +NO_W GETX [97952 ] 97952 +NO_W GETS [178755 ] 178755 +NO_W Lockdown [380692 ] 380692 NO_W Unlockdown [0 ] 0 NO_W Own_Lock_or_Unlock [0 ] 0 NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 NO_W Data_Owner [0 ] 0 NO_W Data_All_Tokens [0 ] 0 NO_W Ack_Owner [0 ] 0 -NO_W Tokens [0 ] 0 -NO_W Ack_All_Tokens [0 ] 0 -NO_W Memory_Data [2 ] 2 +NO_W Tokens [81 ] 81 +NO_W Ack_All_Tokens [235 ] 235 +NO_W Memory_Data [822585 ] 822585 NO_W DMA_READ [0 ] 0 NO_W DMA_WRITE [0 ] 0 NO_W DMA_WRITE_All_Tokens [0 ] 0 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr index 36afc005b..f35d10727 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr @@ -1,74 +1,74 @@ -system.cpu0: completed 10000 read accesses @257947 -system.cpu1: completed 10000 read accesses @260311 -system.cpu3: completed 10000 read accesses @264703 -system.cpu7: completed 10000 read accesses @266036 -system.cpu5: completed 10000 read accesses @266378 -system.cpu4: completed 10000 read accesses @267169 -system.cpu2: completed 10000 read accesses @267625 -system.cpu6: completed 10000 read accesses @271366 -system.cpu0: completed 20000 read accesses @515410 -system.cpu1: completed 20000 read accesses @519078 -system.cpu7: completed 20000 read accesses @528562 -system.cpu3: completed 20000 read accesses @529556 -system.cpu5: completed 20000 read accesses @531753 -system.cpu4: completed 20000 read accesses @536204 -system.cpu6: completed 20000 read accesses @537031 -system.cpu2: completed 20000 read accesses @537314 -system.cpu0: completed 30000 read accesses @772994 -system.cpu1: completed 30000 read accesses @780923 -system.cpu3: completed 30000 read accesses @794263 -system.cpu7: completed 30000 read accesses @796675 -system.cpu4: completed 30000 read accesses @797063 -system.cpu5: completed 30000 read accesses @800026 -system.cpu2: completed 30000 read accesses @802601 -system.cpu6: completed 30000 read accesses @805267 -system.cpu0: completed 40000 read accesses @1033304 -system.cpu1: completed 40000 read accesses @1040457 -system.cpu3: completed 40000 read accesses @1058903 -system.cpu7: completed 40000 read accesses @1062178 -system.cpu5: completed 40000 read accesses @1064117 -system.cpu4: completed 40000 read accesses @1065423 -system.cpu6: completed 40000 read accesses @1066744 -system.cpu2: completed 40000 read accesses @1068649 -system.cpu0: completed 50000 read accesses @1292512 -system.cpu1: completed 50000 read accesses @1299935 -system.cpu3: completed 50000 read accesses @1324981 -system.cpu5: completed 50000 read accesses @1327818 -system.cpu7: completed 50000 read accesses @1328780 -system.cpu4: completed 50000 read accesses @1329164 -system.cpu6: completed 50000 read accesses @1332786 -system.cpu2: completed 50000 read accesses @1334645 -system.cpu0: completed 60000 read accesses @1550153 -system.cpu1: completed 60000 read accesses @1559435 -system.cpu7: completed 60000 read accesses @1591474 -system.cpu3: completed 60000 read accesses @1593078 -system.cpu4: completed 60000 read accesses @1594642 -system.cpu5: completed 60000 read accesses @1595392 -system.cpu2: completed 60000 read accesses @1600002 -system.cpu6: completed 60000 read accesses @1600595 -system.cpu0: completed 70000 read accesses @1802423 -system.cpu1: completed 70000 read accesses @1829858 -system.cpu7: completed 70000 read accesses @1853648 -system.cpu5: completed 70000 read accesses @1854214 -system.cpu3: completed 70000 read accesses @1854818 -system.cpu4: completed 70000 read accesses @1855726 -system.cpu6: completed 70000 read accesses @1868528 -system.cpu2: completed 70000 read accesses @1875446 -system.cpu0: completed 80000 read accesses @2061056 -system.cpu1: completed 80000 read accesses @2090957 -system.cpu7: completed 80000 read accesses @2119055 -system.cpu4: completed 80000 read accesses @2119432 -system.cpu5: completed 80000 read accesses @2121677 -system.cpu3: completed 80000 read accesses @2123217 -system.cpu6: completed 80000 read accesses @2133942 -system.cpu2: completed 80000 read accesses @2139530 -system.cpu0: completed 90000 read accesses @2322313 -system.cpu1: completed 90000 read accesses @2351193 -system.cpu4: completed 90000 read accesses @2382901 -system.cpu7: completed 90000 read accesses @2384445 -system.cpu5: completed 90000 read accesses @2387842 -system.cpu3: completed 90000 read accesses @2390630 -system.cpu6: completed 90000 read accesses @2400244 -system.cpu2: completed 90000 read accesses @2403389 -system.cpu0: completed 100000 read accesses @2583072 +system.cpu5: completed 10000 read accesses @3921160 +system.cpu1: completed 10000 read accesses @3925580 +system.cpu0: completed 10000 read accesses @3934400 +system.cpu2: completed 10000 read accesses @3939680 +system.cpu3: completed 10000 read accesses @3944050 +system.cpu6: completed 10000 read accesses @3950830 +system.cpu7: completed 10000 read accesses @3958280 +system.cpu4: completed 10000 read accesses @3974010 +system.cpu0: completed 20000 read accesses @7820430 +system.cpu5: completed 20000 read accesses @7822630 +system.cpu1: completed 20000 read accesses @7842540 +system.cpu2: completed 20000 read accesses @7858630 +system.cpu3: completed 20000 read accesses @7865210 +system.cpu4: completed 20000 read accesses @7866290 +system.cpu6: completed 20000 read accesses @7899300 +system.cpu7: completed 20000 read accesses @7926330 +system.cpu0: completed 30000 read accesses @11730870 +system.cpu1: completed 30000 read accesses @11752380 +system.cpu5: completed 30000 read accesses @11754100 +system.cpu4: completed 30000 read accesses @11817260 +system.cpu3: completed 30000 read accesses @11833290 +system.cpu2: completed 30000 read accesses @11849820 +system.cpu6: completed 30000 read accesses @11858520 +system.cpu7: completed 30000 read accesses @11878780 +system.cpu1: completed 40000 read accesses @15666470 +system.cpu0: completed 40000 read accesses @15689570 +system.cpu5: completed 40000 read accesses @15693470 +system.cpu3: completed 40000 read accesses @15770740 +system.cpu2: completed 40000 read accesses @15801030 +system.cpu4: completed 40000 read accesses @15802680 +system.cpu6: completed 40000 read accesses @15812300 +system.cpu7: completed 40000 read accesses @15814020 +system.cpu0: completed 50000 read accesses @19587160 +system.cpu1: completed 50000 read accesses @19609890 +system.cpu5: completed 50000 read accesses @19679290 +system.cpu3: completed 50000 read accesses @19706240 +system.cpu6: completed 50000 read accesses @19738150 +system.cpu2: completed 50000 read accesses @19790350 +system.cpu4: completed 50000 read accesses @19793110 +system.cpu7: completed 50000 read accesses @19826670 +system.cpu0: completed 60000 read accesses @23442420 +system.cpu1: completed 60000 read accesses @23506570 +system.cpu5: completed 60000 read accesses @23555050 +system.cpu3: completed 60000 read accesses @23640540 +system.cpu6: completed 60000 read accesses @23651620 +system.cpu4: completed 60000 read accesses @23764590 +system.cpu2: completed 60000 read accesses @23767160 +system.cpu7: completed 60000 read accesses @23798150 +system.cpu0: completed 70000 read accesses @27346650 +system.cpu1: completed 70000 read accesses @27417040 +system.cpu5: completed 70000 read accesses @27459850 +system.cpu3: completed 70000 read accesses @27568910 +system.cpu7: completed 70000 read accesses @27679260 +system.cpu4: completed 70000 read accesses @27695210 +system.cpu2: completed 70000 read accesses @27695820 +system.cpu6: completed 70000 read accesses @27700350 +system.cpu0: completed 80000 read accesses @31228160 +system.cpu5: completed 80000 read accesses @31278826 +system.cpu1: completed 80000 read accesses @31322150 +system.cpu3: completed 80000 read accesses @31508190 +system.cpu2: completed 80000 read accesses @31596330 +system.cpu6: completed 80000 read accesses @31639000 +system.cpu4: completed 80000 read accesses @31655530 +system.cpu7: completed 80000 read accesses @31659000 +system.cpu0: completed 90000 read accesses @35134550 +system.cpu5: completed 90000 read accesses @35282690 +system.cpu1: completed 90000 read accesses @35298090 +system.cpu2: completed 90000 read accesses @35490890 +system.cpu3: completed 90000 read accesses @35500970 +system.cpu6: completed 90000 read accesses @35564170 +system.cpu7: completed 90000 read accesses @35589110 +system.cpu4: completed 90000 read accesses @35604290 +system.cpu0: completed 100000 read accesses @39098820 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index 333832488..82b662fad 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 20 2010 12:14:24 -M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates -M5 started Aug 20 2010 12:14:33 -M5 executing on SC2B0629 +M5 compiled Feb 8 2011 17:50:56 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:51:05 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2583072 because maximum number of loads reached +Exiting @ tick 39098820 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index a96eed002..648e2acef 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 341980 # Number of bytes of host memory used -host_seconds 25.58 # Real time elapsed on the host -host_tick_rate 100993 # Simulator tick rate (ticks/s) +host_mem_usage 346136 # Number of bytes of host memory used +host_seconds 306.11 # Real time elapsed on the host +host_tick_rate 127726 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.002583 # Number of seconds simulated -sim_ticks 2583072 # Number of ticks simulated +sim_seconds 0.039099 # Number of seconds simulated +sim_ticks 39098820 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 53663 # number of write accesses completed +system.cpu0.num_writes 53574 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98827 # number of read accesses completed -system.cpu1.num_writes 53487 # number of write accesses completed +system.cpu1.num_reads 99631 # number of read accesses completed +system.cpu1.num_writes 53502 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 96775 # number of read accesses completed -system.cpu2.num_writes 51846 # number of write accesses completed +system.cpu2.num_reads 99061 # number of read accesses completed +system.cpu2.num_writes 53455 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 97235 # number of read accesses completed -system.cpu3.num_writes 52295 # number of write accesses completed +system.cpu3.num_reads 98999 # number of read accesses completed +system.cpu3.num_writes 53370 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 97597 # number of read accesses completed -system.cpu4.num_writes 52429 # number of write accesses completed +system.cpu4.num_reads 99076 # number of read accesses completed +system.cpu4.num_writes 53347 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 97329 # number of read accesses completed -system.cpu5.num_writes 52105 # number of write accesses completed +system.cpu5.num_reads 99631 # number of read accesses completed +system.cpu5.num_writes 53316 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 96958 # number of read accesses completed -system.cpu6.num_writes 52281 # number of write accesses completed +system.cpu6.num_reads 99060 # number of read accesses completed +system.cpu6.num_writes 53733 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 97500 # number of read accesses completed -system.cpu7.num_writes 52109 # number of write accesses completed +system.cpu7.num_reads 99033 # number of read accesses completed +system.cpu7.num_writes 53376 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini index 1464a2cc5..a9fd7817d 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.cpu0] type=MemTest @@ -142,6 +151,7 @@ type=Directory_Controller children=directory memBuffer probeFilter buffer_size=0 directory=system.dir_cntrl0.directory +full_bit_dir_enabled=false memBuffer=system.dir_cntrl0.memBuffer memory_controller_latency=2 number_of_TBEs=256 @@ -538,10 +548,9 @@ port=system.ruby.cpu_ruby_ports0.physMemPort system.ruby.cpu_ruby_ports1.physMem [system.ruby] type=RubySystem -children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 debug network profiler tracer +children=cpu_ruby_ports0 cpu_ruby_ports1 cpu_ruby_ports2 cpu_ruby_ports3 cpu_ruby_ports4 cpu_ruby_ports5 cpu_ruby_ports6 cpu_ruby_ports7 network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -553,8 +562,9 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports0] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl0.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl0.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -565,8 +575,9 @@ port=system.cpu0.test [system.ruby.cpu_ruby_ports1] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl1.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl1.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -577,8 +588,9 @@ port=system.cpu1.test [system.ruby.cpu_ruby_ports2] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl2.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl2.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -589,8 +601,9 @@ port=system.cpu2.test [system.ruby.cpu_ruby_ports3] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl3.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl3.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -601,8 +614,9 @@ port=system.cpu3.test [system.ruby.cpu_ruby_ports4] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl4.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl4.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -613,8 +627,9 @@ port=system.cpu4.test [system.ruby.cpu_ruby_ports5] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl5.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl5.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -625,8 +640,9 @@ port=system.cpu5.test [system.ruby.cpu_ruby_ports6] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl6.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl6.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -637,8 +653,9 @@ port=system.cpu6.test [system.ruby.cpu_ruby_ports7] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl7.L1DcacheMemory -deadlock_threshold=500000 +deadlock_threshold=1000000 icache=system.l1_cntrl7.L1IcacheMemory max_outstanding_requests=16 physmem=system.physmem @@ -647,14 +664,6 @@ version=7 physMemPort=system.physmem.port[7] port=system.cpu7.test -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - [system.ruby.network] type=SimpleNetwork children=topology diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index dfe8adee6..c229c1989 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -34,29 +34,29 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/20/2010 12:18:32 +Real time: Feb/08/2011 18:01:10 Profiler Stats -------------- -Elapsed_time_in_seconds: 37 -Elapsed_time_in_minutes: 0.616667 -Elapsed_time_in_hours: 0.0102778 -Elapsed_time_in_days: 0.000428241 +Elapsed_time_in_seconds: 247 +Elapsed_time_in_minutes: 4.11667 +Elapsed_time_in_hours: 0.0686111 +Elapsed_time_in_days: 0.0028588 -Virtual_time_in_seconds: 37.71 -Virtual_time_in_minutes: 0.6285 -Virtual_time_in_hours: 0.010475 -Virtual_time_in_days: 0.000436458 +Virtual_time_in_seconds: 247.89 +Virtual_time_in_minutes: 4.1315 +Virtual_time_in_hours: 0.0688583 +Virtual_time_in_days: 0.0028691 -Ruby_current_time: 3305503 +Ruby_current_time: 38059429 Ruby_start_time: 0 -Ruby_cycles: 3305503 +Ruby_cycles: 38059429 -mbytes_resident: 32.625 -mbytes_total: 333.629 -resident_ratio: 0.0978 +mbytes_resident: 35.4062 +mbytes_total: 337.344 +resident_ratio: 0.104968 -ruby_cycles_executed: [ 3305504 3305504 3305504 3305504 3305504 3305504 3305504 3305504 ] +ruby_cycles_executed: [ 38059430 38059430 38059430 38059430 38059430 38059430 38059430 38059430 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -66,31 +66,35 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1224677 average: 1.93738 | standard deviation: 0.24228 | 0 76690 1147987 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1223364 average: 15.9992 | standard deviation: 0.0900488 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 1223244 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 4 max: 483 count: 1224663 average: 41.1802 | standard deviation: 90.1625 | 1000304 0 0 0 0 0 0 0 6153 60 85 52 149 1426 9888 229 0 0 572 595 290 916 294 780 5824 6926 6 0 11 144 538 3682 460 712 2357 12424 1629 9 41 253 572 4554 4085 507 1149 7444 10678 75 147 594 775 4858 7475 253 438 2186 15528 2862 457 1243 2695 3028 7005 1742 123 584 7531 13604 1274 2218 3513 2277 4986 1770 33 219 2917 25781 7533 2700 2830 2319 1154 849 55 5 64 970 1708 10 0 0 0 0 0 1 2 61 362 19 1 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 4 max: 483 count: 795679 average: 22.1087 | standard deviation: 64.9617 | 711546 0 0 0 0 0 0 0 0 0 0 3 81 1318 9716 42 0 0 0 0 0 0 32 322 5158 5628 0 0 0 0 0 1 4 86 1323 9630 98 0 0 0 0 0 0 19 331 5123 5558 6 0 0 0 0 1 3 85 1256 9749 175 0 0 0 0 1 2 25 315 5232 6189 3 0 0 0 0 0 7 127 1898 14203 370 0 0 0 6 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 4 max: 442 count: 428984 average: 76.5539 | standard deviation: 115.993 | 288758 0 0 0 0 0 0 0 6153 60 85 49 68 108 172 187 0 0 572 595 290 916 262 458 666 1298 6 0 11 144 538 3681 456 626 1034 2794 1531 9 41 253 572 4554 4085 488 818 2321 5120 69 147 594 775 4858 7474 250 353 930 5779 2687 457 1243 2695 3028 7004 1740 98 269 2299 7415 1271 2218 3513 2277 4986 1770 26 92 1019 11578 7163 2700 2830 2319 1148 849 55 5 64 970 1708 9 0 0 0 0 0 1 2 61 362 19 0 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 2 count: 1000304 average: 2 | standard deviation: 0 | 0 0 1000304 ] -miss_latency_Directory: [binsize: 2 max: 358 count: 2 average: 303 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_L1Cache_wCC: [binsize: 4 max: 483 count: 224357 average: 215.864 | standard deviation: 83.754 | 0 0 0 0 0 0 0 0 6153 60 85 52 149 1426 9888 229 0 0 572 595 290 916 294 780 5824 6926 6 0 11 144 538 3682 460 712 2357 12424 1629 9 41 253 572 4554 4085 507 1149 7444 10678 75 147 594 775 4858 7475 253 438 2186 15528 2862 457 1243 2695 3028 7004 1742 123 584 7531 13604 1274 2218 3513 2277 4986 1770 33 219 2917 25781 7533 2700 2830 2319 1154 849 55 5 64 970 1708 9 0 0 0 0 0 1 2 61 362 19 1 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 2 count: 140230 average: 1.99996 | standard deviation: 0.00925064 | 3 0 140227 ] -miss_latency_wCC_initial_forward_request: [binsize: 4 max: 459 count: 140230 average: 203.958 | standard deviation: 78.4902 | 0 0 6212 20 98 67 95 140 250 0 0 1 1158 74 1037 220 349 551 1081 592 0 5 113 112 1635 2713 530 808 1650 3233 16 19 103 216 2099 6872 447 621 1222 4793 1914 74 320 1024 1743 7379 3458 282 513 2610 6341 300 767 1912 1837 6522 4902 99 141 770 6765 2933 1663 2774 3916 2940 3746 439 31 325 4465 13834 2498 2827 2733 1196 1565 289 2 23 232 2118 382 0 0 0 0 0 0 1 14 199 231 1 0 0 0 0 0 0 1 3 21 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 24 count: 140230 average: 24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 140230 ] -miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 2 count: 140230 average: 0.125494 | standard deviation: 0.335859 | 122846 17170 214 ] -imcomplete_wCC_Times: 84127 -miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 2 count: 2 average: 2 | standard deviation: 0 | 0 0 2 ] -miss_latency_dir_initial_forward_request: [binsize: 1 max: 8 count: 2 average: 8 | standard deviation: 0 | 0 0 0 0 0 0 0 0 2 ] -miss_latency_dir_forward_to_first_response: [binsize: 1 max: 24 count: 2 average: 24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] -miss_latency_dir_first_response_to_completion: [binsize: 2 max: 324 count: 2 average: 269 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency: [binsize: 128 max: 20160 count: 1223236 average: 3982.16 | standard deviation: 4665.63 | 3708 13781 25116 33223 31921 38797 43604 45421 39533 34780 37348 35273 29185 26408 23841 22826 19268 17942 17660 14791 14436 14028 13947 12589 11213 12158 12485 11406 11283 10763 11315 10826 10964 11697 10326 10963 11210 11863 11224 10479 11754 12169 11782 11935 11747 12526 12312 12508 13274 11956 12572 12763 13270 12822 11784 12738 12948 12280 11992 11264 11881 10994 10700 10686 9540 9613 9236 9204 8301 7394 7524 7032 6512 5971 5447 5391 4756 4563 4247 3623 3363 3219 3041 2542 2170 2242 2127 1734 1545 1433 1353 1137 1013 958 793 705 672 598 488 422 421 364 276 289 244 209 186 152 145 110 83 83 85 66 45 42 32 36 20 29 27 22 17 15 12 12 9 4 5 3 1 6 2 2 1 2 0 2 1 0 0 1 1 0 0 1 0 2 0 0 0 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 19520 count: 795213 average: 3980.28 | standard deviation: 6214.05 | 2367 8989 16262 21781 20893 25190 28254 29586 25661 22626 24278 23085 19116 17158 15560 14786 12693 11723 11422 9539 9375 9108 9013 8099 7236 7910 8080 7444 7303 7019 7374 7036 7048 7598 6668 7111 7166 7768 7191 6845 7679 7799 7673 7710 7667 8206 8031 8008 8632 7748 8177 8242 8718 8331 7736 8254 8467 7936 7684 7323 7701 7199 6981 6919 6216 6337 6018 5989 5426 4831 4902 4625 4293 3782 3464 3552 3151 2882 2715 2314 2186 2084 1953 1677 1406 1498 1375 1132 1013 946 898 735 673 620 507 432 447 388 325 259 259 241 167 189 158 133 121 101 94 71 56 59 58 46 33 24 20 23 11 20 13 14 12 6 8 8 8 3 3 3 0 5 1 2 1 2 0 2 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 128 max: 20160 count: 428023 average: 3985.66 | standard deviation: 3071.42 | 1341 4792 8854 11442 11028 13607 15350 15835 13872 12154 13070 12188 10069 9250 8281 8040 6575 6219 6238 5252 5061 4920 4934 4490 3977 4248 4405 3962 3980 3744 3941 3790 3916 4099 3658 3852 4044 4095 4033 3634 4075 4370 4109 4225 4080 4320 4281 4500 4642 4208 4395 4521 4552 4491 4048 4484 4481 4344 4308 3941 4180 3795 3719 3767 3324 3276 3218 3215 2875 2563 2622 2407 2219 2189 1983 1839 1605 1681 1532 1309 1177 1135 1088 865 764 744 752 602 532 487 455 402 340 338 286 273 225 210 163 163 162 123 109 100 86 76 65 51 51 39 27 24 27 20 12 18 12 13 9 9 14 8 5 9 4 4 1 1 2 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 176 average: 2 | standard deviation: 0 | 0 0 176 ] +miss_latency_L2Cache: [binsize: 64 max: 7472 count: 647 average: 674.793 | standard deviation: 949.886 | 268 12 13 15 15 8 17 19 26 15 17 12 17 12 15 13 8 11 9 9 4 10 4 9 2 5 4 7 4 5 7 5 1 6 2 2 0 2 5 1 1 3 0 4 1 4 0 2 1 1 0 0 2 0 0 1 0 0 0 0 2 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 128 max: 20160 count: 1182550 average: 4001.69 | standard deviation: 4756.29 | 0 12309 23695 31625 30233 37429 42404 44206 38629 33981 36572 34570 28577 25889 23291 22353 18824 17509 17291 14387 14068 13636 13573 12231 10859 11836 12110 11025 10944 10379 10965 10457 10610 11373 9950 10594 10822 11428 10873 10097 11367 11761 11360 11563 11359 12094 11869 12090 12837 11507 12185 12339 12855 12403 11403 12328 12532 11909 11633 10917 11522 10662 10413 10434 9274 9366 8979 8967 8097 7196 7351 6853 6357 5834 5324 5273 4642 4463 4172 3515 3292 3166 2981 2489 2127 2187 2091 1692 1524 1406 1325 1115 994 941 773 686 662 588 470 410 414 359 272 283 240 206 183 148 143 110 81 82 85 66 43 41 32 36 20 29 25 22 17 15 11 12 9 4 5 3 1 6 2 2 1 2 0 2 1 0 0 1 1 0 0 1 0 2 0 0 0 1 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 128 max: 15973 count: 39863 average: 3474.22 | standard deviation: 3059.48 | 3252 1444 1398 1562 1647 1339 1171 1187 885 781 762 690 601 508 541 461 437 429 367 398 364 388 369 356 352 322 373 380 339 384 348 368 354 324 375 368 387 434 351 382 387 407 422 372 387 432 443 418 437 449 386 424 415 419 381 410 416 371 358 347 359 332 287 252 266 247 257 237 204 198 173 179 155 137 123 118 114 100 75 108 71 53 60 53 43 55 36 42 21 27 28 22 19 17 20 19 10 10 18 12 7 5 4 6 4 3 3 4 2 0 2 1 0 0 2 1 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 15941 count: 39794 average: 3295.79 | standard deviation: 3041.63 | 4782 1655 1558 1885 1460 1216 1095 1024 767 582 578 581 481 425 399 394 385 379 414 334 341 367 365 355 294 341 373 395 346 384 352 369 343 366 342 387 372 425 345 348 417 436 381 450 375 452 455 418 478 391 388 415 419 432 349 389 407 386 346 309 334 304 278 264 226 222 243 207 205 154 152 150 125 137 103 98 85 85 86 76 57 54 54 49 28 48 39 31 20 19 11 23 13 14 12 20 12 9 11 8 4 5 3 1 4 1 2 1 2 1 1 1 0 0 2 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 32 max: 3937 count: 39794 average: 155.313 | standard deviation: 325.711 | 28442 688 527 562 440 392 416 416 507 395 365 403 377 520 392 381 375 301 320 247 178 189 197 243 149 167 143 140 203 123 119 106 96 124 70 70 86 79 79 54 49 49 54 57 45 54 40 27 39 20 16 19 23 27 11 12 12 7 16 13 9 3 9 7 14 5 7 5 6 4 5 3 2 3 1 8 3 2 1 3 3 0 3 2 1 2 1 1 2 3 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 24 count: 39794 average: 24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 39794 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 2 count: 39794 average: 0.00693572 | standard deviation: 0.104554 | 39598 116 80 ] +imcomplete_wCC_Times: 69 +miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 18931 count: 1182550 average: 3280.19 | standard deviation: 4734.35 | 141942 48966 47072 55633 43296 35639 31964 31286 23173 17373 17650 17262 14327 13035 12298 12751 11656 11626 11795 10382 10673 10823 11510 10529 9635 10721 10839 10357 10393 10244 10930 10531 10721 11289 10411 11003 11380 12024 11548 10831 12139 12561 12113 12253 11915 12616 12467 12557 13088 11754 12285 12325 12583 11654 10505 11095 11416 10431 9898 9334 9576 8652 8285 8227 7047 6945 6498 6330 5534 4805 4805 4626 4002 3650 3187 3144 2779 2621 2497 1957 1794 1753 1586 1373 1074 1131 1000 900 745 682 575 564 504 441 364 315 262 269 217 181 168 144 126 114 85 73 54 51 54 33 33 39 29 28 16 15 12 13 8 10 8 5 8 3 1 2 1 0 1 0 3 0 0 0 1 0 1 0 0 0 0 0 2 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_dir_initial_forward_request: [binsize: 32 max: 3953 count: 1182550 average: 11.2327 | standard deviation: 55.4198 | 1176058 241 310 250 266 280 304 227 229 176 160 152 130 105 129 136 256 216 237 197 169 232 155 125 118 96 123 99 70 73 79 100 64 99 62 60 89 58 49 46 38 44 20 20 30 18 36 27 22 17 23 29 11 13 11 9 19 13 9 11 8 14 5 8 2 4 7 3 6 0 2 6 2 4 4 4 5 2 3 1 0 2 0 1 1 0 3 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 24 count: 1182550 average: 24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1182550 ] +miss_latency_dir_first_response_to_completion: [binsize: 32 max: 5007 count: 1182550 average: 686.263 | standard deviation: 462.949 | 0 0 0 28916 38265 33160 37401 39584 55260 42321 40747 40392 40085 53028 38562 36031 33187 30850 38321 27204 26928 26598 26438 34392 26147 25688 25635 25251 31433 21500 18732 16190 14137 16687 11945 11134 10675 9960 12643 9263 8744 8518 8273 10710 7211 6333 5563 5023 5917 4093 3823 3621 3391 4336 2997 2800 2797 2617 3266 2331 2041 1720 1632 1921 1373 1234 1199 1071 1382 927 873 878 782 1004 681 634 524 463 542 396 347 338 288 365 264 234 227 203 206 169 154 133 127 128 93 83 79 72 78 73 65 42 42 64 28 39 28 19 21 18 17 14 17 17 16 11 10 7 14 15 6 6 5 7 3 3 1 1 4 3 1 2 1 4 1 0 0 1 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 711546 average: 2 | standard deviation: 0 | 0 0 711546 ] -miss_latency_LD_Directory: [binsize: 2 max: 358 count: 2 average: 303 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 483 count: 84131 average: 192.173 | standard deviation: 86.9918 | 0 0 0 0 0 0 0 0 0 0 0 3 81 1318 9716 42 0 0 0 0 0 0 32 322 5158 5628 0 0 0 0 0 1 4 86 1323 9630 98 0 0 0 0 0 0 19 331 5123 5558 6 0 0 0 0 1 3 85 1256 9749 175 0 0 0 0 0 2 25 315 5232 6189 3 0 0 0 0 0 7 127 1898 14203 370 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 288758 average: 2 | standard deviation: 0 | 0 0 288758 ] -miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 442 count: 140226 average: 230.078 | standard deviation: 78.3858 | 0 0 0 0 0 0 0 0 6153 60 85 49 68 108 172 187 0 0 572 595 290 916 262 458 666 1298 6 0 11 144 538 3681 456 626 1034 2794 1531 9 41 253 572 4554 4085 488 818 2321 5120 69 147 594 775 4858 7474 250 353 930 5779 2687 457 1243 2695 3028 7004 1740 98 269 2299 7415 1271 2218 3513 2277 4986 1770 26 92 1019 11578 7163 2700 2830 2319 1148 849 55 5 64 970 1708 9 0 0 0 0 0 1 2 61 362 19 0 0 0 0 0 0 1 0 11 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 117 average: 2 | standard deviation: 0 | 0 0 117 ] +miss_latency_LD_L2Cache: [binsize: 64 max: 7472 count: 423 average: 721.243 | standard deviation: 1002.1 | 169 5 10 9 10 6 12 13 19 10 10 7 10 7 12 6 7 4 6 6 3 7 1 8 0 4 3 5 3 2 7 5 1 4 2 1 0 2 4 0 1 3 0 3 1 4 0 0 0 0 0 0 2 0 0 1 0 0 0 0 2 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_Directory: [binsize: 128 max: 19520 count: 768954 average: 3998.96 | standard deviation: 6374.36 | 0 8067 15339 20744 19789 24322 27482 28826 25078 22121 23786 22622 18734 16823 15188 14462 12401 11434 11189 9267 9144 8876 8767 7886 7020 7694 7848 7175 7086 6778 7145 6786 6816 7394 6443 6876 6929 7495 6966 6597 7427 7531 7396 7462 7396 7925 7739 7737 8360 7461 7913 7959 8456 8051 7484 7985 8193 7682 7464 7088 7471 6971 6801 6771 6039 6174 5851 5848 5297 4701 4785 4511 4188 3693 3385 3469 3070 2819 2665 2239 2143 2043 1914 1647 1379 1466 1350 1105 1001 927 881 722 661 612 493 421 439 384 312 253 257 239 164 183 156 132 119 97 92 71 54 58 58 46 31 23 20 23 11 20 12 14 12 6 8 8 8 3 3 3 0 5 1 2 1 2 0 2 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 15443 count: 25719 average: 3493.59 | standard deviation: 3062.21 | 2076 903 907 1012 1075 851 755 742 572 493 482 454 378 327 367 312 287 286 231 268 227 229 241 213 216 216 230 268 217 241 227 249 232 204 224 235 237 273 225 248 252 267 277 248 270 281 292 271 272 287 263 283 262 280 252 269 274 254 219 235 230 228 180 148 177 163 167 141 129 130 117 114 105 89 79 83 81 63 50 75 43 41 39 30 27 32 25 27 12 19 17 13 12 8 14 11 8 4 13 6 2 2 3 6 2 1 2 4 2 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 59 average: 2 | standard deviation: 0 | 0 0 59 ] +miss_latency_ST_L2Cache: [binsize: 32 max: 4752 count: 224 average: 587.076 | standard deviation: 837.634 | 90 9 2 5 3 0 3 3 1 4 1 1 2 3 2 4 5 2 3 2 6 1 4 1 4 3 3 2 0 3 2 5 0 1 5 2 1 2 0 3 0 1 1 2 0 3 0 1 0 2 0 1 1 0 0 2 1 0 2 1 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 128 max: 20160 count: 413596 average: 4006.77 | standard deviation: 3069.87 | 0 4242 8356 10881 10444 13107 14922 15380 13551 11860 12786 11948 9843 9066 8103 7891 6423 6075 6102 5120 4924 4760 4806 4345 3839 4142 4262 3850 3858 3601 3820 3671 3794 3979 3507 3718 3893 3933 3907 3500 3940 4230 3964 4101 3963 4169 4130 4353 4477 4046 4272 4380 4399 4352 3919 4343 4339 4227 4169 3829 4051 3691 3612 3663 3235 3192 3128 3119 2800 2495 2566 2342 2169 2141 1939 1804 1572 1644 1507 1276 1149 1123 1067 842 748 721 741 587 523 479 444 393 333 329 280 265 223 204 158 157 157 120 108 100 84 74 64 51 51 39 27 24 27 20 12 18 12 13 9 9 13 8 5 9 3 4 1 1 2 0 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15973 count: 14144 average: 3439 | standard deviation: 3054.29 | 1176 541 491 550 572 488 416 445 313 288 280 236 223 181 174 149 150 143 136 130 137 159 128 143 136 106 143 112 122 143 121 119 122 120 151 133 150 161 126 134 135 140 145 124 117 151 151 147 165 162 123 141 153 139 129 141 142 117 139 112 129 104 107 104 89 84 90 96 75 68 56 65 50 48 44 35 33 37 25 33 28 12 21 23 16 23 11 15 9 8 11 9 7 9 6 8 2 6 5 6 5 3 1 0 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -120,203 +124,242 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 37 +user_time: 247 system_time: 0 -page_reclaims: 9470 +page_reclaims: 10276 page_faults: 0 swaps: 0 -block_inputs: 16 +block_inputs: 0 block_outputs: 0 Network Stats ------------- -total_msg_count_Request_Control: 724737 5797896 -total_msg_count_Response_Data: 603819 43474968 -total_msg_count_Response_Control: 2526462 20211696 -total_msg_count_Broadcast_Control: 2103450 16827600 -total_msg_count_Unblock_Control: 673075 5384600 -total_msgs: 6631543 total_bytes: 91696760 +total_msg_count_Request_Control: 3667506 29340048 +total_msg_count_Response_Data: 3667212 264039264 +total_msg_count_Response_Control: 25550289 204402312 +total_msg_count_Writeback_Data: 1267908 91289376 +total_msg_count_Writeback_Control: 9104502 72836016 +total_msg_count_Broadcast_Control: 18335460 146683680 +total_msg_count_Unblock_Control: 3667290 29338320 +total_msgs: 65260167 total_bytes: 837929016 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.346445 - links_utilized_percent_switch_0_link_0: 0.182474 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.510416 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 2129 17032 [ 0 0 0 2129 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 28059 2020248 [ 0 0 0 0 28059 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 28166 225328 [ 0 0 28166 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 19532 1406304 [ 0 0 0 0 19532 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 105318 842544 [ 0 0 0 0 105318 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 28164 225312 [ 0 0 0 0 0 28164 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.199775 + links_utilized_percent_switch_0_link_0: 0.119966 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.279585 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 152750 10998000 [ 0 0 0 0 152750 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 1064219 8513752 [ 0 0 0 0 1064219 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 144063 1152504 [ 0 0 0 144063 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 1069616 8556928 [ 0 0 0 1069616 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 152755 1222040 [ 0 0 152755 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 4971 357912 [ 0 0 0 0 4971 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 1064653 8517224 [ 0 0 0 0 1064653 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 53143 3826296 [ 0 0 0 0 0 53143 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 234981 1879848 [ 0 0 144063 0 0 90918 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 152753 1222024 [ 0 0 0 0 0 152753 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.345452 - links_utilized_percent_switch_1_link_0: 0.181714 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.50919 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 2107 16856 [ 0 0 0 2107 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 27856 2005632 [ 0 0 0 0 27856 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 104959 839672 [ 0 0 0 0 104959 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Broadcast_Control: 122754 982032 [ 0 0 0 122754 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 27960 223680 [ 0 0 27960 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 19481 1402632 [ 0 0 0 0 19481 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 105379 843032 [ 0 0 0 0 105379 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 27958 223664 [ 0 0 0 0 0 27958 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.199595 + links_utilized_percent_switch_1_link_0: 0.11991 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.279281 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 152625 10989000 [ 0 0 0 0 152625 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1063478 8507824 [ 0 0 0 0 1063478 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 144096 1152768 [ 0 0 0 144096 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 1069741 8557928 [ 0 0 0 1069741 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 152629 1221032 [ 0 0 152629 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 5123 368856 [ 0 0 0 0 5123 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1064628 8517024 [ 0 0 0 0 1064628 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 52709 3795048 [ 0 0 0 0 0 52709 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 235480 1883840 [ 0 0 144096 0 0 91384 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 152628 1221024 [ 0 0 0 0 0 152628 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.347269 - links_utilized_percent_switch_2_link_0: 0.182656 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.511881 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 2164 17312 [ 0 0 0 2164 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 28071 2021112 [ 0 0 0 0 28071 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 105564 844512 [ 0 0 0 0 105564 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Broadcast_Control: 122650 981200 [ 0 0 0 122650 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 28157 225256 [ 0 0 28157 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 19660 1415520 [ 0 0 0 0 19660 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 105153 841224 [ 0 0 0 0 105153 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 28155 225240 [ 0 0 0 0 0 28155 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.199688 + links_utilized_percent_switch_2_link_0: 0.119941 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.279435 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 152700 10994400 [ 0 0 0 0 152700 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 1063864 8510912 [ 0 0 0 0 1063864 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 144072 1152576 [ 0 0 0 144072 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 1069676 8557408 [ 0 0 0 1069676 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 152703 1221624 [ 0 0 152703 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 4948 356256 [ 0 0 0 0 4948 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1064736 8517888 [ 0 0 0 0 1064736 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 53026 3817872 [ 0 0 0 0 0 53026 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 235117 1880936 [ 0 0 144072 0 0 91045 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 152703 1221624 [ 0 0 0 0 0 152703 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.346043 - links_utilized_percent_switch_3_link_0: 0.181891 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.510195 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Request_Control: 2134 17072 [ 0 0 0 2134 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 27884 2007648 [ 0 0 0 0 27884 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 105191 841528 [ 0 0 0 0 105191 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Broadcast_Control: 122712 981696 [ 0 0 0 122712 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 27975 223800 [ 0 0 27975 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 19562 1408464 [ 0 0 0 0 19562 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 105284 842272 [ 0 0 0 0 105284 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 27973 223784 [ 0 0 0 0 0 27973 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_3: 0.199488 + links_utilized_percent_switch_3_link_0: 0.119939 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.279037 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 152694 10993968 [ 0 0 0 0 152694 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 1063941 8511528 [ 0 0 0 0 1063941 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 143990 1151920 [ 0 0 0 143990 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 1069671 8557368 [ 0 0 0 1069671 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 152697 1221576 [ 0 0 152697 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 4898 352656 [ 0 0 0 0 4898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 1064781 8518248 [ 0 0 0 0 1064781 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 52720 3795840 [ 0 0 0 0 0 52720 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 235255 1882040 [ 0 0 143990 0 0 91265 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 152700 1221600 [ 0 0 0 0 0 152700 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.346195 - links_utilized_percent_switch_4_link_0: 0.182121 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.51027 bw: 160000 base_latency: 1 - - outgoing_messages_switch_4_link_0_Request_Control: 2119 16952 [ 0 0 0 2119 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 27936 2011392 [ 0 0 0 0 27936 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 105371 842968 [ 0 0 0 0 105371 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Broadcast_Control: 122686 981488 [ 0 0 0 122686 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 28045 224360 [ 0 0 28045 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 19556 1408032 [ 0 0 0 0 19556 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 105248 841984 [ 0 0 0 0 105248 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 28043 224344 [ 0 0 0 0 0 28043 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_4: 0.199798 + links_utilized_percent_switch_4_link_0: 0.120111 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.279484 bw: 160000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 153036 11018592 [ 0 0 0 0 153036 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 1066246 8529968 [ 0 0 0 0 1066246 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 144181 1153448 [ 0 0 0 144181 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 1069334 8554672 [ 0 0 0 1069334 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 153039 1224312 [ 0 0 153039 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 4983 358776 [ 0 0 0 0 4983 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 1064358 8514864 [ 0 0 0 0 1064358 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Data: 52970 3813840 [ 0 0 0 0 0 52970 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 235391 1883128 [ 0 0 144181 0 0 91210 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 153037 1224296 [ 0 0 0 0 0 153037 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.346499 - links_utilized_percent_switch_5_link_0: 0.181925 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.511074 bw: 160000 base_latency: 1 - - outgoing_messages_switch_5_link_0_Request_Control: 2216 17728 [ 0 0 0 2216 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 27888 2007936 [ 0 0 0 0 27888 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 27996 223968 [ 0 0 27996 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 19618 1412496 [ 0 0 0 0 19618 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 105319 842552 [ 0 0 0 0 105319 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 27994 223952 [ 0 0 0 0 0 27994 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_5: 0.199507 + links_utilized_percent_switch_5_link_0: 0.12002 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.278994 bw: 160000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 152880 11007360 [ 0 0 0 0 152880 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 1065109 8520872 [ 0 0 0 0 1065109 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 143798 1150384 [ 0 0 0 143798 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 1069488 8555904 [ 0 0 0 1069488 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 152883 1223064 [ 0 0 152883 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 5100 367200 [ 0 0 0 0 5100 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 1064397 8515176 [ 0 0 0 0 1064397 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Data: 52502 3780144 [ 0 0 0 0 0 52502 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 235092 1880736 [ 0 0 143798 0 0 91294 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 152884 1223072 [ 0 0 0 0 0 152884 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.34662 - links_utilized_percent_switch_6_link_0: 0.182139 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.511101 bw: 160000 base_latency: 1 - - outgoing_messages_switch_6_link_0_Request_Control: 2183 17464 [ 0 0 0 2183 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 27954 2012688 [ 0 0 0 0 27954 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 105165 841320 [ 0 0 0 0 105165 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Broadcast_Control: 122716 981728 [ 0 0 0 122716 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 28036 224288 [ 0 0 28036 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 19615 1412280 [ 0 0 0 0 19615 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 105283 842264 [ 0 0 0 0 105283 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 28035 224280 [ 0 0 0 0 0 28035 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_6: 0.199626 + links_utilized_percent_switch_6_link_0: 0.120193 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.279058 bw: 160000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 153186 11029392 [ 0 0 0 0 153186 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 1067322 8538576 [ 0 0 0 0 1067322 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 144401 1155208 [ 0 0 0 144401 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 1069185 8553480 [ 0 0 0 1069185 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 153191 1225528 [ 0 0 153191 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 4877 351144 [ 0 0 0 0 4877 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 1064317 8514536 [ 0 0 0 0 1064317 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Data: 52596 3786912 [ 0 0 0 0 0 52596 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Writeback_Control: 236204 1889632 [ 0 0 144401 0 0 91803 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 153190 1225520 [ 0 0 0 0 0 153190 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.346674 - links_utilized_percent_switch_7_link_0: 0.182194 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.511154 bw: 160000 base_latency: 1 - - outgoing_messages_switch_7_link_0_Request_Control: 2154 17232 [ 0 0 0 2154 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 27933 2011176 [ 0 0 0 0 27933 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 105596 844768 [ 0 0 0 0 105596 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Broadcast_Control: 122648 981184 [ 0 0 0 122648 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 28038 224304 [ 0 0 28038 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 19631 1413432 [ 0 0 0 0 19631 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 105170 841360 [ 0 0 0 0 105170 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 28037 224296 [ 0 0 0 0 0 28037 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_7: 0.199581 + links_utilized_percent_switch_7_link_0: 0.11985 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.279313 bw: 160000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 152533 10982376 [ 0 0 0 0 152533 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 1062584 8500672 [ 0 0 0 0 1062584 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 143895 1151160 [ 0 0 0 143895 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 1069837 8558696 [ 0 0 0 1069837 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 152536 1220288 [ 0 0 152536 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 4954 356688 [ 0 0 0 0 4954 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 1064893 8519144 [ 0 0 0 0 1064893 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Data: 52970 3813840 [ 0 0 0 0 0 52970 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Writeback_Control: 234818 1878544 [ 0 0 143895 0 0 90923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 152535 1220280 [ 0 0 0 0 0 152535 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.20393 - links_utilized_percent_switch_8_link_0: 0.169691 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.23817 bw: 160000 base_latency: 1 - - outgoing_messages_switch_8_link_0_Request_Control: 224373 1794984 [ 0 0 224373 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 224358 1794864 [ 0 0 0 0 0 224358 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 17206 137648 [ 0 0 0 17206 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Broadcast_Control: 140230 1121840 [ 0 0 0 140230 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_8: 0.988626 + links_utilized_percent_switch_8_link_0: 0.267047 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 1.7102 bw: 160000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Request_Control: 1222433 9779464 [ 0 0 1222433 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Data: 422636 30429792 [ 0 0 0 0 0 422636 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Writeback_Control: 1882338 15058704 [ 0 0 1152496 0 0 729842 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 1222430 9779440 [ 0 0 0 0 0 1222430 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 69 552 [ 0 0 0 69 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 1182550 85143600 [ 0 0 0 0 1182550 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 1152496 9219968 [ 0 0 0 1152496 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Broadcast_Control: 1222364 9778912 [ 0 0 0 1222364 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 -links_utilized_percent_switch_9: 0.723025 - links_utilized_percent_switch_9_link_0: 0.729898 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 0.726855 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 0.730626 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 0.727564 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 0.728482 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 0.727702 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 0.728558 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 0.728777 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 0.678764 bw: 160000 base_latency: 1 - - outgoing_messages_switch_9_link_0_Request_Control: 2129 17032 [ 0 0 0 2129 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Data: 28059 2020248 [ 0 0 0 0 28059 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Request_Control: 2107 16856 [ 0 0 0 2107 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 27856 2005632 [ 0 0 0 0 27856 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Control: 104959 839672 [ 0 0 0 0 104959 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Broadcast_Control: 122754 982032 [ 0 0 0 122754 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Request_Control: 2164 17312 [ 0 0 0 2164 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 28071 2021112 [ 0 0 0 0 28071 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Control: 105564 844512 [ 0 0 0 0 105564 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Broadcast_Control: 122650 981200 [ 0 0 0 122650 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Request_Control: 2134 17072 [ 0 0 0 2134 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 27884 2007648 [ 0 0 0 0 27884 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Control: 105191 841528 [ 0 0 0 0 105191 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Broadcast_Control: 122712 981696 [ 0 0 0 122712 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Request_Control: 2119 16952 [ 0 0 0 2119 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 27936 2011392 [ 0 0 0 0 27936 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Control: 105371 842968 [ 0 0 0 0 105371 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Broadcast_Control: 122686 981488 [ 0 0 0 122686 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Request_Control: 2216 17728 [ 0 0 0 2216 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 27888 2007936 [ 0 0 0 0 27888 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Control: 105154 841232 [ 0 0 0 0 105154 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Broadcast_Control: 122722 981776 [ 0 0 0 122722 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Request_Control: 2183 17464 [ 0 0 0 2183 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 27954 2012688 [ 0 0 0 0 27954 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Control: 105165 841320 [ 0 0 0 0 105165 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Broadcast_Control: 122716 981728 [ 0 0 0 122716 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Request_Control: 2154 17232 [ 0 0 0 2154 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 27933 2011176 [ 0 0 0 0 27933 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Control: 105596 844768 [ 0 0 0 0 105596 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Broadcast_Control: 122648 981184 [ 0 0 0 122648 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Request_Control: 224373 1794984 [ 0 0 224373 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Unblock_Control: 224358 1794864 [ 0 0 0 0 0 224358 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_9: 0.545323 + links_utilized_percent_switch_9_link_0: 0.479862 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 0.479638 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 0.479765 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 0.479757 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 0.480445 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 0.480081 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 0.480773 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 0.479398 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 1.06819 bw: 160000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 152750 10998000 [ 0 0 0 0 152750 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 1064219 8513752 [ 0 0 0 0 1064219 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 144063 1152504 [ 0 0 0 144063 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Broadcast_Control: 1069616 8556928 [ 0 0 0 1069616 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 152625 10989000 [ 0 0 0 0 152625 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 1063478 8507824 [ 0 0 0 0 1063478 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 144096 1152768 [ 0 0 0 144096 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Broadcast_Control: 1069741 8557928 [ 0 0 0 1069741 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 152700 10994400 [ 0 0 0 0 152700 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Control: 1063864 8510912 [ 0 0 0 0 1063864 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Writeback_Control: 144072 1152576 [ 0 0 0 144072 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Broadcast_Control: 1069676 8557408 [ 0 0 0 1069676 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 152694 10993968 [ 0 0 0 0 152694 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Control: 1063941 8511528 [ 0 0 0 0 1063941 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Writeback_Control: 143990 1151920 [ 0 0 0 143990 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Broadcast_Control: 1069671 8557368 [ 0 0 0 1069671 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Request_Control: 7 56 [ 0 0 0 7 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 153036 11018592 [ 0 0 0 0 153036 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Control: 1066246 8529968 [ 0 0 0 0 1066246 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Writeback_Control: 144181 1153448 [ 0 0 0 144181 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Broadcast_Control: 1069334 8554672 [ 0 0 0 1069334 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 152880 11007360 [ 0 0 0 0 152880 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Control: 1065109 8520872 [ 0 0 0 0 1065109 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Writeback_Control: 143798 1150384 [ 0 0 0 143798 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Broadcast_Control: 1069488 8555904 [ 0 0 0 1069488 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Request_Control: 9 72 [ 0 0 0 9 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 153186 11029392 [ 0 0 0 0 153186 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Control: 1067322 8538576 [ 0 0 0 0 1067322 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Writeback_Control: 144401 1155208 [ 0 0 0 144401 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Broadcast_Control: 1069185 8553480 [ 0 0 0 1069185 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Request_Control: 10 80 [ 0 0 0 10 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 152533 10982376 [ 0 0 0 0 152533 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Control: 1062584 8500672 [ 0 0 0 0 1062584 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Writeback_Control: 143895 1151160 [ 0 0 0 143895 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Broadcast_Control: 1069837 8558696 [ 0 0 0 1069837 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Request_Control: 1222433 9779464 [ 0 0 1222433 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Writeback_Data: 422636 30429792 [ 0 0 0 0 0 422636 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Writeback_Control: 1882338 15058704 [ 0 0 1152496 0 0 729842 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Unblock_Control: 1222430 9779440 [ 0 0 0 0 0 1222430 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory system.l1_cntrl0.L1IcacheMemory_total_misses: 0 @@ -327,229 +370,242 @@ Cache Stats: system.l1_cntrl0.L1IcacheMemory Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 28166 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 28166 + system.l1_cntrl0.L1DcacheMemory_total_misses: 152935 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 152935 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 37.8364% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 62.1636% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 64.8125% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 35.1875% - system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 28166 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 152935 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 28166 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 28166 + system.l1_cntrl0.L2cacheMemory_total_misses: 152935 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 152935 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 37.8364% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 62.1636% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 64.8125% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 35.1875% - system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 28166 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 152935 100% --- L1Cache --- - Event Counts - -Load [99210 99376 100000 99219 99692 99063 99665 99458 ] 795683 +Load [99535 99829 100085 99136 99177 99443 99228 99488 ] 795921 Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [53780 53529 53389 53948 53675 53375 53908 53390 ] 428994 -L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +Store [53745 53262 53330 53614 53839 53432 53726 53441 ] 428389 +L2_Replacement [153026 152866 153174 152520 152738 152617 152685 152681 ] 1222307 +L1_to_L2 [1699797 1701512 1708689 1694889 1695562 1699555 1697205 1695495 ] 13592704 +Trigger_L2_to_L1D [143 150 148 151 180 162 162 168 ] 1264 Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 -Other_GETX [122682 122718 122712 122644 122719 122751 122647 122709 ] 981582 -Other_GETS [3 3 3 3 2 2 2 3 ] 21 -Merged_GETS [2119 2216 2183 2154 2129 2107 2164 2134 ] 17206 +Complete_L2_to_L1 [143 150 148 151 180 162 162 168 ] 1264 +Other_GETX [374083 374559 374492 374205 373994 374401 374093 374381 ] 2994208 +Other_GETS [695251 694929 694693 695632 695622 695340 695583 695290 ] 5562340 +Merged_GETS [7 9 9 10 8 10 8 8 ] 69 Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 Invalidate [0 0 0 0 0 0 0 0 ] 0 -Ack [105371 105154 105165 105596 105154 104959 105564 105191 ] 842154 -Shared_Ack [0 0 0 0 0 0 0 0 ] 0 -Data [2019 1991 2020 2091 2064 2072 2087 2084 ] 16428 -Shared_Data [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130 -Exclusive_Data [15418 15411 15413 15387 15339 15302 15409 15344 ] 123023 -Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +Ack [1066123 1064987 1067202 1062483 1064107 1063381 1063754 1063815 ] 8515852 +Shared_Ack [123 122 120 101 112 97 110 126 ] 911 +Data [5950 5907 5831 5728 5802 5574 5668 5755 ] 46215 +Shared_Data [2067 2123 2065 2036 2070 1972 2052 2038 ] 16423 +Exclusive_Data [145019 144850 145290 144769 144878 145079 144980 144901 ] 1159766 +Writeback_Ack [144181 143798 144401 143895 144063 144096 144072 143990 ] 1152496 Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -All_acks [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130 -All_acks_no_sharers [17544 17508 17514 17582 17508 17476 17580 17517 ] 140229 +All_acks [2171 2229 2168 2123 2163 2061 2147 2146 ] 17208 +All_acks_no_sharers [150865 150653 151021 150410 150588 150564 150555 150549 ] 1205205 - Transitions - -I Load [10500 10487 10521 10455 10657 10484 10576 10457 ] 84137 +I Load [99378 99698 99939 98997 99005 99286 99052 99334 ] 794689 I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [5743 5634 5649 5815 5592 5753 5650 5790 ] 45626 -I L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -I L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -I Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +I Store [53661 53180 53249 53537 53748 53342 53646 53360 ] 427723 +I L2_Replacement [2971 3090 2945 2931 2939 3020 2985 2971 ] 23852 +I L1_to_L2 [649 680 667 679 598 653 650 638 ] 5214 +I Trigger_L2_to_L1D [5 2 8 5 6 2 1 4 ] 33 I Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -I Other_GETX [0 0 0 0 0 0 0 0 ] 0 -I Other_GETS [0 0 0 0 0 0 0 0 ] 0 +I Other_GETX [372211 372642 372741 372402 372213 372557 372267 372508 ] 2979541 +I Other_GETS [691950 691574 691373 692315 692230 691866 692295 692094 ] 5535697 I Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +I NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 I Invalidate [0 0 0 0 0 0 0 0 ] 0 -S Load [18002 18238 18415 17804 18407 18155 18219 18081 ] 145321 +S Load [2 2 0 0 3 3 4 5 ] 19 S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [9708 9676 9707 9635 9816 9635 9796 9625 ] 77598 -S L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -S L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -S Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +S Store [0 3 0 2 1 1 3 2 ] 12 +S L2_Replacement [5874 5978 5827 5694 5736 5501 5628 5720 ] 45958 +S L1_to_L2 [5937 6035 5876 5736 5789 5558 5672 5775 ] 46378 +S Trigger_L2_to_L1D [5 7 1 3 9 7 10 7 ] 49 S Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -S Other_GETX [791 810 814 820 840 847 779 831 ] 6532 -S Other_GETS [0 0 0 0 0 0 0 0 ] 0 +S Other_GETX [73 65 58 57 62 67 47 60 ] 489 +S Other_GETS [115 105 122 102 132 122 105 108 ] 911 S Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +S NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 S Invalidate [0 0 0 0 0 0 0 0 ] 0 -O Load [3730 3928 4020 4060 4122 3754 4001 3925 ] 31540 +O Load [0 3 1 0 2 2 2 0 ] 10 O Ifetch [0 0 0 0 0 0 0 0 ] 0 -O Store [2094 2199 2159 2133 2101 2088 2135 2103 ] 17012 -O L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -O L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -O Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +O Store [0 2 3 0 1 0 2 1 ] 9 +O L2_Replacement [2042 2030 1928 2030 2034 2118 1959 1937 ] 16078 +O L1_to_L2 [435 455 385 450 468 458 455 434 ] 3540 +O Trigger_L2_to_L1D [0 8 4 1 8 2 5 1 ] 29 O Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -O Other_GETX [25 17 24 21 28 19 29 31 ] 194 -O Other_GETS [0 0 0 0 0 0 0 0 ] 0 -O Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +O Other_GETX [15 12 16 12 16 13 18 13 ] 115 +O Other_GETS [20 22 24 23 28 27 21 20 ] 185 +O Merged_GETS [3 4 7 5 5 4 3 4 ] 35 O Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +O NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 O Invalidate [0 0 0 0 0 0 0 0 ] 0 -M Load [0 0 0 0 1 1 1 0 ] 3 +M Load [44 35 46 36 37 47 48 44 ] 337 M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [0 0 0 0 1 1 1 0 ] 3 -M L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -M L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -M Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +M Store [19 20 17 27 19 25 17 19 ] 163 +M L2_Replacement [90283 90403 91011 90081 90028 90430 90271 90451 ] 722958 +M L1_to_L2 [92829 93023 93501 92610 92598 93076 92754 92971 ] 743362 +M Trigger_L2_to_L1D [81 91 94 94 89 95 94 111 ] 749 M Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -M Other_GETX [0 0 0 0 0 0 0 0 ] 0 -M Other_GETS [0 0 0 0 0 0 0 0 ] 0 -M Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +M Other_GETX [1067 1179 1072 1089 1101 1126 1103 1126 ] 8863 +M Other_GETS [2053 2039 1945 2037 2048 2125 1974 1948 ] 16169 +M Merged_GETS [2 1 2 3 3 4 3 2 ] 20 M Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +M NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 M Invalidate [0 0 0 0 0 0 0 0 ] 0 -MM Load [66978 66723 67044 66900 66505 66669 66868 66995 ] 534682 +MM Load [24 15 15 20 27 25 27 21 ] 174 MM Ifetch [0 0 0 0 0 0 0 0 ] 0 -MM Store [36235 36020 35874 36365 36165 35898 36326 35872 ] 288755 -MM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MM Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +MM Store [19 11 21 10 20 16 9 14 ] 120 +MM L2_Replacement [51856 51365 51463 51784 52001 51548 51842 51602 ] 413461 +MM L1_to_L2 [53325 52830 52899 53202 53471 53040 53323 53038 ] 425128 +MM Trigger_L2_to_L1D [52 42 41 48 68 56 52 45 ] 404 MM Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 -MM Other_GETX [15425 15292 15330 15427 15379 15368 15416 15383 ] 123020 -MM Other_GETS [0 0 0 0 0 1 0 0 ] 1 -MM Merged_GETS [2119 2216 2183 2154 2129 2107 2164 2134 ] 17206 +MM Other_GETX [712 654 595 640 595 631 647 665 ] 5139 +MM Other_GETS [1107 1181 1208 1137 1170 1184 1172 1109 ] 9268 +MM Merged_GETS [2 4 0 2 0 2 2 2 ] 14 MM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MM Invalidate [0 0 0 0 0 0 0 0 ] 0 IM Load [0 0 0 0 0 0 0 0 ] 0 IM Ifetch [0 0 0 0 0 0 0 0 ] 0 IM Store [0 0 0 0 0 0 0 0 ] 0 IM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -IM Other_GETX [61926 61585 61837 61982 61426 61580 61822 61858 ] 494016 -IM Other_GETS [0 0 1 0 0 0 0 2 ] 3 +IM L1_to_L2 [539558 542842 538232 540761 543621 538326 538778 539689 ] 4321807 +IM Other_GETX [1 1 5 1 2 3 2 4 ] 19 +IM Other_GETS [1 3 6 4 5 3 4 3 ] 29 IM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +IM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IM Invalidate [0 0 0 0 0 0 0 0 ] 0 -IM Ack [50324 50375 50462 50772 50076 50008 49747 50687 ] 402451 -IM Data [1296 1262 1251 1350 1269 1317 1265 1314 ] 10324 -IM Exclusive_Data [15418 15411 15413 15387 15338 15301 15408 15344 ] 123020 +IM Ack [368543 365321 365720 367312 369025 366472 368657 366475 ] 2937525 +IM Data [2070 1981 2009 2009 2072 1976 2039 2009 ] 16165 +IM Exclusive_Data [51591 51199 51239 51528 51674 51365 51607 51351 ] 411554 SM Load [0 0 0 0 0 0 0 0 ] 0 SM Ifetch [0 0 0 0 0 0 0 0 ] 0 SM Store [0 0 0 0 0 0 0 0 ] 0 SM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -SM Other_GETX [8985 8947 8938 8894 9021 8880 8974 8855 ] 71494 +SM L1_to_L2 [0 0 0 0 0 1 1 3 ] 5 +SM Other_GETX [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS [0 0 0 0 0 0 0 0 ] 0 SM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +SM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 SM Invalidate [0 0 0 0 0 0 0 0 ] 0 -SM Ack [2116 2161 2439 2130 2490 2249 2469 2247 ] 18301 -SM Data [723 729 769 741 795 755 822 770 ] 6104 +SM Ack [0 13 0 10 7 7 16 14 ] 67 +SM Data [0 3 0 2 1 1 3 2 ] 12 +SM Exclusive_Data [0 0 0 0 0 0 0 0 ] 0 OM Load [0 0 0 0 0 0 0 0 ] 0 OM Ifetch [0 0 0 0 0 0 0 0 ] 0 OM Store [0 0 0 0 0 0 0 0 ] 0 OM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 OM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -OM Other_GETX [1987 2093 2078 2029 1996 1986 2051 2014 ] 16234 +OM Other_GETX [0 0 0 0 0 0 0 0 ] 0 OM Other_GETS [0 0 0 0 0 0 0 0 ] 0 OM Merged_GETS [0 0 0 0 0 0 0 0 ] 0 OM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +OM NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OM Invalidate [0 0 0 0 0 0 0 0 ] 0 -OM Ack [749 742 567 728 735 714 588 623 ] 5446 +OM Ack [0 14 21 0 7 0 14 7 ] 63 OM All_acks [0 0 0 0 0 0 0 0 ] 0 -OM All_acks_no_sharers [107 106 81 104 105 102 84 89 ] 778 +OM All_acks_no_sharers [0 2 3 0 1 0 2 1 ] 9 ISM Load [0 0 0 0 0 0 0 0 ] 0 ISM Ifetch [0 0 0 0 0 0 0 0 ] 0 ISM Store [0 0 0 0 0 0 0 0 ] 0 ISM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ISM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -ISM Ack [6059 6066 6055 6411 6149 6074 6336 6177 ] 49327 -ISM All_acks_no_sharers [2019 1991 2020 2091 2064 2072 2087 2084 ] 16428 +ISM L1_to_L2 [0 0 4 0 0 0 0 0 ] 4 +ISM Ack [84 65 58 53 39 31 61 37 ] 428 +ISM All_acks_no_sharers [2070 1984 2009 2011 2073 1977 2042 2011 ] 16177 M_W Load [0 0 0 0 0 0 0 0 ] 0 M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 M_W Store [0 0 0 0 0 0 0 0 ] 0 M_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_W L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -M_W Ack [0 0 0 0 0 0 1 0 ] 1 -M_W All_acks_no_sharers [0 0 0 0 1 1 1 0 ] 3 +M_W L1_to_L2 [72 52 30 60 49 82 77 110 ] 532 +M_W Ack [3358 3397 3332 3546 3317 3311 3651 3384 ] 27296 +M_W All_acks_no_sharers [93428 93651 94051 93241 93204 93714 93373 93550 ] 748212 MM_W Load [0 0 0 0 0 0 0 0 ] 0 MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 MM_W Store [0 0 0 0 0 0 0 0 ] 0 MM_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MM_W L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MM_W Ack [46123 45810 45642 45555 45697 45907 46418 45457 ] 366609 -MM_W All_acks_no_sharers [15418 15411 15413 15387 15338 15301 15408 15344 ] 123020 +MM_W L1_to_L2 [55 48 93 90 84 118 105 65 ] 658 +MM_W Ack [5222 5127 5236 5525 5374 5150 5095 5261 ] 41990 +MM_W All_acks_no_sharers [51591 51199 51239 51528 51674 51365 51607 51351 ] 411554 IS Load [0 0 0 0 0 0 0 0 ] 0 IS Ifetch [0 0 0 0 0 0 0 0 ] 0 IS Store [0 0 0 0 0 0 0 0 ] 0 IS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IS L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -IS Other_GETX [33543 33974 33691 33471 34029 34071 33576 33737 ] 270092 -IS Other_GETS [3 3 2 3 2 1 2 1 ] 17 +IS L1_to_L2 [1006185 1004923 1016403 1000684 998249 1007712 1004842 1002120 ] 8041118 +IS Other_GETX [3 4 3 2 3 1 8 0 ] 24 +IS Other_GETS [4 3 9 10 6 9 8 4 ] 53 IS Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +IS NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IS Invalidate [0 0 0 0 0 0 0 0 ] 0 -IS Ack [0 0 0 0 7 7 5 0 ] 19 -IS Shared_Ack [0 0 0 0 0 0 0 0 ] 0 -IS Data [0 0 0 0 0 0 0 0 ] 0 -IS Shared_Data [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130 -IS Exclusive_Data [0 0 0 0 1 1 1 0 ] 3 +IS Ack [682852 684688 686562 680152 680140 682667 680182 682564 ] 5459807 +IS Shared_Ack [115 113 114 100 103 93 103 120 ] 861 +IS Data [3880 3923 3822 3717 3729 3597 3626 3744 ] 30038 +IS Shared_Data [2067 2123 2065 2036 2070 1972 2052 2038 ] 16423 +IS Exclusive_Data [93428 93651 94051 93241 93204 93714 93373 93550 ] 748212 SS Load [0 0 0 0 0 0 0 0 ] 0 SS Ifetch [0 0 0 0 0 0 0 0 ] 0 SS Store [0 0 0 0 0 0 0 0 ] 0 SS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -SS L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -SS Ack [0 0 0 0 0 0 0 0 ] 0 -SS Shared_Ack [0 0 0 0 0 0 0 0 ] 0 -SS All_acks [10499 10486 10521 10455 10656 10482 10575 10456 ] 84130 -SS All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0 +SS L1_to_L2 [129 89 102 92 113 107 138 70 ] 840 +SS Ack [6064 6362 6273 5885 6198 5743 6078 6073 ] 48676 +SS Shared_Ack [8 9 6 1 9 4 7 6 ] 50 +SS All_acks [2171 2229 2168 2123 2163 2061 2147 2146 ] 17208 +SS All_acks_no_sharers [3776 3817 3719 3630 3636 3508 3531 3636 ] 29253 -OI Load [0 0 0 0 0 0 0 0 ] 0 +OI Load [0 1 0 0 0 0 2 1 ] 4 OI Ifetch [0 0 0 0 0 0 0 0 ] 0 -OI Store [0 0 0 0 0 0 0 0 ] 0 +OI Store [0 1 0 0 0 0 0 0 ] 1 OI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 OI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 OI Other_GETX [0 0 0 0 0 0 0 0 ] 0 OI Other_GETS [0 0 0 0 0 0 0 0 ] 0 OI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 OI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +OI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OI Invalidate [0 0 0 0 0 0 0 0 ] 0 -OI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Ack [2043 2032 1934 2034 2037 2122 1963 1941 ] 16106 -MI Load [0 0 0 0 0 0 0 0 ] 0 +MI Load [26 13 23 19 21 18 24 9 ] 153 MI Ifetch [0 0 0 0 0 0 0 0 ] 0 -MI Store [0 0 0 0 0 0 0 0 ] 0 +MI Store [13 9 9 6 13 10 14 11 ] 85 MI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 MI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MI Other_GETX [0 0 0 0 0 0 0 0 ] 0 -MI Other_GETS [0 0 0 0 0 0 0 0 ] 0 +MI Other_GETX [1 2 2 2 2 3 1 5 ] 18 +MI Other_GETS [1 2 6 4 3 4 4 4 ] 28 MI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 MI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MI NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MI Invalidate [0 0 0 0 0 0 0 0 ] 0 -MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack [142137 141764 142465 141859 142024 141971 142108 142044 ] 1136372 II Load [0 0 0 0 0 0 0 0 ] 0 II Ifetch [0 0 0 0 0 0 0 0 ] 0 @@ -559,68 +615,74 @@ II L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 II Other_GETX [0 0 0 0 0 0 0 0 ] 0 II Other_GETS [0 0 0 0 0 0 0 0 ] 0 II Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +II NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 II Invalidate [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Ack [1 2 2 2 2 3 1 5 ] 18 II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -IT Load [0 0 0 0 0 0 0 0 ] 0 +IT Load [3 1 4 1 1 1 0 3 ] 14 IT Ifetch [0 0 0 0 0 0 0 0 ] 0 -IT Store [0 0 0 0 0 0 0 0 ] 0 +IT Store [0 0 2 1 0 0 0 0 ] 3 IT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -IT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -IT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +IT L1_to_L2 [14 3 22 2 1 4 0 16 ] 62 +IT Complete_L2_to_L1 [5 2 8 5 6 2 1 4 ] 33 IT Other_GETX [0 0 0 0 0 0 0 0 ] 0 IT Other_GETS [0 0 0 0 0 0 0 0 ] 0 IT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 IT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +IT NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 IT Invalidate [0 0 0 0 0 0 0 0 ] 0 -ST Load [0 0 0 0 0 0 0 0 ] 0 +ST Load [2 3 1 2 3 3 3 3 ] 20 ST Ifetch [0 0 0 0 0 0 0 0 ] 0 -ST Store [0 0 0 0 0 0 0 0 ] 0 +ST Store [2 0 0 0 4 1 2 1 ] 10 ST L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -ST L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -ST Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +ST L1_to_L2 [23 6 9 13 42 48 24 46 ] 211 +ST Complete_L2_to_L1 [5 7 1 3 9 7 10 7 ] 49 ST Other_GETX [0 0 0 0 0 0 0 0 ] 0 ST Other_GETS [0 0 0 0 0 0 0 0 ] 0 ST Merged_GETS [0 0 0 0 0 0 0 0 ] 0 ST Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +ST NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 ST Invalidate [0 0 0 0 0 0 0 0 ] 0 -OT Load [0 0 0 0 0 0 0 0 ] 0 +OT Load [0 2 0 1 5 1 1 0 ] 10 OT Ifetch [0 0 0 0 0 0 0 0 ] 0 -OT Store [0 0 0 0 0 0 0 0 ] 0 +OT Store [0 2 1 0 1 0 3 0 ] 7 OT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -OT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -OT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +OT L1_to_L2 [0 15 0 10 23 8 16 0 ] 72 +OT Complete_L2_to_L1 [0 8 4 1 8 2 5 1 ] 29 OT Other_GETX [0 0 0 0 0 0 0 0 ] 0 OT Other_GETS [0 0 0 0 0 0 0 0 ] 0 OT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 OT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +OT NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 OT Invalidate [0 0 0 0 0 0 0 0 ] 0 -MT Load [0 0 0 0 0 0 0 0 ] 0 +MT Load [37 39 47 38 42 35 45 50 ] 333 MT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MT Store [0 0 0 0 0 0 0 0 ] 0 +MT Store [18 21 16 21 20 19 22 27 ] 164 MT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +MT L1_to_L2 [374 324 343 328 308 218 245 407 ] 2547 +MT Complete_L2_to_L1 [81 91 94 94 89 95 94 111 ] 749 MT Other_GETX [0 0 0 0 0 0 0 0 ] 0 MT Other_GETS [0 0 0 0 0 0 0 0 ] 0 MT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 MT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MT NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MT Invalidate [0 0 0 0 0 0 0 0 ] 0 -MMT Load [0 0 0 0 0 0 0 0 ] 0 +MMT Load [19 17 9 22 31 22 20 18 ] 158 MMT Ifetch [0 0 0 0 0 0 0 0 ] 0 -MMT Store [0 0 0 0 0 0 0 0 ] 0 +MMT Store [13 13 12 10 12 18 8 6 ] 92 MMT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 -MMT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 -MMT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +MMT L1_to_L2 [212 187 123 172 148 146 125 113 ] 1226 +MMT Complete_L2_to_L1 [52 42 41 48 68 56 52 45 ] 404 MMT Other_GETX [0 0 0 0 0 0 0 0 ] 0 MMT Other_GETS [0 0 0 0 0 0 0 0 ] 0 MMT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 MMT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MMT NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0 MMT Invalidate [0 0 0 0 0 0 0 0 ] 0 Cache Stats: system.l1_cntrl1.L1IcacheMemory @@ -632,28 +694,28 @@ Cache Stats: system.l1_cntrl1.L1IcacheMemory Cache Stats: system.l1_cntrl1.L1DcacheMemory - system.l1_cntrl1.L1DcacheMemory_total_misses: 27960 - system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 27960 + system.l1_cntrl1.L1DcacheMemory_total_misses: 152791 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 152791 system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L1DcacheMemory_request_type_LD: 37.4964% - system.l1_cntrl1.L1DcacheMemory_request_type_ST: 62.5036% + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 65.047% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 34.953% - system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode: 27960 100% + system.l1_cntrl1.L1DcacheMemory_access_mode_type_SupervisorMode: 152791 100% Cache Stats: system.l1_cntrl1.L2cacheMemory - system.l1_cntrl1.L2cacheMemory_total_misses: 27960 - system.l1_cntrl1.L2cacheMemory_total_demand_misses: 27960 + system.l1_cntrl1.L2cacheMemory_total_misses: 152791 + system.l1_cntrl1.L2cacheMemory_total_demand_misses: 152791 system.l1_cntrl1.L2cacheMemory_total_prefetches: 0 system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L2cacheMemory_request_type_LD: 37.4964% - system.l1_cntrl1.L2cacheMemory_request_type_ST: 62.5036% + system.l1_cntrl1.L2cacheMemory_request_type_LD: 65.047% + system.l1_cntrl1.L2cacheMemory_request_type_ST: 34.953% - system.l1_cntrl1.L2cacheMemory_access_mode_type_SupervisorMode: 27960 100% + system.l1_cntrl1.L2cacheMemory_access_mode_type_SupervisorMode: 152791 100% Cache Stats: system.l1_cntrl2.L1IcacheMemory system.l1_cntrl2.L1IcacheMemory_total_misses: 0 @@ -664,28 +726,28 @@ Cache Stats: system.l1_cntrl2.L1IcacheMemory Cache Stats: system.l1_cntrl2.L1DcacheMemory - system.l1_cntrl2.L1DcacheMemory_total_misses: 28157 - system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 28157 + system.l1_cntrl2.L1DcacheMemory_total_misses: 152865 + system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 152865 system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L1DcacheMemory_request_type_LD: 37.5608% - system.l1_cntrl2.L1DcacheMemory_request_type_ST: 62.4392% + system.l1_cntrl2.L1DcacheMemory_request_type_LD: 64.8723% + system.l1_cntrl2.L1DcacheMemory_request_type_ST: 35.1277% - system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode: 28157 100% + system.l1_cntrl2.L1DcacheMemory_access_mode_type_SupervisorMode: 152865 100% Cache Stats: system.l1_cntrl2.L2cacheMemory - system.l1_cntrl2.L2cacheMemory_total_misses: 28157 - system.l1_cntrl2.L2cacheMemory_total_demand_misses: 28157 + system.l1_cntrl2.L2cacheMemory_total_misses: 152865 + system.l1_cntrl2.L2cacheMemory_total_demand_misses: 152865 system.l1_cntrl2.L2cacheMemory_total_prefetches: 0 system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl2.L2cacheMemory_request_type_LD: 37.5608% - system.l1_cntrl2.L2cacheMemory_request_type_ST: 62.4392% + system.l1_cntrl2.L2cacheMemory_request_type_LD: 64.8723% + system.l1_cntrl2.L2cacheMemory_request_type_ST: 35.1277% - system.l1_cntrl2.L2cacheMemory_access_mode_type_SupervisorMode: 28157 100% + system.l1_cntrl2.L2cacheMemory_access_mode_type_SupervisorMode: 152865 100% Cache Stats: system.l1_cntrl3.L1IcacheMemory system.l1_cntrl3.L1IcacheMemory_total_misses: 0 @@ -696,28 +758,28 @@ Cache Stats: system.l1_cntrl3.L1IcacheMemory Cache Stats: system.l1_cntrl3.L1DcacheMemory - system.l1_cntrl3.L1DcacheMemory_total_misses: 27975 - system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 27975 + system.l1_cntrl3.L1DcacheMemory_total_misses: 152865 + system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 152865 system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L1DcacheMemory_request_type_LD: 37.3798% - system.l1_cntrl3.L1DcacheMemory_request_type_ST: 62.6202% + system.l1_cntrl3.L1DcacheMemory_request_type_LD: 65.0522% + system.l1_cntrl3.L1DcacheMemory_request_type_ST: 34.9478% - system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode: 27975 100% + system.l1_cntrl3.L1DcacheMemory_access_mode_type_SupervisorMode: 152865 100% Cache Stats: system.l1_cntrl3.L2cacheMemory - system.l1_cntrl3.L2cacheMemory_total_misses: 27975 - system.l1_cntrl3.L2cacheMemory_total_demand_misses: 27975 + system.l1_cntrl3.L2cacheMemory_total_misses: 152865 + system.l1_cntrl3.L2cacheMemory_total_demand_misses: 152865 system.l1_cntrl3.L2cacheMemory_total_prefetches: 0 system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl3.L2cacheMemory_request_type_LD: 37.3798% - system.l1_cntrl3.L2cacheMemory_request_type_ST: 62.6202% + system.l1_cntrl3.L2cacheMemory_request_type_LD: 65.0522% + system.l1_cntrl3.L2cacheMemory_request_type_ST: 34.9478% - system.l1_cntrl3.L2cacheMemory_access_mode_type_SupervisorMode: 27975 100% + system.l1_cntrl3.L2cacheMemory_access_mode_type_SupervisorMode: 152865 100% Cache Stats: system.l1_cntrl4.L1IcacheMemory system.l1_cntrl4.L1IcacheMemory_total_misses: 0 @@ -728,28 +790,28 @@ Cache Stats: system.l1_cntrl4.L1IcacheMemory Cache Stats: system.l1_cntrl4.L1DcacheMemory - system.l1_cntrl4.L1DcacheMemory_total_misses: 28045 - system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 28045 + system.l1_cntrl4.L1DcacheMemory_total_misses: 153182 + system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 153182 system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L1DcacheMemory_request_type_LD: 37.4398% - system.l1_cntrl4.L1DcacheMemory_request_type_ST: 62.5602% + system.l1_cntrl4.L1DcacheMemory_request_type_LD: 64.9371% + system.l1_cntrl4.L1DcacheMemory_request_type_ST: 35.0629% - system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode: 28045 100% + system.l1_cntrl4.L1DcacheMemory_access_mode_type_SupervisorMode: 153182 100% Cache Stats: system.l1_cntrl4.L2cacheMemory - system.l1_cntrl4.L2cacheMemory_total_misses: 28045 - system.l1_cntrl4.L2cacheMemory_total_demand_misses: 28045 + system.l1_cntrl4.L2cacheMemory_total_misses: 153182 + system.l1_cntrl4.L2cacheMemory_total_demand_misses: 153182 system.l1_cntrl4.L2cacheMemory_total_prefetches: 0 system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl4.L2cacheMemory_request_type_LD: 37.4398% - system.l1_cntrl4.L2cacheMemory_request_type_ST: 62.5602% + system.l1_cntrl4.L2cacheMemory_request_type_LD: 64.9371% + system.l1_cntrl4.L2cacheMemory_request_type_ST: 35.0629% - system.l1_cntrl4.L2cacheMemory_access_mode_type_SupervisorMode: 28045 100% + system.l1_cntrl4.L2cacheMemory_access_mode_type_SupervisorMode: 153182 100% Cache Stats: system.l1_cntrl5.L1IcacheMemory system.l1_cntrl5.L1IcacheMemory_total_misses: 0 @@ -760,28 +822,28 @@ Cache Stats: system.l1_cntrl5.L1IcacheMemory Cache Stats: system.l1_cntrl5.L1DcacheMemory - system.l1_cntrl5.L1DcacheMemory_total_misses: 27996 - system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 27996 + system.l1_cntrl5.L1DcacheMemory_total_misses: 153033 + system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 153033 system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L1DcacheMemory_request_type_LD: 37.4589% - system.l1_cntrl5.L1DcacheMemory_request_type_ST: 62.5411% + system.l1_cntrl5.L1DcacheMemory_request_type_LD: 65.2088% + system.l1_cntrl5.L1DcacheMemory_request_type_ST: 34.7912% - system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode: 27996 100% + system.l1_cntrl5.L1DcacheMemory_access_mode_type_SupervisorMode: 153033 100% Cache Stats: system.l1_cntrl5.L2cacheMemory - system.l1_cntrl5.L2cacheMemory_total_misses: 27996 - system.l1_cntrl5.L2cacheMemory_total_demand_misses: 27996 + system.l1_cntrl5.L2cacheMemory_total_misses: 153033 + system.l1_cntrl5.L2cacheMemory_total_demand_misses: 153033 system.l1_cntrl5.L2cacheMemory_total_prefetches: 0 system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl5.L2cacheMemory_request_type_LD: 37.4589% - system.l1_cntrl5.L2cacheMemory_request_type_ST: 62.5411% + system.l1_cntrl5.L2cacheMemory_request_type_LD: 65.2088% + system.l1_cntrl5.L2cacheMemory_request_type_ST: 34.7912% - system.l1_cntrl5.L2cacheMemory_access_mode_type_SupervisorMode: 27996 100% + system.l1_cntrl5.L2cacheMemory_access_mode_type_SupervisorMode: 153033 100% Cache Stats: system.l1_cntrl6.L1IcacheMemory system.l1_cntrl6.L1IcacheMemory_total_misses: 0 @@ -792,28 +854,28 @@ Cache Stats: system.l1_cntrl6.L1IcacheMemory Cache Stats: system.l1_cntrl6.L1DcacheMemory - system.l1_cntrl6.L1DcacheMemory_total_misses: 28036 - system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 28036 + system.l1_cntrl6.L1DcacheMemory_total_misses: 153339 + system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 153339 system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L1DcacheMemory_request_type_LD: 37.5268% - system.l1_cntrl6.L1DcacheMemory_request_type_ST: 62.4732% + system.l1_cntrl6.L1DcacheMemory_request_type_LD: 65.2345% + system.l1_cntrl6.L1DcacheMemory_request_type_ST: 34.7655% - system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode: 28036 100% + system.l1_cntrl6.L1DcacheMemory_access_mode_type_SupervisorMode: 153339 100% Cache Stats: system.l1_cntrl6.L2cacheMemory - system.l1_cntrl6.L2cacheMemory_total_misses: 28036 - system.l1_cntrl6.L2cacheMemory_total_demand_misses: 28036 + system.l1_cntrl6.L2cacheMemory_total_misses: 153339 + system.l1_cntrl6.L2cacheMemory_total_demand_misses: 153339 system.l1_cntrl6.L2cacheMemory_total_prefetches: 0 system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl6.L2cacheMemory_request_type_LD: 37.5268% - system.l1_cntrl6.L2cacheMemory_request_type_ST: 62.4732% + system.l1_cntrl6.L2cacheMemory_request_type_LD: 65.2345% + system.l1_cntrl6.L2cacheMemory_request_type_ST: 34.7655% - system.l1_cntrl6.L2cacheMemory_access_mode_type_SupervisorMode: 28036 100% + system.l1_cntrl6.L2cacheMemory_access_mode_type_SupervisorMode: 153339 100% Cache Stats: system.l1_cntrl7.L1IcacheMemory system.l1_cntrl7.L1IcacheMemory_total_misses: 0 @@ -824,28 +886,28 @@ Cache Stats: system.l1_cntrl7.L1IcacheMemory Cache Stats: system.l1_cntrl7.L1DcacheMemory - system.l1_cntrl7.L1DcacheMemory_total_misses: 28038 - system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 28038 + system.l1_cntrl7.L1DcacheMemory_total_misses: 152687 + system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 152687 system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L1DcacheMemory_request_type_LD: 37.2887% - system.l1_cntrl7.L1DcacheMemory_request_type_ST: 62.7113% + system.l1_cntrl7.L1DcacheMemory_request_type_LD: 64.8994% + system.l1_cntrl7.L1DcacheMemory_request_type_ST: 35.1006% - system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode: 28038 100% + system.l1_cntrl7.L1DcacheMemory_access_mode_type_SupervisorMode: 152687 100% Cache Stats: system.l1_cntrl7.L2cacheMemory - system.l1_cntrl7.L2cacheMemory_total_misses: 28038 - system.l1_cntrl7.L2cacheMemory_total_demand_misses: 28038 + system.l1_cntrl7.L2cacheMemory_total_misses: 152687 + system.l1_cntrl7.L2cacheMemory_total_demand_misses: 152687 system.l1_cntrl7.L2cacheMemory_total_prefetches: 0 system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl7.L2cacheMemory_request_type_LD: 37.2887% - system.l1_cntrl7.L2cacheMemory_request_type_ST: 62.7113% + system.l1_cntrl7.L2cacheMemory_request_type_LD: 64.8994% + system.l1_cntrl7.L2cacheMemory_request_type_ST: 35.1006% - system.l1_cntrl7.L2cacheMemory_access_mode_type_SupervisorMode: 28038 100% + system.l1_cntrl7.L2cacheMemory_access_mode_type_SupervisorMode: 152687 100% Cache Stats: system.dir_cntrl0.probeFilter system.dir_cntrl0.probeFilter_total_misses: 0 @@ -856,42 +918,42 @@ Cache Stats: system.dir_cntrl0.probeFilter Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 2 - memory_reads: 2 - memory_writes: 0 - memory_refreshes: 22 - memory_total_request_delays: 31 - memory_delays_per_request: 15.5 - memory_delays_in_input_queue: 1 - memory_delays_behind_head_of_bank_queue: 10 - memory_delays_stalled_at_head_of_bank_queue: 20 - memory_stalls_for_bank_busy: 20 + memory_total_requests: 1605206 + memory_reads: 1182555 + memory_writes: 422632 + memory_refreshes: 79291 + memory_total_request_delays: 102402684 + memory_delays_per_request: 63.7941 + memory_delays_in_input_queue: 1299437 + memory_delays_behind_head_of_bank_queue: 41856577 + memory_delays_stalled_at_head_of_bank_queue: 59246670 + memory_stalls_for_bank_busy: 8937619 memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 0 - memory_stalls_for_bus: 0 + memory_stalls_for_anti_starvation: 15070759 + memory_stalls_for_arbitration: 12094661 + memory_stalls_for_bus: 16398548 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 0 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + memory_stalls_for_read_write_turnaround: 4057082 + memory_stalls_for_read_read_turnaround: 2688001 + accesses_per_bank: 50458 50374 50220 50357 50425 50704 50742 49982 50496 50326 50505 50322 50256 50180 50160 49801 50242 49867 50410 49981 49983 50012 49966 49937 50095 49827 49802 49652 50037 49876 50349 49862 --- Directory --- - Event Counts - -GETX [829725 ] 829725 -GETS [354236 ] 354236 -PUT [0 ] 0 -Unblock [0 ] 0 -UnblockS [84130 ] 84130 -UnblockM [140228 ] 140228 -Writeback_Clean [0 ] 0 -Writeback_Dirty [0 ] 0 -Writeback_Exclusive_Clean [0 ] 0 -Writeback_Exclusive_Dirty [0 ] 0 +GETX [434154 ] 434154 +GETS [806552 ] 806552 +PUT [1152892 ] 1152892 +Unblock [18 ] 18 +UnblockS [46460 ] 46460 +UnblockM [1175952 ] 1175952 +Writeback_Clean [15933 ] 15933 +Writeback_Dirty [173 ] 173 +Writeback_Exclusive_Clean [713909 ] 713909 +Writeback_Exclusive_Dirty [422463 ] 422463 Pf_Replacement [0 ] 0 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -Memory_Data [2 ] 2 -Memory_Ack [0 ] 0 +Memory_Data [1182550 ] 1182550 +Memory_Ack [422632 ] 422632 Ack [0 ] 0 Shared_Ack [0 ] 0 Shared_Data [0 ] 0 @@ -900,19 +962,19 @@ Exclusive_Data [0 ] 0 All_acks_and_shared_data [0 ] 0 All_acks_and_owner_data [0 ] 0 All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [17206 ] 17206 +All_Unblocks [69 ] 69 - Transitions - -NX GETX [17206 ] 17206 -NX GETS [0 ] 0 -NX PUT [0 ] 0 +NX GETX [124 ] 124 +NX GETS [185 ] 185 +NX PUT [16124 ] 16124 NX Pf_Replacement [0 ] 0 NX DMA_READ [0 ] 0 NX DMA_WRITE [0 ] 0 -NO GETX [123021 ] 123021 -NO GETS [1 ] 1 -NO PUT [0 ] 0 +NO GETX [14020 ] 14020 +NO GETS [25465 ] 25465 +NO PUT [1136372 ] 1136372 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 @@ -924,15 +986,15 @@ S Pf_Replacement [0 ] 0 S DMA_READ [0 ] 0 S DMA_WRITE [0 ] 0 -O GETX [0 ] 0 -O GETS [0 ] 0 +O GETX [16045 ] 16045 +O GETS [30010 ] 30010 O PUT [0 ] 0 O Pf_Replacement [0 ] 0 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 -E GETX [0 ] 0 -E GETS [2 ] 2 +E GETX [397555 ] 397555 +E GETS [738960 ] 738960 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 @@ -967,66 +1029,69 @@ NO_R Data [0 ] 0 NO_R Exclusive_Data [0 ] 0 NO_R All_acks_and_data_no_sharers [0 ] 0 -NO_B GETX [123022 ] 123022 -NO_B GETS [17206 ] 17206 -NO_B PUT [0 ] 0 -NO_B UnblockS [0 ] 0 -NO_B UnblockM [2 ] 2 +NO_B GETX [44 ] 44 +NO_B GETS [69 ] 69 +NO_B PUT [395 ] 395 +NO_B UnblockS [16331 ] 16331 +NO_B UnblockM [1175890 ] 1175890 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 -NO_B_X GETX [468040 ] 468040 -NO_B_X GETS [270091 ] 270091 +NO_B_X GETX [0 ] 0 +NO_B_X GETS [0 ] 0 NO_B_X PUT [0 ] 0 -NO_B_X UnblockS [0 ] 0 -NO_B_X UnblockM [123020 ] 123020 +NO_B_X UnblockS [16 ] 16 +NO_B_X UnblockM [28 ] 28 NO_B_X Pf_Replacement [0 ] 0 +NO_B_X DMA_READ [0 ] 0 +NO_B_X DMA_WRITE [0 ] 0 -NO_B_S GETX [36312 ] 36312 -NO_B_S GETS [66924 ] 66924 +NO_B_S GETX [0 ] 0 +NO_B_S GETS [0 ] 0 NO_B_S PUT [0 ] 0 -NO_B_S UnblockS [0 ] 0 -NO_B_S UnblockM [17206 ] 17206 +NO_B_S UnblockS [35 ] 35 +NO_B_S UnblockM [34 ] 34 NO_B_S Pf_Replacement [0 ] 0 NO_B_S DMA_READ [0 ] 0 NO_B_S DMA_WRITE [0 ] 0 -NO_B_S_W GETX [62122 ] 62122 +NO_B_S_W GETX [0 ] 0 NO_B_S_W GETS [0 ] 0 -NO_B_S_W PUT [0 ] 0 -NO_B_S_W UnblockS [84130 ] 84130 +NO_B_S_W PUT [1 ] 1 +NO_B_S_W UnblockS [69 ] 69 NO_B_S_W Pf_Replacement [0 ] 0 NO_B_S_W DMA_READ [0 ] 0 NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [17206 ] 17206 +NO_B_S_W All_Unblocks [69 ] 69 O_B GETX [0 ] 0 O_B GETS [0 ] 0 O_B PUT [0 ] 0 -O_B UnblockS [0 ] 0 +O_B UnblockS [30009 ] 30009 +O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 -NO_B_W GETX [2 ] 2 -NO_B_W GETS [12 ] 12 +NO_B_W GETX [3976 ] 3976 +NO_B_W GETS [7420 ] 7420 NO_B_W PUT [0 ] 0 NO_B_W UnblockS [0 ] 0 NO_B_W UnblockM [0 ] 0 NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [2 ] 2 +NO_B_W Memory_Data [1152540 ] 1152540 -O_B_W GETX [0 ] 0 -O_B_W GETS [0 ] 0 +O_B_W GETX [103 ] 103 +O_B_W GETS [194 ] 194 O_B_W PUT [0 ] 0 O_B_W UnblockS [0 ] 0 O_B_W Pf_Replacement [0 ] 0 O_B_W DMA_READ [0 ] 0 O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [0 ] 0 +O_B_W Memory_Data [30010 ] 30010 NO_W GETX [0 ] 0 NO_W GETS [0 ] 0 @@ -1127,14 +1192,14 @@ O_DR_B Shared_Ack [0 ] 0 O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 -WB GETX [0 ] 0 -WB GETS [0 ] 0 +WB GETX [171 ] 171 +WB GETS [322 ] 322 WB PUT [0 ] 0 -WB Unblock [0 ] 0 -WB Writeback_Clean [0 ] 0 -WB Writeback_Dirty [0 ] 0 -WB Writeback_Exclusive_Clean [0 ] 0 -WB Writeback_Exclusive_Dirty [0 ] 0 +WB Unblock [18 ] 18 +WB Writeback_Clean [15933 ] 15933 +WB Writeback_Dirty [173 ] 173 +WB Writeback_Exclusive_Clean [713909 ] 713909 +WB Writeback_Exclusive_Dirty [422463 ] 422463 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 @@ -1145,10 +1210,10 @@ WB_O_W PUT [0 ] 0 WB_O_W Pf_Replacement [0 ] 0 WB_O_W DMA_READ [0 ] 0 WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [0 ] 0 +WB_O_W Memory_Ack [173 ] 173 -WB_E_W GETX [0 ] 0 -WB_E_W GETS [0 ] 0 +WB_E_W GETX [2116 ] 2116 +WB_E_W GETS [3927 ] 3927 WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr index 1aa1be599..894fb5f71 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr @@ -1,74 +1,74 @@ -system.cpu2: completed 10000 read accesses @332309 -system.cpu0: completed 10000 read accesses @332762 -system.cpu3: completed 10000 read accesses @333275 -system.cpu7: completed 10000 read accesses @334660 -system.cpu4: completed 10000 read accesses @336400 -system.cpu6: completed 10000 read accesses @336827 -system.cpu1: completed 10000 read accesses @336833 -system.cpu5: completed 10000 read accesses @339345 -system.cpu3: completed 20000 read accesses @659139 -system.cpu0: completed 20000 read accesses @662762 -system.cpu2: completed 20000 read accesses @662918 -system.cpu4: completed 20000 read accesses @663822 -system.cpu6: completed 20000 read accesses @664214 -system.cpu7: completed 20000 read accesses @673557 -system.cpu1: completed 20000 read accesses @673720 -system.cpu5: completed 20000 read accesses @675222 -system.cpu3: completed 30000 read accesses @990404 -system.cpu6: completed 30000 read accesses @991868 -system.cpu0: completed 30000 read accesses @993980 -system.cpu2: completed 30000 read accesses @994621 -system.cpu4: completed 30000 read accesses @995936 -system.cpu5: completed 30000 read accesses @1005609 -system.cpu1: completed 30000 read accesses @1008145 -system.cpu7: completed 30000 read accesses @1008840 -system.cpu6: completed 40000 read accesses @1322251 -system.cpu0: completed 40000 read accesses @1324139 -system.cpu3: completed 40000 read accesses @1324341 -system.cpu2: completed 40000 read accesses @1325019 -system.cpu4: completed 40000 read accesses @1328462 -system.cpu5: completed 40000 read accesses @1335869 -system.cpu1: completed 40000 read accesses @1336407 -system.cpu7: completed 40000 read accesses @1342910 -system.cpu6: completed 50000 read accesses @1654106 -system.cpu0: completed 50000 read accesses @1654925 -system.cpu3: completed 50000 read accesses @1657897 -system.cpu2: completed 50000 read accesses @1658205 -system.cpu1: completed 50000 read accesses @1668347 -system.cpu5: completed 50000 read accesses @1668465 -system.cpu4: completed 50000 read accesses @1670315 -system.cpu7: completed 50000 read accesses @1681232 -system.cpu6: completed 60000 read accesses @1984633 -system.cpu0: completed 60000 read accesses @1986549 -system.cpu2: completed 60000 read accesses @1989981 -system.cpu3: completed 60000 read accesses @1993690 -system.cpu1: completed 60000 read accesses @2001694 -system.cpu4: completed 60000 read accesses @2002313 -system.cpu5: completed 60000 read accesses @2005561 -system.cpu7: completed 60000 read accesses @2014675 -system.cpu6: completed 70000 read accesses @2317222 -system.cpu0: completed 70000 read accesses @2318277 -system.cpu2: completed 70000 read accesses @2322048 -system.cpu3: completed 70000 read accesses @2324750 -system.cpu4: completed 70000 read accesses @2332151 -system.cpu1: completed 70000 read accesses @2332386 -system.cpu5: completed 70000 read accesses @2332911 -system.cpu7: completed 70000 read accesses @2343337 -system.cpu0: completed 80000 read accesses @2646207 -system.cpu6: completed 80000 read accesses @2646561 -system.cpu3: completed 80000 read accesses @2652685 -system.cpu2: completed 80000 read accesses @2655532 -system.cpu5: completed 80000 read accesses @2662477 -system.cpu4: completed 80000 read accesses @2665813 -system.cpu7: completed 80000 read accesses @2668350 -system.cpu1: completed 80000 read accesses @2668666 -system.cpu6: completed 90000 read accesses @2976982 -system.cpu0: completed 90000 read accesses @2982010 -system.cpu2: completed 90000 read accesses @2983845 -system.cpu3: completed 90000 read accesses @2993125 -system.cpu5: completed 90000 read accesses @2995492 -system.cpu4: completed 90000 read accesses @2998220 -system.cpu7: completed 90000 read accesses @3003787 -system.cpu1: completed 90000 read accesses @3004322 -system.cpu6: completed 100000 read accesses @3305503 +system.cpu5: completed 10000 read accesses @3773579 +system.cpu6: completed 10000 read accesses @3800919 +system.cpu4: completed 10000 read accesses @3806319 +system.cpu7: completed 10000 read accesses @3815919 +system.cpu3: completed 10000 read accesses @3847469 +system.cpu1: completed 10000 read accesses @3858049 +system.cpu2: completed 10000 read accesses @3865769 +system.cpu0: completed 10000 read accesses @3909119 +system.cpu6: completed 20000 read accesses @7545009 +system.cpu5: completed 20000 read accesses @7578569 +system.cpu3: completed 20000 read accesses @7650419 +system.cpu4: completed 20000 read accesses @7653039 +system.cpu7: completed 20000 read accesses @7660349 +system.cpu1: completed 20000 read accesses @7666509 +system.cpu2: completed 20000 read accesses @7676969 +system.cpu0: completed 20000 read accesses @7778949 +system.cpu5: completed 30000 read accesses @11400279 +system.cpu6: completed 30000 read accesses @11403319 +system.cpu3: completed 30000 read accesses @11463329 +system.cpu4: completed 30000 read accesses @11476649 +system.cpu1: completed 30000 read accesses @11482109 +system.cpu2: completed 30000 read accesses @11515599 +system.cpu7: completed 30000 read accesses @11523379 +system.cpu0: completed 30000 read accesses @11644619 +system.cpu6: completed 40000 read accesses @15163509 +system.cpu5: completed 40000 read accesses @15247859 +system.cpu1: completed 40000 read accesses @15285159 +system.cpu4: completed 40000 read accesses @15331509 +system.cpu2: completed 40000 read accesses @15338199 +system.cpu3: completed 40000 read accesses @15352259 +system.cpu7: completed 40000 read accesses @15377169 +system.cpu0: completed 40000 read accesses @15448399 +system.cpu6: completed 50000 read accesses @18963379 +system.cpu5: completed 50000 read accesses @19066919 +system.cpu1: completed 50000 read accesses @19138729 +system.cpu3: completed 50000 read accesses @19175839 +system.cpu4: completed 50000 read accesses @19193269 +system.cpu2: completed 50000 read accesses @19229269 +system.cpu0: completed 50000 read accesses @19286699 +system.cpu7: completed 50000 read accesses @19288339 +system.cpu6: completed 60000 read accesses @22830379 +system.cpu5: completed 60000 read accesses @22876169 +system.cpu1: completed 60000 read accesses @22895139 +system.cpu4: completed 60000 read accesses @23008339 +system.cpu3: completed 60000 read accesses @23024099 +system.cpu2: completed 60000 read accesses @23042669 +system.cpu7: completed 60000 read accesses @23113989 +system.cpu0: completed 60000 read accesses @23166249 +system.cpu6: completed 70000 read accesses @26656369 +system.cpu5: completed 70000 read accesses @26704159 +system.cpu1: completed 70000 read accesses @26732409 +system.cpu4: completed 70000 read accesses @26782879 +system.cpu3: completed 70000 read accesses @26845059 +system.cpu2: completed 70000 read accesses @26884599 +system.cpu7: completed 70000 read accesses @26960819 +system.cpu0: completed 70000 read accesses @26960869 +system.cpu6: completed 80000 read accesses @30376569 +system.cpu5: completed 80000 read accesses @30517259 +system.cpu4: completed 80000 read accesses @30578729 +system.cpu1: completed 80000 read accesses @30606099 +system.cpu3: completed 80000 read accesses @30658599 +system.cpu2: completed 80000 read accesses @30711719 +system.cpu0: completed 80000 read accesses @30713219 +system.cpu7: completed 80000 read accesses @30760569 +system.cpu6: completed 90000 read accesses @34228379 +system.cpu5: completed 90000 read accesses @34328029 +system.cpu4: completed 90000 read accesses @34428059 +system.cpu1: completed 90000 read accesses @34475699 +system.cpu3: completed 90000 read accesses @34504539 +system.cpu0: completed 90000 read accesses @34548119 +system.cpu7: completed 90000 read accesses @34567549 +system.cpu2: completed 90000 read accesses @34597039 +system.cpu6: completed 100000 read accesses @38059429 hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 9fe27411d..33243fda5 100755 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 20 2010 12:17:38 -M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates -M5 started Aug 20 2010 12:17:55 -M5 executing on SC2B0629 +M5 compiled Feb 8 2011 17:56:59 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:57:03 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3305503 because maximum number of loads reached +Exiting @ tick 38059429 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index d441ad68e..72aea01e6 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 341640 # Number of bytes of host memory used -host_seconds 37.52 # Real time elapsed on the host -host_tick_rate 88100 # Simulator tick rate (ticks/s) +host_mem_usage 345444 # Number of bytes of host memory used +host_seconds 247.62 # Real time elapsed on the host +host_tick_rate 153698 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003306 # Number of seconds simulated -sim_ticks 3305503 # Number of ticks simulated +sim_seconds 0.038059 # Number of seconds simulated +sim_ticks 38059429 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99692 # number of read accesses completed -system.cpu0.num_writes 53673 # number of write accesses completed +system.cpu0.num_reads 99072 # number of read accesses completed +system.cpu0.num_writes 53787 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99062 # number of read accesses completed -system.cpu1.num_writes 53374 # number of write accesses completed +system.cpu1.num_reads 99360 # number of read accesses completed +system.cpu1.num_writes 53383 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99665 # number of read accesses completed -system.cpu2.num_writes 53906 # number of write accesses completed +system.cpu2.num_reads 99132 # number of read accesses completed +system.cpu2.num_writes 53677 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99457 # number of read accesses completed -system.cpu3.num_writes 53389 # number of write accesses completed +system.cpu3.num_reads 99402 # number of read accesses completed +system.cpu3.num_writes 53396 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99209 # number of read accesses completed -system.cpu4.num_writes 53779 # number of write accesses completed +system.cpu4.num_reads 99445 # number of read accesses completed +system.cpu4.num_writes 53699 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99375 # number of read accesses completed -system.cpu5.num_writes 53528 # number of write accesses completed +system.cpu5.num_reads 99752 # number of read accesses completed +system.cpu5.num_writes 53216 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 53388 # number of write accesses completed +system.cpu6.num_writes 53289 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99219 # number of read accesses completed -system.cpu7.num_writes 53946 # number of write accesses completed +system.cpu7.num_reads 99050 # number of read accesses completed +system.cpu7.num_writes 53576 # number of write accesses completed ---------- End Simulation Statistics ---------- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini index d0385930a..f899b1907 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.dir_cntrl0] type=Directory_Controller @@ -130,6 +139,7 @@ tracer=system.ruby.tracer [system.ruby.cpu_ruby_ports] type=RubySequencer +access_phys_mem=true dcache=system.l1_cntrl0.L1DcacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.L1IcacheMemory diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats index 4c6a0f41e..48846b6c8 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/13/2011 22:36:32 +Real time: Feb/08/2011 17:31:55 Profiler Stats -------------- -Elapsed_time_in_seconds: 2 -Elapsed_time_in_minutes: 0.0333333 -Elapsed_time_in_hours: 0.000555556 -Elapsed_time_in_days: 2.31481e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 2.32 -Virtual_time_in_minutes: 0.0386667 -Virtual_time_in_hours: 0.000644444 -Virtual_time_in_days: 2.68519e-05 +Virtual_time_in_seconds: 0.79 +Virtual_time_in_minutes: 0.0131667 +Virtual_time_in_hours: 0.000219444 +Virtual_time_in_days: 9.14352e-06 Ruby_current_time: 352261 Ruby_start_time: 0 Ruby_cycles: 352261 -mbytes_resident: 19.4023 -mbytes_total: 155.219 -resident_ratio: 0.12505 +mbytes_resident: 33.6719 +mbytes_total: 208.004 +resident_ratio: 0.161956 ruby_cycles_executed: [ 352262 ] @@ -117,9 +117,9 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4457 average: 0 | standa Resource Usage -------------- page_size: 4096 -user_time: 2 +user_time: 0 system_time: 0 -page_reclaims: 5638 +page_reclaims: 9831 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout index 866f889aa..b6aef8b2e 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jan 13 2011 22:36:25 -M5 revision 81b32f1a8f29 7836 default MESI_CMP_update_ref.patch qtip tip -M5 started Jan 13 2011 22:36:30 -M5 executing on scamorza.cs.wisc.edu +M5 compiled Feb 8 2011 17:31:51 +M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:31:55 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index ea583927f..bf0d1f08a 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 158948 # Number of bytes of host memory used -host_seconds 1.84 # Real time elapsed on the host -host_tick_rate 191255 # Simulator tick rate (ticks/s) +host_mem_usage 213000 # Number of bytes of host memory used +host_seconds 0.47 # Real time elapsed on the host +host_tick_rate 753338 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_seconds 0.000352 # Number of seconds simulated sim_ticks 352261 # Number of ticks simulated diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini index f737a2a36..326e421d1 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.dir_cntrl0] type=Directory_Controller @@ -52,32 +61,19 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory buffer_size=0 l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 request_latency=2 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.l1_cntrl0.sequencer.dcache] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=3 @@ -85,7 +81,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=3 @@ -121,14 +117,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -138,13 +133,18 @@ randomization=true stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] [system.ruby.network] type=SimpleNetwork @@ -160,9 +160,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -name=Crossbar num_int_nodes=4 print_config=false @@ -224,3 +224,10 @@ num_of_sequencers=1 type=RubyTracer warmup_length=100000 +[system.tester] +type=RubyTester +checks_to_complete=100 +deadlock_threshold=50000 +wakeup_frequency=10 +cpuPort=system.ruby.cpu_ruby_ports.port[0] + diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats index 8aa6f62e7..034586735 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:40:25 +Real time: Feb/08/2011 17:41:43 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0.0166667 Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 1.03 -Virtual_time_in_minutes: 0.0171667 -Virtual_time_in_hours: 0.000286111 -Virtual_time_in_days: 1.19213e-05 +Virtual_time_in_seconds: 0.8 +Virtual_time_in_minutes: 0.0133333 +Virtual_time_in_hours: 0.000222222 +Virtual_time_in_days: 9.25926e-06 Ruby_current_time: 372291 Ruby_start_time: 0 Ruby_cycles: 372291 -mbytes_resident: 31.6016 -mbytes_total: 31.6094 -resident_ratio: 1 +mbytes_resident: 33.7734 +mbytes_total: 208.148 +resident_ratio: 0.162313 ruby_cycles_executed: [ 372292 ] @@ -119,8 +119,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7050 -page_faults: 1907 +page_reclaims: 9846 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -201,20 +201,20 @@ links_utilized_percent_switch_3: 0.174693 outgoing_messages_switch_3_link_2_Writeback_Control: 953 7624 [ 0 874 79 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 0 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 --- L1Cache --- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout index f20a07162..835c245b9 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 10:34:54 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:40:24 -M5 executing on svvint09 +M5 compiled Feb 8 2011 17:41:34 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:41:42 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index c117a9137..e7af0eda4 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 210064 # Number of bytes of host memory used -host_seconds 0.80 # Real time elapsed on the host -host_tick_rate 465329 # Simulator tick rate (ticks/s) +host_mem_usage 213148 # Number of bytes of host memory used +host_seconds 0.50 # Real time elapsed on the host +host_tick_rate 746373 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_seconds 0.000372 # Number of seconds simulated sim_ticks 372291 # Number of ticks simulated diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini index e21f56989..76dc82aa2 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini @@ -1,13 +1,22 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby tester mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.dir_cntrl0] type=Directory_Controller @@ -55,9 +64,9 @@ version=0 [system.l1_cntrl0] type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L1DcacheMemory L1IcacheMemory +L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory +L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory N_tokens=2 buffer_size=0 dynamic_timeout_enabled=true @@ -69,24 +78,11 @@ no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 retry_threshold=1 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.l1_cntrl0.sequencer.dcache] +[system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 latency=2 @@ -94,7 +90,7 @@ replacement_policy=PSEUDO_LRU size=256 start_index_bit=6 -[system.l1_cntrl0.sequencer.icache] +[system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 latency=2 @@ -132,14 +128,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -149,13 +144,18 @@ randomization=true stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.L1DcacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.L1IcacheMemory +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] [system.ruby.network] type=SimpleNetwork @@ -171,9 +171,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -name=Crossbar num_int_nodes=4 print_config=false @@ -235,3 +235,10 @@ num_of_sequencers=1 type=RubyTracer warmup_length=100000 +[system.tester] +type=RubyTester +checks_to_complete=100 +deadlock_threshold=50000 +wakeup_frequency=10 +cpuPort=system.ruby.cpu_ruby_ports.port[0] + diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats index 10b36c0bf..0c7ecf183 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, ordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 10:45:27 +Real time: Feb/08/2011 17:51:05 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.75 -Virtual_time_in_minutes: 0.0125 -Virtual_time_in_hours: 0.000208333 -Virtual_time_in_days: 8.68056e-06 +Virtual_time_in_seconds: 0.43 +Virtual_time_in_minutes: 0.00716667 +Virtual_time_in_hours: 0.000119444 +Virtual_time_in_days: 4.97685e-06 -Ruby_current_time: 273851 +Ruby_current_time: 267511 Ruby_start_time: 0 -Ruby_cycles: 273851 +Ruby_cycles: 267511 -mbytes_resident: 31.5859 -mbytes_total: 31.5938 -resident_ratio: 1 +mbytes_resident: 33.7617 +mbytes_total: 208.121 +resident_ratio: 0.162259 -ruby_cycles_executed: [ 273852 ] +ruby_cycles_executed: [ 267512 ] Busy Controller Counts: L1Cache-0:0 @@ -66,17 +66,17 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1015 average: 15.8108 | standard deviation: 1.12266 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 71 929 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 969 average: 15.8225 | standard deviation: 1.14181 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 53 902 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 256 max: 25954 count: 1000 average: 4306.83 | standard deviation: 6237.5 | 90 103 157 85 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 8 max: 1385 count: 59 average: 543.102 | standard deviation: 246.871 | 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 1 1 2 0 1 0 6 3 1 0 0 0 0 0 1 1 2 1 1 3 2 0 0 0 0 0 1 1 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 128 max: 21253 count: 41 average: 5185.15 | standard deviation: 6664.34 | 3 0 2 1 2 3 5 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_ST: [binsize: 256 max: 25954 count: 900 average: 4513.56 | standard deviation: 6344.01 | 83 72 134 72 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 115 count: 78 average: 10.8205 | standard deviation: 28.5871 | 0 16 15 20 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ] -miss_latency_L2Cache: [binsize: 8 max: 1002 count: 20 average: 461.5 | standard deviation: 273.391 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Directory: [binsize: 256 max: 25954 count: 902 average: 4763.59 | standard deviation: 6403.26 | 6 96 154 81 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 64 max: 6580 count: 954 average: 4444.74 | standard deviation: 1862.02 | 67 9 3 1 6 4 9 12 10 7 1 8 5 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1214 count: 48 average: 548.458 | standard deviation: 260.39 | 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 1 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 32 max: 6135 count: 52 average: 4940.85 | standard deviation: 1334.03 | 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ] +miss_latency_ST: [binsize: 64 max: 6580 count: 854 average: 4633.53 | standard deviation: 1690.7 | 62 8 1 0 3 2 5 7 3 2 0 1 1 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 117 count: 73 average: 12.8356 | standard deviation: 32.0687 | 0 17 17 15 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 2 ] +miss_latency_L2Cache: [binsize: 8 max: 812 count: 13 average: 309.154 | standard deviation: 223.678 | 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 2 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 64 max: 6580 count: 868 average: 4879.41 | standard deviation: 1307.99 | 0 0 1 1 4 2 7 12 10 6 1 8 4 1 3 0 1 1 1 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 2 0 4 2 0 3 3 7 8 7 10 19 13 19 31 34 41 31 33 38 49 47 50 44 30 44 35 33 34 26 17 12 12 14 21 8 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -86,16 +86,15 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_dir_Times: 902 -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 1 average: 4 | standard deviation: 0 | 0 0 0 0 1 ] -miss_latency_IFETCH_L2Cache: [binsize: 4 max: 568 count: 7 average: 329.571 | standard deviation: 182.864 | 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_Directory: [binsize: 8 max: 1385 count: 51 average: 582.98 | standard deviation: 229.926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 0 1 0 1 0 6 3 1 0 0 0 0 0 0 1 2 1 1 3 2 0 0 0 0 0 1 0 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 3 average: 2.33333 | standard deviation: 1.22474 | 0 1 0 2 ] -miss_latency_LD_L2Cache: [binsize: 8 max: 843 count: 2 average: 551.5 | standard deviation: 412.244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_LD_Directory: [binsize: 128 max: 21253 count: 36 average: 5874.47 | standard deviation: 6836.32 | 0 0 1 1 2 3 4 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 115 count: 74 average: 11.2568 | standard deviation: 29.2947 | 0 15 15 18 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ] -miss_latency_ST_L2Cache: [binsize: 8 max: 1002 count: 11 average: 529.091 | standard deviation: 293.469 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_Directory: [binsize: 256 max: 25954 count: 815 average: 4976.13 | standard deviation: 6494.33 | 5 70 132 69 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_dir_Times: 868 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 108 count: 2 average: 55.5 | standard deviation: 74.2496 | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_L2Cache: [binsize: 2 max: 359 count: 3 average: 181.333 | standard deviation: 165.7 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1214 count: 43 average: 597 | standard deviation: 225.443 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 0 0 1 2 1 2 1 1 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 2 1 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 3 average: 1.66667 | standard deviation: 0.707107 | 0 1 2 ] +miss_latency_LD_Directory: [binsize: 32 max: 6135 count: 49 average: 5243.24 | standard deviation: 522.306 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 2 0 1 0 1 0 2 1 0 1 1 0 2 1 0 6 1 0 3 1 1 0 1 1 0 1 1 2 1 0 0 0 0 1 1 0 1 2 0 2 0 1 1 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 68 average: 12.0735 | standard deviation: 31.0217 | 0 16 15 14 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 2 ] +miss_latency_ST_L2Cache: [binsize: 8 max: 812 count: 10 average: 347.5 | standard deviation: 231.361 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 64 max: 6580 count: 776 average: 5093.73 | standard deviation: 906.859 | 0 0 0 0 1 1 3 7 3 1 0 1 0 1 1 0 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 2 0 0 0 0 1 1 0 1 0 4 1 0 3 3 7 8 6 9 18 11 18 28 33 40 29 32 36 47 46 43 41 28 43 34 31 31 26 17 10 11 12 19 6 5 5 2 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -127,8 +126,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7004 -page_faults: 1904 +page_reclaims: 9836 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -136,120 +135,116 @@ block_outputs: 0 Network Stats ------------- -total_msg_count_Request_Control: 5485 43880 -total_msg_count_Response_Data: 2871 206712 -total_msg_count_ResponseL2hit_Data: 51 3672 -total_msg_count_Response_Control: 9 72 -total_msg_count_Writeback_Data: 5349 385128 -total_msg_count_Writeback_Control: 246 1968 -total_msg_count_Persistent_Control: 2292 18336 -total_msgs: 16303 total_bytes: 659768 +total_msg_count_Request_Control: 5259 42072 +total_msg_count_Response_Data: 2727 196344 +total_msg_count_ResponseL2hit_Data: 33 2376 +total_msg_count_Response_Control: 3 24 +total_msg_count_Writeback_Data: 5187 373464 +total_msg_count_Writeback_Control: 234 1872 +total_msg_count_Persistent_Control: 2388 19104 +total_msgs: 15831 total_bytes: 635256 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.115928 - links_utilized_percent_switch_0_link_0: 0.0432124 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.188643 bw: 160000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 923 7384 [ 0 923 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 977 70344 [ 0 0 0 0 977 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.115486 + links_utilized_percent_switch_0_link_0: 0.0430356 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.187936 bw: 160000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 955 68760 [ 0 0 0 0 955 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0997532 - links_utilized_percent_switch_1_link_0: 0.0435821 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.155924 bw: 160000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 796 57312 [ 0 0 0 0 796 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.0975123 + links_utilized_percent_switch_1_link_0: 0.0428627 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.152162 bw: 160000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 768 55296 [ 0 0 0 0 768 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.09541 - links_utilized_percent_switch_2_link_0: 0.040428 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.150392 bw: 160000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 905 65160 [ 0 0 0 0 905 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.0934167 + links_utilized_percent_switch_2_link_0: 0.0396432 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.14719 bw: 160000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 869 62568 [ 0 0 0 0 869 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.167305 - links_utilized_percent_switch_3_link_0: 0.165875 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.174328 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.161712 bw: 160000 base_latency: 1 - - outgoing_messages_switch_3_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 - -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 58 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 58 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - - system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% - - system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 58 100% - -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 865 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 865 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - - system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.39306% - system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.6069% - - system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 865 100% +links_utilized_percent_switch_3: 0.164909 + links_utilized_percent_switch_3_link_0: 0.164704 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.171451 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.158573 bw: 160000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 889 64008 [ 0 0 0 0 889 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 877 63144 [ 0 0 0 0 877 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 871 6968 [ 0 0 871 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 20 1440 [ 0 0 0 0 20 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 773 55656 [ 0 0 0 0 773 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 78 624 [ 0 0 0 0 78 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Persistent_Control: 398 3184 [ 0 0 0 398 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.L1IcacheMemory + system.l1_cntrl0.L1IcacheMemory_total_misses: 46 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 46 + system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% + + system.l1_cntrl0.L1IcacheMemory_access_mode_type_SupervisorMode: 46 100% + +Cache Stats: system.l1_cntrl0.L1DcacheMemory + system.l1_cntrl0.L1DcacheMemory_total_misses: 836 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 836 + system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 5.86124% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 94.1388% + + system.l1_cntrl0.L1DcacheMemory_access_mode_type_SupervisorMode: 836 100% --- L1Cache --- - Event Counts - -Load [41 ] 41 -Ifetch [59 ] 59 -Store [901 ] 901 +Load [52 ] 52 +Ifetch [48 ] 48 +Store [855 ] 855 Atomic [0 ] 0 -L1_Replacement [388292 ] 388292 -Data_Shared [9 ] 9 -Data_Owner [2 ] 2 -Data_All_Tokens [998 ] 998 -Ack [2 ] 2 -Ack_All_Tokens [2 ] 2 +L1_Replacement [19142 ] 19142 +Data_Shared [3 ] 3 +Data_Owner [0 ] 0 +Data_All_Tokens [976 ] 976 +Ack [1 ] 1 +Ack_All_Tokens [0 ] 0 Transient_GETX [0 ] 0 Transient_Local_GETX [0 ] 0 Transient_GETS [0 ] 0 @@ -259,21 +254,21 @@ Transient_Local_GETS_Last_Token [0 ] 0 Persistent_GETX [0 ] 0 Persistent_GETS [0 ] 0 Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [382 ] 382 -Request_Timeout [674 ] 674 +Own_Lock_or_Unlock [398 ] 398 +Request_Timeout [783 ] 783 Use_TimeoutStarverX [0 ] 0 Use_TimeoutStarverS [0 ] 0 -Use_TimeoutNoStarvers [912 ] 912 +Use_TimeoutNoStarvers [877 ] 877 Use_TimeoutNoStarvers_NoMig [0 ] 0 - Transitions - -NP Load [38 ] 38 -NP Ifetch [58 ] 58 -NP Store [826 ] 826 +NP Load [49 ] 49 +NP Ifetch [46 ] 46 +NP Store [787 ] 787 NP Atomic [0 ] 0 NP Data_Shared [0 ] 0 NP Data_Owner [0 ] 0 -NP Data_All_Tokens [87 ] 87 +NP Data_All_Tokens [98 ] 98 NP Ack [0 ] 0 NP Transient_GETX [0 ] 0 NP Transient_Local_GETX [0 ] 0 @@ -282,7 +277,7 @@ NP Transient_Local_GETS [0 ] 0 NP Persistent_GETX [0 ] 0 NP Persistent_GETS [0 ] 0 NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [175 ] 175 +NP Own_Lock_or_Unlock [190 ] 190 I Load [0 ] 0 I Ifetch [0 ] 0 @@ -305,10 +300,10 @@ I Persistent_GETS_Last_Token [0 ] 0 I Own_Lock_or_Unlock [0 ] 0 S Load [0 ] 0 -S Ifetch [1 ] 1 -S Store [1 ] 1 +S Ifetch [2 ] 2 +S Store [0 ] 0 S Atomic [0 ] 0 -S L1_Replacement [8 ] 8 +S L1_Replacement [3 ] 3 S Data_Shared [0 ] 0 S Data_Owner [0 ] 0 S Data_All_Tokens [0 ] 0 @@ -348,33 +343,33 @@ M Load [0 ] 0 M Ifetch [0 ] 0 M Store [0 ] 0 M Atomic [0 ] 0 -M L1_Replacement [83 ] 83 +M L1_Replacement [88 ] 88 M Transient_GETX [0 ] 0 M Transient_Local_GETX [0 ] 0 M Transient_GETS [0 ] 0 M Transient_Local_GETS [0 ] 0 M Persistent_GETX [0 ] 0 M Persistent_GETS [0 ] 0 -M Own_Lock_or_Unlock [12 ] 12 +M Own_Lock_or_Unlock [15 ] 15 MM Load [2 ] 2 MM Ifetch [0 ] 0 -MM Store [64 ] 64 +MM Store [57 ] 57 MM Atomic [0 ] 0 -MM L1_Replacement [826 ] 826 +MM L1_Replacement [786 ] 786 MM Transient_GETX [0 ] 0 MM Transient_Local_GETX [0 ] 0 MM Transient_GETS [0 ] 0 MM Transient_Local_GETS [0 ] 0 MM Persistent_GETX [0 ] 0 MM Persistent_GETS [0 ] 0 -MM Own_Lock_or_Unlock [27 ] 27 +MM Own_Lock_or_Unlock [15 ] 15 -M_W Load [0 ] 0 +M_W Load [1 ] 1 M_W Ifetch [0 ] 0 M_W Store [1 ] 1 M_W Atomic [0 ] 0 -M_W L1_Replacement [1338 ] 1338 +M_W L1_Replacement [396 ] 396 M_W Transient_GETX [0 ] 0 M_W Transient_Local_GETX [0 ] 0 M_W Transient_GETS [0 ] 0 @@ -384,35 +379,35 @@ M_W Persistent_GETS [0 ] 0 M_W Own_Lock_or_Unlock [1 ] 1 M_W Use_TimeoutStarverX [0 ] 0 M_W Use_TimeoutStarverS [0 ] 0 -M_W Use_TimeoutNoStarvers [85 ] 85 +M_W Use_TimeoutNoStarvers [90 ] 90 M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 -MM_W Load [1 ] 1 +MM_W Load [0 ] 0 MM_W Ifetch [0 ] 0 -MM_W Store [9 ] 9 +MM_W Store [10 ] 10 MM_W Atomic [0 ] 0 -MM_W L1_Replacement [30069 ] 30069 +MM_W L1_Replacement [7395 ] 7395 MM_W Transient_GETX [0 ] 0 MM_W Transient_Local_GETX [0 ] 0 MM_W Transient_GETS [0 ] 0 MM_W Transient_Local_GETS [0 ] 0 MM_W Persistent_GETX [0 ] 0 MM_W Persistent_GETS [0 ] 0 -MM_W Own_Lock_or_Unlock [26 ] 26 +MM_W Own_Lock_or_Unlock [25 ] 25 MM_W Use_TimeoutStarverX [0 ] 0 MM_W Use_TimeoutStarverS [0 ] 0 -MM_W Use_TimeoutNoStarvers [827 ] 827 +MM_W Use_TimeoutNoStarvers [787 ] 787 MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 IM Load [0 ] 0 IM Ifetch [0 ] 0 IM Store [0 ] 0 IM Atomic [0 ] 0 -IM L1_Replacement [341249 ] 341249 +IM L1_Replacement [9791 ] 9791 IM Data_Shared [0 ] 0 -IM Data_Owner [2 ] 2 -IM Data_All_Tokens [823 ] 823 -IM Ack [2 ] 2 +IM Data_Owner [0 ] 0 +IM Data_All_Tokens [786 ] 786 +IM Ack [1 ] 1 IM Transient_GETX [0 ] 0 IM Transient_Local_GETX [0 ] 0 IM Transient_GETS [0 ] 0 @@ -422,8 +417,8 @@ IM Transient_Local_GETS_Last_Token [0 ] 0 IM Persistent_GETX [0 ] 0 IM Persistent_GETS [0 ] 0 IM Persistent_GETS_Last_Token [0 ] 0 -IM Own_Lock_or_Unlock [124 ] 124 -IM Request_Timeout [608 ] 608 +IM Own_Lock_or_Unlock [135 ] 135 +IM Request_Timeout [709 ] 709 SM Load [0 ] 0 SM Ifetch [0 ] 0 @@ -432,7 +427,7 @@ SM Atomic [0 ] 0 SM L1_Replacement [0 ] 0 SM Data_Shared [0 ] 0 SM Data_Owner [0 ] 0 -SM Data_All_Tokens [1 ] 1 +SM Data_All_Tokens [0 ] 0 SM Ack [0 ] 0 SM Transient_GETX [0 ] 0 SM Transient_Local_GETX [0 ] 0 @@ -454,7 +449,7 @@ OM L1_Replacement [0 ] 0 OM Data_Shared [0 ] 0 OM Data_All_Tokens [0 ] 0 OM Ack [0 ] 0 -OM Ack_All_Tokens [2 ] 2 +OM Ack_All_Tokens [0 ] 0 OM Transient_GETX [0 ] 0 OM Transient_Local_GETX [0 ] 0 OM Transient_GETS [0 ] 0 @@ -464,17 +459,17 @@ OM Transient_Local_GETS_Last_Token [0 ] 0 OM Persistent_GETX [0 ] 0 OM Persistent_GETS [0 ] 0 OM Persistent_GETS_Last_Token [0 ] 0 -OM Own_Lock_or_Unlock [1 ] 1 -OM Request_Timeout [1 ] 1 +OM Own_Lock_or_Unlock [0 ] 0 +OM Request_Timeout [0 ] 0 IS Load [0 ] 0 IS Ifetch [0 ] 0 IS Store [0 ] 0 IS Atomic [0 ] 0 -IS L1_Replacement [14719 ] 14719 -IS Data_Shared [9 ] 9 +IS L1_Replacement [683 ] 683 +IS Data_Shared [3 ] 3 IS Data_Owner [0 ] 0 -IS Data_All_Tokens [87 ] 87 +IS Data_All_Tokens [92 ] 92 IS Ack [0 ] 0 IS Transient_GETX [0 ] 0 IS Transient_Local_GETX [0 ] 0 @@ -485,8 +480,8 @@ IS Transient_Local_GETS_Last_Token [0 ] 0 IS Persistent_GETX [0 ] 0 IS Persistent_GETS [0 ] 0 IS Persistent_GETS_Last_Token [0 ] 0 -IS Own_Lock_or_Unlock [16 ] 16 -IS Request_Timeout [65 ] 65 +IS Own_Lock_or_Unlock [17 ] 17 +IS Request_Timeout [74 ] 74 I_L Load [0 ] 0 I_L Ifetch [0 ] 0 @@ -590,50 +585,50 @@ IS_L Own_Lock_or_Unlock [0 ] 0 IS_L Request_Timeout [0 ] 0 Cache Stats: system.l2_cntrl0.L2cacheMemory - system.l2_cntrl0.L2cacheMemory_total_misses: 906 - system.l2_cntrl0.L2cacheMemory_total_demand_misses: 906 + system.l2_cntrl0.L2cacheMemory_total_misses: 871 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 871 system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_request_type_GETS: 9.60265% - system.l2_cntrl0.L2cacheMemory_request_type_GETX: 90.3974% + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 10.5626% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 89.4374% - system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 906 100% + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 871 100% --- L2Cache --- - Event Counts - L1_GETS [95 ] 95 -L1_GETS_Last_Token [1 ] 1 -L1_GETX [826 ] 826 +L1_GETS_Last_Token [0 ] 0 +L1_GETX [787 ] 787 L1_INV [0 ] 0 Transient_GETX [0 ] 0 Transient_GETS [0 ] 0 Transient_GETS_Last_Token [0 ] 0 -L2_Replacement [857 ] 857 +L2_Replacement [799 ] 799 Writeback_Tokens [0 ] 0 -Writeback_Shared_Data [8 ] 8 -Writeback_All_Tokens [908 ] 908 +Writeback_Shared_Data [3 ] 3 +Writeback_All_Tokens [874 ] 874 Writeback_Owned [0 ] 0 Data_Shared [0 ] 0 Data_Owner [0 ] 0 Data_All_Tokens [0 ] 0 Ack [0 ] 0 Ack_All_Tokens [0 ] 0 -Persistent_GETX [173 ] 173 -Persistent_GETS [18 ] 18 +Persistent_GETX [179 ] 179 +Persistent_GETS [20 ] 20 Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [191 ] 191 +Own_Lock_or_Unlock [199 ] 199 - Transitions - -NP L1_GETS [87 ] 87 -NP L1_GETX [816 ] 816 +NP L1_GETS [92 ] 92 +NP L1_GETX [777 ] 777 NP L1_INV [0 ] 0 NP Transient_GETX [0 ] 0 NP Transient_GETS [0 ] 0 NP Writeback_Tokens [0 ] 0 -NP Writeback_Shared_Data [7 ] 7 -NP Writeback_All_Tokens [852 ] 852 +NP Writeback_Shared_Data [3 ] 3 +NP Writeback_All_Tokens [798 ] 798 NP Writeback_Owned [0 ] 0 NP Data_Shared [0 ] 0 NP Data_Owner [0 ] 0 @@ -642,7 +637,7 @@ NP Ack [0 ] 0 NP Persistent_GETX [0 ] 0 NP Persistent_GETS [0 ] 0 NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [168 ] 168 +NP Own_Lock_or_Unlock [181 ] 181 I L1_GETS [0 ] 0 I L1_GETS_Last_Token [0 ] 0 @@ -651,10 +646,10 @@ I L1_INV [0 ] 0 I Transient_GETX [0 ] 0 I Transient_GETS [0 ] 0 I Transient_GETS_Last_Token [0 ] 0 -I L2_Replacement [28 ] 28 +I L2_Replacement [24 ] 24 I Writeback_Tokens [0 ] 0 -I Writeback_Shared_Data [1 ] 1 -I Writeback_All_Tokens [5 ] 5 +I Writeback_Shared_Data [0 ] 0 +I Writeback_All_Tokens [3 ] 3 I Writeback_Owned [0 ] 0 I Data_Shared [0 ] 0 I Data_Owner [0 ] 0 @@ -666,13 +661,13 @@ I Persistent_GETS_Last_Token [0 ] 0 I Own_Lock_or_Unlock [0 ] 0 S L1_GETS [0 ] 0 -S L1_GETS_Last_Token [1 ] 1 -S L1_GETX [2 ] 2 +S L1_GETS_Last_Token [0 ] 0 +S L1_GETX [1 ] 1 S L1_INV [0 ] 0 S Transient_GETX [0 ] 0 S Transient_GETS [0 ] 0 S Transient_GETS_Last_Token [0 ] 0 -S L2_Replacement [5 ] 5 +S L2_Replacement [2 ] 2 S Writeback_Tokens [0 ] 0 S Writeback_Shared_Data [0 ] 0 S Writeback_All_Tokens [0 ] 0 @@ -688,12 +683,12 @@ S Own_Lock_or_Unlock [0 ] 0 O L1_GETS [0 ] 0 O L1_GETS_Last_Token [0 ] 0 -O L1_GETX [1 ] 1 +O L1_GETX [0 ] 0 O L1_INV [0 ] 0 O Transient_GETX [0 ] 0 O Transient_GETS [0 ] 0 O Transient_GETS_Last_Token [0 ] 0 -O L2_Replacement [7 ] 7 +O L2_Replacement [3 ] 3 O Writeback_Tokens [0 ] 0 O Writeback_Shared_Data [0 ] 0 O Writeback_All_Tokens [0 ] 0 @@ -706,34 +701,34 @@ O Persistent_GETS [0 ] 0 O Persistent_GETS_Last_Token [0 ] 0 O Own_Lock_or_Unlock [0 ] 0 -M L1_GETS [8 ] 8 -M L1_GETX [7 ] 7 +M L1_GETS [3 ] 3 +M L1_GETX [8 ] 8 M L1_INV [0 ] 0 M Transient_GETX [0 ] 0 M Transient_GETS [0 ] 0 -M L2_Replacement [814 ] 814 -M Persistent_GETX [26 ] 26 +M L2_Replacement [768 ] 768 +M Persistent_GETX [20 ] 20 M Persistent_GETS [0 ] 0 M Own_Lock_or_Unlock [0 ] 0 I_L L1_GETS [0 ] 0 -I_L L1_GETX [0 ] 0 +I_L L1_GETX [1 ] 1 I_L L1_INV [0 ] 0 I_L Transient_GETX [0 ] 0 I_L Transient_GETS [0 ] 0 I_L Transient_GETS_Last_Token [0 ] 0 -I_L L2_Replacement [3 ] 3 +I_L L2_Replacement [2 ] 2 I_L Writeback_Tokens [0 ] 0 I_L Writeback_Shared_Data [0 ] 0 -I_L Writeback_All_Tokens [51 ] 51 +I_L Writeback_All_Tokens [73 ] 73 I_L Writeback_Owned [0 ] 0 I_L Data_Shared [0 ] 0 I_L Data_Owner [0 ] 0 I_L Data_All_Tokens [0 ] 0 I_L Ack [0 ] 0 -I_L Persistent_GETX [147 ] 147 -I_L Persistent_GETS [18 ] 18 -I_L Own_Lock_or_Unlock [23 ] 23 +I_L Persistent_GETX [159 ] 159 +I_L Persistent_GETS [20 ] 20 +I_L Own_Lock_or_Unlock [18 ] 18 S_L L1_GETS [0 ] 0 S_L L1_GETS_Last_Token [0 ] 0 @@ -757,93 +752,93 @@ S_L Persistent_GETS_Last_Token [0 ] 0 S_L Own_Lock_or_Unlock [0 ] 0 Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 1720 - memory_reads: 902 - memory_writes: 818 - memory_refreshes: 571 - memory_total_request_delays: 1302 - memory_delays_per_request: 0.756977 - memory_delays_in_input_queue: 202 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 1100 - memory_stalls_for_bank_busy: 220 + memory_total_requests: 1655 + memory_reads: 869 + memory_writes: 786 + memory_refreshes: 558 + memory_total_request_delays: 1116 + memory_delays_per_request: 0.67432 + memory_delays_in_input_queue: 156 + memory_delays_behind_head_of_bank_queue: 3 + memory_delays_stalled_at_head_of_bank_queue: 957 + memory_stalls_for_bank_busy: 245 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 97 - memory_stalls_for_bus: 424 + memory_stalls_for_arbitration: 76 + memory_stalls_for_bus: 363 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 268 - memory_stalls_for_read_read_turnaround: 91 - accesses_per_bank: 61 42 48 69 122 69 58 56 55 51 54 41 43 47 55 55 46 45 53 50 43 51 55 52 43 56 60 54 49 40 40 57 + memory_stalls_for_read_write_turnaround: 197 + memory_stalls_for_read_read_turnaround: 76 + accesses_per_bank: 42 44 54 72 110 62 62 43 42 53 38 40 51 47 54 42 48 54 39 56 64 58 51 54 48 46 43 52 46 43 49 48 --- Directory --- - Event Counts - -GETX [828 ] 828 -GETS [87 ] 87 -Lockdown [191 ] 191 -Unlockdown [191 ] 191 +GETX [807 ] 807 +GETS [92 ] 92 +Lockdown [199 ] 199 +Unlockdown [199 ] 199 Own_Lock_or_Unlock [0 ] 0 Own_Lock_or_Unlock_Tokens [0 ] 0 -Data_Owner [7 ] 7 -Data_All_Tokens [825 ] 825 +Data_Owner [3 ] 3 +Data_All_Tokens [790 ] 790 Ack_Owner [0 ] 0 Ack_Owner_All_Tokens [76 ] 76 -Tokens [2 ] 2 -Ack_All_Tokens [3 ] 3 +Tokens [0 ] 0 +Ack_All_Tokens [2 ] 2 Request_Timeout [0 ] 0 -Memory_Data [902 ] 902 -Memory_Ack [817 ] 817 +Memory_Data [868 ] 868 +Memory_Ack [786 ] 786 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX [811 ] 811 -O GETS [83 ] 83 -O Lockdown [6 ] 6 +O GETX [773 ] 773 +O GETS [90 ] 90 +O Lockdown [5 ] 5 O Unlockdown [0 ] 0 O Own_Lock_or_Unlock [0 ] 0 O Own_Lock_or_Unlock_Tokens [0 ] 0 O Data_Owner [0 ] 0 O Data_All_Tokens [0 ] 0 O Tokens [0 ] 0 -O Ack_All_Tokens [3 ] 3 +O Ack_All_Tokens [2 ] 2 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 O DMA_WRITE_All_Tokens [0 ] 0 -NO GETX [8 ] 8 -NO GETS [4 ] 4 -NO Lockdown [168 ] 168 +NO GETX [2 ] 2 +NO GETS [2 ] 2 +NO Lockdown [180 ] 180 NO Unlockdown [0 ] 0 NO Own_Lock_or_Unlock [0 ] 0 NO Own_Lock_or_Unlock_Tokens [0 ] 0 -NO Data_Owner [7 ] 7 -NO Data_All_Tokens [811 ] 811 +NO Data_Owner [3 ] 3 +NO Data_All_Tokens [783 ] 783 NO Ack_Owner [0 ] 0 NO Ack_Owner_All_Tokens [76 ] 76 -NO Tokens [1 ] 1 +NO Tokens [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 -L GETX [0 ] 0 +L GETX [4 ] 4 L GETS [0 ] 0 L Lockdown [0 ] 0 -L Unlockdown [189 ] 189 +L Unlockdown [199 ] 199 L Own_Lock_or_Unlock [0 ] 0 L Own_Lock_or_Unlock_Tokens [0 ] 0 L Data_Owner [0 ] 0 -L Data_All_Tokens [14 ] 14 +L Data_All_Tokens [7 ] 7 L Ack_Owner [0 ] 0 L Ack_Owner_All_Tokens [0 ] 0 -L Tokens [1 ] 1 +L Tokens [0 ] 0 L DMA_READ [0 ] 0 L DMA_WRITE [0 ] 0 L DMA_WRITE_All_Tokens [0 ] 0 -O_W GETX [9 ] 9 +O_W GETX [0 ] 0 O_W GETS [0 ] 0 -O_W Lockdown [3 ] 3 +O_W Lockdown [1 ] 1 O_W Unlockdown [0 ] 0 O_W Own_Lock_or_Unlock [0 ] 0 O_W Own_Lock_or_Unlock_Tokens [0 ] 0 @@ -852,16 +847,16 @@ O_W Data_All_Tokens [0 ] 0 O_W Ack_Owner [0 ] 0 O_W Tokens [0 ] 0 O_W Ack_All_Tokens [0 ] 0 -O_W Memory_Data [1 ] 1 -O_W Memory_Ack [815 ] 815 +O_W Memory_Data [0 ] 0 +O_W Memory_Ack [785 ] 785 O_W DMA_READ [0 ] 0 O_W DMA_WRITE [0 ] 0 O_W DMA_WRITE_All_Tokens [0 ] 0 -L_O_W GETX [0 ] 0 +L_O_W GETX [28 ] 28 L_O_W GETS [0 ] 0 L_O_W Lockdown [0 ] 0 -L_O_W Unlockdown [2 ] 2 +L_O_W Unlockdown [0 ] 0 L_O_W Own_Lock_or_Unlock [0 ] 0 L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 L_O_W Data_Owner [0 ] 0 @@ -869,8 +864,8 @@ L_O_W Data_All_Tokens [0 ] 0 L_O_W Ack_Owner [0 ] 0 L_O_W Tokens [0 ] 0 L_O_W Ack_All_Tokens [0 ] 0 -L_O_W Memory_Data [7 ] 7 -L_O_W Memory_Ack [2 ] 2 +L_O_W Memory_Data [6 ] 6 +L_O_W Memory_Ack [1 ] 1 L_O_W DMA_READ [0 ] 0 L_O_W DMA_WRITE [0 ] 0 L_O_W DMA_WRITE_All_Tokens [0 ] 0 @@ -886,7 +881,7 @@ L_NO_W Data_All_Tokens [0 ] 0 L_NO_W Ack_Owner [0 ] 0 L_NO_W Tokens [0 ] 0 L_NO_W Ack_All_Tokens [0 ] 0 -L_NO_W Memory_Data [14 ] 14 +L_NO_W Memory_Data [13 ] 13 L_NO_W DMA_READ [0 ] 0 L_NO_W DMA_WRITE [0 ] 0 L_NO_W DMA_WRITE_All_Tokens [0 ] 0 @@ -927,7 +922,7 @@ DW_L_W DMA_WRITE_All_Tokens [0 ] 0 NO_W GETX [0 ] 0 NO_W GETS [0 ] 0 -NO_W Lockdown [14 ] 14 +NO_W Lockdown [13 ] 13 NO_W Unlockdown [0 ] 0 NO_W Own_Lock_or_Unlock [0 ] 0 NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 @@ -936,7 +931,7 @@ NO_W Data_All_Tokens [0 ] 0 NO_W Ack_Owner [0 ] 0 NO_W Tokens [0 ] 0 NO_W Ack_All_Tokens [0 ] 0 -NO_W Memory_Data [880 ] 880 +NO_W Memory_Data [849 ] 849 NO_W DMA_READ [0 ] 0 NO_W DMA_WRITE [0 ] 0 NO_W DMA_WRITE_All_Tokens [0 ] 0 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout index 5d4c3c605..69ecd7e2d 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 10:41:36 -M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip -M5 started Aug 5 2010 10:45:27 -M5 executing on svvint09 +M5 compiled Feb 8 2011 17:50:56 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:51:05 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 273851 because Ruby Tester completed +Exiting @ tick 267511 because Ruby Tester completed diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index a749dd61b..74696574a 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 210052 # Number of bytes of host memory used -host_seconds 0.53 # Real time elapsed on the host -host_tick_rate 516678 # Simulator tick rate (ticks/s) +host_mem_usage 213120 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 1663377 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000274 # Number of seconds simulated -sim_ticks 273851 # Number of ticks simulated +sim_seconds 0.000268 # Number of seconds simulated +sim_ticks 267511 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini index 24f058dce..dda1ea910 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini @@ -1,19 +1,29 @@ [root] type=Root children=system -dummy=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 [system] type=System -children=dir_cntrl0 l1_cntrl0 physmem ruby +children=dir_cntrl0 l1_cntrl0 physmem ruby tester mem_mode=timing physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 [system.dir_cntrl0] type=Directory_Controller children=directory memBuffer probeFilter buffer_size=0 directory=system.dir_cntrl0.directory +full_bit_dir_enabled=false memBuffer=system.dir_cntrl0.memBuffer memory_controller_latency=2 number_of_TBEs=256 @@ -62,17 +72,18 @@ start_index_bit=6 [system.l1_cntrl0] type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.l1_cntrl0.sequencer.dcache -L1IcacheMemory=system.l1_cntrl0.sequencer.icache +children=L2cacheMemory +L1DcacheMemory=system.ruby.cpu_ruby_ports.dcache +L1IcacheMemory=system.ruby.cpu_ruby_ports.icache L2cacheMemory=system.l1_cntrl0.L2cacheMemory buffer_size=0 cache_response_latency=10 issue_latency=2 +l2_cache_hit_latency=10 no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 -sequencer=system.l1_cntrl0.sequencer +sequencer=system.ruby.cpu_ruby_ports transitions_per_cycle=32 version=0 @@ -84,35 +95,6 @@ replacement_policy=PSEUDO_LRU size=512 start_index_bit=6 -[system.l1_cntrl0.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.l1_cntrl0.sequencer.dcache -deadlock_threshold=500000 -icache=system.l1_cntrl0.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.l1_cntrl0.sequencer.dcache] -type=RubyCache -assoc=2 -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - -[system.l1_cntrl0.sequencer.icache] -type=RubyCache -assoc=2 -latency=2 -replacement_policy=PSEUDO_LRU -size=256 -start_index_bit=6 - [system.physmem] type=PhysicalMemory file= @@ -121,14 +103,13 @@ latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort +port=system.ruby.cpu_ruby_ports.physMemPort [system.ruby] type=RubySystem -children=debug network profiler tracer +children=cpu_ruby_ports network profiler tracer block_size_bytes=64 clock=1 -debug=system.ruby.debug mem_size=134217728 network=system.ruby.network no_mem_vec=false @@ -138,13 +119,35 @@ randomization=true stats_filename=ruby.stats tracer=system.ruby.tracer -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none +[system.ruby.cpu_ruby_ports] +type=RubySequencer +children=dcache icache +access_phys_mem=true +dcache=system.ruby.cpu_ruby_ports.dcache +deadlock_threshold=500000 +icache=system.ruby.cpu_ruby_ports.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=system.tester.cpuPort[0] + +[system.ruby.cpu_ruby_ports.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.ruby.cpu_ruby_ports.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 [system.ruby.network] type=SimpleNetwork @@ -160,9 +163,9 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology children=ext_links0 ext_links1 int_links0 int_links1 +description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -name=Crossbar num_int_nodes=3 print_config=false @@ -208,3 +211,10 @@ num_of_sequencers=1 type=RubyTracer warmup_length=100000 +[system.tester] +type=RubyTester +checks_to_complete=100 +deadlock_threshold=50000 +wakeup_frequency=10 +cpuPort=system.ruby.cpu_ruby_ports.port[0] + diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats index 57c443be3..d1706cac4 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats @@ -13,7 +13,7 @@ RubySystem config: Network Configuration --------------------- network: SIMPLE_NETWORK -topology: Crossbar +topology: virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Aug/05/2010 14:46:32 +Real time: Feb/08/2011 17:57:03 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.69 -Virtual_time_in_minutes: 0.0115 -Virtual_time_in_hours: 0.000191667 -Virtual_time_in_days: 7.98611e-06 +Virtual_time_in_seconds: 0.4 +Virtual_time_in_minutes: 0.00666667 +Virtual_time_in_hours: 0.000111111 +Virtual_time_in_days: 4.62963e-06 -Ruby_current_time: 213851 +Ruby_current_time: 210961 Ruby_start_time: 0 -Ruby_cycles: 213851 +Ruby_cycles: 210961 -mbytes_resident: 31.293 -mbytes_total: 31.3008 -resident_ratio: 1 +mbytes_resident: 33.4023 +mbytes_total: 207.566 +resident_ratio: 0.160961 -ruby_cycles_executed: [ 213852 ] +ruby_cycles_executed: [ 210962 ] Busy Controller Counts: L1Cache-0:0 @@ -65,17 +65,17 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 963 average: 15.8069 | standard deviation: 1.15034 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 65 883 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.8016 | standard deviation: 1.14461 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 3 71 891 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 23081 count: 948 average: 3529.13 | standard deviation: 5116.76 | 71 12 47 82 73 59 68 59 47 38 28 25 17 14 12 7 10 4 1 9 4 5 5 7 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 4 4 5 5 1 4 3 3 3 3 3 3 4 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 8 max: 1215 count: 59 average: 478.39 | standard deviation: 246.067 | 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 128 max: 15642 count: 41 average: 3000.32 | standard deviation: 4886.74 | 5 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 128 max: 23081 count: 848 average: 3766.95 | standard deviation: 5236.59 | 61 10 32 62 58 52 60 56 43 35 27 24 17 14 12 5 10 4 0 9 4 5 5 6 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 4 3 4 4 1 4 3 3 3 3 3 3 4 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L1Cache: [binsize: 1 max: 118 count: 65 average: 15.8923 | standard deviation: 35.394 | 0 9 14 16 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ] -miss_latency_L2Cache: [binsize: 128 max: 19544 count: 29 average: 3519.03 | standard deviation: 5619.12 | 6 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Directory: [binsize: 128 max: 23081 count: 854 average: 3796.87 | standard deviation: 5197.84 | 0 10 46 78 72 57 67 59 47 38 27 25 16 14 12 7 10 3 1 9 4 5 5 6 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 3 4 5 4 1 4 3 3 3 3 3 3 3 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 64 max: 8993 count: 963 average: 3469.42 | standard deviation: 1599.67 | 72 11 5 3 10 7 13 12 7 12 1 8 4 1 1 2 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 6 10 12 7 16 18 17 32 34 24 31 26 29 36 35 35 28 41 44 32 34 21 30 17 25 22 20 20 10 10 6 8 9 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1126 count: 52 average: 473.327 | standard deviation: 221.338 | 0 2 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 5235 count: 48 average: 3979.79 | standard deviation: 1306.56 | 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ] +miss_latency_ST: [binsize: 64 max: 8993 count: 863 average: 3621.56 | standard deviation: 1476.69 | 66 9 4 1 5 2 6 6 3 6 0 0 2 1 1 2 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 5 10 11 7 16 18 17 32 31 23 31 25 28 35 30 31 23 40 43 29 34 20 27 16 25 22 19 19 7 8 6 5 8 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 117 count: 71 average: 13.3803 | standard deviation: 32.5601 | 0 10 15 23 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ] +miss_latency_L2Cache: [binsize: 64 max: 8993 count: 33 average: 2589.88 | standard deviation: 2554.56 | 8 4 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] +miss_latency_Directory: [binsize: 32 max: 6151 count: 859 average: 3788.87 | standard deviation: 1226.92 | 0 0 0 0 0 5 1 1 8 2 2 5 13 0 0 12 6 0 4 8 1 0 7 1 1 3 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 3 6 3 4 7 4 3 6 10 11 6 4 12 14 14 15 17 13 9 17 13 7 19 18 10 17 19 20 15 17 17 8 20 25 16 22 22 14 18 15 19 10 10 19 11 9 8 14 11 15 7 12 8 9 11 5 5 4 6 3 3 3 5 4 5 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -85,15 +85,14 @@ miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -imcomplete_dir_Times: 854 -miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2 average: 2.5 | standard deviation: 1 | 0 0 1 1 ] -miss_latency_IFETCH_L2Cache: [binsize: 1 max: 123 count: 3 average: 50 | standard deviation: 63.2218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_IFETCH_Directory: [binsize: 8 max: 1215 count: 54 average: 519.815 | standard deviation: 213.139 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD_L1Cache: [binsize: 1 max: 4 count: 5 average: 3 | standard deviation: 0.707107 | 0 0 1 3 1 ] -miss_latency_LD_Directory: [binsize: 128 max: 15642 count: 36 average: 3416.61 | standard deviation: 5082.33 | 0 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 118 count: 58 average: 17.4655 | standard deviation: 37.1906 | 0 9 12 12 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ] -miss_latency_ST_L2Cache: [binsize: 128 max: 19544 count: 26 average: 3919.31 | standard deviation: 5809.69 | 3 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_Directory: [binsize: 128 max: 23081 count: 764 average: 4046.41 | standard deviation: 5309.16 | 0 8 31 58 57 50 59 56 43 35 26 24 16 14 12 5 10 3 0 9 4 5 5 5 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 3 3 4 3 1 4 3 3 3 3 3 3 3 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_dir_Times: 859 +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 117 count: 4 average: 62.25 | standard deviation: 62.0725 | 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1126 count: 48 average: 507.583 | standard deviation: 193.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 4 average: 2 | standard deviation: 0.816497 | 0 1 2 1 ] +miss_latency_LD_Directory: [binsize: 32 max: 5235 count: 44 average: 4341.41 | standard deviation: 510.099 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 67 average: 14.0597 | standard deviation: 33.4075 | 0 9 13 22 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ] +miss_latency_ST_L2Cache: [binsize: 64 max: 8993 count: 29 average: 2938.52 | standard deviation: 2533.58 | 6 2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] +miss_latency_ST_Directory: [binsize: 32 max: 6151 count: 767 average: 3962.52 | standard deviation: 973.04 | 0 0 0 0 0 4 0 0 4 1 0 2 6 0 0 6 2 0 1 5 0 0 0 0 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 2 6 3 4 6 4 3 6 10 11 6 4 12 14 14 13 16 13 8 17 13 6 19 17 10 16 19 18 12 15 15 7 16 25 15 22 21 13 16 15 19 9 10 17 10 8 8 14 11 15 7 12 7 9 10 5 2 4 4 3 3 3 2 4 4 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -125,8 +124,8 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 6929 -page_faults: 1882 +page_reclaims: 9722 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -134,117 +133,118 @@ block_outputs: 0 Network Stats ------------- -total_msg_count_Request_Control: 2568 20544 -total_msg_count_Response_Data: 2562 184464 -total_msg_count_Writeback_Data: 2281 164232 -total_msg_count_Writeback_Control: 5351 42808 -total_msg_count_Unblock_Control: 2559 20472 -total_msgs: 15321 total_bytes: 432520 +total_msg_count_Request_Control: 2577 20616 +total_msg_count_Response_Data: 2577 185544 +total_msg_count_Writeback_Data: 2301 165672 +total_msg_count_Writeback_Control: 5367 42936 +total_msg_count_Unblock_Control: 2574 20592 +total_msgs: 15396 total_bytes: 435360 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.13593 - links_utilized_percent_switch_0_link_0: 0.0498829 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.221977 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.138684 + links_utilized_percent_switch_0_link_0: 0.0508566 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.226511 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 761 54792 [ 0 0 0 0 0 761 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 936 7488 [ 0 0 849 0 0 87 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.127495 - links_utilized_percent_switch_1_link_0: 0.0554358 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.199555 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.130027 + links_utilized_percent_switch_1_link_0: 0.0566278 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.203426 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 849 6792 [ 0 0 0 849 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.210637 - links_utilized_percent_switch_2_link_0: 0.199531 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.221743 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.214969 + links_utilized_percent_switch_2_link_0: 0.203426 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.226511 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 859 61848 [ 0 0 0 0 859 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 852 6816 [ 0 0 0 852 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 859 6872 [ 0 0 859 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 767 55224 [ 0 0 0 0 0 767 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 937 7496 [ 0 0 852 0 0 85 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1 -Cache Stats: system.l1_cntrl0.sequencer.icache - system.l1_cntrl0.sequencer.icache_total_misses: 57 - system.l1_cntrl0.sequencer.icache_total_demand_misses: 57 - system.l1_cntrl0.sequencer.icache_total_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.ruby.cpu_ruby_ports.icache + system.ruby.cpu_ruby_ports.icache_total_misses: 52 + system.ruby.cpu_ruby_ports.icache_total_demand_misses: 52 + system.ruby.cpu_ruby_ports.icache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% + system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100% - system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 57 100% + system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 52 100% -Cache Stats: system.l1_cntrl0.sequencer.dcache - system.l1_cntrl0.sequencer.dcache_total_misses: 840 - system.l1_cntrl0.sequencer.dcache_total_demand_misses: 840 - system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.ruby.cpu_ruby_ports.dcache + system.ruby.cpu_ruby_ports.dcache_total_misses: 852 + system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 852 + system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0 + system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0 - system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.28571% - system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.7143% + system.ruby.cpu_ruby_ports.dcache_request_type_LD: 5.28169% + system.ruby.cpu_ruby_ports.dcache_request_type_ST: 94.7183% - system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 840 100% + system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 852 100% Cache Stats: system.l1_cntrl0.L2cacheMemory - system.l1_cntrl0.L2cacheMemory_total_misses: 856 - system.l1_cntrl0.L2cacheMemory_total_demand_misses: 856 + system.l1_cntrl0.L2cacheMemory_total_misses: 904 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 904 system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.20561% - system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.486% - system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 6.30841% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.97788% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.2699% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.75221% - system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 856 100% + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 904 100% --- L1Cache --- - Event Counts - -Load [41 ] 41 -Ifetch [106 ] 106 -Store [906 ] 906 -L2_Replacement [849 ] 849 -L1_to_L2 [303164 ] 303164 -Trigger_L2_to_L1D [38 ] 38 -Trigger_L2_to_L1I [3 ] 3 -Complete_L2_to_L1 [41 ] 41 +Load [48 ] 48 +Ifetch [53 ] 53 +Store [888 ] 888 +L2_Replacement [854 ] 854 +L1_to_L2 [16074 ] 16074 +Trigger_L2_to_L1D [39 ] 39 +Trigger_L2_to_L1I [4 ] 4 +Complete_L2_to_L1 [43 ] 43 Other_GETX [0 ] 0 Other_GETS [0 ] 0 Merged_GETS [0 ] 0 Other_GETS_No_Mig [0 ] 0 +NC_DMA_GETS [0 ] 0 Invalidate [0 ] 0 Ack [0 ] 0 Shared_Ack [0 ] 0 Data [0 ] 0 Shared_Data [0 ] 0 -Exclusive_Data [854 ] 854 -Writeback_Ack [848 ] 848 +Exclusive_Data [859 ] 859 +Writeback_Ack [852 ] 852 Writeback_Nack [0 ] 0 All_acks [0 ] 0 -All_acks_no_sharers [853 ] 853 +All_acks_no_sharers [859 ] 859 - Transitions - -I Load [36 ] 36 -I Ifetch [54 ] 54 -I Store [766 ] 766 +I Load [44 ] 44 +I Ifetch [48 ] 48 +I Store [769 ] 769 I L2_Replacement [0 ] 0 I L1_to_L2 [0 ] 0 I Trigger_L2_to_L1D [0 ] 0 @@ -252,6 +252,7 @@ I Trigger_L2_to_L1I [0 ] 0 I Other_GETX [0 ] 0 I Other_GETS [0 ] 0 I Other_GETS_No_Mig [0 ] 0 +I NC_DMA_GETS [0 ] 0 I Invalidate [0 ] 0 S Load [0 ] 0 @@ -264,6 +265,7 @@ S Trigger_L2_to_L1I [0 ] 0 S Other_GETX [0 ] 0 S Other_GETS [0 ] 0 S Other_GETS_No_Mig [0 ] 0 +S NC_DMA_GETS [0 ] 0 S Invalidate [0 ] 0 O Load [0 ] 0 @@ -277,46 +279,50 @@ O Other_GETX [0 ] 0 O Other_GETS [0 ] 0 O Merged_GETS [0 ] 0 O Other_GETS_No_Mig [0 ] 0 +O NC_DMA_GETS [0 ] 0 O Invalidate [0 ] 0 M Load [0 ] 0 -M Ifetch [1 ] 1 -M Store [1 ] 1 -M L2_Replacement [87 ] 87 -M L1_to_L2 [88 ] 88 -M Trigger_L2_to_L1D [1 ] 1 +M Ifetch [0 ] 0 +M Store [3 ] 3 +M L2_Replacement [85 ] 85 +M L1_to_L2 [95 ] 95 +M Trigger_L2_to_L1D [9 ] 9 M Trigger_L2_to_L1I [0 ] 0 M Other_GETX [0 ] 0 M Other_GETS [0 ] 0 M Merged_GETS [0 ] 0 M Other_GETS_No_Mig [0 ] 0 +M NC_DMA_GETS [0 ] 0 M Invalidate [0 ] 0 -MM Load [5 ] 5 +MM Load [4 ] 4 MM Ifetch [4 ] 4 -MM Store [82 ] 82 -MM L2_Replacement [762 ] 762 +MM Store [92 ] 92 +MM L2_Replacement [769 ] 769 MM L1_to_L2 [804 ] 804 -MM Trigger_L2_to_L1D [37 ] 37 -MM Trigger_L2_to_L1I [3 ] 3 +MM Trigger_L2_to_L1D [30 ] 30 +MM Trigger_L2_to_L1I [4 ] 4 MM Other_GETX [0 ] 0 MM Other_GETS [0 ] 0 MM Merged_GETS [0 ] 0 MM Other_GETS_No_Mig [0 ] 0 +MM NC_DMA_GETS [0 ] 0 MM Invalidate [0 ] 0 IM Load [0 ] 0 IM Ifetch [0 ] 0 IM Store [0 ] 0 IM L2_Replacement [0 ] 0 -IM L1_to_L2 [275518 ] 275518 +IM L1_to_L2 [9842 ] 9842 IM Other_GETX [0 ] 0 IM Other_GETS [0 ] 0 IM Other_GETS_No_Mig [0 ] 0 +IM NC_DMA_GETS [0 ] 0 IM Invalidate [0 ] 0 IM Ack [0 ] 0 IM Data [0 ] 0 -IM Exclusive_Data [764 ] 764 +IM Exclusive_Data [767 ] 767 SM Load [0 ] 0 SM Ifetch [0 ] 0 @@ -326,9 +332,11 @@ SM L1_to_L2 [0 ] 0 SM Other_GETX [0 ] 0 SM Other_GETS [0 ] 0 SM Other_GETS_No_Mig [0 ] 0 +SM NC_DMA_GETS [0 ] 0 SM Invalidate [0 ] 0 SM Ack [0 ] 0 SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 OM Load [0 ] 0 OM Ifetch [0 ] 0 @@ -339,6 +347,7 @@ OM Other_GETX [0 ] 0 OM Other_GETS [0 ] 0 OM Merged_GETS [0 ] 0 OM Other_GETS_No_Mig [0 ] 0 +OM NC_DMA_GETS [0 ] 0 OM Invalidate [0 ] 0 OM Ack [0 ] 0 OM All_acks [0 ] 0 @@ -354,34 +363,35 @@ ISM All_acks_no_sharers [0 ] 0 M_W Load [0 ] 0 M_W Ifetch [0 ] 0 -M_W Store [0 ] 0 +M_W Store [1 ] 1 M_W L2_Replacement [0 ] 0 -M_W L1_to_L2 [483 ] 483 +M_W L1_to_L2 [310 ] 310 M_W Ack [0 ] 0 -M_W All_acks_no_sharers [89 ] 89 +M_W All_acks_no_sharers [91 ] 91 MM_W Load [0 ] 0 MM_W Ifetch [0 ] 0 -MM_W Store [1 ] 1 +MM_W Store [0 ] 0 MM_W L2_Replacement [0 ] 0 -MM_W L1_to_L2 [10887 ] 10887 +MM_W L1_to_L2 [4284 ] 4284 MM_W Ack [0 ] 0 -MM_W All_acks_no_sharers [764 ] 764 +MM_W All_acks_no_sharers [768 ] 768 IS Load [0 ] 0 IS Ifetch [0 ] 0 IS Store [0 ] 0 IS L2_Replacement [0 ] 0 -IS L1_to_L2 [14644 ] 14644 +IS L1_to_L2 [621 ] 621 IS Other_GETX [0 ] 0 IS Other_GETS [0 ] 0 IS Other_GETS_No_Mig [0 ] 0 +IS NC_DMA_GETS [0 ] 0 IS Invalidate [0 ] 0 IS Ack [0 ] 0 IS Shared_Ack [0 ] 0 IS Data [0 ] 0 IS Shared_Data [0 ] 0 -IS Exclusive_Data [90 ] 90 +IS Exclusive_Data [92 ] 92 SS Load [0 ] 0 SS Ifetch [0 ] 0 @@ -402,20 +412,22 @@ OI Other_GETX [0 ] 0 OI Other_GETS [0 ] 0 OI Merged_GETS [0 ] 0 OI Other_GETS_No_Mig [0 ] 0 +OI NC_DMA_GETS [0 ] 0 OI Invalidate [0 ] 0 OI Writeback_Ack [0 ] 0 MI Load [0 ] 0 -MI Ifetch [36 ] 36 -MI Store [5 ] 5 +MI Ifetch [1 ] 1 +MI Store [0 ] 0 MI L2_Replacement [0 ] 0 MI L1_to_L2 [0 ] 0 MI Other_GETX [0 ] 0 MI Other_GETS [0 ] 0 MI Merged_GETS [0 ] 0 MI Other_GETS_No_Mig [0 ] 0 +MI NC_DMA_GETS [0 ] 0 MI Invalidate [0 ] 0 -MI Writeback_Ack [848 ] 848 +MI Writeback_Ack [852 ] 852 II Load [0 ] 0 II Ifetch [0 ] 0 @@ -425,6 +437,7 @@ II L1_to_L2 [0 ] 0 II Other_GETX [0 ] 0 II Other_GETS [0 ] 0 II Other_GETS_No_Mig [0 ] 0 +II NC_DMA_GETS [0 ] 0 II Invalidate [0 ] 0 II Writeback_Ack [0 ] 0 II Writeback_Nack [0 ] 0 @@ -439,6 +452,7 @@ IT Other_GETX [0 ] 0 IT Other_GETS [0 ] 0 IT Merged_GETS [0 ] 0 IT Other_GETS_No_Mig [0 ] 0 +IT NC_DMA_GETS [0 ] 0 IT Invalidate [0 ] 0 ST Load [0 ] 0 @@ -451,6 +465,7 @@ ST Other_GETX [0 ] 0 ST Other_GETS [0 ] 0 ST Merged_GETS [0 ] 0 ST Other_GETS_No_Mig [0 ] 0 +ST NC_DMA_GETS [0 ] 0 ST Invalidate [0 ] 0 OT Load [0 ] 0 @@ -463,30 +478,33 @@ OT Other_GETX [0 ] 0 OT Other_GETS [0 ] 0 OT Merged_GETS [0 ] 0 OT Other_GETS_No_Mig [0 ] 0 +OT NC_DMA_GETS [0 ] 0 OT Invalidate [0 ] 0 MT Load [0 ] 0 MT Ifetch [0 ] 0 -MT Store [10 ] 10 +MT Store [2 ] 2 MT L2_Replacement [0 ] 0 -MT L1_to_L2 [154 ] 154 -MT Complete_L2_to_L1 [1 ] 1 +MT L1_to_L2 [39 ] 39 +MT Complete_L2_to_L1 [9 ] 9 MT Other_GETX [0 ] 0 MT Other_GETS [0 ] 0 MT Merged_GETS [0 ] 0 MT Other_GETS_No_Mig [0 ] 0 +MT NC_DMA_GETS [0 ] 0 MT Invalidate [0 ] 0 MMT Load [0 ] 0 -MMT Ifetch [11 ] 11 -MMT Store [41 ] 41 +MMT Ifetch [0 ] 0 +MMT Store [21 ] 21 MMT L2_Replacement [0 ] 0 -MMT L1_to_L2 [586 ] 586 -MMT Complete_L2_to_L1 [40 ] 40 +MMT L1_to_L2 [79 ] 79 +MMT Complete_L2_to_L1 [34 ] 34 MMT Other_GETX [0 ] 0 MMT Other_GETS [0 ] 0 MMT Merged_GETS [0 ] 0 MMT Other_GETS_No_Mig [0 ] 0 +MMT NC_DMA_GETS [0 ] 0 MMT Invalidate [0 ] 0 Cache Stats: system.dir_cntrl0.probeFilter @@ -498,42 +516,42 @@ Cache Stats: system.dir_cntrl0.probeFilter Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 1616 - memory_reads: 856 - memory_writes: 760 - memory_refreshes: 446 - memory_total_request_delays: 1108 - memory_delays_per_request: 0.685644 - memory_delays_in_input_queue: 161 - memory_delays_behind_head_of_bank_queue: 2 - memory_delays_stalled_at_head_of_bank_queue: 945 - memory_stalls_for_bank_busy: 192 + memory_total_requests: 1626 + memory_reads: 859 + memory_writes: 767 + memory_refreshes: 440 + memory_total_request_delays: 1086 + memory_delays_per_request: 0.667897 + memory_delays_in_input_queue: 156 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 930 + memory_stalls_for_bank_busy: 238 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 83 - memory_stalls_for_bus: 395 + memory_stalls_for_arbitration: 61 + memory_stalls_for_bus: 358 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 154 - memory_stalls_for_read_read_turnaround: 121 - accesses_per_bank: 34 44 48 84 67 62 61 53 41 30 54 49 46 47 41 52 49 35 67 45 67 44 44 46 55 52 53 50 44 47 56 49 + memory_stalls_for_read_write_turnaround: 169 + memory_stalls_for_read_read_turnaround: 104 + accesses_per_bank: 41 42 40 76 63 66 54 43 49 56 52 46 53 60 61 57 50 44 44 42 48 49 42 47 53 52 49 52 50 47 41 57 --- Directory --- - Event Counts - -GETX [770 ] 770 -GETS [91 ] 91 -PUT [909 ] 909 +GETX [767 ] 767 +GETS [93 ] 93 +PUT [907 ] 907 Unblock [0 ] 0 UnblockS [0 ] 0 -UnblockM [853 ] 853 +UnblockM [856 ] 856 Writeback_Clean [0 ] 0 Writeback_Dirty [0 ] 0 -Writeback_Exclusive_Clean [86 ] 86 -Writeback_Exclusive_Dirty [760 ] 760 +Writeback_Exclusive_Clean [85 ] 85 +Writeback_Exclusive_Dirty [767 ] 767 Pf_Replacement [0 ] 0 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -Memory_Data [854 ] 854 -Memory_Ack [760 ] 760 +Memory_Data [859 ] 859 +Memory_Ack [767 ] 767 Ack [0 ] 0 Shared_Ack [0 ] 0 Shared_Data [0 ] 0 @@ -554,7 +572,7 @@ NX DMA_WRITE [0 ] 0 NO GETX [0 ] 0 NO GETS [0 ] 0 -NO PUT [849 ] 849 +NO PUT [852 ] 852 NO Pf_Replacement [0 ] 0 NO DMA_READ [0 ] 0 NO DMA_WRITE [0 ] 0 @@ -573,8 +591,8 @@ O Pf_Replacement [0 ] 0 O DMA_READ [0 ] 0 O DMA_WRITE [0 ] 0 -E GETX [766 ] 766 -E GETS [90 ] 90 +E GETX [767 ] 767 +E GETS [92 ] 92 E PUT [0 ] 0 E DMA_READ [0 ] 0 E DMA_WRITE [0 ] 0 @@ -611,9 +629,9 @@ NO_R All_acks_and_data_no_sharers [0 ] 0 NO_B GETX [0 ] 0 NO_B GETS [0 ] 0 -NO_B PUT [60 ] 60 +NO_B PUT [55 ] 55 NO_B UnblockS [0 ] 0 -NO_B UnblockM [853 ] 853 +NO_B UnblockM [856 ] 856 NO_B Pf_Replacement [0 ] 0 NO_B DMA_READ [0 ] 0 NO_B DMA_WRITE [0 ] 0 @@ -624,6 +642,8 @@ NO_B_X PUT [0 ] 0 NO_B_X UnblockS [0 ] 0 NO_B_X UnblockM [0 ] 0 NO_B_X Pf_Replacement [0 ] 0 +NO_B_X DMA_READ [0 ] 0 +NO_B_X DMA_WRITE [0 ] 0 NO_B_S GETX [0 ] 0 NO_B_S GETS [0 ] 0 @@ -647,6 +667,7 @@ O_B GETX [0 ] 0 O_B GETS [0 ] 0 O_B PUT [0 ] 0 O_B UnblockS [0 ] 0 +O_B UnblockM [0 ] 0 O_B Pf_Replacement [0 ] 0 O_B DMA_READ [0 ] 0 O_B DMA_WRITE [0 ] 0 @@ -659,7 +680,7 @@ NO_B_W UnblockM [0 ] 0 NO_B_W Pf_Replacement [0 ] 0 NO_B_W DMA_READ [0 ] 0 NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [854 ] 854 +NO_B_W Memory_Data [859 ] 859 O_B_W GETX [0 ] 0 O_B_W GETS [0 ] 0 @@ -769,14 +790,14 @@ O_DR_B Shared_Ack [0 ] 0 O_DR_B All_acks_and_owner_data [0 ] 0 O_DR_B All_acks_and_data_no_sharers [0 ] 0 -WB GETX [2 ] 2 -WB GETS [1 ] 1 +WB GETX [0 ] 0 +WB GETS [0 ] 0 WB PUT [0 ] 0 WB Unblock [0 ] 0 WB Writeback_Clean [0 ] 0 WB Writeback_Dirty [0 ] 0 -WB Writeback_Exclusive_Clean [86 ] 86 -WB Writeback_Exclusive_Dirty [760 ] 760 +WB Writeback_Exclusive_Clean [85 ] 85 +WB Writeback_Exclusive_Dirty [767 ] 767 WB Pf_Replacement [0 ] 0 WB DMA_READ [0 ] 0 WB DMA_WRITE [0 ] 0 @@ -789,8 +810,8 @@ WB_O_W DMA_READ [0 ] 0 WB_O_W DMA_WRITE [0 ] 0 WB_O_W Memory_Ack [0 ] 0 -WB_E_W GETX [2 ] 2 -WB_E_W GETS [0 ] 0 +WB_E_W GETX [0 ] 0 +WB_E_W GETS [1 ] 1 WB_E_W PUT [0 ] 0 WB_E_W Pf_Replacement [0 ] 0 WB_E_W DMA_READ [0 ] 0 diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index 03174a5ad..1073821b9 100755 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 5 2010 14:43:33 -M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates -M5 started Aug 5 2010 14:46:32 -M5 executing on svvint09 +M5 compiled Feb 8 2011 17:56:59 +M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip +M5 started Feb 8 2011 17:57:03 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 213851 because Ruby Tester completed +Exiting @ tick 210961 because Ruby Tester completed diff --git a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 6827d9d11..a2b6d6c54 100644 --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 209796 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host -host_tick_rate 485996 # Simulator tick rate (ticks/s) +host_mem_usage 212552 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 1803209 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000214 # Number of seconds simulated -sim_ticks 213851 # Number of ticks simulated +sim_seconds 0.000211 # Number of seconds simulated +sim_ticks 210961 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff --git a/util/make_release.py b/util/make_release.py deleted file mode 100755 index 5a47f0658..000000000 --- a/util/make_release.py +++ /dev/null @@ -1,222 +0,0 @@ -#!/usr/bin/env python -# Copyright (c) 2006-2008 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Ali Saidi -# Steve Reinhardt -# Nathan Binkert - -import os -import re -import shutil -import sys -import time - -from glob import glob -from os import system -from os.path import basename, dirname, exists, isdir, isfile, join as joinpath - -def mkdir(*args): - path = joinpath(*args) - os.mkdir(path) - -def touch(*args, **kwargs): - when = kwargs.get('when', None) - path = joinpath(*args) - os.utime(path, when) - -def rmtree(*args): - path = joinpath(*args) - for match in glob(path): - if isdir(match): - shutil.rmtree(match) - else: - os.unlink(match) - -def remove(*args): - path = joinpath(*args) - for match in glob(path): - if not isdir(match): - os.unlink(match) - -def movedir(srcdir, destdir, dir): - src = joinpath(srcdir, dir) - dest = joinpath(destdir, dir) - - if not isdir(src): - raise AttributeError - - os.makedirs(dirname(dest)) - shutil.move(src, dest) - -if not isdir('.hg'): - sys.exit('Not in the top level of an m5 tree!') - -usage = '%s <destdir> <release name>' % sys.argv[0] - -if len(sys.argv) != 3: - sys.exit(usage) - -destdir = sys.argv[1] -releasename = sys.argv[2] -release_dest = joinpath(destdir, 'release') -#encumbered_dest = joinpath(destdir, 'encumbered') -release_dir = joinpath(release_dest, releasename) -#encumbered_dir = joinpath(encumbered_dest, releasename) - -if exists(destdir): - if not isdir(destdir): - raise AttributeError, '%s exists, but is not a directory' % destdir -else: - mkdir(destdir) - -if exists(release_dest): - if not isdir(release_dest): - raise AttributeError, \ - '%s exists, but is not a directory' % release_dest - rmtree(release_dest) - -#if exists(encumbered_dest): -# if not isdir(encumbered_dest): -# raise AttributeError, \ -# '%s exists, but is not a directory' % encumbered_dest -# rmtree(encumbered_dest) - -mkdir(release_dest) -#mkdir(encumbered_dest) -mkdir(release_dir) -#mkdir(encumbered_dir) - -system('hg update') -system('rsync -av --exclude ".hg*" --exclude build . %s' % release_dir) -# move the time forward on some files by a couple of minutes so we can -# avoid building things unnecessarily -when = int(time.time()) + 120 - -# make sure scons doesn't try to run flex unnecessarily -#touch(release_dir, 'src/encumbered/eio/exolex.cc', when=(when, when)) - -# get rid of non-shipping code -#rmtree(release_dir, 'src/encumbered/dev') -rmtree(release_dir, 'src/cpu/ozone') -#rmtree(release_dir, 'src/mem/cache/tags/split*.cc') -#rmtree(release_dir, 'src/mem/cache/tags/split*.hh') -#rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.cc') -#rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.hh') -#rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.cc') -#rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh') -rmtree(release_dir, 'configs/fullsys') -rmtree(release_dir, 'configs/test') -rmtree(release_dir, 'tests/long/*/ref') -rmtree(release_dir, 'tests/old') -rmtree(release_dir, 'tests/quick/00.hello/ref/x86') -rmtree(release_dir, 'tests/quick/02.insttest') -rmtree(release_dir, 'tests/test-progs/hello/bin/x86') - -remove(release_dir, 'src/cpu/nativetrace.hh') -remove(release_dir, 'src/cpu/nativetrace.cc') - -# get rid of some of private scripts -remove(release_dir, 'util/chgcopyright') -remove(release_dir, 'util/make_release.py') - -def remove_sources(regex, subdir): - script = joinpath(release_dir, subdir, 'SConscript') - if isinstance(regex, str): - regex = re.compile(regex) - inscript = file(script, 'r').readlines() - outscript = file(script, 'w') - for line in inscript: - if regex.match(line): - continue - - outscript.write(line) - outscript.close() - -def remove_lines(s_regex, e_regex, f): - f = joinpath(release_dir, f) - if isinstance(s_regex, str): - s_regex = re.compile(s_regex) - if isinstance(e_regex, str): - e_regex = re.compile(e_regex) - inscript = file(f, 'r').readlines() - outscript = file(f, 'w') - skipping = False - for line in inscript: - if (not skipping and s_regex.match(line)) or \ - (e_regex and skipping and not e_regex.match(line)): - if e_regex: - skipping = True - continue - skipping = False - outscript.write(line) - outscript.close() - -def replace_line(s_regex, f, rl): - f = joinpath(release_dir, f) - if isinstance(s_regex, str): - s_regex = re.compile(s_regex) - inscript = file(f, 'r').readlines() - outscript = file(f, 'w') - for line in inscript: - if s_regex.match(line): - outscript.write(rl) - continue - outscript.write(line) - outscript.close() - - -# fix up the SConscript to deal with files we've removed -#remove_sources(r'.*split.*\.cc', 'src/mem/cache/tags') -#remove_sources(r'.*(ghb|stride)_prefetcher\.cc', 'src/mem/cache/prefetch') -remove_sources(r'.*nativetrace.*', 'src/cpu') - -benches = [ 'bzip2', 'eon', 'gzip', 'mcf', 'parser', 'perlbmk', - 'twolf', 'vortex' ] -for bench in benches: - rmtree(release_dir, 'tests', 'test-progs', bench) - -#movedir(release_dir, encumbered_dir, 'src/encumbered') -rmtree(release_dir, 'tests/test-progs/anagram') -rmtree(release_dir, 'tests/quick/20.eio-short') - -f = open('src/cpu/SConsopts', 'w+') -f.writelines(("Import('*')\n", "all_cpu_list.append('DummyCPUMakeSconsHappy')\n")) -f.close() - - -def taritup(directory, destdir, filename): - basedir = dirname(directory) - tarball = joinpath(destdir, filename) - tardir = basename(directory) - - system('cd %s; tar cfj %s %s' % (basedir, tarball, tardir)) - -taritup(release_dir, destdir, '%s.tar.bz2' % releasename) -#taritup(encumbered_dir, destdir, '%s-encumbered.tar.bz2' % releasename) - -print "release created in %s" % destdir -print "don't forget to tag the repository!" |