diff options
55 files changed, 6666 insertions, 6662 deletions
diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini index 474c2633d..80a3274df 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip +executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout index 223344a8e..e75420ce2 100755 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:02:05 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:52:49 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index b56c75dd6..319df7c1b 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 207071 # Simulator instruction rate (inst/s) -host_mem_usage 192708 # Number of bytes of host memory used -host_seconds 2731.20 # Real time elapsed on the host -host_tick_rate 61173967 # Simulator tick rate (ticks/s) +host_inst_rate 206060 # Simulator instruction rate (inst/s) +host_mem_usage 206972 # Number of bytes of host memory used +host_seconds 2744.60 # Real time elapsed on the host +host_tick_rate 61062862 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.167078 # Number of seconds simulated -sim_ticks 167078146500 # Number of ticks simulated +sim_seconds 0.167593 # Number of seconds simulated +sim_ticks 167593085500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 65718859 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 73181368 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 70112287 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 76039018 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 63922842 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 71487962 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 180 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4121924 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70504427 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76440051 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1674270 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 18448626 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 322711250 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.865001 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.301723 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 323575021 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.860023 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.297815 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 108088758 33.49% 33.49% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 100475751 31.13% 64.63% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 37367184 11.58% 76.21% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 9733028 3.02% 79.22% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 10676883 3.31% 82.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 22147835 6.86% 89.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 13251874 4.11% 93.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 3269687 1.01% 94.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 17700250 5.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 107931872 33.36% 33.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 101513205 31.37% 64.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 37265964 11.52% 76.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 10166735 3.14% 79.39% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 11290718 3.49% 82.88% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 21721468 6.71% 89.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 12702626 3.93% 93.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 2533807 0.78% 94.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 18448626 5.70% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 322711250 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 323575021 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed system.cpu.commit.COM:loads 115049510 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 154862033 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4121096 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61418165 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 61591802 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 113146786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 19647.173839 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.243845 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 112293703 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 16760670000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 853083 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 636806 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1688311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses +system.cpu.cpi 0.592670 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.592670 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 113443216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 19248.740390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7746.370369 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 112634831 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 15560393000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007126 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 808385 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 590181 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1690289000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001923 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 218204 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6922.723577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21318.181818 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 317.179202 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_avg_miss_latency 32797.392555 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35638.802347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 37116231 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 76584863381 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.059189 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2335090 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1996724 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12058958995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.008577 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 338366 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6528.414634 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 316.462124 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 123 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 851495 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 234500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 802995 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 235000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 152598107 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29275.574871 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency -system.cpu.dcache.demand_hits 149415339 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 93177362881 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3182768 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2629213 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 13708105995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 152894537 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29313.182507 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149751062 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 92145256381 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.020560 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3143475 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2586905 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 13749247995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003640 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 556570 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999561 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.203417 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 152598107 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29275.574871 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 24763.765109 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999563 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.208277 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 152894537 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29313.182507 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 149415339 # number of overall hits -system.cpu.dcache.overall_miss_latency 93177362881 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3182768 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2629213 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 13708105995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses +system.cpu.dcache.overall_hits 149751062 # number of overall hits +system.cpu.dcache.overall_miss_latency 92145256381 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.020560 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3143475 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2586905 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 13749247995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003640 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 556570 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 468828 # number of replacements -system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 470982 # number of replacements +system.cpu.dcache.sampled_refs 475078 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.203417 # Cycle average of tags in use -system.cpu.dcache.total_refs 150001657 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126581000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 334123 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 49202518 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689696194 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144199483 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 123896058 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9869862 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 163077390 # DTB accesses +system.cpu.dcache.tagsinuse 4094.208277 # Cycle average of tags in use +system.cpu.dcache.total_refs 150344193 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126612000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 335213 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 51119249 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 861 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4177292 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 689843810 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 144051375 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 122990983 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9853353 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 3386 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5413414 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 163070578 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 163013880 # DTB hits -system.cpu.dtb.data_misses 63510 # DTB misses +system.cpu.dtb.data_hits 163012019 # DTB hits +system.cpu.dtb.data_misses 58559 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 122284109 # DTB read accesses +system.cpu.dtb.read_accesses 122259759 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122260496 # DTB read hits -system.cpu.dtb.read_misses 23613 # DTB read misses -system.cpu.dtb.write_accesses 40793281 # DTB write accesses +system.cpu.dtb.read_hits 122237048 # DTB read hits +system.cpu.dtb.read_misses 22711 # DTB read misses +system.cpu.dtb.write_accesses 40810819 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40753384 # DTB write hits -system.cpu.dtb.write_misses 39897 # DTB write misses -system.cpu.fetch.Branches 76039018 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 66014406 # Number of cache lines fetched -system.cpu.fetch.Cycles 197129335 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 698864013 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4233115 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 66014406 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 67411078 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.091429 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 332581112 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.101334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.065263 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 40774971 # DTB write hits +system.cpu.dtb.write_misses 35848 # DTB write misses +system.cpu.fetch.Branches 76440051 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65631744 # Number of cache lines fetched +system.cpu.fetch.Cycles 195845469 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1315609 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 699070033 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4181068 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.228053 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65631744 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 65597112 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.085617 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 333428374 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.096612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.077342 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 201466223 60.58% 60.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 10360747 3.12% 63.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 15882081 4.78% 68.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 14599006 4.39% 72.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 12362950 3.72% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 14822134 4.46% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 6008311 1.81% 82.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 3307530 0.99% 83.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 53772130 16.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 203214688 60.95% 60.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 10311898 3.09% 64.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 15894466 4.77% 68.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 13958250 4.19% 72.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 12033268 3.61% 76.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 13973782 4.19% 80.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 5916300 1.77% 82.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 3411105 1.02% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 54714617 16.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 332581112 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 66014406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36214.713430 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35498.337029 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 66013237 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42335000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 333428374 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 65631744 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36217.817562 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35518.743109 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65630571 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42483500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32019500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1173 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 266 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32215500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 73185.406874 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 72360.056229 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 66014406 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36214.713430 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency -system.cpu.icache.demand_hits 66013237 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42335000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 65631744 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36217.817562 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency +system.cpu.icache.demand_hits 65630571 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42483500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32019500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1173 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 266 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32215500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 907 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.375881 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 769.803945 # Average occupied blocks per context -system.cpu.icache.overall_accesses 66014406 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36214.713430 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35498.337029 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.378038 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 774.221896 # Average occupied blocks per context +system.cpu.icache.overall_accesses 65631744 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36217.817562 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 66013237 # number of overall hits -system.cpu.icache.overall_miss_latency 42335000 # number of overall miss cycles +system.cpu.icache.overall_hits 65630571 # number of overall hits +system.cpu.icache.overall_miss_latency 42483500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.overall_misses 1169 # number of overall misses -system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32019500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1173 # number of overall misses +system.cpu.icache.overall_mshr_hits 266 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32215500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 907 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks. +system.cpu.icache.replacements 35 # number of replacements +system.cpu.icache.sampled_refs 907 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 769.803945 # Cycle average of tags in use -system.cpu.icache.total_refs 66013237 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 774.221896 # Cycle average of tags in use +system.cpu.icache.total_refs 65630571 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1575182 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67316859 # Number of branches executed -system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate -system.cpu.iew.EXEC:refs 164017993 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41189464 # Number of stores executed +system.cpu.idleCycles 1757798 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67441684 # Number of branches executed +system.cpu.iew.EXEC:nop 43298534 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.787674 # Inst execution rate +system.cpu.iew.EXEC:refs 164010690 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 41206389 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 487237002 # num instructions consuming a value -system.cpu.iew.WB:count 596051147 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back +system.cpu.iew.WB:consumers 488922033 # num instructions consuming a value +system.cpu.iew.WB:count 596002683 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.810520 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 395375802 # num instructions producing a value -system.cpu.iew.WB:rate 1.783750 # insts written-back per cycle -system.cpu.iew.WB:sent 597227180 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4671561 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2251979 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126977202 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663379957 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122828529 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6459968 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599258144 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2443 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 396281024 # num instructions producing a value +system.cpu.iew.WB:rate 1.778124 # insts written-back per cycle +system.cpu.iew.WB:sent 597106328 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4603784 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2069078 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126900612 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3145838 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 43054897 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 663551547 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122804301 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6319339 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599203767 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4454 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9869862 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 84552 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 32589 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9853353 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 86305 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 194 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 8787843 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 12289 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11927692 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 540315 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.692479 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.692479 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 89737 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5921 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11851102 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3242374 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 89737 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 943709 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3660075 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.687279 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.687279 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 438834840 72.45% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6546 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 124855453 20.61% 93.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 42021230 6.94% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 438810493 72.47% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6669 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.47% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 124770612 20.61% 93.07% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 41935289 6.93% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 605718112 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 7232323 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 605523106 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 7132172 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5390831 74.54% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 67 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 74.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1490139 20.60% 95.14% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 351286 4.86% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5335622 74.81% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 49 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 74.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1469402 20.60% 95.41% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 327099 4.59% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 332581112 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.821264 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.674645 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 333428374 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.816052 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.661323 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 92203773 27.72% 27.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 67051353 20.16% 47.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 80133780 24.09% 71.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 36043478 10.84% 82.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 30084945 9.05% 91.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14579095 4.38% 96.25% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 10850493 3.26% 99.51% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 1143008 0.34% 99.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 491187 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 91844434 27.55% 27.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 66796624 20.03% 47.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 82026036 24.60% 72.18% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 37142853 11.14% 83.32% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 29318508 8.79% 92.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 13804488 4.14% 96.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 11015283 3.30% 99.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 983503 0.29% 99.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 496645 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 332581112 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate -system.cpu.iq.iqInstsAdded 620382553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605718112 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53519286 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29313548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 333428374 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.806528 # Inst issue rate +system.cpu.iq.iqInstsAdded 620252984 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605523106 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 53278148 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 39411 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 29138505 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 66014446 # ITB accesses +system.cpu.itb.fetch_accesses 65631783 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 66014406 # ITB hits -system.cpu.itb.fetch_misses 40 # ITB misses +system.cpu.itb.fetch_hits 65631744 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,106 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 256875 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.188321 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.765450 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 8801356500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 256875 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 7998513500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34303.986479 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.630238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1227945500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1110235500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 256875 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 219110 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34284.038279 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31037.107304 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 183268 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1228808500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.163580 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35842 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1112432000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.163580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35842 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 81505 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34131.924422 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31025.814367 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2781922500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 81505 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528759000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5083.333333 # average number of cycles each access was blocked +system.cpu.l2cache.UpgradeReq_mshr_misses 81505 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 335213 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 335213 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5455.882353 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 78 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 3.750936 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 68 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 396500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 371000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34265.684253 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10020759500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 475985 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34265.741313 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 183268 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10030165000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.614971 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 292717 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9102618000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9110945500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.614971 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 292717 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.051040 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.447409 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1672.465668 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14660.696789 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34265.684253 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.127143 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.051123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.447698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1675.210024 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14670.153699 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 475985 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34265.741313 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 181383 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10020759500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 292443 # number of overall misses +system.cpu.l2cache.overall_hits 183268 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10030165000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.614971 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 292717 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9102618000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9110945500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.614971 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 292717 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 85262 # number of replacements -system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 85307 # number of replacements +system.cpu.l2cache.sampled_refs 100934 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16333.162457 # Cycle average of tags in use -system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16345.363723 # Cycle average of tags in use +system.cpu.l2cache.total_refs 378597 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 63236 # number of writebacks -system.cpu.memDep0.conflictingLoads 19292303 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 14732751 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 126977202 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43223597 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 334156294 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 15214853 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 63240 # number of writebacks +system.cpu.memDep0.conflictingLoads 18950859 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15231969 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 126900612 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 43054897 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 335186172 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14808263 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31587363 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 151899436 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 896816353 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680424744 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 519473797 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 116400987 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9869862 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 39195268 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 55618908 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 77660298 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.timesIdled 36534 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 34154270 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 151775927 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2034435 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 895748431 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 680023810 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 518612424 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 115460168 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9853353 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 41529646 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 54757535 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 1017 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 80752072 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 33 # count of temporary serializing insts renamed +system.cpu.timesIdled 42487 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini index 4a852e5ff..7751f11d1 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout index 23f626d38..0c73642e7 100755 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:32 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:45:56 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:48:22 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -43,4 +43,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1102659088000 because target called exit() +Exiting @ tick 1088715493000 because target called exit() diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt index e06d74489..74618889d 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,422 +1,422 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 117151 # Simulator instruction rate (inst/s) -host_mem_usage 194316 # Number of bytes of host memory used -host_seconds 11998.32 # Real time elapsed on the host -host_tick_rate 91901100 # Simulator tick rate (ticks/s) +host_inst_rate 141900 # Simulator instruction rate (inst/s) +host_mem_usage 208776 # Number of bytes of host memory used +host_seconds 9905.67 # Real time elapsed on the host +host_tick_rate 109908342 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1405618365 # Number of instructions simulated -sim_seconds 1.102659 # Number of seconds simulated -sim_ticks 1102659088000 # Number of ticks simulated +sim_insts 1405618369 # Number of instructions simulated +sim_seconds 1.088715 # Number of seconds simulated +sim_ticks 1088715493000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 182414509 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 203429498 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 173332559 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 194142411 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 254458061 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 254458061 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 81910123 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 251618660 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 251618660 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 86248929 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 8096109 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 8014877 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1964055004 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.758399 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.188214 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1942378796 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.766863 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.200662 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 1088074201 55.40% 55.40% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 575643784 29.31% 84.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 120435541 6.13% 90.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 120975798 6.16% 97.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 27955067 1.42% 98.42% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 8084166 0.41% 98.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 10447088 0.53% 99.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 4343250 0.22% 99.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 8096109 0.41% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 1072972593 55.24% 55.24% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 568760584 29.28% 84.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 118179777 6.08% 90.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 122167717 6.29% 96.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 27965504 1.44% 98.34% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 8603273 0.44% 98.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 11084471 0.57% 99.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 4630000 0.24% 99.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 8014877 0.41% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1964055004 # Number of insts commited each cycle -system.cpu.commit.COM:count 1489537508 # Number of instructions committed -system.cpu.commit.COM:loads 402517243 # Number of loads committed +system.cpu.commit.COM:committed_per_cycle::total 1942378796 # Number of insts commited each cycle +system.cpu.commit.COM:count 1489537512 # Number of instructions committed +system.cpu.commit.COM:loads 402517247 # Number of loads committed system.cpu.commit.COM:membars 51356 # Number of memory barriers committed -system.cpu.commit.COM:refs 569375199 # Number of memory references committed +system.cpu.commit.COM:refs 569375203 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions +system.cpu.commit.branchMispredicts 81910123 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 1489537512 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1390237652 # The number of squashed insts skipped by commit -system.cpu.committedInsts 1405618365 # Number of Instructions Simulated -system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated -system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14297.662769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.135084 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 425346235 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 13092355500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 915699 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 667386 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1685830500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses +system.cpu.commit.commitSquashedInsts 1349352602 # The number of squashed insts skipped by commit +system.cpu.committedInsts 1405618369 # Number of Instructions Simulated +system.cpu.committedInsts_total 1405618369 # Number of Instructions Simulated +system.cpu.cpi 1.549091 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.549091 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 421562233 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 14361.598866 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6977.217093 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 420657692 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 12990655000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 904541 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 666380 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1661701000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000565 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 238161 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 38025 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35025 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits -system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 1521000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses -system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 1401000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37763.269313 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.327068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 83930150000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 12696288000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 37779.329951 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36098.948570 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 164660283 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 82976518000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.013163 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 2196347 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1851198 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 12459516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 345149 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 1119.158447 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 1140.488307 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30916.284897 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency -system.cpu.dcache.demand_hits 589980331 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 97022505500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses -system.cpu.dcache.demand_misses 3138233 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2538011 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 14382118500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 588418863 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30948.287394 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency +system.cpu.dcache.demand_hits 585317975 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 95967173000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005270 # miss rate for demand accesses +system.cpu.dcache.demand_misses 3100888 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2517578 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 14121217000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.000991 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 583310 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999897 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.579742 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30916.284897 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23961.331807 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999896 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.574437 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 588418863 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30948.287394 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 589980331 # number of overall hits -system.cpu.dcache.overall_miss_latency 97022505500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses -system.cpu.dcache.overall_misses 3138233 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2538011 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 14382118500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses +system.cpu.dcache.overall_hits 585317975 # number of overall hits +system.cpu.dcache.overall_miss_latency 95967173000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005270 # miss rate for overall accesses +system.cpu.dcache.overall_misses 3100888 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2517578 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 14121217000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.000991 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 583310 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 523278 # number of replacements -system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 509323 # number of replacements +system.cpu.dcache.sampled_refs 513419 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use -system.cpu.dcache.total_refs 590215067 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 348749 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 416443317 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 3435538799 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 762668513 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 782001789 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 239759977 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 2941385 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 254458061 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 354588619 # Number of cache lines fetched -system.cpu.fetch.Cycles 1199300749 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 10659931 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3732201000 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 88873599 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 354588619 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 2203814981 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.693518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.831719 # Number of instructions fetched each cycle (Total) +system.cpu.dcache.tagsinuse 4095.574437 # Cycle average of tags in use +system.cpu.dcache.total_refs 585548366 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 166128000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 341989 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 421912263 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 3394284142 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 753420072 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 764076323 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 233540433 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 2970138 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 251618660 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 350290492 # Number of cache lines fetched +system.cpu.fetch.Cycles 1175688320 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 10057151 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3685758924 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 87714492 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.115558 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 350290492 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 173332559 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.692710 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 2175919229 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.693886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.844671 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 1359102894 61.67% 61.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 256500547 11.64% 73.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 81150170 3.68% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 38425919 1.74% 78.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 85384463 3.87% 82.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 41200023 1.87% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 32567288 1.48% 85.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 20688755 0.94% 86.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 288794922 13.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 290862633 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2203814981 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 354588619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 354586492 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 2175919229 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 350290492 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33351.843100 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.230992 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 350288376 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 70572500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 2116 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 735 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 48060500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 1381 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 257319.660377 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 253832.156522 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 354588619 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency -system.cpu.icache.demand_hits 354586492 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 350290492 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33351.843100 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency +system.cpu.icache.demand_hits 350288376 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 70572500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 2116 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 735 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 48060500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 1381 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.516598 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1057.993144 # Average occupied blocks per context -system.cpu.icache.overall_accesses 354588619 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.517203 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1059.231284 # Average occupied blocks per context +system.cpu.icache.overall_accesses 350290492 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33351.843100 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 354586492 # number of overall hits -system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles +system.cpu.icache.overall_hits 350288376 # number of overall hits +system.cpu.icache.overall_miss_latency 70572500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_misses 2127 # number of overall misses -system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 2116 # number of overall misses +system.cpu.icache.overall_mshr_hits 735 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 48060500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 1381 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 222 # number of replacements -system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks. +system.cpu.icache.replacements 223 # number of replacements +system.cpu.icache.sampled_refs 1380 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1057.993144 # Cycle average of tags in use -system.cpu.icache.total_refs 354586492 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1059.231284 # Cycle average of tags in use +system.cpu.icache.total_refs 350288376 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1503196 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 128154505 # Number of branches executed -system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate -system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 207432555 # Number of stores executed +system.cpu.idleCycles 1511758 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 126596313 # Number of branches executed +system.cpu.iew.EXEC:nop 341046394 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.865157 # Inst execution rate +system.cpu.iew.EXEC:refs 745176720 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 207345254 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1490113215 # num instructions consuming a value -system.cpu.iew.WB:count 1862924801 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back +system.cpu.iew.WB:consumers 1478969218 # num instructions consuming a value +system.cpu.iew.WB:count 1850021692 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.963149 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1435567297 # num instructions producing a value -system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle -system.cpu.iew.WB:sent 1872447487 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 91815044 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3100855 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 21390967 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 17059392 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 301399339 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2879831174 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94512444 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 1894795217 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1424467072 # num instructions producing a value +system.cpu.iew.WB:rate 0.849635 # insts written-back per cycle +system.cpu.iew.WB:sent 1860023576 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 88314915 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3103548 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 732453281 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 21345324 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 16485503 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 296886262 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2838946953 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 537831466 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 95847914 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1883819308 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 43195 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 9892 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 239759977 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 75722 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9926 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 233540433 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 76384 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 116246750 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 24118 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 134541383 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 90333500 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 6075012 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 329936034 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 130028306 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 6075012 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2827686 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 85487229 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.645540 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.645540 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1186637129 59.65% 59.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.65% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2990803 0.15% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 571681967 28.74% 88.54% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 227997762 11.46% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1178571095 59.53% 59.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 59.53% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2996630 0.15% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 570412087 28.81% 88.50% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 227687410 11.50% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 1989307661 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4014627 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 1979667222 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 5110932 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.002582 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 142220 3.54% 3.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.54% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 232755 5.80% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.34% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3328922 82.92% 92.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 310730 7.74% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 148685 2.91% 2.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 233686 4.57% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.48% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 4411963 86.32% 93.81% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 316598 6.19% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 2203814981 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.902665 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.144866 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 2175919229 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.909807 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.157368 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 1083881876 49.18% 49.18% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 586425801 26.61% 75.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 298714420 13.55% 89.35% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 164995038 7.49% 96.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 47215803 2.14% 98.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 14943143 0.68% 99.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 6716019 0.30% 99.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 790183 0.04% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 132698 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 1068255963 49.09% 49.09% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 579314637 26.62% 75.72% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 292421261 13.44% 89.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 161809686 7.44% 96.59% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 50369072 2.31% 98.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 14937591 0.69% 99.60% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 7897011 0.36% 99.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 777368 0.04% 99.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 136640 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 2203814981 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate -system.cpu.iq.iqInstsAdded 2506731488 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 1989307661 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 21683045 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1079315429 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 646014 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 19439374 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 1293054156 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.562838 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.514866 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 9570275000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::total 2175919229 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.909176 # Inst issue rate +system.cpu.iq.iqInstsAdded 2476265906 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 1979667222 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 21634653 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 1050976502 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1545941 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 19390982 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 1261656908 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 275258 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34298.440009 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.934352 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 9440920000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 275258 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 8578397500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34106.857257 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384760 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 214678 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1194217500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.140229 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 35014 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1085517500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140229 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 35014 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 275258 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 239542 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34105.753589 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.482948 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 204503 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1195031500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.146275 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 35039 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1086296000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.146275 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 35039 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 69939 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34214.100859 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.876206 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 2392900000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 69939 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2169639000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 348749 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 348749 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 69939 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 341989 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 341989 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 4.234507 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 4.064673 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34273.636870 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 214678 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10764492500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.593992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 314075 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 514800 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34276.681695 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 204503 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 10635951500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.602753 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 310297 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 9781481000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.593992 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 314075 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 9664693500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.602753 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 310297 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.055938 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.444640 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1832.969770 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 14569.950583 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34273.636870 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.774576 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.056082 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.444448 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1837.702550 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 14563.687199 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 514800 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34276.681695 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 214678 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10764492500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.593992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 314075 # number of overall misses +system.cpu.l2cache.overall_hits 204503 # number of overall hits +system.cpu.l2cache.overall_miss_latency 10635951500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.602753 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 310297 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 9781481000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.593992 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 314075 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 9664693500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.602753 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 310297 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 84499 # number of replacements -system.cpu.l2cache.sampled_refs 99950 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 84514 # number of replacements +system.cpu.l2cache.sampled_refs 99965 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 16402.920353 # Cycle average of tags in use -system.cpu.l2cache.total_refs 423239 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 16401.389748 # Cycle average of tags in use +system.cpu.l2cache.total_refs 406325 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 61948 # number of writebacks -system.cpu.memDep0.conflictingLoads 460341314 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 141106002 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 301399339 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 2205318177 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 17694861 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed -system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers -system.cpu.rename.RENAME:IQFullEvents 27117 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 826425901 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 23298995 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 4917191691 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 3093611594 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2420068259 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 717791884 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 239759977 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 32521130 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1175289009 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 369621228 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 21984761 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 170791702 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 21775082 # count of temporary serializing insts renamed -system.cpu.timesIdled 43184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.l2cache.writebacks 61949 # number of writebacks +system.cpu.memDep0.conflictingLoads 446168372 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144446189 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 732453281 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 296886262 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 2177430987 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 18705831 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 1244779258 # Number of HB maps that are committed +system.cpu.rename.RENAME:FullRegisterEvents 818 # Number of times there has been no free registers +system.cpu.rename.RENAME:IQFullEvents 29460 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 816810065 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 24399902 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 4857699412 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 3052479029 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2393152182 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 700108886 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 233540433 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 34052536 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1148372924 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 372701478 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 21719371 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 176909620 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 21553732 # count of temporary serializing insts renamed +system.cpu.timesIdled 44523 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 49 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 803aca1ba..035a139c8 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -660,7 +660,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -680,7 +680,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -806,7 +806,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index f51a48835..cde3a8c1f 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -2,6 +2,6 @@ warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: 125740500: Trying to launch CPU number 1! +warn: 125751000: Trying to launch CPU number 1! For more information see: http://www.m5sim.org/warn/8f7d2563 hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index dc5374eea..fa47c5c0e 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:11 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:36:15 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:36:17 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1907705384500 because m5_exit instruction encountered +Exiting @ tick 1907689250500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 5561f4961..3e4d779fa 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,447 +1,447 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 126888 # Simulator instruction rate (inst/s) -host_mem_usage 280000 # Number of bytes of host memory used -host_seconds 442.84 # Real time elapsed on the host -host_tick_rate 4307932213 # Simulator tick rate (ticks/s) +host_inst_rate 123563 # Simulator instruction rate (inst/s) +host_mem_usage 293920 # Number of bytes of host memory used +host_seconds 454.60 # Real time elapsed on the host +host_tick_rate 4196424819 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56190549 # Number of instructions simulated -sim_seconds 1.907705 # Number of seconds simulated -sim_ticks 1907705384500 # Number of ticks simulated +sim_insts 56171530 # Number of instructions simulated +sim_seconds 1.907689 # Number of seconds simulated +sim_ticks 1907689250500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 4976194 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 9270305 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 24350 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 550496 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 8475185 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 10093433 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 690374 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 5979895 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 670392 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5124021 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 9548324 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 25931 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 576265 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 8953132 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 10665388 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 730260 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 6306789 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 727470 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 69432713 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.574171 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.330726 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 73665183 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.571097 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.330919 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0-1 52133999 75.09% 75.09% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1-2 7662367 11.04% 86.12% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2-3 4443977 6.40% 92.52% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3-4 2023862 2.91% 95.44% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4-5 1473823 2.12% 97.56% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5-6 453845 0.65% 98.21% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6-7 276436 0.40% 98.61% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7-8 294012 0.42% 99.03% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 670392 0.97% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0-1 55454240 75.28% 75.28% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1-2 8064036 10.95% 86.23% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2-3 4660922 6.33% 92.55% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3-4 2129949 2.89% 95.44% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4-5 1559149 2.12% 97.56% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5-6 477103 0.65% 98.21% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6-7 293859 0.40% 98.61% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7-8 298455 0.41% 99.01% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 727470 0.99% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 69432713 # Number of insts commited each cycle -system.cpu0.commit.COM:count 39866260 # Number of instructions committed -system.cpu0.commit.COM:loads 6404474 # Number of loads committed -system.cpu0.commit.COM:membars 151021 # Number of memory barriers committed -system.cpu0.commit.COM:refs 10831640 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 73665183 # Number of insts commited each cycle +system.cpu0.commit.COM:count 42069937 # Number of instructions committed +system.cpu0.commit.COM:loads 6784715 # Number of loads committed +system.cpu0.commit.COM:membars 161083 # Number of memory barriers committed +system.cpu0.commit.COM:refs 11506692 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 524450 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 39866260 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 458375 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 6218733 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 37660679 # Number of Instructions Simulated -system.cpu0.committedInsts_total 37660679 # Number of Instructions Simulated -system.cpu0.cpi 2.679241 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.679241 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 147686 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147686 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15414.654688 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 548150 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 42069937 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 486094 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 6570892 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 39732534 # Number of Instructions Simulated +system.cpu0.committedInsts_total 39732534 # Number of Instructions Simulated +system.cpu0.cpi 2.659989 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.659989 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 157022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157022 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15337.494650 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 135219 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 135219 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 192174500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.084416 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 12467 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12467 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 3210 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109971000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.062680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11734.631539 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 143004 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 143004 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 215001000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.089274 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 14018 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 14018 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 3542 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 122932000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.066717 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9257 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 6414671 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6414671 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 28975.322669 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 10476 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 6796922 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6796922 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 28045.834026 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.577320 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27628.067292 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 5468114 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5468114 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 27426794500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.147561 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 946557 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 946557 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 250848 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 19979077000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.108456 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 5780701 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5780701 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 28500765500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.149512 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1016221 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1016221 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 272772 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 20540059000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.109380 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 695709 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639862500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 156551 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 156551 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54668.039693 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 743449 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639143000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 165236 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 165236 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 54890.406800 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51668.039693 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 140528 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 140528 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 875946000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.102350 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 16023 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 16023 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827877000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.102350 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51890.406800 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 147119 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147119 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 994449500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.109643 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 18117 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18117 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 940098500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.109643 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 16023 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 4258061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4258061 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 48857.609099 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 18117 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 4544003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4544003 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 48917.848661 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.542507 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54316.339615 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 2612712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2612712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 80387818274 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.386408 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1645349 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1645349 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1362208 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 15269947736 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.066495 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 2781940 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2781940 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 86196331165 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.387778 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1762063 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1762063 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1458631 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 16481315562 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.066776 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 283141 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050789497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9307.081114 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 16250 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 9.224233 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 116343 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 1082813738 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 32500 # number of cycles access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 303432 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1049908497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9537.404034 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 9.143990 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 120871 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 1152795563 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 10672732 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 11340925 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10672732 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 41596.652338 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 11340925 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 41283.431307 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 8080826 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 8562641 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8080826 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 107814612774 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.242853 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 8562641 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 114697096665 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.244979 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2591906 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2778284 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2591906 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1613056 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 35249024736 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.091715 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2778284 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1731403 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 37021374562 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.092310 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 978850 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1046881 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.863629 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 442.178159 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 10672732 # number of overall (read+write) accesses +system.cpu0.dcache.occ_%::0 0.870622 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 445.758667 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 11340925 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10672732 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 41596.652338 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 11340925 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 41283.431307 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.649983 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 35363.498394 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 8080826 # number of overall hits +system.cpu0.dcache.overall_hits::0 8562641 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 8080826 # number of overall hits -system.cpu0.dcache.overall_miss_latency 107814612774 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.242853 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 8562641 # number of overall hits +system.cpu0.dcache.overall_miss_latency 114697096665 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.244979 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2591906 # number of overall misses +system.cpu0.dcache.overall_misses::0 2778284 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2591906 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1613056 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 35249024736 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.091715 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2778284 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1731403 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 37021374562 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.092310 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 978850 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 1690651997 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1046881 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 1689051497 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 922726 # number of replacements -system.cpu0.dcache.sampled_refs 923123 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 987239 # number of replacements +system.cpu0.dcache.sampled_refs 987751 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 442.178159 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8515102 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 297339 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 33638519 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 26518 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 401378 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 50930123 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 25726073 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 9143955 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1094070 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 84180 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 924165 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 812672 # DTB accesses -system.cpu0.dtb.data_acv 801 # DTB access violations -system.cpu0.dtb.data_hits 11625422 # DTB hits -system.cpu0.dtb.data_misses 28525 # DTB misses +system.cpu0.dcache.tagsinuse 445.758667 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9031985 # Total number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.writebacks 319854 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 35782513 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 28650 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 428056 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 53705173 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 27333196 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 9585932 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1147003 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 91050 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 963541 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 873282 # DTB accesses +system.cpu0.dtb.data_acv 817 # DTB access violations +system.cpu0.dtb.data_hits 12339819 # DTB hits +system.cpu0.dtb.data_misses 31654 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 605265 # DTB read accesses -system.cpu0.dtb.read_acv 596 # DTB read access violations -system.cpu0.dtb.read_hits 7063658 # DTB read hits -system.cpu0.dtb.read_misses 24056 # DTB read misses -system.cpu0.dtb.write_accesses 207407 # DTB write accesses -system.cpu0.dtb.write_acv 205 # DTB write access violations -system.cpu0.dtb.write_hits 4561764 # DTB write hits -system.cpu0.dtb.write_misses 4469 # DTB write misses -system.cpu0.fetch.Branches 10093433 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 6456937 # Number of cache lines fetched -system.cpu0.fetch.Cycles 16710986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 292610 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 52006541 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 660337 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.100032 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 6456937 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 5666568 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.515416 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 70526783 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.737401 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.023896 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 648811 # DTB read accesses +system.cpu0.dtb.read_acv 602 # DTB read access violations +system.cpu0.dtb.read_hits 7477600 # DTB read hits +system.cpu0.dtb.read_misses 25745 # DTB read misses +system.cpu0.dtb.write_accesses 224471 # DTB write accesses +system.cpu0.dtb.write_acv 215 # DTB write access violations +system.cpu0.dtb.write_hits 4862219 # DTB write hits +system.cpu0.dtb.write_misses 5909 # DTB write misses +system.cpu0.fetch.Branches 10665388 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 6760263 # Number of cache lines fetched +system.cpu0.fetch.Cycles 17500096 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 314893 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 54825819 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 690026 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.100914 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 6760263 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 5854281 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.518751 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 74812186 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.732846 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.023907 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0-1 60303519 85.50% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1-2 761816 1.08% 86.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2-3 1433855 2.03% 88.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3-4 636077 0.90% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4-5 2329701 3.30% 92.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5-6 474692 0.67% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6-7 552515 0.78% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7-8 815434 1.16% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3219174 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0-1 64104390 85.69% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1-2 792685 1.06% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2-3 1475450 1.97% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3-4 663490 0.89% 89.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4-5 2416214 3.23% 92.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5-6 489674 0.65% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6-7 557514 0.75% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7-8 868698 1.16% 95.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3444071 4.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 70526783 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 6456937 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6456937 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15194.125887 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 74812186 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 6760263 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6760263 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15111.361670 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12131.650508 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 5806694 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5806694 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 9879873999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.100705 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 650243 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 650243 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 29877 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7526063499 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.096077 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12055.592401 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6055842 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6055842 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 10644760499 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.104200 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 704421 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 704421 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 31973 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 8106758999 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.099471 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 620366 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11808.794118 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 672448 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 11292.658537 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 9.361634 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu0.icache.avg_refs 9.007622 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 41 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 401499 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 462999 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 6456937 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 6760263 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6456937 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15194.125887 # average overall miss latency +system.cpu0.icache.demand_accesses::total 6760263 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15111.361670 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12131.650508 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 5806694 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6055842 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5806694 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 9879873999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.100705 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6055842 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 10644760499 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.104200 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 650243 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 704421 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 650243 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 29877 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7526063499 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.096077 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 704421 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 31973 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 8106758999 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.099471 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 620366 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 672448 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.995760 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.829037 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 6456937 # number of overall (read+write) accesses +system.cpu0.icache.occ_%::0 0.995774 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 509.836147 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 6760263 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6456937 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15194.125887 # average overall miss latency +system.cpu0.icache.overall_accesses::total 6760263 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15111.361670 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12131.650508 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12055.592401 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 5806694 # number of overall hits +system.cpu0.icache.overall_hits::0 6055842 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 5806694 # number of overall hits -system.cpu0.icache.overall_miss_latency 9879873999 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.100705 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6055842 # number of overall hits +system.cpu0.icache.overall_miss_latency 10644760499 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.104200 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 650243 # number of overall misses +system.cpu0.icache.overall_misses::0 704421 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 650243 # number of overall misses -system.cpu0.icache.overall_mshr_hits 29877 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7526063499 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.096077 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 704421 # number of overall misses +system.cpu0.icache.overall_mshr_hits 31973 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 8106758999 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.099471 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 620366 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 672448 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 619753 # number of replacements -system.cpu0.icache.sampled_refs 620265 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 671790 # number of replacements +system.cpu0.icache.sampled_refs 672302 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.829037 # Cycle average of tags in use -system.cpu0.icache.total_refs 5806694 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 25308080000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tagsinuse 509.836147 # Cycle average of tags in use +system.cpu0.icache.total_refs 6055842 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 25289603000 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 30375240 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 6436261 # Number of branches executed -system.cpu0.iew.EXEC:nop 2512857 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.402648 # Inst execution rate -system.cpu0.iew.EXEC:refs 11740586 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 4575950 # Number of stores executed +system.cpu0.idleCycles 30875932 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 6794464 # Number of branches executed +system.cpu0.iew.EXEC:nop 2650714 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.405657 # Inst execution rate +system.cpu0.iew.EXEC:refs 12475412 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 4878585 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 24161341 # num instructions consuming a value -system.cpu0.iew.WB:count 40226053 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.779058 # average fanout of values written-back +system.cpu0.iew.WB:consumers 25547065 # num instructions consuming a value +system.cpu0.iew.WB:count 42445288 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.775506 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 18823082 # num instructions producing a value -system.cpu0.iew.WB:rate 0.398664 # insts written-back per cycle -system.cpu0.iew.WB:sent 40293911 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 568843 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 7178019 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 7553743 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1229599 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 771955 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 4836003 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 46191057 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 7164636 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 359402 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 40627967 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 33758 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 19811901 # num instructions producing a value +system.cpu0.iew.WB:rate 0.401609 # insts written-back per cycle +system.cpu0.iew.WB:sent 42518285 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 591859 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 7490199 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 8008916 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1306307 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 773924 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5151785 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 48752960 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 7596827 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 385648 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 42873082 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 34285 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 4184 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1094070 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 453368 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 4894 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1147003 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 462624 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 243041 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 357779 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 8886 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 256589 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 371728 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 8138 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 34087 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 12236 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1149269 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 408837 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 34087 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 255799 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 313044 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.373240 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.373240 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3326 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 28267868 68.97% 68.98% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 42211 0.10% 69.08% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.08% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 12076 0.03% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1657 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 7398159 18.05% 87.16% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 4612021 11.25% 98.41% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 650051 1.59% 100.00% # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 36722 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 12836 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1224201 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 429808 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 36722 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 290524 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 301335 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.375941 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.375941 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 29744442 68.76% 68.77% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 44172 0.10% 68.87% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.87% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 13702 0.03% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.90% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1883 0.00% 68.91% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.91% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 7844859 18.13% 87.04% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 4914921 11.36% 98.40% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 690973 1.60% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 40987369 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 290458 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007087 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 43258732 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 310534 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007179 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 33502 11.53% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 185621 63.91% 75.44% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 71335 24.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 34104 10.98% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.98% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 200961 64.71% 75.70% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 75469 24.30% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 70526783 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.581160 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.133092 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 74812186 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.578231 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.135171 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 49764700 70.56% 70.56% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 10507721 14.90% 85.46% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4625277 6.56% 92.02% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2839073 4.03% 96.04% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1729944 2.45% 98.50% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 663617 0.94% 99.44% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 315224 0.45% 99.88% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 67146 0.10% 99.98% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 14081 0.02% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 52955077 70.78% 70.78% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 11074556 14.80% 85.59% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 4848896 6.48% 92.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 2948908 3.94% 96.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 1827398 2.44% 98.45% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 727506 0.97% 99.43% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 332197 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 81828 0.11% 99.98% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 15820 0.02% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 70526783 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.406210 # Inst issue rate -system.cpu0.iq.iqInstsAdded 42280479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 40987369 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1397721 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 5737875 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 23380 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 939346 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3058582 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 74812186 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.409306 # Inst issue rate +system.cpu0.iq.iqInstsAdded 44617182 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 43258732 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1485064 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 6087251 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 24441 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 998970 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3229124 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 875811 # ITB accesses -system.cpu0.itb.fetch_acv 900 # ITB acv -system.cpu0.itb.fetch_hits 845925 # ITB hits -system.cpu0.itb.fetch_misses 29886 # ITB misses +system.cpu0.itb.fetch_accesses 930014 # ITB accesses +system.cpu0.itb.fetch_acv 893 # ITB acv +system.cpu0.itb.fetch_hits 898869 # ITB hits +system.cpu0.itb.fetch_misses 31145 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -452,551 +452,549 @@ system.cpu0.itb.write_hits 0 # DT system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wripir 96 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2410 1.86% 1.94% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.04% 1.98% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.98% # number of callpals executed -system.cpu0.kern.callpal::swpipl 116005 89.53% 91.51% # number of callpals executed -system.cpu0.kern.callpal::rdps 6357 4.91% 96.41% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.41% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.42% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.42% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.42% # number of callpals executed -system.cpu0.kern.callpal::rti 4116 3.18% 99.60% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.29% 99.90% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.10% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 129578 # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2652 1.92% 1.99% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.04% 2.03% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 2.04% # number of callpals executed +system.cpu0.kern.callpal::swpipl 124030 89.84% 91.88% # number of callpals executed +system.cpu0.kern.callpal::rdps 6358 4.61% 96.48% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.48% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.49% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.49% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.50% # number of callpals executed +system.cpu0.kern.callpal::rti 4305 3.12% 99.61% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.29% 99.90% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.10% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 138052 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 144417 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 4856 # number of quiesce instructions executed -system.cpu0.kern.ipl_count::0 47763 39.05% 39.05% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 239 0.20% 39.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1931 1.58% 40.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 17 0.01% 40.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 72358 59.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 122308 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 47113 48.87% 48.87% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 239 0.25% 49.12% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1931 2.00% 51.13% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 17 0.02% 51.14% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 47097 48.86% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 96397 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1871606920000 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 101495000 0.01% 98.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398001000 0.02% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 9331000 0.00% 98.16% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 35173046500 1.84% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907288793500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.986391 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.hwrei 153418 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 4853 # number of quiesce instructions executed +system.cpu0.kern.ipl_count::0 51417 39.39% 39.39% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 237 0.18% 39.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1931 1.48% 41.06% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 41.07% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 76919 58.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 130520 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 50665 48.95% 48.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 237 0.23% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1931 1.87% 51.05% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.02% 51.06% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 50649 48.94% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 103498 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1871325988500 98.09% 98.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 101211000 0.01% 98.10% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398014500 0.02% 98.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 8513500 0.00% 98.12% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 35854604500 1.88% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1907688332000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.985374 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.650889 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.ipl_used::31 0.658472 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1370 +system.cpu0.kern.mode_good::user 1371 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 5894 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 6220 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.217679 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.220257 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905143965500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2121516000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1905422249500 99.88% 99.88% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2266074500 0.12% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2411 # number of times the context was actually changed -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2050556 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1832562 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 7553743 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4836003 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 100902023 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 10627685 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 27337911 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 742850 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 26930386 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1646609 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 16617 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 58880297 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 48158408 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 32535845 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 9104791 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1094070 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 3612728 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5197934 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 19157121 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1163461 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 8536823 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 181475 # count of temporary serializing insts renamed -system.cpu0.timesIdled 904727 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.kern.swap_context 2653 # number of times the context was actually changed +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.memDep0.conflictingLoads 2188476 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1997712 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 8008916 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5151785 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 105688118 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 11112209 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 28779848 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 792454 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 28590888 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1753238 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 16675 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 62049686 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 50763826 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 34216131 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 9514762 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1147003 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3857610 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5436281 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 20589712 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1236784 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 9152277 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 192000 # count of temporary serializing insts renamed +system.cpu0.timesIdled 961954 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 2271371 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 5052294 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 16405 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 327507 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 4551940 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 5538388 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 417428 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 2947825 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 401526 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1953599 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 4355656 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 14923 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 286606 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 4049478 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 4938226 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 376891 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 2617539 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 356362 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 37477420 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.524684 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.336555 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 33118489 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.526612 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.338198 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0-1 29419430 78.50% 78.50% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1-2 3577485 9.55% 88.04% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2-3 1728132 4.61% 92.66% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3-4 1049887 2.80% 95.46% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4-5 708572 1.89% 97.35% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5-6 265966 0.71% 98.06% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6-7 180885 0.48% 98.54% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7-8 145537 0.39% 98.93% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 401526 1.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0-1 25969028 78.41% 78.41% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1-2 3179753 9.60% 88.01% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2-3 1522948 4.60% 92.61% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3-4 936064 2.83% 95.44% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4-5 628296 1.90% 97.34% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5-6 237537 0.72% 98.05% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6-7 164527 0.50% 98.55% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7-8 123974 0.37% 98.92% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 356362 1.08% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 37477420 # Number of insts commited each cycle -system.cpu1.commit.COM:count 19663805 # Number of instructions committed -system.cpu1.commit.COM:loads 3551077 # Number of loads committed -system.cpu1.commit.COM:membars 87378 # Number of memory barriers committed -system.cpu1.commit.COM:refs 5861573 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 33118489 # Number of insts commited each cycle +system.cpu1.commit.COM:count 17440586 # Number of instructions committed +system.cpu1.commit.COM:loads 3166581 # Number of loads committed +system.cpu1.commit.COM:membars 77258 # Number of memory barriers committed +system.cpu1.commit.COM:refs 5179825 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 311117 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 19663805 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 255745 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 3737019 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 18529870 # Number of Instructions Simulated -system.cpu1.committedInsts_total 18529870 # Number of Instructions Simulated -system.cpu1.cpi 2.312190 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.312190 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 72126 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72126 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14445.783133 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 272102 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 17440586 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 227930 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 3329840 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 16438996 # Number of Instructions Simulated +system.cpu1.committedInsts_total 16438996 # Number of Instructions Simulated +system.cpu1.cpi 2.304097 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.304097 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 63271 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 63271 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14821.069300 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11202.181535 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 59842 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59842 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 177452000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.170313 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 12284 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12284 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 2016 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 115024000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.142362 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 11124.971610 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 52535 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 52535 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 159119000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.169683 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 10736 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10736 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 1930 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97966500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.139179 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 10268 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 3589394 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3589394 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15546.336868 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 8806 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 3203716 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3203716 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15842.853412 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12022.349090 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12100.517465 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 2947184 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2947184 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 9984013000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.178919 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 642210 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 642210 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 211141 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 5182462000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.120095 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 2644617 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2644617 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 8857723500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.174516 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 559099 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 559099 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 185547 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 4520172500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.116600 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 431069 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298578500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 68169 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 68169 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 54676.100066 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_mshr_misses 373552 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 298583500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::0 59498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 54415.622389 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51676.100066 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits::0 51420 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 51420 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 915770000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.245698 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 16749 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 16749 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 865523000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.245698 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 51415.622389 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::0 45134 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 45134 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency 781626000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.241420 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 14364 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 14364 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 738534000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.241420 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 16749 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 2234886 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2234886 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 49366.459666 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 14364 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1946502 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1946502 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 49498.272766 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54247.809571 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 54160.909528 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1540754 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1540754 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 34266839381 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.310589 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 694132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 694132 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 551528 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 7735954636 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.063808 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1381655 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1381655 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 27958950877 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.290186 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 564847 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 564847 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 446490 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 6410322769 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.060805 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 142604 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526038500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13994.026145 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 8.879077 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 31364 # number of cycles access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 118357 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 526362000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13351.888091 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 18500 # average number of cycles each access was blocked +system.cpu1.dcache.avg_refs 9.264017 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 24797 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 438908636 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5000 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 331086769 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18500 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 5824280 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 5150218 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5824280 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 33113.418856 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 5150218 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 32756.622095 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 22518.780971 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 4487938 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 4026272 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4487938 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 44250852381 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.229443 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 4026272 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 36816674377 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.218233 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 1336342 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 1123946 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1336342 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 762669 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 12918416636 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.098497 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 1123946 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 632037 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 10930495269 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.095512 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 573673 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 491909 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.953247 # Average percentage of cache occupancy -system.cpu1.dcache.occ_%::1 -0.003823 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 488.062339 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -1.957577 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 5824280 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.951616 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 487.227171 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 5150218 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5824280 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 33113.418856 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 5150218 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 32756.622095 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 22518.780971 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 22220.563700 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 4487938 # number of overall hits +system.cpu1.dcache.overall_hits::0 4026272 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 4487938 # number of overall hits -system.cpu1.dcache.overall_miss_latency 44250852381 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.229443 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 4026272 # number of overall hits +system.cpu1.dcache.overall_miss_latency 36816674377 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.218233 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 1336342 # number of overall misses +system.cpu1.dcache.overall_misses::0 1123946 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 1336342 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 762669 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 12918416636 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.098497 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 1123946 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 632037 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 10930495269 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.095512 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 573673 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 824617000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 491909 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 824945500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 531784 # number of replacements -system.cpu1.dcache.sampled_refs 532296 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 455363 # number of replacements +system.cpu1.dcache.sampled_refs 455691 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 487.083551 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4726297 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 39405720000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 158239 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 17789619 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 18017 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 246499 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 26253455 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 14731428 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 4724231 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 641523 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 52769 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 232141 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 433929 # DTB accesses -system.cpu1.dtb.data_acv 77 # DTB access violations -system.cpu1.dtb.data_hits 6280304 # DTB hits -system.cpu1.dtb.data_misses 17153 # DTB misses +system.cpu1.dcache.tagsinuse 487.227171 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4221529 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 41371153000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 131807 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 15690044 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 15658 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 221514 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 23293804 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 13052984 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 4174567 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 566096 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 47077 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 200893 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 379955 # DTB accesses +system.cpu1.dtb.data_acv 65 # DTB access violations +system.cpu1.dtb.data_hits 5542909 # DTB hits +system.cpu1.dtb.data_misses 13981 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 314117 # DTB read accesses -system.cpu1.dtb.read_acv 13 # DTB read access violations -system.cpu1.dtb.read_hits 3872751 # DTB read hits -system.cpu1.dtb.read_misses 13436 # DTB read misses -system.cpu1.dtb.write_accesses 119812 # DTB write accesses -system.cpu1.dtb.write_acv 64 # DTB write access violations -system.cpu1.dtb.write_hits 2407553 # DTB write hits -system.cpu1.dtb.write_misses 3717 # DTB write misses -system.cpu1.fetch.Branches 5538388 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 3089103 # Number of cache lines fetched -system.cpu1.fetch.Cycles 8137045 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 192731 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 26826558 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 1090 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 373512 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.129267 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 3089103 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 2688799 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.626137 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 38118943 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.703759 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.021088 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 276518 # DTB read accesses +system.cpu1.dtb.read_acv 12 # DTB read access violations +system.cpu1.dtb.read_hits 3445692 # DTB read hits +system.cpu1.dtb.read_misses 11718 # DTB read misses +system.cpu1.dtb.write_accesses 103437 # DTB write accesses +system.cpu1.dtb.write_acv 53 # DTB write access violations +system.cpu1.dtb.write_hits 2097217 # DTB write hits +system.cpu1.dtb.write_misses 2263 # DTB write misses +system.cpu1.fetch.Branches 4938226 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 2741713 # Number of cache lines fetched +system.cpu1.fetch.Cycles 7194016 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 172775 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 23780795 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 326197 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.130375 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 2741713 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 2330490 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.627842 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 33684585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.705985 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.028331 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0-1 33077920 86.78% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1-2 338218 0.89% 87.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2-3 684572 1.80% 89.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3-4 401329 1.05% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4-5 792382 2.08% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5-6 254420 0.67% 93.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6-7 341251 0.90% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7-8 404733 1.06% 95.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1824118 4.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0-1 29238127 86.80% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1-2 297283 0.88% 87.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2-3 597287 1.77% 89.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3-4 350001 1.04% 90.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4-5 693611 2.06% 92.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5-6 228580 0.68% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6-7 280979 0.83% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7-8 354019 1.05% 95.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1644698 4.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 38118943 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 3089103 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 3089103 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14554.957905 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 33684585 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 2741713 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 2741713 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14618.155893 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11604.745633 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 2620972 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2620972 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 6813626999 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.151543 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 468131 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 468131 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 20962 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 5189282500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.144757 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11660.018500 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 2328949 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 2328949 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 6033848499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.150550 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 412764 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 412764 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 18169 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 4600985000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.143923 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 447169 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11057.692308 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 394595 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11340.909091 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.861938 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.avg_refs 5.902933 # Average number of references to valid blocks. +system.cpu1.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 287500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 249500 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 3089103 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 2741713 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 3089103 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14554.957905 # average overall miss latency +system.cpu1.icache.demand_accesses::total 2741713 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14618.155893 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11604.745633 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 2620972 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 2328949 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2620972 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 6813626999 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.151543 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 2328949 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 6033848499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.150550 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 468131 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 412764 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 468131 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 20962 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 5189282500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.144757 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 412764 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 18169 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 4600985000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.143923 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 447169 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 394595 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.985305 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 504.476148 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 3089103 # number of overall (read+write) accesses +system.cpu1.icache.occ_%::0 0.984930 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 504.284109 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 2741713 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 3089103 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14554.957905 # average overall miss latency +system.cpu1.icache.overall_accesses::total 2741713 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14618.155893 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11604.745633 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11660.018500 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 2620972 # number of overall hits +system.cpu1.icache.overall_hits::0 2328949 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 2620972 # number of overall hits -system.cpu1.icache.overall_miss_latency 6813626999 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.151543 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 2328949 # number of overall hits +system.cpu1.icache.overall_miss_latency 6033848499 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.150550 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 468131 # number of overall misses +system.cpu1.icache.overall_misses::0 412764 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 468131 # number of overall misses -system.cpu1.icache.overall_mshr_hits 20962 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 5189282500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.144757 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 412764 # number of overall misses +system.cpu1.icache.overall_mshr_hits 18169 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 4600985000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.143923 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 447169 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 394595 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 446606 # number of replacements -system.cpu1.icache.sampled_refs 447117 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 394030 # number of replacements +system.cpu1.icache.sampled_refs 394541 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 504.476148 # Cycle average of tags in use -system.cpu1.icache.total_refs 2620972 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 54243392000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tagsinuse 504.284109 # Cycle average of tags in use +system.cpu1.icache.total_refs 2328949 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 54145022000 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 4725629 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 3215720 # Number of branches executed -system.cpu1.iew.EXEC:nop 1316352 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.474690 # Inst execution rate -system.cpu1.iew.EXEC:refs 6453151 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 2418978 # Number of stores executed +system.cpu1.idleCycles 4192462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 2856676 # Number of branches executed +system.cpu1.iew.EXEC:nop 1154303 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.475940 # Inst execution rate +system.cpu1.iew.EXEC:refs 5695199 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 2106410 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 12377931 # num instructions consuming a value -system.cpu1.iew.WB:count 20081292 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.731656 # average fanout of values written-back +system.cpu1.iew.WB:consumers 11059026 # num instructions consuming a value +system.cpu1.iew.WB:count 17811363 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.729393 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 9056386 # num instructions producing a value -system.cpu1.iew.WB:rate 0.468701 # insts written-back per cycle -system.cpu1.iew.WB:sent 20123893 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 338961 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 2501197 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 4247431 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 782465 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 352902 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 2557372 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 23476845 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 4034173 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 224909 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 20337896 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 13271 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 8066373 # num instructions producing a value +system.cpu1.iew.WB:rate 0.470242 # insts written-back per cycle +system.cpu1.iew.WB:sent 17846809 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 295481 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 2247167 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 3784809 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 705322 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 304722 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 2229881 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 20840957 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 3588789 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 201614 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 18027204 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 12484 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 2314 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 641523 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 92599 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 2361 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 566096 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 83136 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 96430 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 136935 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 5812 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 73212 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 122514 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 3897 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 18287 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 7643 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 696354 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 246876 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 18287 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 160561 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 178400 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.432490 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.432490 # IPC: Total IPC of All Threads -system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3984 0.02% 0.02% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 13476075 65.54% 65.56% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 28965 0.14% 65.70% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.70% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 13702 0.07% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1986 0.01% 65.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.77% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 4173782 20.30% 86.07% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 2443072 11.88% 97.95% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 421241 2.05% 100.00% # Type of FU issued +system.cpu1.iew.lsq.thread.0.memOrderViolation 16678 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 6458 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 618228 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 216637 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 16678 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 152685 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 142796 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.434009 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.434009 # IPC: Total IPC of All Threads +system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3528 0.02% 0.02% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 11967153 65.65% 65.67% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 27009 0.15% 65.82% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.82% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 12064 0.07% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.88% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1759 0.01% 65.89% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.89% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 3711124 20.36% 86.25% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 2127008 11.67% 97.92% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 379173 2.08% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 20562807 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 221150 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.010755 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 18228818 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 196946 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.010804 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 16139 7.30% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 131899 59.64% 66.94% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 73112 33.06% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 13962 7.09% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.09% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 116519 59.16% 66.25% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 66465 33.75% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 38118943 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.539438 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.158785 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 33684585 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.541162 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.162170 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 28405834 74.52% 74.52% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4664798 12.24% 86.76% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1989487 5.22% 91.98% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1362185 3.57% 95.55% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 979454 2.57% 98.12% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 465472 1.22% 99.34% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 186874 0.49% 99.83% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 52652 0.14% 99.97% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 12187 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 25088136 74.48% 74.48% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 4124812 12.25% 86.72% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 1756786 5.22% 91.94% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 1209447 3.59% 95.53% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 865609 2.57% 98.10% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 413218 1.23% 99.33% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 164057 0.49% 99.81% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 50935 0.15% 99.97% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 11585 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 38118943 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.479940 # Inst issue rate -system.cpu1.iq.iqInstsAdded 21283926 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 20562807 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 876567 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 3483517 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 16728 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 620822 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 1775091 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 33684585 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.481263 # Inst issue rate +system.cpu1.iq.iqInstsAdded 18897687 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 18228818 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 788967 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 3125649 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 15583 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 561037 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 1602623 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 525294 # ITB accesses -system.cpu1.itb.fetch_acv 109 # ITB acv -system.cpu1.itb.fetch_hits 518481 # ITB hits -system.cpu1.itb.fetch_misses 6813 # ITB misses +system.cpu1.itb.fetch_accesses 472041 # ITB accesses +system.cpu1.itb.fetch_acv 106 # ITB acv +system.cpu1.itb.fetch_hits 466299 # ITB hits +system.cpu1.itb.fetch_misses 5742 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1006,95 +1004,95 @@ system.cpu1.itb.write_acv 0 # DT system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1838 2.10% 2.13% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 2.13% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.14% # number of callpals executed -system.cpu1.kern.callpal::swpipl 79684 91.22% 93.36% # number of callpals executed -system.cpu1.kern.callpal::rdps 2408 2.76% 96.11% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.11% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.12% # number of callpals executed -system.cpu1.kern.callpal::rti 3206 3.67% 99.79% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.16% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.05% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1586 2.01% 2.04% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.04% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.05% # number of callpals executed +system.cpu1.kern.callpal::swpipl 71639 90.87% 92.92% # number of callpals executed +system.cpu1.kern.callpal::rdps 2407 3.05% 95.97% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 95.97% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 95.97% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 95.98% # number of callpals executed +system.cpu1.kern.callpal::rti 3007 3.81% 99.79% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.15% 99.95% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.05% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 87355 # number of callpals executed +system.cpu1.kern.callpal::total 78839 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 93966 # number of hwrei instructions executed -system.cpu1.kern.inst.quiesce 3806 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 34143 40.21% 40.21% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1928 2.27% 42.48% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 96 0.11% 42.59% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 48748 57.41% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 84915 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 33416 48.60% 48.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1928 2.80% 51.40% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 96 0.14% 51.54% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 33320 48.46% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 68760 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1871986905500 98.13% 98.13% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 352078000 0.02% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 40004500 0.00% 98.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 35325543000 1.85% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907704531000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978707 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.hwrei 84815 # number of hwrei instructions executed +system.cpu1.kern.inst.quiesce 3812 # number of quiesce instructions executed +system.cpu1.kern.ipl_count::0 30474 39.75% 39.75% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1928 2.51% 42.26% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 96 0.13% 42.39% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 44173 57.61% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 76671 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 29849 48.44% 48.44% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1928 3.13% 51.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 96 0.16% 51.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 29753 48.28% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 61626 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872267971000 98.16% 98.16% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 351911000 0.02% 98.18% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 40319500 0.00% 98.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 34610873000 1.81% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1907271074500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979491 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.683515 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 521 -system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.ipl_used::31 0.673556 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 424 +system.cpu1.kern.mode_good::user 366 system.cpu1.kern.mode_good::idle 58 -system.cpu1.kern.mode_switch::kernel 2305 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2035 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.226030 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch::kernel 1953 # number of protection mode switches +system.cpu1.kern.mode_switch::user 366 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.217102 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.028501 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.254532 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 46750182500 2.45% 2.45% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1015923000 0.05% 2.50% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1859938417500 97.50% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1839 # number of times the context was actually changed -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 906343 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 817120 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 4247431 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 2557372 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 42844572 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 3655833 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 13191652 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 331503 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 15199726 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 648645 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 1226 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 29419521 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 24525143 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 16182603 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 4333690 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 641523 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 1812010 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 2990949 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 12476159 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 728375 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 4962161 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 86287 # count of temporary serializing insts renamed -system.cpu1.timesIdled 480522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.kern.mode_switch_good::idle 0.028473 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.245575 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 44394454000 2.33% 2.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 886105500 0.05% 2.37% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1861549295500 97.63% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1587 # number of times the context was actually changed +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.memDep0.conflictingLoads 820507 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 719564 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 3784809 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 2229881 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 37877047 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 3238650 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 11736980 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 293624 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 13473240 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 554151 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 942 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 26045586 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 21738411 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 14384581 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 3820320 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 566096 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 1590671 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 2647601 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 10995606 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 652471 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 4381532 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 75403 # count of temporary serializing insts renamed +system.cpu1.timesIdled 422616 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1107,262 +1105,262 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115331.417143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115252.862069 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63331.417143 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 20182998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63252.862069 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 20053998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses::1 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 11082998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.ReadReq_mshr_miss_latency 11005998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137844.166490 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137849.677657 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85840.579852 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5727700806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85846.237437 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5727929806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3566847774 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3567082858 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6165.982406 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6166.374068 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10458 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64483844 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64487940 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137749.749658 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137755.447539 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5747883804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5747983804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses +system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3577930772 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3578088856 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_misses 41727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.024239 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.387817 # Average occupied blocks per context +system.iocache.occ_%::1 0.028124 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.449991 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137749.749658 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137755.447539 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85746.178062 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85752.021665 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5747883804 # number of overall miss cycles +system.iocache.overall_miss_latency 5747983804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses +system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3577930772 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3578088856 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_misses 41727 # number of overall MSHR misses +system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.replacements 41697 # number of replacements -system.iocache.sampled_refs 41713 # Sample count of references to valid blocks. +system.iocache.replacements 41696 # number of replacements +system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.387817 # Cycle average of tags in use +system.iocache.tagsinuse 0.449991 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1717170531000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1717168496000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41522 # number of writebacks -system.l2c.ReadExReq_accesses::0 221647 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 95855 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 317502 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 75026.275109 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 173484.417078 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 236243 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 78291 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 314534 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 69731.847293 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 210415.766819 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40223.037770 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 16629348799 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_mshr_miss_latency 40217.604332 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 16473660800 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 221647 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 95855 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 317502 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12770894938 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 1.432467 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 3.312315 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 236243 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 78291 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 314534 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12649803961 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 1.331400 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 4.017499 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 317502 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1321671 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 883108 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2204779 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 53351.845432 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 2020931.340670 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 314534 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1423603 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 771316 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2194919 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 53400.832785 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1985457.471546 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39977.821348 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 39990.811057 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1018788 # number of ReadReq hits -system.l2c.ReadReq_hits::1 875112 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1893900 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16159367000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.229167 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.009054 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 302883 # number of ReadReq misses -system.l2c.ReadReq_misses::1 7996 # number of ReadReq misses -system.l2c.ReadReq_misses::total 310879 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12427585500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.235204 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.352009 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1119803 # number of ReadReq hits +system.l2c.ReadReq_hits::1 763145 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1882948 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16223173000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.213402 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.010594 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 303800 # number of ReadReq misses +system.l2c.ReadReq_misses::1 8171 # number of ReadReq misses +system.l2c.ReadReq_misses::total 311971 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12475173500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.219128 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.404440 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 310862 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840472000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 78396 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 63553 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 141949 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 92463.818205 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 114059.029346 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 311951 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 839822000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 86460 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 54412 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 140872 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 83177.133796 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 132167.444461 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40093.290548 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 7248793492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40094.049918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 7191494988 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 78396 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 63553 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 141949 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5691202500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.810666 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.233553 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 86460 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 54412 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 140872 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5648129000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.629331 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.588988 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 141949 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 140872 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1423763998 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 455578 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 455578 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 455578 # number of Writeback hits -system.l2c.Writeback_hits::total 455578 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1423289998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 451661 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 451661 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 451661 # number of Writeback hits +system.l2c.Writeback_hits::total 451661 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.834791 # Average number of references to valid blocks. +system.l2c.avg_refs 4.797703 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 1543318 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 978963 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 1659846 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 849607 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2522281 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 62510.658683 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 315728.455181 # average overall miss latency +system.l2c.demand_accesses::total 2509453 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 60544.871057 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 378164.208554 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency -system.l2c.demand_hits::0 1018788 # number of demand (read+write) hits -system.l2c.demand_hits::1 875112 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency +system.l2c.demand_hits::0 1119803 # number of demand (read+write) hits +system.l2c.demand_hits::1 763145 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1893900 # number of demand (read+write) hits -system.l2c.demand_miss_latency 32788715799 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.339872 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.106083 # miss rate for demand accesses +system.l2c.demand_hits::total 1882948 # number of demand (read+write) hits +system.l2c.demand_miss_latency 32696833800 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.325357 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.101767 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 524530 # number of demand (read+write) misses -system.l2c.demand_misses::1 103851 # number of demand (read+write) misses +system.l2c.demand_misses::0 540043 # number of demand (read+write) misses +system.l2c.demand_misses::1 86462 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 628381 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 25198480438 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.407151 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.641867 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 626505 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 25124977461 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.377436 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.737382 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 628364 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 626485 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.065210 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.029545 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.380758 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 4273.595958 # Average occupied blocks per context -system.l2c.occ_blocks::1 1936.249784 # Average occupied blocks per context -system.l2c.occ_blocks::2 24953.333071 # Average occupied blocks per context -system.l2c.overall_accesses::0 1543318 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 978963 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.066802 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.029576 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.372873 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 4377.904620 # Average occupied blocks per context +system.l2c.occ_blocks::1 1938.298251 # Average occupied blocks per context +system.l2c.occ_blocks::2 24436.623036 # Average occupied blocks per context +system.l2c.overall_accesses::0 1659846 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 849607 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2522281 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 62510.658683 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 315728.455181 # average overall miss latency +system.l2c.overall_accesses::total 2509453 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 60544.871057 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 378164.208554 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40101.725175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40104.675229 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1018788 # number of overall hits -system.l2c.overall_hits::1 875112 # number of overall hits +system.l2c.overall_hits::0 1119803 # number of overall hits +system.l2c.overall_hits::1 763145 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 1893900 # number of overall hits -system.l2c.overall_miss_latency 32788715799 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.339872 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.106083 # miss rate for overall accesses +system.l2c.overall_hits::total 1882948 # number of overall hits +system.l2c.overall_miss_latency 32696833800 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.325357 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.101767 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 524530 # number of overall misses -system.l2c.overall_misses::1 103851 # number of overall misses +system.l2c.overall_misses::0 540043 # number of overall misses +system.l2c.overall_misses::1 86462 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 628381 # number of overall misses -system.l2c.overall_mshr_hits 17 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 25198480438 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.407151 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.641867 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 626505 # number of overall misses +system.l2c.overall_mshr_hits 20 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 25124977461 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.377436 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.737382 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 628364 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2264235998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 626485 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2263111998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 402142 # number of replacements -system.l2c.sampled_refs 433669 # Sample count of references to valid blocks. +system.l2c.replacements 402176 # number of replacements +system.l2c.sampled_refs 435074 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 31163.178813 # Cycle average of tags in use -system.l2c.total_refs 2096699 # Total number of references to valid blocks. -system.l2c.warmup_cycle 9278348000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 124293 # number of writebacks +system.l2c.tagsinuse 30752.825907 # Cycle average of tags in use +system.l2c.total_refs 2087356 # Total number of references to valid blocks. +system.l2c.warmup_cycle 9278644000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 124146 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 6eea1f6ec..8128ce648 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console +console=/dist/m5/system/binaries/console init_param=0 -kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +kernel=/dist/m5/system/binaries/vmlinux mem_mode=timing -pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal +pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -355,7 +355,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -375,7 +375,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -501,7 +501,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img +image_file=/dist/m5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 00e25aeac..f6482ad23 100755 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:35:15 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:36:15 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:37:22 +M5 executing on zizzer command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux +info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1867362977500 because m5_exit instruction encountered +Exiting @ tick 1867360295500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 75071ea91..6ec7aca0a 100644 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,447 +1,449 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 86499 # Simulator instruction rate (inst/s) -host_mem_usage 277924 # Number of bytes of host memory used -host_seconds 613.76 # Real time elapsed on the host -host_tick_rate 3042478511 # Simulator tick rate (ticks/s) +host_inst_rate 154746 # Simulator instruction rate (inst/s) +host_mem_usage 291744 # Number of bytes of host memory used +host_seconds 343.04 # Real time elapsed on the host +host_tick_rate 5443609822 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53090223 # Number of instructions simulated -sim_seconds 1.867363 # Number of seconds simulated -sim_ticks 1867362977500 # Number of ticks simulated +sim_insts 53083414 # Number of instructions simulated +sim_seconds 1.867360 # Number of seconds simulated +sim_ticks 1867360295500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6932886 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 13334785 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 41560 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 829405 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 12127013 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14563706 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1034705 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8461925 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 978098 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6774596 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12988394 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 41867 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 814870 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 12133144 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14563531 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1033178 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8461193 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 999873 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 100629475 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.559325 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.322901 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 100508484 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.559927 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.327303 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 76387036 75.91% 75.91% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 10760374 10.69% 86.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 5981089 5.94% 92.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 2990150 2.97% 95.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2079430 2.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 662647 0.66% 98.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 398739 0.40% 98.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 391912 0.39% 99.03% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 978098 0.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 76371825 75.99% 75.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 10652369 10.60% 86.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 5995069 5.96% 92.55% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 2948172 2.93% 95.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2094039 2.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 649751 0.65% 98.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 415244 0.41% 98.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 382142 0.38% 99.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 999873 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 100629475 # Number of insts commited each cycle -system.cpu.commit.COM:count 56284559 # Number of instructions committed -system.cpu.commit.COM:loads 9308572 # Number of loads committed -system.cpu.commit.COM:membars 228000 # Number of memory barriers committed -system.cpu.commit.COM:refs 15700770 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 100508484 # Number of insts commited each cycle +system.cpu.commit.COM:count 56277376 # Number of instructions committed +system.cpu.commit.COM:loads 9307406 # Number of loads committed +system.cpu.commit.COM:membars 227986 # Number of memory barriers committed +system.cpu.commit.COM:refs 15698987 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 787906 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56284559 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667787 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 9472622 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53090223 # Number of Instructions Simulated -system.cpu.committedInsts_total 53090223 # Number of Instructions Simulated -system.cpu.cpi 2.580471 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.580471 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 214422 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 214422 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.537615 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 773341 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56277376 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667767 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 9507253 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53083414 # Number of Instructions Simulated +system.cpu.committedInsts_total 53083414 # Number of Instructions Simulated +system.cpu.cpi 2.579204 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.579204 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 214827 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 214827 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15515.595548 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.147928 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 192250 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 192250 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 344010500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103404 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22172 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22172 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4650 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207007500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081717 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11814.625753 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 192545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 192545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 345718500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103721 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22282 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22282 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4847 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205988000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081158 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17522 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9342386 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9342386 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 23884.018523 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17435 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9344739 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9344739 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 23910.895806 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22765.012818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22793.768876 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7810012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7810012 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 36599249000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.164024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1532374 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1532374 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 447551 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24696009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7810277 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7810277 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 36690361000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.164206 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1534462 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1534462 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 450067 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24717449000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116043 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084823 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904976000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219797 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56331.488950 # average StoreCondReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 1084395 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904961500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219814 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219814 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56332.344016 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.488950 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 189796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 189796 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 1690001000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.136494 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 30001 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 30001 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599998000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136494 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53332.344016 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_hits::0 189827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 189827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 1689238000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.136420 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 29987 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29987 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599277000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136420 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 30001 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6157245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157245 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 49037.572489 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 29987 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6156609 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156609 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 49095.565499 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54494.404609 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54537.318055 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 3926713 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 3926713 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 109379874638 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.362261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 2230532 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2230532 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1833591 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 21631063460 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064467 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 3926536 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 3926536 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 109486695038 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.362224 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 2230073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2230073 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1833805 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 21611393951 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064365 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 396941 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235842997 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10022.289139 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.827872 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 137083 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 1373885462 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 66000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 396268 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235673497 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9968.474051 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.834980 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 138443 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 1380065453 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 85000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15499631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15501348 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15499631 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15501348 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 38830.043030 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 11736725 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 11736813 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11736725 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 145979123638 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.242774 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 11736813 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 146177056038 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.242852 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3762906 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3764535 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3762906 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2281142 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 46327072960 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.095600 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3764535 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2283872 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 46328842951 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.095518 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1481764 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1480663 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995450 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15499631 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::1 -0.019112 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.995421 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::1 -9.785268 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15501348 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15499631 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 38794.252006 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15501348 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 38830.043030 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31264.812048 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31289.255523 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 11736725 # number of overall hits +system.cpu.dcache.overall_hits::0 11736813 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 11736725 # number of overall hits -system.cpu.dcache.overall_miss_latency 145979123638 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.242774 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 11736813 # number of overall hits +system.cpu.dcache.overall_miss_latency 146177056038 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.242852 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3762906 # number of overall misses +system.cpu.dcache.overall_misses::0 3764535 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3762906 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2281142 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 46327072960 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.095600 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3764535 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2283872 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 46328842951 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.095518 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1481764 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2140818997 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1480663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2140634997 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1402110 # number of replacements -system.cpu.dcache.sampled_refs 1402622 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1401152 # number of replacements +system.cpu.dcache.sampled_refs 1401664 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995450 # Cycle average of tags in use -system.cpu.dcache.total_refs 12382168 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 430447 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48442278 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42798 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 614586 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 72711050 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37969720 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 13062350 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1643233 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134839 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1155126 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1236133 # DTB accesses +system.cpu.dcache.tagsinuse 507.102797 # Cycle average of tags in use +system.cpu.dcache.total_refs 12383673 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 430200 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 48440098 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42540 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 615090 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 72709786 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37935584 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12980555 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1639247 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 136073 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1152246 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1232975 # DTB accesses system.cpu.dtb.data_acv 823 # DTB access violations -system.cpu.dtb.data_hits 16770289 # DTB hits -system.cpu.dtb.data_misses 44393 # DTB misses +system.cpu.dtb.data_hits 16785642 # DTB hits +system.cpu.dtb.data_misses 44486 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 909859 # DTB read accesses -system.cpu.dtb.read_acv 588 # DTB read access violations -system.cpu.dtb.read_hits 10173052 # DTB read hits -system.cpu.dtb.read_misses 36219 # DTB read misses -system.cpu.dtb.write_accesses 326274 # DTB write accesses -system.cpu.dtb.write_acv 235 # DTB write access violations -system.cpu.dtb.write_hits 6597237 # DTB write hits -system.cpu.dtb.write_misses 8174 # DTB write misses -system.cpu.fetch.Branches 14563706 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8997144 # Number of cache lines fetched -system.cpu.fetch.Cycles 23480265 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 455601 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 74265234 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 2366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 967433 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.106306 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8997144 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7967591 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.542091 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 102272708 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.726149 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.019798 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 911401 # DTB read accesses +system.cpu.dtb.read_acv 582 # DTB read access violations +system.cpu.dtb.read_hits 10188595 # DTB read hits +system.cpu.dtb.read_misses 36193 # DTB read misses +system.cpu.dtb.write_accesses 321574 # DTB write accesses +system.cpu.dtb.write_acv 241 # DTB write access violations +system.cpu.dtb.write_hits 6597047 # DTB write hits +system.cpu.dtb.write_misses 8293 # DTB write misses +system.cpu.fetch.Branches 14563531 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8983923 # Number of cache lines fetched +system.cpu.fetch.Cycles 23375540 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 455206 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 74277236 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2199 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 956999 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.106371 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8983923 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7807774 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.542514 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 102147731 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.727155 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.025450 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 87829962 85.88% 85.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1051726 1.03% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 2021481 1.98% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 968950 0.95% 89.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 2998384 2.93% 92.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 688876 0.67% 93.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 831559 0.81% 94.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1217734 1.19% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4664036 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 87794438 85.95% 85.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1023092 1.00% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1967534 1.93% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 960313 0.94% 89.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 2993138 2.93% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 661201 0.65% 93.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 802863 0.79% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1218814 1.19% 95.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4726338 4.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 102272708 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8997144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8997144 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14906.743449 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 102147731 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8983923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8983923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14917.128866 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.437092 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7949609 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7949609 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15615335499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.116430 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1047535 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1047535 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51877 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11855735000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11909.331981 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7937479 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7937479 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15609939999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.116480 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1046444 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1046444 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 50514 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11860861000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110857 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 995658 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 11545.454545 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 995930 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 10883.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.985800 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.971412 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 60 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 635000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 653000 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8997144 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8983923 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8997144 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.demand_accesses::total 8983923 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14917.128866 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7949609 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7937479 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7949609 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15615335499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.116430 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7937479 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15609939999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.116480 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1047535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1046444 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1047535 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51877 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11855735000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.110664 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1046444 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 50514 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11860861000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.110857 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 995658 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 995930 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995649 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.772438 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8997144 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995671 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.783438 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8983923 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8997144 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14906.743449 # average overall miss latency +system.cpu.icache.overall_accesses::total 8983923 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14917.128866 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11907.437092 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11909.331981 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7949609 # number of overall hits +system.cpu.icache.overall_hits::0 7937479 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7949609 # number of overall hits -system.cpu.icache.overall_miss_latency 15615335499 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.116430 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7937479 # number of overall hits +system.cpu.icache.overall_miss_latency 15609939999 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.116480 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1047535 # number of overall misses +system.cpu.icache.overall_misses::0 1046444 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1047535 # number of overall misses -system.cpu.icache.overall_mshr_hits 51877 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11855735000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.110664 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1046444 # number of overall misses +system.cpu.icache.overall_mshr_hits 50514 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11860861000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.110857 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 995658 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 995930 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 994957 # number of replacements -system.cpu.icache.sampled_refs 995468 # Sample count of references to valid blocks. +system.cpu.icache.replacements 995232 # number of replacements +system.cpu.icache.sampled_refs 995743 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.772438 # Cycle average of tags in use -system.cpu.icache.total_refs 7949608 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 509.783438 # Cycle average of tags in use +system.cpu.icache.total_refs 7937478 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 25287643000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 34725081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9164165 # Number of branches executed -system.cpu.iew.EXEC:nop 3679313 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.420337 # Inst execution rate -system.cpu.iew.EXEC:refs 17053432 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6620337 # Number of stores executed +system.cpu.idleCycles 34765240 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9170733 # Number of branches executed +system.cpu.iew.EXEC:nop 3662671 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.420879 # Inst execution rate +system.cpu.iew.EXEC:refs 17068903 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6620272 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 34505393 # num instructions consuming a value -system.cpu.iew.WB:count 56992809 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.764525 # average fanout of values written-back +system.cpu.iew.WB:consumers 34614422 # num instructions consuming a value +system.cpu.iew.WB:count 57031603 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.763117 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26380221 # num instructions producing a value -system.cpu.iew.WB:rate 0.416013 # insts written-back per cycle -system.cpu.iew.WB:sent 57095823 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 857525 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9717535 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 11048107 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1799892 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1045221 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 7018400 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65886993 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10433095 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539578 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57585192 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 49355 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26414846 # num instructions producing a value +system.cpu.iew.WB:rate 0.416554 # insts written-back per cycle +system.cpu.iew.WB:sent 57130351 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 839771 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9768928 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 11058875 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1801420 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1004974 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 7015626 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65914650 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10448631 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 528111 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57623776 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 52093 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 6548 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1643233 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 548828 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 6603 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1639247 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 554420 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 307987 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 427807 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 311339 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 434411 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 10284 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 45865 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 15487 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1739535 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 626202 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 45865 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 381050 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 476475 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.387526 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.387526 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7284 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39611417 68.15% 68.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62110 0.11% 68.27% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 46318 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 18429 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1751469 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 624045 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 46318 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 408059 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 431712 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.387716 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.387716 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7287 0.01% 0.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39633385 68.15% 68.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62109 0.11% 68.27% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.32% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10788116 18.56% 86.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6673339 11.48% 98.36% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 953263 1.64% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10799740 18.57% 86.90% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6666948 11.46% 98.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 953172 1.64% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 58124772 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 433051 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007450 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 58151889 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 434913 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007479 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 50716 11.71% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 279321 64.50% 76.21% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 103014 23.79% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 52889 12.16% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 280249 64.44% 76.60% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 101775 23.40% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 102272708 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.568331 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.133996 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 102147731 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569292 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137713 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 73147659 71.52% 71.52% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 14648372 14.32% 85.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 6417102 6.27% 92.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 3925012 3.84% 95.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 2528533 2.47% 98.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 1035489 1.01% 99.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 441110 0.43% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 106525 0.10% 99.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 22906 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 73060847 71.52% 71.52% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14641510 14.33% 85.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 6377407 6.24% 92.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 3918998 3.84% 95.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 2506307 2.45% 98.39% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 1046173 1.02% 99.42% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 456673 0.45% 99.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 116088 0.11% 99.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 23728 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 102272708 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.424275 # Inst issue rate -system.cpu.iq.iqInstsAdded 60155940 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 58124772 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2051740 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8691644 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 34825 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1383953 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4676225 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 102147731 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.424736 # Inst issue rate +system.cpu.iq.iqInstsAdded 60199205 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 58151889 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2052774 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8775393 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 35779 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1385007 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4703772 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1303750 # ITB accesses -system.cpu.itb.fetch_acv 951 # ITB acv -system.cpu.itb.fetch_hits 1264322 # ITB hits -system.cpu.itb.fetch_misses 39428 # ITB misses +system.cpu.itb.fetch_accesses 1302209 # ITB accesses +system.cpu.itb.fetch_acv 948 # ITB acv +system.cpu.itb.fetch_hits 1264828 # ITB hits +system.cpu.itb.fetch_misses 37381 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -457,51 +459,51 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175681 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6794 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175662 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5221 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192652 # number of callpals executed +system.cpu.kern.callpal::total 192631 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211811 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74956 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211789 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6384 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74950 40.95% 40.95% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 237 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105947 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183030 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105933 57.88% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183009 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73583 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149305 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1824761131000 97.72% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 102621000 0.01% 97.72% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 392338000 0.02% 97.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 42106013000 2.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1867362103000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981763 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73583 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149292 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1824774879500 97.72% 97.72% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 102464000 0.01% 97.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 392165500 0.02% 97.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 42089912000 2.25% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1867359421000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981761 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694583 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.ipl_used::31 0.694618 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5972 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5971 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.319826 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320047 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.400971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 31331138500 1.68% 1.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3191204500 0.17% 1.85% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832839752000 98.15% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 1.401192 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 31307096500 1.68% 1.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 3189085000 0.17% 1.85% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1832863231500 98.15% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed @@ -534,29 +536,29 @@ system.cpu.kern.syscall::132 4 1.23% 98.77% # nu system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 3077147 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2881540 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 11048107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7018400 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 136997789 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14285499 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38258957 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1096982 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39563718 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2259510 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 15713 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 83436015 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 68679972 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 46025419 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12707474 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1643233 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 5244444 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7766460 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 28828338 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1705072 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 12828278 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 257070 # count of temporary serializing insts renamed -system.cpu.timesIdled 1322055 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3116609 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2798105 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 11058875 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 7015626 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 136912971 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 14296513 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38253474 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1101619 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39527204 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 2223744 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 15702 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 83467187 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 68675679 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 46041377 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12627654 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1639247 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 5214289 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7787901 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 28842822 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1704528 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 12805525 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 256634 # count of temporary serializing insts renamed +system.cpu.timesIdled 1324969 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -572,14 +574,14 @@ system.disk2.dma_write_txs 1 # Nu system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115260.104046 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115277.445087 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63260.104046 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19939998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10943998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -587,37 +589,37 @@ system.iocache.ReadReq_mshr_misses 173 # nu system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137794.253129 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137793.747738 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85790.836302 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5725626806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85790.377840 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5725605806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3564780830 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3564761780 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6161.136802 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6164.456543 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10470 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64537908 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64541860 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137700.390749 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5745566804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5745548804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -625,7 +627,7 @@ system.iocache.demand_misses::0 0 # nu system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3575724828 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3575708778 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -633,20 +635,20 @@ system.iocache.demand_mshr_misses 41725 # nu system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.079213 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.267415 # Average occupied blocks per context +system.iocache.occ_%::1 0.079211 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.267376 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137700.822145 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137700.390749 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85697.419485 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85697.034823 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5745566804 # number of overall miss cycles +system.iocache.overall_miss_latency 5745548804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -654,7 +656,7 @@ system.iocache.overall_misses::0 0 # nu system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3575724828 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3575708778 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -664,137 +666,137 @@ system.iocache.overall_mshr_uncacheable_misses 0 system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.267415 # Cycle average of tags in use +system.iocache.tagsinuse 1.267376 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1716179713000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1716180121000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52361.965557 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300511 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300511 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52374.719501 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40206.978448 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 15739064331 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_mshr_miss_latency 40217.943752 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 15739179332 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 300582 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 300582 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 12085493996 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses::0 300511 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 300511 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 12085934495 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 300582 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2097743 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2097743 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52046.745492 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 300511 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2097129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2097129 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52047.601080 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.135689 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40016.046370 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1786590 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1786590 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16194501000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.148328 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 311153 # number of ReadReq misses -system.l2c.ReadReq_misses::total 311153 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1785718 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1785718 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16208195500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.148494 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 311411 # number of ReadReq misses +system.l2c.ReadReq_misses::total 311411 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12450789500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.148327 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12461397000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.148493 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 311152 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 810515500 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 130274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 130274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 52273.201045 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 311410 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 810521500 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 130096 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 130096 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52274.462658 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.567435 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 6809838993 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_avg_mshr_miss_latency 40097.358873 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 6800698494 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 130274 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 130274 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 5223670500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses::0 130096 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 130096 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 5216506000 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 130274 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 130096 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1116273498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 430447 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 430447 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 430447 # number of Writeback hits -system.l2c.Writeback_hits::total 430447 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1116126498 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 430200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430200 # number of Writeback hits +system.l2c.Writeback_hits::total 430200 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 4.597861 # Average number of references to valid blocks. +system.l2c.avg_refs 4.595902 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2398325 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2397640 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2398325 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.demand_accesses::total 2397640 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52208.246855 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency -system.l2c.demand_hits::0 1786590 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency +system.l2c.demand_hits::0 1785718 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1786590 # number of demand (read+write) hits -system.l2c.demand_miss_latency 31933565331 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.255068 # miss rate for demand accesses +system.l2c.demand_hits::total 1785718 # number of demand (read+write) hits +system.l2c.demand_miss_latency 31947374832 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.255218 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 611735 # number of demand (read+write) misses +system.l2c.demand_misses::0 611922 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 611735 # number of demand (read+write) misses +system.l2c.demand_misses::total 611922 # number of demand (read+write) misses system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 24536283496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.255067 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 24547331495 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.255218 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 611734 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 611921 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.090392 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.377907 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5923.908547 # Average occupied blocks per context -system.l2c.occ_blocks::1 24766.488602 # Average occupied blocks per context -system.l2c.overall_accesses::0 2398325 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.090196 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.378860 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5911.076462 # Average occupied blocks per context +system.l2c.occ_blocks::1 24828.993432 # Average occupied blocks per context +system.l2c.overall_accesses::0 2397640 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2398325 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52201.631966 # average overall miss latency +system.l2c.overall_accesses::total 2397640 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52208.246855 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40109.399667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40115.197052 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1786590 # number of overall hits +system.l2c.overall_hits::0 1785718 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1786590 # number of overall hits -system.l2c.overall_miss_latency 31933565331 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.255068 # miss rate for overall accesses +system.l2c.overall_hits::total 1785718 # number of overall hits +system.l2c.overall_miss_latency 31947374832 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.255218 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 611735 # number of overall misses +system.l2c.overall_misses::0 611922 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 611735 # number of overall misses +system.l2c.overall_misses::total 611922 # number of overall misses system.l2c.overall_mshr_hits 1 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 24536283496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.255067 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 24547331495 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.255218 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 611734 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1926788998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 611921 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1926647998 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 396039 # number of replacements -system.l2c.sampled_refs 427720 # Sample count of references to valid blocks. +system.l2c.replacements 396067 # number of replacements +system.l2c.sampled_refs 427735 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 30690.397149 # Cycle average of tags in use -system.l2c.total_refs 1966597 # Total number of references to valid blocks. -system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 119094 # number of writebacks +system.l2c.tagsinuse 30740.069893 # Cycle average of tags in use +system.l2c.total_refs 1965828 # Total number of references to valid blocks. +system.l2c.warmup_cycle 5645113000 # Cycle when the warmup percentage was hit. +system.l2c.writebacks 119080 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini index ef5381d49..c1d630de3 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -353,12 +353,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon +executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout index 84704aca2..d81198635 100755 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:54 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:18:35 -M5 executing on SC2B0619 -command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/30.eon/alpha/tru64/o3-timing +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:43:41 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 86e5c6d82..ca20bd45c 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 119207 # Simulator instruction rate (inst/s) -host_mem_usage 198920 # Number of bytes of host memory used -host_seconds 3150.62 # Real time elapsed on the host -host_tick_rate 42847667 # Simulator tick rate (ticks/s) +host_inst_rate 229808 # Simulator instruction rate (inst/s) +host_mem_usage 213388 # Number of bytes of host memory used +host_seconds 1634.30 # Real time elapsed on the host +host_tick_rate 82387662 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated -sim_seconds 0.134997 # Number of seconds simulated -sim_ticks 134996684500 # Number of ticks simulated +sim_seconds 0.134646 # Number of seconds simulated +sim_ticks 134646047500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 38296034 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 45834466 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 62209737 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 35411688 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 43873215 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1393 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 5500503 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 35240813 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 62127254 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 12478438 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 44587532 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 13023462 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 254545673 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.566181 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.242361 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 253935739 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.569943 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.243237 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 123085210 48.35% 48.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 50466868 19.83% 68.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 18758377 7.37% 75.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 19955031 7.84% 83.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 11844121 4.65% 88.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 8478667 3.33% 91.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 5819307 2.29% 93.66% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 2974518 1.17% 94.83% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 13163574 5.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 122688628 48.31% 48.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 50190176 19.76% 68.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 18710011 7.37% 75.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 19547996 7.70% 83.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 12735073 5.02% 88.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 8256826 3.25% 91.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 5486679 2.16% 93.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 3296888 1.30% 94.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 13023462 5.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 254545673 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 253935739 # Number of insts commited each cycle system.cpu.commit.COM:count 398664594 # Number of instructions committed system.cpu.commit.COM:loads 100651995 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 174183397 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 5496166 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 95019473 # The number of squashed insts skipped by commit system.cpu.committedInsts 375574819 # Number of Instructions Simulated system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated -system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads +system.cpu.cpi 0.717013 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.717013 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33016.637478 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95499596 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 56557500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 95369422 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33035.714286 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31908.121827 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 95367714 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 56425000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1713 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 729 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1708 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 723 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 31429500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 30397.287074 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36179.950785 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73502664 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 549126991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000246 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 18065 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 14753 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 119827997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3249.700000 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 3312 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3499.727273 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40460.272684 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.avg_refs 40390.006697 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 32497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 38497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30545.726047 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169002312 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 602544992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 168890151 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30625.195519 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35200.720735 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168870378 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 605551991 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses -system.cpu.dcache.demand_misses 19726 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 15433 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 19773 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 15476 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 151257497 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4297 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.804192 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3293.970402 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30545.726047 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.804196 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3293.985737 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 168890151 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30625.195519 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35200.720735 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169002312 # number of overall hits -system.cpu.dcache.overall_miss_latency 602544992 # number of overall miss cycles +system.cpu.dcache.overall_hits 168870378 # number of overall hits +system.cpu.dcache.overall_miss_latency 605551991 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses -system.cpu.dcache.overall_misses 19726 # number of overall misses -system.cpu.dcache.overall_mshr_hits 15433 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 19773 # number of overall misses +system.cpu.dcache.overall_mshr_hits 15476 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 151257497 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4297 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 782 # number of replacements -system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 786 # number of replacements +system.cpu.dcache.sampled_refs 4181 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use -system.cpu.dcache.total_refs 169002559 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3293.985737 # Cycle average of tags in use +system.cpu.dcache.total_refs 168870618 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 635 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 185115437 # DTB accesses +system.cpu.dcache.writebacks 639 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 20455851 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4411 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11313984 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 531721678 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 132373008 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 100014717 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 15215664 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 13188 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1092163 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 184984239 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 185076670 # DTB hits -system.cpu.dtb.data_misses 38767 # DTB misses +system.cpu.dtb.data_hits 184965275 # DTB hits +system.cpu.dtb.data_misses 18964 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 104449499 # DTB read accesses +system.cpu.dtb.read_accesses 104315848 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 104412186 # DTB read hits -system.cpu.dtb.read_misses 37313 # DTB read misses -system.cpu.dtb.write_accesses 80665938 # DTB write accesses +system.cpu.dtb.read_hits 104298344 # DTB read hits +system.cpu.dtb.read_misses 17504 # DTB read misses +system.cpu.dtb.write_accesses 80668391 # DTB write accesses system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_hits 80664484 # DTB write hits -system.cpu.dtb.write_misses 1454 # DTB write misses -system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched -system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 6123542 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 269852647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.019263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.001909 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 80666931 # DTB write hits +system.cpu.dtb.write_misses 1460 # DTB write misses +system.cpu.fetch.Branches 62127254 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 63793845 # Number of cache lines fetched +system.cpu.fetch.Cycles 167246591 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1555705 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 544184292 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 5877257 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.230706 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 63793845 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 47890126 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.020796 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 269151403 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.021852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.019136 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 164102333 60.81% 60.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 12367121 4.58% 65.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 12410556 4.60% 69.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 6615129 2.45% 72.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 15923029 5.90% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 8709903 3.23% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 6580254 2.44% 84.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 4007808 1.49% 85.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39136514 14.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 165698966 61.56% 61.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 11106934 4.13% 65.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 11530416 4.28% 69.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 6307474 2.34% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 14437862 5.36% 77.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 9686725 3.60% 81.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 7134176 2.65% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 3886825 1.44% 85.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39362025 14.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269852647 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 269151403 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 63793845 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 32214.491857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30831.032720 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 63788994 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 156272500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 4851 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 939 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120611000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 3912 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16305.980061 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency -system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 63793845 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 32214.491857 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30831.032720 # average overall mshr miss latency +system.cpu.icache.demand_hits 63788994 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 156272500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses -system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 4851 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 939 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120611000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3912 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.890401 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1823.540410 # Average occupied blocks per context -system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.890533 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1823.811736 # Average occupied blocks per context +system.cpu.icache.overall_accesses 63793845 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 32214.491857 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30831.032720 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 63861348 # number of overall hits -system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles +system.cpu.icache.overall_hits 63788994 # number of overall hits +system.cpu.icache.overall_miss_latency 156272500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses -system.cpu.icache.overall_misses 4841 # number of overall misses -system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 4851 # number of overall misses +system.cpu.icache.overall_mshr_hits 939 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120611000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3912 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1991 # number of replacements +system.cpu.icache.sampled_refs 3912 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use -system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1823.811736 # Cycle average of tags in use +system.cpu.icache.total_refs 63788994 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 50976851 # Number of branches executed -system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate -system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 80676625 # Number of stores executed +system.cpu.idleCycles 140695 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 51026412 # Number of branches executed +system.cpu.iew.EXEC:nop 27112711 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.557485 # Inst execution rate +system.cpu.iew.EXEC:refs 191688570 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80679099 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 285463485 # num instructions consuming a value -system.cpu.iew.WB:count 415481237 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back +system.cpu.iew.WB:consumers 288216530 # num instructions consuming a value +system.cpu.iew.WB:count 415792778 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.699054 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 200770520 # num instructions producing a value -system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle -system.cpu.iew.WB:sent 416287464 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6390313 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10261544 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 419338652 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 201478800 # num instructions producing a value +system.cpu.iew.WB:rate 1.544021 # insts written-back per cycle +system.cpu.iew.WB:sent 416379790 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6053312 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 2368258 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 124922222 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 241 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 6336167 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 92376215 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 493684492 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 111009471 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9414741 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 419418502 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 122120 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 26143 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 15215664 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 517890 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 8752772 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 41071 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 5542509 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 605872 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 176126 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 24270227 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 18844813 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 605872 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1054390 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 4998922 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.394674 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.394674 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 166319014 38.71% 38.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 2152935 0.50% 39.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 35077566 8.17% 47.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7830879 1.82% 49.21% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2898460 0.67% 49.89% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 16788316 3.91% 53.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1569716 0.37% 54.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.16% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 113503270 26.42% 80.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 83426459 19.42% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 166405736 38.80% 38.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 2152798 0.50% 39.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34694447 8.09% 47.40% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7781263 1.81% 49.22% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2950957 0.69% 49.91% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 16800389 3.92% 53.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571056 0.37% 54.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 113131674 26.38% 80.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 83311342 19.43% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 429600196 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 428833243 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 10058147 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.023455 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 40640 0.39% 0.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 76056 0.73% 1.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 13381 0.13% 1.24% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 12891 0.12% 1.37% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 1723474 16.48% 17.85% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 1473560 14.09% 31.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 31.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 5907144 56.49% 88.43% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1209900 11.57% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 25860 0.26% 0.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.26% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 93260 0.93% 1.18% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 5650 0.06% 1.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 7446 0.07% 1.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 1317455 13.10% 14.41% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 1454078 14.46% 28.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 28.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 5920939 58.87% 87.74% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 1233459 12.26% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 269852647 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.591981 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720906 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 269151403 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.593279 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.717169 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 99465935 36.86% 36.86% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 57766030 21.41% 58.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 39984554 14.82% 73.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 29664959 10.99% 84.08% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 23966120 8.88% 92.96% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 10452563 3.87% 96.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 5712016 2.12% 98.95% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 2252970 0.83% 99.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 587500 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 98731931 36.68% 36.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 57661044 21.42% 58.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 40586976 15.08% 73.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 29421704 10.93% 84.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 23908046 8.88% 93.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 10239078 3.80% 96.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 5871323 2.18% 98.99% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 2172785 0.81% 99.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 558516 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 269852647 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate -system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 429600196 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 68228113 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 269151403 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.592446 # Inst issue rate +system.cpu.iq.iqInstsAdded 466571540 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 428833243 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 89966373 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 863763 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 69307198 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 63866476 # ITB accesses +system.cpu.itb.fetch_accesses 63794154 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 63866189 # ITB hits -system.cpu.itb.fetch_misses 287 # ITB misses +system.cpu.itb.fetch_hits 63793845 # ITB hits +system.cpu.itb.fetch_misses 309 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,106 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 3200 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34587.968437 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31457.812500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 110681499 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 3200 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 100665000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 3200 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4893 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34357.615894 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31171.594134 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 665 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 145264000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.864092 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4228 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 131793500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864092 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4228 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34466.386555 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31289.915966 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4101500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3000 # average number of cycles each access was blocked +system.cpu.l2cache.Writeback_accesses 639 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 639 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2666.666667 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.131910 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 6000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 8000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8093 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34456.852316 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31294.897684 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 665 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 255945499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.917830 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7428 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 232458500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.917830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7428 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.106709 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.011557 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3496.652993 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 378.690415 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.106843 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.011587 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3501.040941 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 379.684950 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 8093 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34456.852316 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31294.897684 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 655 # number of overall hits -system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7418 # number of overall misses +system.cpu.l2cache.overall_hits 665 # number of overall hits +system.cpu.l2cache.overall_miss_latency 255945499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.917830 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7428 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 232458500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.917830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7428 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 14 # number of replacements -system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 15 # number of replacements +system.cpu.l2cache.sampled_refs 4685 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use -system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3880.725891 # Cycle average of tags in use +system.cpu.l2cache.total_refs 618 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 73961217 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54131405 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 92324076 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 269993372 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 74849853 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55363768 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 124922222 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 92376215 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 269292098 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 9673248 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IQFullEvents 1504479 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 137416112 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8012015 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed -system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 682754738 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 518229128 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 335302113 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 95729398 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 15215664 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 10747190 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 75769772 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 369791 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37587 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 23404736 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed +system.cpu.timesIdled 3105 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index a58d921a8..cbeb23be8 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 6590e3c76..4e9d17041 100755 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:45:31 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:44:11 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 6efaa543d..88b7dc5dd 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,295 +1,295 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 178423 # Simulator instruction rate (inst/s) -host_mem_usage 199584 # Number of bytes of host memory used -host_seconds 10217.56 # Real time elapsed on the host -host_tick_rate 69014447 # Simulator tick rate (ticks/s) +host_inst_rate 173583 # Simulator instruction rate (inst/s) +host_mem_usage 213764 # Number of bytes of host memory used +host_seconds 10502.41 # Real time elapsed on the host +host_tick_rate 66694888 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated -sim_seconds 0.705159 # Number of seconds simulated -sim_ticks 705159454500 # Number of ticks simulated +sim_seconds 0.700457 # Number of seconds simulated +sim_ticks 700456762500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 240462096 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 294213603 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 3593 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 29107758 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 233918302 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 349424731 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 49888256 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 237313176 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 290294551 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 3578 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 28357853 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 231827098 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 346133867 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 49328779 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 266706457 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 68860244 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 69311011 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1310002801 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.533575 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.199105 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1302157693 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.542814 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.203929 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 603585597 46.08% 46.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 273587005 20.88% 66.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 174037133 13.29% 80.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 65399708 4.99% 85.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 48333001 3.69% 88.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 34003110 2.60% 91.52% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 18481318 1.41% 92.93% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 23715685 1.81% 94.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 68860244 5.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 596380613 45.80% 45.80% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 273242120 20.98% 66.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 173533589 13.33% 80.11% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 65306568 5.02% 85.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 48690140 3.74% 88.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 33944722 2.61% 91.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 18456166 1.42% 92.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 23292764 1.79% 94.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 69311011 5.32% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1310002801 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1302157693 # Number of insts commited each cycle system.cpu.commit.COM:count 2008987604 # Number of instructions committed system.cpu.commit.COM:loads 511595302 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 722390433 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 29095954 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 28346017 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 696013930 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 686852992 # The number of squashed insts skipped by commit system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.773607 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.773607 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 6 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 465737269 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37550.774879 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34829.991989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 463802710 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 72644189500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004154 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1934559 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 475266 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 50827163500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003133 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1459293 # number of ReadReq MSHR misses +system.cpu.cpi 0.768448 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.768448 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 9 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 463363512 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37524.078898 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34794.219854 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 461428955 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 72592469500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004175 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1934557 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 475286 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 50774196000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1459271 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 38583.618605 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.752250 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 210235541 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 21581939985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 38582.382670 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36523.414699 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210235446 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 21584913985 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 559355 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 484574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2731357498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 559450 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 484668 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2731293998 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 74781 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5124.928571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 440.284636 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 74782 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4879.241379 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 438.740100 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 143498 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 141498 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 676532165 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 37782.429340 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency -system.cpu.dcache.demand_hits 674038251 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 94226129485 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003686 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2493914 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 959840 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 53558520998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002268 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1534074 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 674158408 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 37761.475202 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency +system.cpu.dcache.demand_hits 671664401 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 94177383485 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003699 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2494007 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 959954 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 53505489998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002276 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1534053 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.104513 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 676532165 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 37782.429340 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34912.605909 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999780 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4095.099733 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 674158408 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 37761.475202 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 674038251 # number of overall hits -system.cpu.dcache.overall_miss_latency 94226129485 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003686 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2493914 # number of overall misses -system.cpu.dcache.overall_mshr_hits 959840 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 53558520998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002268 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1534074 # number of overall MSHR misses +system.cpu.dcache.overall_hits 671664401 # number of overall hits +system.cpu.dcache.overall_miss_latency 94177383485 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003699 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2494007 # number of overall misses +system.cpu.dcache.overall_mshr_hits 959954 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 53505489998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002276 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1534053 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1526847 # number of replacements -system.cpu.dcache.sampled_refs 1530943 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1526826 # number of replacements +system.cpu.dcache.sampled_refs 1530922 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.104513 # Cycle average of tags in use -system.cpu.dcache.total_refs 674050682 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 274499000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4095.099733 # Cycle average of tags in use +system.cpu.dcache.total_refs 671676872 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 274383000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 74589 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 32190527 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12129 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 30585324 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2936172402 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 716337474 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 561391036 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 100159084 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45706 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 83764 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 775959987 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 32140341 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 12074 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 30417175 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2923062124 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 711773443 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 558159581 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 98598096 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45812 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 84328 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 772918649 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 775335043 # DTB hits -system.cpu.dtb.data_misses 624944 # DTB misses +system.cpu.dtb.data_hits 772293170 # DTB hits +system.cpu.dtb.data_misses 625479 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 516992085 # DTB read accesses +system.cpu.dtb.read_accesses 514591069 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 516404963 # DTB read hits -system.cpu.dtb.read_misses 587122 # DTB read misses -system.cpu.dtb.write_accesses 258967902 # DTB write accesses +system.cpu.dtb.read_hits 514003488 # DTB read hits +system.cpu.dtb.read_misses 587581 # DTB read misses +system.cpu.dtb.write_accesses 258327580 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 258930080 # DTB write hits -system.cpu.dtb.write_misses 37822 # DTB write misses -system.cpu.fetch.Branches 349424731 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 348447899 # Number of cache lines fetched -system.cpu.fetch.Cycles 928021937 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 4387629 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3030218619 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 29544621 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.247763 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 348447899 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 290350352 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.148605 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1410161885 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.148845 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.029305 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 258289682 # DTB write hits +system.cpu.dtb.write_misses 37898 # DTB write misses +system.cpu.fetch.Branches 346133867 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 346369631 # Number of cache lines fetched +system.cpu.fetch.Cycles 922290632 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4326238 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3015904698 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28794725 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.247077 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 346369631 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 286641955 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.152813 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1400755789 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.153055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.032526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 830588040 58.90% 58.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 53463106 3.79% 62.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 39766072 2.82% 65.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 63538024 4.51% 70.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 121390719 8.61% 78.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 35256321 2.50% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 38761682 2.75% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 6988644 0.50% 84.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 220409277 15.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 824834992 58.88% 58.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 53206817 3.80% 62.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 38924738 2.78% 65.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 62366133 4.45% 69.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 120532729 8.60% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 35808657 2.56% 81.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 38526871 2.75% 83.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 7024237 0.50% 84.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 219530615 15.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1410161885 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 348447899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15851.065828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.513514 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 348437250 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 168798000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1400755789 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 346369631 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15843.963981 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11642.396973 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 346358970 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 168912500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10649 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 881 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 113685000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 10661 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 882 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 113851000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 9768 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 9779 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 35671.299140 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 35418.649146 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 348447899 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15851.065828 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency -system.cpu.icache.demand_hits 348437250 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 168798000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 346369631 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15843.963981 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency +system.cpu.icache.demand_hits 346358970 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 168912500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses -system.cpu.icache.demand_misses 10649 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 881 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 113685000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 10661 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 882 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 113851000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 9768 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 9779 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.788136 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1614.102824 # Average occupied blocks per context -system.cpu.icache.overall_accesses 348447899 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15851.065828 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11638.513514 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.788131 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1614.092315 # Average occupied blocks per context +system.cpu.icache.overall_accesses 346369631 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15843.963981 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 348437250 # number of overall hits -system.cpu.icache.overall_miss_latency 168798000 # number of overall miss cycles +system.cpu.icache.overall_hits 346358970 # number of overall hits +system.cpu.icache.overall_miss_latency 168912500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses -system.cpu.icache.overall_misses 10649 # number of overall misses -system.cpu.icache.overall_mshr_hits 881 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 113685000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 10661 # number of overall misses +system.cpu.icache.overall_mshr_hits 882 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 113851000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 9768 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 9779 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8097 # number of replacements -system.cpu.icache.sampled_refs 9768 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8106 # number of replacements +system.cpu.icache.sampled_refs 9779 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1614.102824 # Cycle average of tags in use -system.cpu.icache.total_refs 348437250 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1614.092315 # Cycle average of tags in use +system.cpu.icache.total_refs 346358970 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 157025 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 274534145 # Number of branches executed -system.cpu.iew.EXEC:nop 329178061 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.421117 # Inst execution rate -system.cpu.iew.EXEC:refs 776495503 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 258968900 # Number of stores executed +system.cpu.idleCycles 157737 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 273840918 # Number of branches executed +system.cpu.iew.EXEC:nop 328413541 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.427157 # Inst execution rate +system.cpu.iew.EXEC:refs 773454371 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 258328581 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1631503179 # num instructions consuming a value -system.cpu.iew.WB:count 2002130585 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.696431 # average fanout of values written-back +system.cpu.iew.WB:consumers 1628963056 # num instructions consuming a value +system.cpu.iew.WB:count 1998305294 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.696273 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1136229268 # num instructions producing a value -system.cpu.iew.WB:rate 1.419630 # insts written-back per cycle -system.cpu.iew.WB:sent 2003425032 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 31680133 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3459468 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 655954745 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 62130 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 303651290 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2715209778 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 517526603 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 85279852 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2004227953 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 131519 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1134203072 # num instructions producing a value +system.cpu.iew.WB:rate 1.426430 # insts written-back per cycle +system.cpu.iew.WB:sent 1999262446 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 30877558 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3458881 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 652332333 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 52328 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 302847672 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2706062248 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 515125790 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 84024827 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1999323821 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 131467 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 100159084 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 141229 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2941 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 98598096 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 141241 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 50663539 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 152 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 63 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 50635810 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 214 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3589 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 4102 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 144359443 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 92856159 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3589 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 816990 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 30863143 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.292646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.292646 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 3618 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 4111 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 140737031 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 92052541 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3618 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 787831 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 30089727 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.301325 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.301325 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1204412678 57.64% 57.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 17591 0.00% 57.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851349 1.33% 58.97% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254694 0.40% 59.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.34% 59.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 557993260 26.70% 86.42% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 283770831 13.58% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1201800948 57.69% 57.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 17591 0.00% 57.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.69% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27851361 1.34% 59.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254692 0.40% 59.42% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.35% 59.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.77% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 555085010 26.64% 86.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 283131644 13.59% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2089507805 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 37093546 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017752 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 2083348648 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 37044117 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017781 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 8291 0.02% 0.02% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 7263 0.02% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available @@ -298,43 +298,43 @@ system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # at system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.02% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 28032977 75.57% 75.60% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 9052278 24.40% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 27908776 75.34% 75.36% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 9128078 24.64% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1410161885 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.481750 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.637343 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1400755789 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.487303 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.636763 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 537278436 38.10% 38.10% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 285217724 20.23% 58.33% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 273546804 19.40% 77.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 154810620 10.98% 88.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 63341841 4.49% 93.19% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 51438515 3.65% 96.84% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 32491109 2.30% 99.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 9036668 0.64% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 3000168 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 530170444 37.85% 37.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 284246633 20.29% 58.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 272843485 19.48% 77.62% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 155156600 11.08% 88.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 63055400 4.50% 93.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 50914622 3.63% 96.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 32393130 2.31% 99.15% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 9012045 0.64% 99.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 2963430 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1410161885 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.481585 # Inst issue rate -system.cpu.iq.iqInstsAdded 2386031660 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2089507805 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 562621267 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12403599 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 516017454 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 1400755789 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.487136 # Inst issue rate +system.cpu.iq.iqInstsAdded 2377648640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2083348648 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 554578210 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12403574 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 512095612 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 348448092 # ITB accesses +system.cpu.itb.fetch_accesses 346369835 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 348447899 # ITB hits -system.cpu.itb.fetch_misses 193 # ITB misses +system.cpu.itb.fetch_hits 346369631 # ITB hits +system.cpu.itb.fetch_misses 204 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,106 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.990928 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.847872 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2514269500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 71651 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.884984 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.644583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2514297000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 71650 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297518000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 71651 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297535500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 71650 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1469061 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34325.576147 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.455515 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 28934 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 49433189000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.980304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1440127 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 44644593000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980304 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1440127 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 3137 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34069.333758 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.659229 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 106875500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 71651 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1469050 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34290.352977 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.454128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 28927 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 49382326000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.980309 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1440123 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 44644467000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980309 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1440123 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 3136 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34061.702806 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.830357 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 106817500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 3137 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97362000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 3136 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97331500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 3137 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 3136 # number of UpgradeReq MSHR misses system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8187.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6458.333333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.023462 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.023460 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 65500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1540711 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34361.852641 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 28934 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 51947458500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981220 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1511777 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 1540701 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34328.294441 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 28927 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 51896623000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981225 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1511774 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 46942111000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981220 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1511777 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 46942002500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981225 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1511774 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.927694 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.046416 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 30398.691034 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1520.954518 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1540711 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34361.852641 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.949313 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.927763 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.046370 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 30400.923469 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1519.457016 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1540701 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34328.294441 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 28934 # number of overall hits -system.cpu.l2cache.overall_miss_latency 51947458500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981220 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1511777 # number of overall misses +system.cpu.l2cache.overall_hits 28927 # number of overall hits +system.cpu.l2cache.overall_miss_latency 51896623000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981225 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1511774 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 46942111000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981220 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1511777 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 46942002500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981225 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1511774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1474251 # number of replacements -system.cpu.l2cache.sampled_refs 1506809 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1474248 # number of replacements +system.cpu.l2cache.sampled_refs 1506806 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31919.645552 # Cycle average of tags in use -system.cpu.l2cache.total_refs 35353 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31920.380484 # Cycle average of tags in use +system.cpu.l2cache.total_refs 35349 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66899 # number of writebacks -system.cpu.memDep0.conflictingLoads 118847053 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21034746 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 655954745 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 303651290 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 1410318910 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 20063964 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 118618588 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21042992 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 652332333 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 302847672 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1400913526 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 20115016 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 687776 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 730652071 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 11530186 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3303379014 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2836019296 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1886227369 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 545599397 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 100159084 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 13665899 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 501258299 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 21470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2842 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 27803045 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 61 # count of temporary serializing insts renamed -system.cpu.timesIdled 4055 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 673890 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 725392322 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 11324949 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3294871470 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2827359257 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1880881832 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 543088621 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 98598096 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 13538505 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 495912762 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 23229 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2930 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 27590681 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 73 # count of temporary serializing insts renamed +system.cpu.timesIdled 4075 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 0d46bf33c..19b19681f 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 10 2010 23:43:53 -M5 revision 1633bdfc3b0a+ 7062+ default qtip regression_update tip -M5 started Apr 10 2010 23:43:54 -M5 executing on zooks +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:54:51 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index c2f55abfb..f3687e9fd 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 44191 # Simulator instruction rate (inst/s) -host_mem_usage 166876 # Number of bytes of host memory used -host_seconds 1999.07 # Real time elapsed on the host -host_tick_rate 53020649 # Simulator tick rate (ticks/s) +host_inst_rate 55482 # Simulator instruction rate (inst/s) +host_mem_usage 223108 # Number of bytes of host memory used +host_seconds 1592.24 # Real time elapsed on the host +host_tick_rate 66617861 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.105992 # Number of seconds simulated -sim_ticks 105992011500 # Number of ticks simulated +sim_seconds 0.106071 # Number of seconds simulated +sim_ticks 106071426500 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 35224018 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 4998012 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 12031092 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 1659840 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 10756510 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 8920903 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 88349561 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.lookups 13755144 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 5445744 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 8309400 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1659840 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 88349561 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.BTBHits 4715785 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 11658962 # Number of BTB lookups +system.cpu.Branch-Predictor.RASInCorrect 1659877 # Number of incorrect RAS predictions. +system.cpu.Branch-Predictor.condIncorrect 10683155 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 8920904 # Number of conditional branches predicted +system.cpu.Branch-Predictor.instReqsProcessed 88352585 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.lookups 13755709 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 5728293 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 8027416 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.usedRAS 1659877 # Number of times the RAS was used to get a target. +system.cpu.Decode-Unit.instReqsProcessed 88352585 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.cyclesExecuted 53070972 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 53075554 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 147919 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 2299191 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.250354 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 187445797 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 393312 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 2262427 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.250166 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 187375293 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 88340673 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 82202 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 41101 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 165543786 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 85.618119 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.instReqsProcessed 165543836 # Number of Instructions Requests that completed in this resource. +system.cpu.activity 85.696841 # Percentage of cycles cpu is active system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.399619 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.399620 # CPI: Total CPI of All Threads +system.cpu.cpi 2.401417 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.401418 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 38174.521937 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35069.282164 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 38148.092683 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35044.037784 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2319713000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 2318107000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2131020000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2129486000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56457.935284 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53457.935284 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56431.835934 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53431.835934 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 8457003500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 8453094000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 8007624500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8003715000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 51181.457454 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 48151.085919 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 51155.262895 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 48125.233308 # average overall mshr miss latency system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10776716500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10771201000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 10138644500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 10133201000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995315 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4076.810579 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.995316 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4076.814935 # Average occupied blocks per context system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 51181.457454 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 48151.085919 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 51155.262895 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 48125.233308 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 34679456 # number of overall hits -system.cpu.dcache.overall_miss_latency 10776716500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10771201000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses system.cpu.dcache.overall_misses 210559 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 10138644500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 10133201000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,9 +98,9 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.810579 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.814935 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 842828000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.warmup_cycle 843108000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 147714 # number of writebacks system.cpu.dcache_port.instReqsProcessed 35224018 # Number of Instructions Requests that completed in this resource. system.cpu.dtb.data_accesses 34987415 # DTB accesses @@ -119,74 +119,74 @@ system.cpu.dtb.write_accesses 14620629 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.icache.ReadReq_accesses 99095978 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 18966.643194 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15796.304290 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 99013611 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1562225500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 99022487 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 18976.095303 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15795.359051 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 98940181 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1561846500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000831 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 82367 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 3600 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1244227500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000795 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 78767 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_misses 82306 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 3529 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1244311000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000796 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 78777 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 10833.333333 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1257.044333 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles::no_targets 10666.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1255.952638 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 32500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 32000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 99095978 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 18966.643194 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15796.304290 # average overall mshr miss latency -system.cpu.icache.demand_hits 99013611 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1562225500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 99022487 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 18976.095303 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15795.359051 # average overall mshr miss latency +system.cpu.icache.demand_hits 98940181 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1561846500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000831 # miss rate for demand accesses -system.cpu.icache.demand_misses 82367 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 3600 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1244227500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000795 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 78767 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_misses 82306 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 3529 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1244311000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 78777 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.914749 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1873.406096 # Average occupied blocks per context -system.cpu.icache.overall_accesses 99095978 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 18966.643194 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15796.304290 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.914772 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1873.453452 # Average occupied blocks per context +system.cpu.icache.overall_accesses 99022487 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 18976.095303 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15795.359051 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 99013611 # number of overall hits -system.cpu.icache.overall_miss_latency 1562225500 # number of overall miss cycles +system.cpu.icache.overall_hits 98940181 # number of overall hits +system.cpu.icache.overall_miss_latency 1561846500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000831 # miss rate for overall accesses -system.cpu.icache.overall_misses 82367 # number of overall misses -system.cpu.icache.overall_mshr_hits 3600 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1244227500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000795 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 78767 # number of overall MSHR misses +system.cpu.icache.overall_misses 82306 # number of overall misses +system.cpu.icache.overall_mshr_hits 3529 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1244311000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 78777 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 76721 # number of replacements -system.cpu.icache.sampled_refs 78767 # Sample count of references to valid blocks. +system.cpu.icache.replacements 76731 # number of replacements +system.cpu.icache.sampled_refs 78777 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1873.406096 # Cycle average of tags in use -system.cpu.icache.total_refs 99013611 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1873.453452 # Cycle average of tags in use +system.cpu.icache.total_refs 98940181 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 99096235 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 30487290 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.416733 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.416733 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 99022707 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 30343130 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.416421 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.416421 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 99100019 # ITB accesses +system.cpu.itb.fetch_accesses 99026503 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 99095980 # ITB hits -system.cpu.itb.fetch_misses 4039 # ITB misses +system.cpu.itb.fetch_hits 99022489 # ITB hits +system.cpu.itb.fetch_misses 4014 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -196,28 +196,28 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52468.598950 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52441.606653 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.219393 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7533336500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 7529461000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743151500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 139533 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52305.583032 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 139543 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52270.364151 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.968830 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 96062 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2273776000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.311546 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_hits 96072 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2272245000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.311524 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 43471 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 1739056000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.311546 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.311524 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 43471 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 51892.920354 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 51886.725664 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.654867 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 322514500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 322476000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248616500 # number of UpgradeReq MSHR miss cycles @@ -227,73 +227,73 @@ system.cpu.l2cache.Writeback_accesses 147714 # nu system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.642674 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.642732 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 283111 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52430.713342 # average overall miss latency +system.cpu.l2cache.demand_accesses 283121 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52401.809152 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.323183 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 96062 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9807112500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.660691 # miss rate for demand accesses +system.cpu.l2cache.demand_hits 96072 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9801706000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.660668 # miss rate for demand accesses system.cpu.l2cache.demand_misses 187049 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_miss_latency 7482207500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.660691 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.660668 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 187049 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.083121 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.474048 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2723.711212 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15533.588628 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 283111 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52430.713342 # average overall miss latency +system.cpu.l2cache.occ_%::1 0.474053 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2723.703646 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15533.764861 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 283121 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52401.809152 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.323183 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 96062 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9807112500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.660691 # miss rate for overall accesses +system.cpu.l2cache.overall_hits 96072 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9801706000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.660668 # miss rate for overall accesses system.cpu.l2cache.overall_misses 187049 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_miss_latency 7482207500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.660691 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.660668 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 187049 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 147734 # number of replacements system.cpu.l2cache.sampled_refs 172940 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18257.299840 # Cycle average of tags in use -system.cpu.l2cache.total_refs 111144 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18257.468506 # Cycle average of tags in use +system.cpu.l2cache.total_refs 111154 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 120636 # number of writebacks -system.cpu.numCycles 211984025 # number of cpu cycles simulated -system.cpu.runCycles 181496735 # Number of cycles cpu stages are processed. +system.cpu.numCycles 212142855 # number of cpu cycles simulated +system.cpu.runCycles 181799725 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 112884006 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 99100019 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 46.748815 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 123634464 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 88349561 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 41.677462 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 122168239 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 113116352 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 99026503 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 46.679160 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 123790270 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 88352585 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 41.647684 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 122327069 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 42.369129 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 176752755 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 42.337408 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 176911585 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 16.619776 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 123643352 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 16.607333 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 123802182 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 41.673269 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 211983985 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 41.642069 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 212142815 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 1 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 821bc3ec9..978c677a5 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout index dddba13b1..361003678 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:28:19 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:52:23 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index d2ad10f5b..182c67d63 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 172212 # Simulator instruction rate (inst/s) -host_mem_usage 201796 # Number of bytes of host memory used -host_seconds 462.17 # Real time elapsed on the host -host_tick_rate 58711424 # Simulator tick rate (ticks/s) +host_inst_rate 184348 # Simulator instruction rate (inst/s) +host_mem_usage 216288 # Number of bytes of host memory used +host_seconds 431.75 # Real time elapsed on the host +host_tick_rate 62947203 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.027135 # Number of seconds simulated -sim_ticks 27134794500 # Number of ticks simulated +sim_seconds 0.027177 # Number of seconds simulated +sim_ticks 27177245500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 8039250 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 14256744 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 10551565 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 16249463 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 8069483 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 14149168 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 34397 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 454823 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 10566027 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 16273288 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1942431 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3320894 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3319944 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 51751169 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.707028 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.326549 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 51827032 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.704529 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.326613 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 22506446 43.49% 43.49% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 11357579 21.95% 65.44% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 5114502 9.88% 75.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 3560855 6.88% 82.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2552504 4.93% 87.13% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 1532717 2.96% 90.09% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 1008933 1.95% 92.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 796739 1.54% 93.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3320894 6.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 22597378 43.60% 43.60% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 11350095 21.90% 65.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 5102840 9.85% 75.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 3559000 6.87% 82.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2567186 4.95% 87.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 1515845 2.92% 90.09% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 1002832 1.93% 92.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 811912 1.57% 93.59% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 3319944 6.41% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 51751169 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 51827032 # Number of insts commited each cycle system.cpu.commit.COM:count 88340672 # Number of instructions committed system.cpu.commit.COM:loads 20379399 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 35224018 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 359545 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8296858 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8408904 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads +system.cpu.cpi 0.682916 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.682916 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20425513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30386.330224 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20275869 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4547132000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 149644 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 88108 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 20447523 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30372.255855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20950.835512 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20297704 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4550341000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 149819 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 88240 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1290131500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61579 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 32253.546396 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35751.235092 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13562946 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 33880124994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.071881 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1050431 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 900647 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 5354962997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3166.333333 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 149784 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3083 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.103737 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.176300 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 18998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 18498 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35038890 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32023.260673 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33838925 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 38426791994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1199965 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 988640 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 35060900 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32018.717762 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33860650 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 38430465994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.034233 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1200250 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 988887 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6645094497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.006028 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 211363 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995440 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4077.324152 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 35038890 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32023.260673 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.995485 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4077.505020 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 35060900 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32018.717762 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33838925 # number of overall hits -system.cpu.dcache.overall_miss_latency 38426791994 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1199965 # number of overall misses -system.cpu.dcache.overall_mshr_hits 988640 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses +system.cpu.dcache.overall_hits 33860650 # number of overall hits +system.cpu.dcache.overall_miss_latency 38430465994 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.034233 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1200250 # number of overall misses +system.cpu.dcache.overall_mshr_hits 988887 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6645094497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.006028 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 211363 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 200933 # number of replacements -system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200975 # number of replacements +system.cpu.dcache.sampled_refs 205071 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4077.324152 # Cycle average of tags in use -system.cpu.dcache.total_refs 33851054 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 183223000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147760 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3553993 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3655575 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101758318 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28531763 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19520694 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1290101 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 144719 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 36599689 # DTB accesses -system.cpu.dtb.data_acv 39 # DTB access violations -system.cpu.dtb.data_hits 36425481 # DTB hits -system.cpu.dtb.data_misses 174208 # DTB misses +system.cpu.dcache.tagsinuse 4077.505020 # Cycle average of tags in use +system.cpu.dcache.total_refs 33872869 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 182118000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147751 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3544786 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 96141 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3662025 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101883380 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28549595 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19586782 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1306643 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 281833 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 145869 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 36634667 # DTB accesses +system.cpu.dtb.data_acv 32 # DTB access violations +system.cpu.dtb.data_hits 36459913 # DTB hits +system.cpu.dtb.data_misses 174754 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 21541288 # DTB read accesses -system.cpu.dtb.read_acv 37 # DTB read access violations -system.cpu.dtb.read_hits 21383020 # DTB read hits -system.cpu.dtb.read_misses 158268 # DTB read misses -system.cpu.dtb.write_accesses 15058401 # DTB write accesses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15042461 # DTB write hits -system.cpu.dtb.write_misses 15940 # DTB write misses -system.cpu.fetch.Branches 16249463 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched -system.cpu.fetch.Cycles 33247230 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103308065 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 567637 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 9981179 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 53041270 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.947692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.940902 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 21560876 # DTB read accesses +system.cpu.dtb.read_acv 29 # DTB read access violations +system.cpu.dtb.read_hits 21402283 # DTB read hits +system.cpu.dtb.read_misses 158593 # DTB read misses +system.cpu.dtb.write_accesses 15073791 # DTB write accesses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_hits 15057630 # DTB write hits +system.cpu.dtb.write_misses 16161 # DTB write misses +system.cpu.fetch.Branches 16273288 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13390069 # Number of cache lines fetched +system.cpu.fetch.Cycles 33318554 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 152706 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103441312 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 571617 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.299392 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13390069 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 10011914 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.903087 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 53133675 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.946813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.939021 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 33206277 62.60% 62.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1871594 3.53% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 1529415 2.88% 69.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 1809626 3.41% 72.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 3985239 7.51% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1867239 3.52% 83.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 695846 1.31% 84.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1111736 2.10% 86.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6964298 13.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 33232285 62.54% 62.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1906283 3.59% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1507954 2.84% 68.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 1896878 3.57% 72.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 3940139 7.42% 79.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1882924 3.54% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 690153 1.30% 84.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1104079 2.08% 86.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6972980 13.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53041270 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9527.179672 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13297366 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 845118000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 88706 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 2770 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 53133675 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 13390069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9552.030813 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6056.454886 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13301016 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 850637000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006651 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 89053 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2816 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 522290500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006440 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 86237 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 154.737488 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 154.239714 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9527.179672 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency -system.cpu.icache.demand_hits 13297366 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 845118000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses -system.cpu.icache.demand_misses 88706 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 2770 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13390069 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9552.030813 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6056.454886 # average overall mshr miss latency +system.cpu.icache.demand_hits 13301016 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 850637000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006651 # miss rate for demand accesses +system.cpu.icache.demand_misses 89053 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2816 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 522290500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006440 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 86237 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.936032 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1916.994169 # Average occupied blocks per context -system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9527.179672 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.936831 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1918.630870 # Average occupied blocks per context +system.cpu.icache.overall_accesses 13390069 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9552.030813 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6056.454886 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13297366 # number of overall hits -system.cpu.icache.overall_miss_latency 845118000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses -system.cpu.icache.overall_misses 88706 # number of overall misses -system.cpu.icache.overall_mshr_hits 2770 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses +system.cpu.icache.overall_hits 13301016 # number of overall hits +system.cpu.icache.overall_miss_latency 850637000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006651 # miss rate for overall accesses +system.cpu.icache.overall_misses 89053 # number of overall misses +system.cpu.icache.overall_mshr_hits 2816 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 522290500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006440 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 86237 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 83888 # number of replacements -system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks. +system.cpu.icache.replacements 84189 # number of replacements +system.cpu.icache.sampled_refs 86236 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1916.994169 # Cycle average of tags in use -system.cpu.icache.total_refs 13297366 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1918.630870 # Cycle average of tags in use +system.cpu.icache.total_refs 13301016 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1228320 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14745486 # Number of branches executed -system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.562957 # Inst execution rate -system.cpu.iew.EXEC:refs 36941993 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15291392 # Number of stores executed +system.cpu.idleCycles 1220817 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14763362 # Number of branches executed +system.cpu.iew.EXEC:nop 9403936 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.562245 # Inst execution rate +system.cpu.iew.EXEC:refs 36977571 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15306943 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42302279 # num instructions consuming a value -system.cpu.iew.WB:count 84351875 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back +system.cpu.iew.WB:consumers 42200934 # num instructions consuming a value +system.cpu.iew.WB:count 84440980 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765693 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32396987 # num instructions producing a value -system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle -system.cpu.iew.WB:sent 84585274 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 627293 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 23001213 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16328872 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 98972097 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21650601 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84821059 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 32312963 # num instructions producing a value +system.cpu.iew.WB:rate 1.553523 # insts written-back per cycle +system.cpu.iew.WB:sent 84676788 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 400577 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 625766 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 23022182 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 5008 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 344811 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16353481 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 99092373 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21670628 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 531948 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84915051 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 11175 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1290101 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 44031 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 9016 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1306643 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 43564 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 953335 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 730 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2621814 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1484253 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 19282 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1358 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2642783 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1508862 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 19282 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 131988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 268589 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.464309 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.464309 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 47898565 56.12% 56.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 42953 0.05% 56.17% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 47956060 56.12% 56.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 42959 0.05% 56.17% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 121655 0.14% 56.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 88 0.00% 56.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122104 0.14% 56.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 53 0.00% 56.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38535 0.05% 56.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 21753622 25.49% 81.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 15368770 18.01% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122263 0.14% 56.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.32% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122397 0.14% 56.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 52 0.00% 56.46% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38515 0.05% 56.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.51% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 21777529 25.49% 81.99% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 15387138 18.01% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 85346345 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 979640 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 85446999 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 982918 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011503 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 97100 9.91% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 9.91% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 470602 48.04% 57.95% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 411938 42.05% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 100696 10.24% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.24% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 446429 45.42% 55.66% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 435793 44.34% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 53041270 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.609055 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.711333 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 53133675 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.608151 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.716289 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 17563410 33.11% 33.11% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 13937999 26.28% 59.39% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 8266125 15.58% 74.97% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 4784809 9.02% 84.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 4627568 8.72% 92.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2066740 3.90% 96.62% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1112374 2.10% 98.71% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 454507 0.86% 99.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 227738 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 17599811 33.12% 33.12% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 14135768 26.60% 59.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 8101815 15.25% 74.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 4767583 8.97% 83.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 4587960 8.63% 92.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2114458 3.98% 96.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1132800 2.13% 98.69% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 463918 0.87% 99.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 229562 0.43% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 53041270 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate -system.cpu.iq.iqInstsAdded 89571437 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85346345 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9777311 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 49841 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6793875 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 53133675 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.572032 # Inst issue rate +system.cpu.iq.iqInstsAdded 89683429 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85446999 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 5008 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9879316 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 48902 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 6828439 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 13412237 # ITB accesses +system.cpu.itb.fetch_accesses 13417164 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 13386072 # ITB hits -system.cpu.itb.fetch_misses 26165 # ITB misses +system.cpu.itb.fetch_hits 13390069 # ITB hits +system.cpu.itb.fetch_misses 27095 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,106 +343,106 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 143493 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.441443 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.837093 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 4926895499 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 143493 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481550000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.569397 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1383428000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses 143493 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147815 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34139.493240 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.309786 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 103139 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1525216000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.302243 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 44676 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1386533500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302243 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 44676 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_accesses 6336 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34034.485480 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31031.960227 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 215642500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_misses 6336 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196618500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_mshr_misses 6336 # number of UpgradeReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147751 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147751 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.679657 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 291308 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34288.918467 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 103139 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6452111499 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.645945 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 188169 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5865241500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 5868083500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.645945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 188169 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.089962 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.474123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2947.876007 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15536.049051 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.315275 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.090420 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.474090 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2962.888778 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15534.990261 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 291308 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34288.918467 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 102894 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 188071 # number of overall misses +system.cpu.l2cache.overall_hits 103139 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6452111499 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.645945 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 188169 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5865241500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 5868083500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.645945 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 188169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 148779 # number of replacements -system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 148882 # number of replacements +system.cpu.l2cache.sampled_refs 174101 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18483.925058 # Cycle average of tags in use -system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18497.879039 # Cycle average of tags in use +system.cpu.l2cache.total_refs 118329 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120647 # number of writebacks -system.cpu.memDep0.conflictingLoads 12835812 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11558188 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 23001213 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16328872 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 54269590 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2047052 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 120652 # number of writebacks +system.cpu.memDep0.conflictingLoads 12671277 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11281308 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 23022182 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16353481 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 54354492 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2040280 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 64606 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28934151 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 121625306 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 100952091 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60736832 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19265135 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1290101 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1421430 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8189951 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2801993 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed -system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 60824 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28947603 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1285549 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 34 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 121774399 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 101069730 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60794101 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19336245 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1306643 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1420628 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8247220 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 82276 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5281 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 2797354 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5278 # count of temporary serializing insts renamed +system.cpu.timesIdled 42409 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index 0f49fe322..c38fd9b15 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 10 2010 23:44:54 -M5 revision 1633bdfc3b0a+ 7062+ default qtip regression_update tip -M5 started Apr 10 2010 23:44:56 -M5 executing on zooks +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:53:58 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 3d8fcc484..bfc24ccd9 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 45830 # Simulator instruction rate (inst/s) -host_mem_usage 156280 # Number of bytes of host memory used -host_seconds 2005.28 # Real time elapsed on the host -host_tick_rate 49263361 # Simulator tick rate (ticks/s) +host_inst_rate 58773 # Simulator instruction rate (inst/s) +host_mem_usage 210528 # Number of bytes of host memory used +host_seconds 1563.70 # Real time elapsed on the host +host_tick_rate 63236927 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.098787 # Number of seconds simulated -sim_ticks 98787075000 # Number of ticks simulated +sim_seconds 0.098884 # Number of seconds simulated +sim_ticks 98883816000 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 26537108 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 5943749 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 9141724 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBHits 5701477 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 8843835 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 1029596 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 11377435 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 7465155 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 92001832 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.lookups 10240963 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 2255511 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 7985452 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.condIncorrect 11272469 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 7465254 # Number of conditional branches predicted +system.cpu.Branch-Predictor.instReqsProcessed 92102614 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.lookups 10241221 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 2498039 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 7743182 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 1029596 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 92001832 # Number of Instructions Requests that completed in this resource. +system.cpu.Decode-Unit.instReqsProcessed 92102614 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.cyclesExecuted 64907308 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 64907696 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 78179 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 3313804 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.328521 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 195282323 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 267967 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 3261320 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.328200 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 195278137 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 91903056 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 916504 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 458252 # Number of Multiply Requests Processed. -system.cpu.RegFile-Manager.instReqsProcessed 196150553 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 96.136450 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.instReqsProcessed 196150546 # Number of Instructions Requests that completed in this resource. +system.cpu.activity 96.104408 # Percentage of cycles cpu is active system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.149810 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.149810 # CPI: Total CPI of All Threads +system.cpu.cpi 2.151916 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 2.151916 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51560 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48531.578947 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 51575.789474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48548.421053 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24491000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 24498500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23052500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 23060500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56135.825713 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53135.825713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56234.265734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53234.265734 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 104356500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 104539500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 98779500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 98962500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 55204.584404 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52198.800343 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 55286.203942 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 52280.634105 # average overall mshr miss latency system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 128847500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 129038000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 121832000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 122023000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352013 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1441.845036 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.352005 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1441.813640 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 55204.584404 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52198.800343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55286.203942 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 52280.634105 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 26494967 # number of overall hits -system.cpu.dcache.overall_miss_latency 128847500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 129038000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses system.cpu.dcache.overall_misses 2334 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 121832000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 122023000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,7 +98,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.845036 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 1441.813640 # Cycle average of tags in use system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 104 # number of writebacks @@ -119,73 +119,73 @@ system.cpu.dtb.write_accesses 6501126 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.icache.ReadReq_accesses 103280491 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27107.378354 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23969.601677 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 103271695 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 238436500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_accesses 103175523 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 27130.157283 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.529994 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 103166749 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 238040000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8796 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 210 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 205803000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 8774 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 189 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 205787000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 8586 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 8585 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 2500 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12027.916958 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12017.093652 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 2500 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 103280491 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27107.378354 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23969.601677 # average overall mshr miss latency -system.cpu.icache.demand_hits 103271695 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 238436500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 103175523 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 27130.157283 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23970.529994 # average overall mshr miss latency +system.cpu.icache.demand_hits 103166749 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 238040000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses -system.cpu.icache.demand_misses 8796 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 210 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 205803000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 8774 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 189 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 205787000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 8586 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 8585 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.697585 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1428.655102 # Average occupied blocks per context -system.cpu.icache.overall_accesses 103280491 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27107.378354 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23969.601677 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.697574 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1428.631049 # Average occupied blocks per context +system.cpu.icache.overall_accesses 103175523 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 27130.157283 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23970.529994 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 103271695 # number of overall hits -system.cpu.icache.overall_miss_latency 238436500 # number of overall miss cycles +system.cpu.icache.overall_hits 103166749 # number of overall hits +system.cpu.icache.overall_miss_latency 238040000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses -system.cpu.icache.overall_misses 8796 # number of overall misses -system.cpu.icache.overall_mshr_hits 210 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 205803000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 8774 # number of overall misses +system.cpu.icache.overall_mshr_hits 189 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 205787000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 8586 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 8585 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 6752 # number of replacements -system.cpu.icache.sampled_refs 8586 # Sample count of references to valid blocks. +system.cpu.icache.replacements 6751 # number of replacements +system.cpu.icache.sampled_refs 8585 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1428.655102 # Cycle average of tags in use -system.cpu.icache.total_refs 103271695 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1428.631049 # Cycle average of tags in use +system.cpu.icache.total_refs 103166749 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 103280490 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 7633377 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.465157 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.465157 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 103175522 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 7704221 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.464702 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.464702 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 103280539 # ITB accesses +system.cpu.itb.fetch_accesses 103175571 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 103280492 # ITB hits +system.cpu.itb.fetch_hits 103175524 # ITB hits system.cpu.itb.fetch_misses 47 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -196,28 +196,28 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52126.144165 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52230.263158 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 91116500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 91298500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 9061 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52164.544564 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5998 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 159780000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338042 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses 9060 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52165.034280 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40019.915116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5997 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 159781500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.338079 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338042 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 122581000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 52220.720721 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 52229.729730 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40009.009009 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 5796500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 5797500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4441000 # number of UpgradeReq MSHR miss cycles @@ -227,73 +227,73 @@ system.cpu.l2cache.Writeback_accesses 104 # nu system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.974917 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 1.974587 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10809 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52150.592392 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 5998 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 250896500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.445092 # miss rate for demand accesses +system.cpu.l2cache.demand_accesses 10808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52188.734151 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.757847 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 5997 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 251080000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.445133 # miss rate for demand accesses system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 192511500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.445092 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_latency 192511000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.445133 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 4811 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.061820 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.061819 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2025.719647 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.727958 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 10809 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52150.592392 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2025.680452 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.727236 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 10808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52188.734151 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.757847 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 5998 # number of overall hits -system.cpu.l2cache.overall_miss_latency 250896500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.445092 # miss rate for overall accesses +system.cpu.l2cache.overall_hits 5997 # number of overall hits +system.cpu.l2cache.overall_miss_latency 251080000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.445133 # miss rate for overall accesses system.cpu.l2cache.overall_misses 4811 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 192511500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.445092 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency 192511000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.445133 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 4811 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 3030 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2039.447605 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5984 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2039.407688 # Cycle average of tags in use +system.cpu.l2cache.total_refs 5983 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 197574151 # number of cpu cycles simulated -system.cpu.runCycles 189940774 # Number of cycles cpu stages are processed. +system.cpu.numCycles 197767633 # number of cpu cycles simulated +system.cpu.runCycles 190063412 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 94293612 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 103280539 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 52.274318 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 105572319 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 92001832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 46.565723 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 104081667 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 94592062 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 103175571 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 52.170100 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 105665019 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 92102614 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 46.571126 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 104275149 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.320200 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 171037020 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 47.273906 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 171230502 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 13.431479 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 105671095 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 13.418339 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 105864577 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 46.515729 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 197574151 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 46.470221 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 197767633 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 5dc5abaaf..0b7fa9656 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout index ce84b73e7..6a7caf9b4 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -5,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:44:07 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:45:37 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 96c3646b7..92d71f0ba 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 80276 # Simulator instruction rate (inst/s) -host_mem_usage 196620 # Number of bytes of host memory used -host_seconds 1048.63 # Real time elapsed on the host -host_tick_rate 38925589 # Simulator tick rate (ticks/s) +host_inst_rate 153450 # Simulator instruction rate (inst/s) +host_mem_usage 210984 # Number of bytes of host memory used +host_seconds 548.58 # Real time elapsed on the host +host_tick_rate 73456175 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040819 # Number of seconds simulated -sim_ticks 40818658500 # Number of ticks simulated +sim_seconds 0.040297 # Number of seconds simulated +sim_ticks 40296654500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 13008791 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 16964874 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19468548 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 11897638 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 15852760 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1209 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1887267 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 14560688 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 19536875 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1737186 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2855802 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2907966 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 73457197 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.251110 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.949680 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 72454759 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.268420 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.963909 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 36278942 49.39% 49.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 18156304 24.72% 74.10% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 7455517 10.15% 84.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 3880419 5.28% 89.54% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 2046448 2.79% 92.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 1301140 1.77% 94.09% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 721823 0.98% 95.08% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 760802 1.04% 96.11% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2855802 3.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 35335976 48.77% 48.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 18219580 25.15% 73.92% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 7350657 10.15% 84.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 3843959 5.31% 89.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 2026400 2.80% 92.16% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 1285963 1.77% 93.94% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 738665 1.02% 94.96% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 745593 1.03% 95.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2907966 4.01% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 73457197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 72454759 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed system.cpu.commit.COM:loads 20034413 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 26537108 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1874087 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 55786698 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30623.414072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32082.015810 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26550500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16233500 # number of ReadReq MSHR miss cycles +system.cpu.cpi 0.957396 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.957396 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 23323647 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30060.090703 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32045.634921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23322765 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26513000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 882 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 378 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 16151000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 504 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 35743.318729 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36228.400108 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6492795 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 296955492 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001278 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8308 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 67094997 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2649.700000 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 1852 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4187.125000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.avg_refs 13310.644643 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 26497 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 33497 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35255.314688 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 323326491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses -system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 83194497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 29824750 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35197.877258 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29815560 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 323468492 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000308 # miss rate for demand accesses +system.cpu.dcache.demand_misses 9190 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6834 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 83245997 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2356 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356054 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1458.398369 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35255.314688 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35296.774289 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.356016 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1458.239906 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 29824750 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35197.877258 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29894354 # number of overall hits -system.cpu.dcache.overall_miss_latency 323326491 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses -system.cpu.dcache.overall_misses 9171 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 83194497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 29815560 # number of overall hits +system.cpu.dcache.overall_miss_latency 323468492 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000308 # miss rate for overall accesses +system.cpu.dcache.overall_misses 9190 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6834 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 83245997 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2356 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 159 # number of replacements +system.cpu.dcache.replacements 160 # number of replacements system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1458.398369 # Cycle average of tags in use -system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1458.239906 # Cycle average of tags in use +system.cpu.dcache.total_refs 29815844 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 105 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39569074 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 31911121 # DTB accesses +system.cpu.dcache.writebacks 106 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3560307 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3136527 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162153476 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39273061 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29418237 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8029960 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 48947 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 203154 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 31794123 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 31454022 # DTB hits -system.cpu.dtb.data_misses 457099 # DTB misses +system.cpu.dtb.data_hits 31394253 # DTB hits +system.cpu.dtb.data_misses 399870 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 24718123 # DTB read accesses +system.cpu.dtb.read_accesses 24584547 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24262026 # DTB read hits -system.cpu.dtb.read_misses 456097 # DTB read misses -system.cpu.dtb.write_accesses 7192998 # DTB write accesses +system.cpu.dtb.read_hits 24185700 # DTB read hits +system.cpu.dtb.read_misses 398847 # DTB read misses +system.cpu.dtb.write_accesses 7209576 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7191996 # DTB write hits -system.cpu.dtb.write_misses 1002 # DTB write misses -system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched -system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2079596 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 81528343 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.055174 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.061669 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 7208553 # DTB write hits +system.cpu.dtb.write_misses 1023 # DTB write misses +system.cpu.fetch.Branches 19536875 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19049745 # Number of cache lines fetched +system.cpu.fetch.Cycles 49533111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 485697 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167120080 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2034068 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.242413 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19049745 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13634824 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.073622 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 80484719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.076420 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.094224 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 50560378 62.02% 62.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 3114212 3.82% 65.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 2012618 2.47% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 3505366 4.30% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 4590613 5.63% 78.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1506961 1.85% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 2028359 2.49% 82.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 1846743 2.27% 84.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12363093 15.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 50001427 62.13% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 3132178 3.89% 66.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1884597 2.34% 68.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 3228306 4.01% 72.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 4370184 5.43% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1507606 1.87% 79.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 1854945 2.30% 81.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 1658454 2.06% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12847022 15.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81528343 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 80484719 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 19049745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15752.064632 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11876.097465 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19038605 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 175478000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11140 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120388000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1878.130117 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency -system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses -system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 19049745 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15752.064632 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency +system.cpu.icache.demand_hits 19038605 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 175478000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses +system.cpu.icache.demand_misses 11140 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120388000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.753902 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1543.991602 # Average occupied blocks per context -system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.755796 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1547.870707 # Average occupied blocks per context +system.cpu.icache.overall_accesses 19049745 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15752.064632 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19218965 # number of overall hits -system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses -system.cpu.icache.overall_misses 11038 # number of overall misses -system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses +system.cpu.icache.overall_hits 19038605 # number of overall hits +system.cpu.icache.overall_miss_latency 175478000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses +system.cpu.icache.overall_misses 11140 # number of overall misses +system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120388000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8143 # number of replacements -system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8223 # number of replacements +system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use -system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1547.870707 # Cycle average of tags in use +system.cpu.icache.total_refs 19038605 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108975 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12812003 # Number of branches executed -system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate -system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7194632 # Number of stores executed +system.cpu.idleCycles 108591 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12897175 # Number of branches executed +system.cpu.iew.EXEC:nop 12739019 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.262855 # Inst execution rate +system.cpu.iew.EXEC:refs 31847616 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7211217 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 90937302 # num instructions consuming a value -system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back +system.cpu.iew.WB:consumers 91218394 # num instructions consuming a value +system.cpu.iew.WB:count 99932054 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.721984 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 65837672 # num instructions producing a value -system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle -system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 65858228 # num instructions producing a value +system.cpu.iew.WB:rate 1.239955 # insts written-back per cycle +system.cpu.iew.WB:sent 100793715 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2037312 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 220727 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33778811 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1499848 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10610374 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 147688610 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24636399 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2142931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101777656 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 90810 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 223 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8029960 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 123733 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 852201 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2584 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 270101 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9831 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13744398 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4107679 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 270101 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 440641 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1596671 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.044500 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.044500 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 64430040 61.93% 61.93% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 475055 0.46% 62.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2782164 2.67% 65.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 115645 0.11% 65.18% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2377276 2.29% 67.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 305748 0.29% 67.76% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755245 0.73% 68.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% 68.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25462424 24.48% 92.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7324714 7.04% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 64410892 61.98% 61.98% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 474451 0.46% 62.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.44% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2784957 2.68% 65.12% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114528 0.11% 65.23% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2385482 2.30% 67.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 305123 0.29% 67.82% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755228 0.73% 68.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.54% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 25350766 24.39% 92.94% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7338829 7.06% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 104028641 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 103920587 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1852625 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017827 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 274346 14.19% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 31 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.19% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 6547 0.34% 14.53% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 2333 0.12% 14.65% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 832912 43.09% 57.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 57.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 743147 38.44% 96.18% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 73812 3.82% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 210356 11.35% 11.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.35% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 363 0.02% 11.37% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 3342 0.18% 11.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 2324 0.13% 11.68% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 819264 44.22% 55.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 55.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 748090 40.38% 96.28% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 68886 3.72% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 81528343 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.275981 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540298 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 80484719 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.291184 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.543424 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 35305774 43.30% 43.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 18904885 23.19% 66.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 11574997 14.20% 80.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 6762756 8.29% 88.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 5075415 6.23% 95.21% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 2394533 2.94% 98.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 1208963 1.48% 99.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 250769 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 50251 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 34420666 42.77% 42.77% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 18632497 23.15% 65.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 11734091 14.58% 80.50% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 6720766 8.35% 88.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 5079668 6.31% 95.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 2378591 2.96% 98.11% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 1227784 1.53% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 245969 0.31% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 44687 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 81528343 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate -system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 80484719 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.289444 # Inst issue rate +system.cpu.iq.iqInstsAdded 134949157 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 103920587 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50119883 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 297027 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 46887079 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 19230073 # ITB accesses +system.cpu.itb.fetch_accesses 19049819 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 19230003 # ITB hits -system.cpu.itb.fetch_misses 70 # ITB misses +system.cpu.itb.fetch_hits 19049745 # ITB hits +system.cpu.itb.fetch_misses 74 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,105 +343,105 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34694.700461 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31523.329493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 60230000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 54724500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34278.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 115689000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 104895000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10641 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34281.074697 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.421317 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 116110000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.318297 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3387 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 105266000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318297 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3387 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34414.634146 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31256.097561 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 4233000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3844500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses -system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4333.333333 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.165420 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 3000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34416.438356 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 175868000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34421.237556 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7254 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 176340000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.413913 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5123 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 159585500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 159990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.413913 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5123 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.068091 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::0 0.068298 # Average percentage of cache occupancy system.cpu.l2cache.occ_%::1 0.000414 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2231.205034 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 13.564546 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34416.438356 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.039139 # average overall mshr miss latency +system.cpu.l2cache.occ_blocks::0 2237.998108 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 13.556876 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34421.237556 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7186 # number of overall hits -system.cpu.l2cache.overall_miss_latency 175868000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5110 # number of overall misses +system.cpu.l2cache.overall_hits 7254 # number of overall hits +system.cpu.l2cache.overall_miss_latency 176340000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.413913 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5123 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159585500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 159990500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.413913 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5123 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3343 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2244.769579 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2251.554984 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7239 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 17216078 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5041116 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10628051 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 81637318 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 17229574 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5033996 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 33778811 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10610374 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 80593310 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1589033 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40833183 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed -system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 926186 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40466713 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 962025 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202340521 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157033543 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115331786 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28409670 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8029960 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1983994 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 46904425 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5349 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4530466 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed +system.cpu.timesIdled 2422 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 94e787873..3181a01cf 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 10 2010 23:42:32 -M5 revision 1633bdfc3b0a 7062 default qtip regression_update tip -M5 started Apr 10 2010 23:42:34 -M5 executing on zooks +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:43:43 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 31225500 because target called exit() +Exiting @ tick 31242000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index adbfbe35c..8b050d9d7 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30166 # Simulator instruction rate (inst/s) -host_mem_usage 153332 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 146878557 # Simulator tick rate (ticks/s) +host_inst_rate 29156 # Simulator instruction rate (inst/s) +host_mem_usage 203904 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 142052352 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31225500 # Number of ticks simulated +sim_ticks 31242000 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2050 # Number of Instructions Requests that completed in this resource. -system.cpu.Branch-Predictor.BTBHits 202 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 582 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBHits 94 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 314 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 125 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 957 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condIncorrect 895 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 751 # Number of conditional branches predicted -system.cpu.Branch-Predictor.instReqsProcessed 6537 # Number of Instructions Requests that completed in this resource. +system.cpu.Branch-Predictor.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 721 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 345 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.predictedNotTaken 829 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 237 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target. -system.cpu.Decode-Unit.instReqsProcessed 6537 # Number of Instructions Requests that completed in this resource. +system.cpu.Decode-Unit.instReqsProcessed 6554 # Number of Instructions Requests that completed in this resource. system.cpu.Execution-Unit.cyclesExecuted 4340 # Number of Cycles Execution Unit was used. system.cpu.Execution-Unit.instReqsProcessed 4354 # Number of Instructions Requests that completed in this resource. -system.cpu.Execution-Unit.predictedNotTakenIncorrect 447 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 165 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.Execution-Unit.utilization 0.069493 # Utilization of Execution Unit (cycles / totalCycles). -system.cpu.Fetch-Seq-Unit.instReqsProcessed 13895 # Number of Instructions Requests that completed in this resource. +system.cpu.Execution-Unit.predictedNotTakenIncorrect 524 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 134 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.utilization 0.069457 # Utilization of Execution Unit (cycles / totalCycles). +system.cpu.Fetch-Seq-Unit.instReqsProcessed 13850 # Number of Instructions Requests that completed in this resource. system.cpu.Graduation-Unit.instReqsProcessed 6404 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.divInstReqsProcessed 0 # Number of Divide Requests Processed. system.cpu.Mult-Div-Unit.instReqsProcessed 2 # Number of Instructions Requests that completed in this resource. system.cpu.Mult-Div-Unit.multInstReqsProcessed 1 # Number of Multiply Requests Processed. system.cpu.RegFile-Manager.instReqsProcessed 19960 # Number of Instructions Requests that completed in this resource. -system.cpu.activity 22.223468 # Percentage of cycles cpu is active +system.cpu.activity 22.272545 # Percentage of cycles cpu is active system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.752030 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.752030 # CPI: Total CPI of All Threads +system.cpu.cpi 9.757183 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 9.757183 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56342.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53342.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56336.842105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53336.842105 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5352500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5352000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5067500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5067000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56063.218391 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53063.218391 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56057.471264 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53057.471264 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4877500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 4877000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 4616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 4616000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -66,31 +66,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56208.791209 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56203.296703 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10230000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10229000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9684000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9683000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025299 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 103.624059 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.025306 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 103.651945 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56208.791209 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53208.791209 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56203.296703 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53203.296703 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1868 # number of overall hits -system.cpu.dcache.overall_miss_latency 10230000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10229000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses system.cpu.dcache.overall_misses 182 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9684000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9683000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -98,7 +98,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 103.624059 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.651945 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -119,73 +119,73 @@ system.cpu.dtb.write_accesses 868 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 7358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55544.850498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52868.421053 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 7057 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16719000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.040908 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 7296 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55536.544850 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52863.157895 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6995 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 16716500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.041255 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 301 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15067500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.038733 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 15066000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.039062 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 24.848592 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 24.630282 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7358 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55544.850498 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52868.421053 # average overall mshr miss latency -system.cpu.icache.demand_hits 7057 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16719000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.040908 # miss rate for demand accesses +system.cpu.icache.demand_accesses 7296 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55536.544850 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency +system.cpu.icache.demand_hits 6995 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 16716500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.041255 # miss rate for demand accesses system.cpu.icache.demand_misses 301 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15067500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.038733 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 15066000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.039062 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.063597 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 130.247335 # Average occupied blocks per context -system.cpu.icache.overall_accesses 7358 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55544.850498 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52868.421053 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.063623 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 130.299954 # Average occupied blocks per context +system.cpu.icache.overall_accesses 7296 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55536.544850 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52863.157895 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 7057 # number of overall hits -system.cpu.icache.overall_miss_latency 16719000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.040908 # miss rate for overall accesses +system.cpu.icache.overall_hits 6995 # number of overall hits +system.cpu.icache.overall_miss_latency 16716500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.041255 # miss rate for overall accesses system.cpu.icache.overall_misses 301 # number of overall misses system.cpu.icache.overall_mshr_hits 16 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15067500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.038733 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 15066000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.039062 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 130.247335 # Cycle average of tags in use -system.cpu.icache.total_refs 7057 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 130.299954 # Cycle average of tags in use +system.cpu.icache.total_refs 6995 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache_port.instReqsProcessed 7356 # Number of Instructions Requests that completed in this resource. -system.cpu.idleCycles 48573 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.102543 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.102543 # IPC: Total IPC of All Threads +system.cpu.icache_port.instReqsProcessed 7294 # Number of Instructions Requests that completed in this resource. +system.cpu.idleCycles 48568 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.102489 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.102489 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 7375 # ITB accesses +system.cpu.itb.fetch_accesses 7313 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 7358 # ITB hits +system.cpu.itb.fetch_hits 7296 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -196,19 +196,19 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52061.643836 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52054.794521 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3800500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3800000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52069.920844 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52065.963061 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39944.591029 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19734500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 19733000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 15139000 # number of ReadReq MSHR miss cycles @@ -232,10 +232,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52068.584071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52064.159292 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23535000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23533000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997792 # miss rate for demand accesses system.cpu.l2cache.demand_misses 452 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -245,14 +245,14 @@ system.cpu.l2cache.demand_mshr_misses 452 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005535 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 181.381905 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005537 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 181.445272 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52068.584071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52064.159292 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 39955.752212 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23535000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23533000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997792 # miss rate for overall accesses system.cpu.l2cache.overall_misses 452 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -264,32 +264,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 181.381905 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 181.445272 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 62452 # number of cpu cycles simulated -system.cpu.runCycles 13879 # Number of cycles cpu stages are processed. +system.cpu.numCycles 62485 # number of cpu cycles simulated +system.cpu.runCycles 13917 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 55077 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 7375 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 11.809069 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 55915 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 6537 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.467239 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 55982 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 55172 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 7313 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 11.703609 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 55931 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 6554 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 10.488917 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 56015 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.359956 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 60399 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.utilization 10.354485 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 60432 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.287325 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 56048 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.285589 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 56081 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.254275 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 62452 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 10.248860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 62485 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 1b5a762f3..409d22ab8 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 0bdde157a..2c74abf7c 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:54 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 01:04:08 -M5 executing on SC2B0619 -command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/o3-timing +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:59:38 +M5 executing on zizzer +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12474500 because target called exit() +Exiting @ tick 12497500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 7fffd3b0b..1208848c5 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,259 +1,259 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 104903 # Simulator instruction rate (inst/s) -host_mem_usage 190976 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 203948336 # Simulator tick rate (ticks/s) +host_inst_rate 84020 # Simulator instruction rate (inst/s) +host_mem_usage 204400 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 163850067 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6386 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12474500 # Number of ticks simulated +sim_ticks 12497500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 806 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1370 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2263 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 304 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1337 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2245 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 315 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1051 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 12417 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.515664 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.304890 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 12431 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.515083 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.305811 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 9514 76.62% 76.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1627 13.10% 89.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 488 3.93% 93.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 267 2.15% 95.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 153 1.23% 97.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 9528 76.65% 76.65% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1629 13.10% 89.75% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 491 3.95% 93.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 259 2.08% 95.78% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 156 1.25% 97.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 104 0.84% 97.88% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::6-7 96 0.77% 98.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 53 0.43% 99.07% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 49 0.39% 99.04% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 119 0.96% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 12417 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 12431 # Number of insts commited each cycle system.cpu.commit.COM:count 6403 # Number of instructions committed system.cpu.commit.COM:loads 1185 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2050 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 367 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4640 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4622 # The number of squashed insts skipped by commit system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.906984 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.906984 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1793 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34316.091954 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.623762 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1619 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5971000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.097044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 174 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3660000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056330 # mshr miss rate for ReadReq accesses +system.cpu.cpi 3.914187 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.914187 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1782 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34993.902439 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1618 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5739000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.092031 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 164 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056678 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35168.421053 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35747.126437 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35082.894737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35729.885057 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13364000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 13331500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3110000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3108500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.281609 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.275862 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2658 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2104 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 19335000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.208427 # miss rate for demand accesses -system.cpu.dcache.demand_misses 554 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 6770000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.070730 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2647 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 35056.066176 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2103 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 19070500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.205516 # miss rate for demand accesses +system.cpu.dcache.demand_misses 544 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 6770500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.071024 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026922 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 110.270477 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2658 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34900.722022 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36010.638298 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 110.050975 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2647 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 35056.066176 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2104 # number of overall hits -system.cpu.dcache.overall_miss_latency 19335000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.208427 # miss rate for overall accesses -system.cpu.dcache.overall_misses 554 # number of overall misses -system.cpu.dcache.overall_mshr_hits 366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 6770000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.070730 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2103 # number of overall hits +system.cpu.dcache.overall_miss_latency 19070500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.205516 # miss rate for overall accesses +system.cpu.dcache.overall_misses 544 # number of overall misses +system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 6770500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.071024 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.270477 # Cycle average of tags in use -system.cpu.dcache.total_refs 2137 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 110.050975 # Cycle average of tags in use +system.cpu.dcache.total_refs 2136 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1058 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 74 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 192 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12405 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 8939 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2366 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 897 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 1123 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 188 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12474 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 8945 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2313 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 900 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 2951 # DTB accesses +system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 2948 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 2890 # DTB hits +system.cpu.dtb.data_hits 2887 # DTB hits system.cpu.dtb.data_misses 61 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 1876 # DTB read accesses +system.cpu.dtb.read_accesses 1865 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1840 # DTB read hits +system.cpu.dtb.read_hits 1829 # DTB read hits system.cpu.dtb.read_misses 36 # DTB read misses -system.cpu.dtb.write_accesses 1075 # DTB write accesses +system.cpu.dtb.write_accesses 1083 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1050 # DTB write hits +system.cpu.dtb.write_hits 1058 # DTB write hits system.cpu.dtb.write_misses 25 # DTB write misses -system.cpu.fetch.Branches 2263 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched -system.cpu.fetch.Cycles 4308 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13251 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 501 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.090701 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.531102 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 13314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.995268 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.362110 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2245 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1792 # Number of cache lines fetched +system.cpu.fetch.Cycles 4238 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13309 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.089814 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1792 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1007 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.532445 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13331 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.998350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.390717 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 10844 81.45% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 252 1.89% 83.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 238 1.79% 85.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 230 1.73% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 272 2.04% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 162 1.22% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 232 1.74% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 129 0.97% 92.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 955 7.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 10920 81.91% 81.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 245 1.84% 83.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 221 1.66% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 185 1.39% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 233 1.75% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 164 1.23% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 228 1.71% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 133 1.00% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1002 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13314 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1802 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35400.943396 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35286.644951 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1378 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15010000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.235294 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 424 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 117 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 10833000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.170366 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 13331 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1792 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35303.990610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1366 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15039500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.237723 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.171317 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.488599 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.449511 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1802 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency -system.cpu.icache.demand_hits 1378 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15010000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.235294 # miss rate for demand accesses -system.cpu.icache.demand_misses 424 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 117 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10833000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.170366 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 1792 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency +system.cpu.icache.demand_hits 1366 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15039500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.237723 # miss rate for demand accesses +system.cpu.icache.demand_misses 426 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.171317 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077417 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 158.550695 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1802 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35400.943396 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35286.644951 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.077094 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 157.888110 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1792 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35303.990610 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1378 # number of overall hits -system.cpu.icache.overall_miss_latency 15010000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.235294 # miss rate for overall accesses -system.cpu.icache.overall_misses 424 # number of overall misses -system.cpu.icache.overall_mshr_hits 117 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10833000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.170366 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 1366 # number of overall hits +system.cpu.icache.overall_miss_latency 15039500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.237723 # miss rate for overall accesses +system.cpu.icache.overall_misses 426 # number of overall misses +system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.171317 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 158.550695 # Cycle average of tags in use -system.cpu.icache.total_refs 1378 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 157.888110 # Cycle average of tags in use +system.cpu.icache.total_refs 1366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1450 # Number of branches executed -system.cpu.iew.EXEC:nop 82 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.362325 # Inst execution rate -system.cpu.iew.EXEC:refs 2959 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1077 # Number of stores executed +system.cpu.idleCycles 11665 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1448 # Number of branches executed +system.cpu.iew.EXEC:nop 83 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.362498 # Inst execution rate +system.cpu.iew.EXEC:refs 2956 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1085 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 6020 # num instructions consuming a value -system.cpu.iew.WB:count 8734 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.746013 # average fanout of values written-back +system.cpu.iew.WB:consumers 6049 # num instructions consuming a value +system.cpu.iew.WB:count 8759 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.745247 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4491 # num instructions producing a value -system.cpu.iew.WB:rate 0.350060 # insts written-back per cycle -system.cpu.iew.WB:sent 8835 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 102 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 201 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11078 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1882 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 305 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 9040 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 8 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 4508 # num instructions producing a value +system.cpu.iew.WB:rate 0.350416 # insts written-back per cycle +system.cpu.iew.WB:sent 8858 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 427 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 73 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2269 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 11059 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1871 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 304 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 9061 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 897 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 900 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores @@ -262,77 +262,77 @@ system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Nu system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1102 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 401 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1084 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 406 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 138 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.255952 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.255952 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.255481 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.255481 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6254 66.92% 66.94% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 66.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.96% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1986 21.25% 88.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1100 11.77% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6287 67.13% 67.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1968 21.01% 88.20% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1105 11.80% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 9345 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 105 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011236 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 9365 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 92 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009824 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 14 13.33% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 56 53.33% 66.67% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 35 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.09% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 56 60.87% 61.96% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.04% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 13314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.701893 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302449 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13331 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.702498 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.304735 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 9113 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1716 12.89% 81.34% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 1071 8.04% 89.38% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 725 5.45% 94.82% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 355 2.67% 97.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 172 1.29% 98.78% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 115 0.86% 99.65% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.26% 99.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 13 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 9142 68.58% 68.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1697 12.73% 81.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 1062 7.97% 89.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 730 5.48% 94.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 359 2.69% 97.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 188 1.41% 98.85% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 105 0.79% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 36 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 13314 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.374549 # Inst issue rate -system.cpu.iq.iqInstsAdded 10972 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 9345 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4189 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2547 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 13331 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.374660 # Inst issue rate +system.cpu.iq.iqInstsAdded 10951 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9365 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 4181 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 2504 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1838 # ITB accesses +system.cpu.itb.fetch_accesses 1827 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 1802 # ITB hits -system.cpu.itb.fetch_misses 36 # ITB misses +system.cpu.itb.fetch_hits 1792 # ITB hits +system.cpu.itb.fetch_misses 35 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -342,31 +342,31 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34547.945205 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31465.753425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2522000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.753425 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31376.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2516000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2290500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34421.375921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31240.786241 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34418.918919 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31239.557740 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14009500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14008500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12715000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12714500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34357.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31142.857143 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 481000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -378,31 +378,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34426.041667 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 16531500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 16524500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15012000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15005000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006558 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 214.901533 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006535 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 214.135921 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34440.625000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34426.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 16531500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 16524500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15012000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15005000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -410,32 +410,32 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 214.901533 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 214.135921 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 24950 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 371 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2269 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 24996 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 340 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 9094 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 226 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15058 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11988 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8902 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2263 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 897 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 258 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4319 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 663 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed -system.cpu.timesIdled 237 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 9 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 9098 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 255 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 15174 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 12043 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8961 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2203 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 900 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 292 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4378 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 750 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed +system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index c164849b4..73089a2aa 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 703e5cb77..95c4493ba 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:44:06 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:10:59 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7183000 because target called exit() +Exiting @ tick 7285000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 48416d4fa..c49e5f817 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,337 +1,337 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 86395 # Simulator instruction rate (inst/s) -host_mem_usage 189960 # Number of bytes of host memory used +host_inst_rate 87095 # Simulator instruction rate (inst/s) +host_mem_usage 203396 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 257307637 # Simulator tick rate (ticks/s) +host_tick_rate 263805903 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7183000 # Number of ticks simulated +sim_ticks 7285000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 198 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 684 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 190 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 674 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 447 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 859 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 463 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 916 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 178 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 396 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 6197 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.415685 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.207973 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 6323 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.407402 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.198077 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 5240 84.56% 84.56% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 263 4.24% 88.80% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 334 5.39% 94.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 134 2.16% 96.35% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 73 1.18% 97.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 63 1.02% 98.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 32 0.52% 99.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 20 0.32% 99.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 38 0.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 5366 84.86% 84.86% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 262 4.14% 89.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 338 5.35% 94.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 131 2.07% 96.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 72 1.14% 97.56% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 64 1.01% 98.58% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 32 0.51% 99.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 19 0.30% 99.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 39 0.62% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 6197 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 6323 # Number of insts commited each cycle system.cpu.commit.COM:count 2576 # Number of instructions committed system.cpu.commit.COM:loads 415 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 709 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 143 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1946 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses +system.cpu.cpi 6.104315 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.104315 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35822.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35663.934426 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 505 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3224000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.151261 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2175500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.102521 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 37219.626168 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37702.702703 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 3982500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1395000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.600000 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.demand_accesses 889 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 36581.218274 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency -system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses -system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_hits 692 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 7206500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.221597 # miss rate for demand accesses +system.cpu.dcache.demand_misses 197 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 99 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.110236 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.011202 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 45.884316 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency +system.cpu.dcache.occ_%::0 0.011290 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 46.245716 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 889 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 36581.218274 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 674 # number of overall hits -system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses -system.cpu.dcache.overall_misses 193 # number of overall misses -system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits +system.cpu.dcache.overall_hits 692 # number of overall hits +system.cpu.dcache.overall_miss_latency 7206500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.221597 # miss rate for overall accesses +system.cpu.dcache.overall_misses 197 # number of overall misses +system.cpu.dcache.overall_mshr_hits 99 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.110236 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use -system.cpu.dcache.total_refs 715 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.245716 # Cycle average of tags in use +system.cpu.dcache.total_refs 731 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BlockedCycles 169 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BranchResolved 142 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 5018 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 5179 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 974 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 367 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 971 # DTB accesses +system.cpu.dtb.data_accesses 1010 # DTB accesses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 946 # DTB hits -system.cpu.dtb.data_misses 25 # DTB misses +system.cpu.dtb.data_hits 979 # DTB hits +system.cpu.dtb.data_misses 31 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 611 # DTB read accesses +system.cpu.dtb.read_accesses 638 # DTB read accesses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 600 # DTB read hits -system.cpu.dtb.read_misses 11 # DTB read misses -system.cpu.dtb.write_accesses 360 # DTB write accesses +system.cpu.dtb.read_hits 623 # DTB read hits +system.cpu.dtb.read_misses 15 # DTB read misses +system.cpu.dtb.write_accesses 372 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 346 # DTB write hits -system.cpu.dtb.write_misses 14 # DTB write misses -system.cpu.fetch.Branches 859 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 747 # Number of cache lines fetched -system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 239 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6528 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.826134 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.219931 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 356 # DTB write hits +system.cpu.dtb.write_misses 16 # DTB write misses +system.cpu.fetch.Branches 916 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 789 # Number of cache lines fetched +system.cpu.fetch.Cycles 1801 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 119 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 5736 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 250 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.062865 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 789 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 368 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.393659 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 6690 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.857399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.271719 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 5595 85.71% 85.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 36 0.55% 86.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 100 1.53% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 69 1.06% 88.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 130 1.99% 90.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 72 1.10% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 45 0.69% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 48 0.74% 93.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 433 6.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 5707 85.31% 85.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 48 0.72% 86.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 101 1.51% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 74 1.11% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 57 0.85% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 51 0.76% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 51 0.76% 92.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 478 7.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6528 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 6690 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 789 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36081.196581 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.154696 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 555 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 8443000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.296578 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 234 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 6391500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.229404 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.066298 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency -system.cpu.icache.demand_hits 512 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses -system.cpu.icache.demand_misses 235 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses +system.cpu.icache.demand_accesses 789 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36081.196581 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency +system.cpu.icache.demand_hits 555 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 8443000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.296578 # miss rate for demand accesses +system.cpu.icache.demand_misses 234 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 6391500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.229404 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.043324 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 88.727286 # Average occupied blocks per context -system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.043805 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 89.711886 # Average occupied blocks per context +system.cpu.icache.overall_accesses 789 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36081.196581 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 512 # number of overall hits -system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses -system.cpu.icache.overall_misses 235 # number of overall misses -system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses +system.cpu.icache.overall_hits 555 # number of overall hits +system.cpu.icache.overall_miss_latency 8443000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.296578 # miss rate for overall accesses +system.cpu.icache.overall_misses 234 # number of overall misses +system.cpu.icache.overall_mshr_hits 53 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 6391500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.229404 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use -system.cpu.icache.total_refs 512 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 89.711886 # Cycle average of tags in use +system.cpu.icache.total_refs 555 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 584 # Number of branches executed -system.cpu.iew.EXEC:nop 286 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate -system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 360 # Number of stores executed +system.cpu.idleCycles 7881 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 607 # Number of branches executed +system.cpu.iew.EXEC:nop 310 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.241370 # Inst execution rate +system.cpu.iew.EXEC:refs 1013 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 372 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1896 # num instructions consuming a value -system.cpu.iew.WB:count 3311 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back +system.cpu.iew.WB:consumers 1984 # num instructions consuming a value +system.cpu.iew.WB:count 3409 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.798891 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1509 # num instructions producing a value -system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle -system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions +system.cpu.iew.WB:producers 1585 # num instructions producing a value +system.cpu.iew.WB:rate 0.233958 # insts written-back per cycle +system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 787 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispStoreInsts 432 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 4536 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 641 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 117 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3517 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 372 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 138 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 110 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads +system.cpu.ipc 0.163819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.163819 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2506 71.31% 71.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 639 18.18% 89.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 368 10.47% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2590 71.27% 71.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 666 18.33% 89.63% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 377 10.37% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 3514 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 3634 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009631 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.94% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.94% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 11 32.35% 35.29% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 22 64.71% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.86% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 12 34.29% 37.14% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 6528 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.538297 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220228 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 6690 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543199 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215587 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 5051 77.37% 77.37% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 569 8.72% 86.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 331 5.07% 91.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 253 3.88% 95.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 172 2.63% 97.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 97 1.49% 99.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 39 0.60% 99.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.17% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 5134 76.74% 76.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 621 9.28% 86.02% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 357 5.34% 91.36% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 240 3.59% 94.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 184 2.75% 97.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 102 1.52% 99.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 36 0.54% 99.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 11 0.16% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 6528 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate -system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 6690 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.249399 # Inst issue rate +system.cpu.iq.iqInstsAdded 4220 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 3634 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 874 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 776 # ITB accesses +system.cpu.itb.fetch_accesses 818 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 747 # ITB hits +system.cpu.itb.fetch_hits 789 # ITB hits system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,21 +351,21 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34324.380165 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 8306500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31107.142857 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 435500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -377,10 +377,10 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 34349.624060 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 9137000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -390,14 +390,14 @@ system.cpu.l2cache.demand_mshr_misses 266 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.003380 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 110.762790 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.003416 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 111.924793 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34349.624060 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 9137000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits @@ -409,32 +409,31 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 111.924793 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 738 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 411 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 14367 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 787 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 432 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 14571 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 7 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IdleCycles 5259 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 8 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 5438 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 4848 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 3462 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 895 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 367 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 16 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 1694 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 80 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index aa3193437..12732e5e1 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 23 2010 00:25:27 -M5 revision ba1ff0a71710+ 7040+ default tip -M5 started Mar 23 2010 00:25:28 -M5 executing on zooks +M5 compiled May 12 2010 02:40:58 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:41:01 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 6c70d7ee8..76dc624e3 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 30626 # Simulator instruction rate (inst/s) -host_mem_usage 154136 # Number of bytes of host memory used +host_inst_rate 30301 # Simulator instruction rate (inst/s) +host_mem_usage 205096 # Number of bytes of host memory used host_seconds 0.19 # Real time elapsed on the host -host_tick_rate 153245779 # Simulator tick rate (ticks/s) +host_tick_rate 151651964 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated sim_ticks 29206500 # Number of ticks simulated system.cpu.AGEN-Unit.instReqsProcessed 2090 # Number of Instructions Requests that completed in this resource. system.cpu.Branch-Predictor.BTBHits 0 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 641 # Number of BTB lookups +system.cpu.Branch-Predictor.BTBLookups 499 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.Branch-Predictor.condIncorrect 666 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 677 # Number of conditional branches predicted diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index a93b6565a..a56ef0667 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -412,7 +412,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index f2820f9aa..0c4704bfb 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:04 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:11:23 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:40:58 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:41:01 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 14060500 because target called exit() +Exiting @ tick 14021500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index e79cbdaa4..ab93396d9 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 82851 # Simulator instruction rate (inst/s) -host_mem_usage 191760 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 224354167 # Simulator tick rate (ticks/s) +host_inst_rate 60574 # Simulator instruction rate (inst/s) +host_mem_usage 205208 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 163793003 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5169 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14060500 # Number of ticks simulated +sim_ticks 14021500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 572 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1960 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 546 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1900 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 751 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1593 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2416 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 404 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 747 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1589 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2405 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 916 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 65 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14561 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.400110 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.121131 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 14488 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.402126 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.127822 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 11999 82.41% 82.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1213 8.33% 90.74% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 529 3.63% 94.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 291 2.00% 96.37% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 294 2.02% 98.39% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 71 0.49% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.30% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 37 0.25% 99.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 65 0.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 11934 82.37% 82.37% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1210 8.35% 90.72% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 523 3.61% 94.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 292 2.02% 96.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 294 2.03% 98.38% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 67 0.46% 98.84% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 62 0.43% 99.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 37 0.26% 99.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 69 0.48% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 14561 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 14488 # Number of insts commited each cycle system.cpu.commit.COM:count 5826 # Number of instructions committed system.cpu.commit.COM:loads 1164 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 2089 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 620 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 616 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 6017 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5972 # The number of squashed insts skipped by commit system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 5.440511 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.440511 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2321 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 34074.626866 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36043.956044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2187 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4566000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.057734 # miss rate for ReadReq accesses +system.cpu.cpi 5.425421 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.425421 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2310 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34156.716418 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36032.967033 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2176 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4577000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.058009 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3280000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039207 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 3279000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.039394 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27570.707071 # average WriteReq miss latency @@ -73,56 +73,56 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # m system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.226950 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.148936 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3246 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 29592.807425 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2815 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 12754500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.132779 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 3235 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 29618.329466 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2804 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 12765500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.133230 # miss rate for demand accesses system.cpu.dcache.demand_misses 431 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 276 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.047751 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 5586000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.047913 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022292 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 91.308954 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 3246 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 29592.807425 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36045.161290 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.022304 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 91.357241 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 3235 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 29618.329466 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2815 # number of overall hits -system.cpu.dcache.overall_miss_latency 12754500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.132779 # miss rate for overall accesses +system.cpu.dcache.overall_hits 2804 # number of overall hits +system.cpu.dcache.overall_miss_latency 12765500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.133230 # miss rate for overall accesses system.cpu.dcache.overall_misses 431 # number of overall misses system.cpu.dcache.overall_mshr_hits 276 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.047751 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 5586000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.047913 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.308954 # Cycle average of tags in use -system.cpu.dcache.total_refs 2852 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.357241 # Cycle average of tags in use +system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 519 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 139 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 139 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 14436 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 10077 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3965 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1080 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 521 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 138 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 14337 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 10064 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3903 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1073 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits @@ -133,151 +133,151 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2416 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 2220 # Number of cache lines fetched -system.cpu.fetch.Cycles 6371 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 355 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 15622 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 767 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.085911 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 2220 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.555508 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15641 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.998785 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.252974 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2405 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2216 # Number of cache lines fetched +system.cpu.fetch.Cycles 6303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 358 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 15547 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 763 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.085758 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2216 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 946 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.554379 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 15561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.999100 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.261901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 11507 73.57% 73.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 1847 11.81% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 223 1.43% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 141 0.90% 87.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 312 1.99% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 120 0.77% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 308 1.97% 92.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 254 1.62% 94.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 929 5.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 11491 73.84% 73.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1812 11.64% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 195 1.25% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 140 0.90% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 320 2.06% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 114 0.73% 90.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 289 1.86% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 259 1.66% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 941 6.05% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15641 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 2220 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35681.279621 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34902.735562 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1798 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15057500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.190090 # miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 15561 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 2216 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35687.203791 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34908.814590 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1794 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15060000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.190433 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 422 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 93 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11483000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.148198 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 11485000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.148466 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.465046 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.452888 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2220 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35681.279621 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency -system.cpu.icache.demand_hits 1798 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15057500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.190090 # miss rate for demand accesses +system.cpu.icache.demand_accesses 2216 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35687.203791 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency +system.cpu.icache.demand_hits 1794 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15060000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.190433 # miss rate for demand accesses system.cpu.icache.demand_misses 422 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 93 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11483000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.148198 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 11485000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.148466 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.076179 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 156.015053 # Average occupied blocks per context -system.cpu.icache.overall_accesses 2220 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35681.279621 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34902.735562 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.076241 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 156.140617 # Average occupied blocks per context +system.cpu.icache.overall_accesses 2216 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35687.203791 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1798 # number of overall hits -system.cpu.icache.overall_miss_latency 15057500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.190090 # miss rate for overall accesses +system.cpu.icache.overall_hits 1794 # number of overall hits +system.cpu.icache.overall_miss_latency 15060000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.190433 # miss rate for overall accesses system.cpu.icache.overall_misses 422 # number of overall misses system.cpu.icache.overall_mshr_hits 93 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11483000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.148198 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 11485000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.148466 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 16 # number of replacements system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 156.015053 # Cycle average of tags in use -system.cpu.icache.total_refs 1798 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 156.140617 # Cycle average of tags in use +system.cpu.icache.total_refs 1794 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12481 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1253 # Number of branches executed -system.cpu.iew.EXEC:nop 1830 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.295249 # Inst execution rate -system.cpu.iew.EXEC:refs 3456 # number of memory reference insts executed +system.cpu.idleCycles 12483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1268 # Number of branches executed +system.cpu.iew.EXEC:nop 1827 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.295643 # Inst execution rate +system.cpu.iew.EXEC:refs 3444 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1049 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 4132 # num instructions consuming a value -system.cpu.iew.WB:count 7536 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.703291 # average fanout of values written-back +system.cpu.iew.WB:consumers 4139 # num instructions consuming a value +system.cpu.iew.WB:count 7538 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.704035 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 2906 # num instructions producing a value -system.cpu.iew.WB:rate 0.267975 # insts written-back per cycle -system.cpu.iew.WB:sent 7618 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 681 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 2914 # num instructions producing a value +system.cpu.iew.WB:rate 0.268792 # insts written-back per cycle +system.cpu.iew.WB:sent 7625 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 679 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2806 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2797 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 963 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 953 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 11847 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2407 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 549 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8303 # Number of executed instructions +system.cpu.iew.iewDispatchedInsts 11802 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 2395 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8291 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1080 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1073 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1642 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1633 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 272 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 409 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.183806 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.183806 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 395 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.184318 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184318 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5184 58.56% 58.56% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.62% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.64% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.66% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2595 29.32% 87.98% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.02% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5173 58.55% 58.55% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.63% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2589 29.30% 87.96% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.04% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8852 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 8835 # Type of FU issued system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.018301 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.018336 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntAlu 8 4.94% 4.94% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available @@ -292,31 +292,31 @@ system.cpu.iq.ISSUE:fu_full::MemRead 100 61.73% 66.67% # at system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15641 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.565948 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.209939 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 15561 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567766 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217819 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 11653 74.50% 74.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1757 11.23% 85.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 814 5.20% 90.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 738 4.72% 95.66% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 342 2.19% 97.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 199 1.27% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.58% 99.70% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.20% 99.90% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 11605 74.58% 74.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1745 11.21% 85.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 791 5.08% 90.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 727 4.67% 95.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 340 2.18% 97.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 213 1.37% 99.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 93 0.60% 99.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 32 0.21% 99.90% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15641 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.314771 # Inst issue rate -system.cpu.iq.iqInstsAdded 10005 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8852 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 15561 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.315041 # Inst issue rate +system.cpu.iq.iqInstsAdded 9963 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8835 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4214 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 36 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2725 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2680 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -337,12 +337,12 @@ system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.221154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31133.413462 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12953500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12951500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) @@ -364,30 +364,30 @@ system.cpu.l2cache.blocked_cycles::no_targets 0 system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 34356.223176 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits system.cpu.l2cache.demand_miss_latency 16010000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 14521500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14519500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.991489 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 466 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.006413 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 210.151573 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.006418 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 210.308968 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31162.017167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits system.cpu.l2cache.overall_miss_latency 16010000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses system.cpu.l2cache.overall_misses 466 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 14521500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14519500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.991489 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 466 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -395,27 +395,27 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 402 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 210.151573 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 210.308968 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2806 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2797 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28122 # number of cpu cycles simulated +system.cpu.numCycles 28044 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 5 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 10468 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 10455 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 9 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 15900 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 13681 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8420 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3575 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1080 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 15765 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 13587 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8333 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3513 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1073 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 5010 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:UndoneMaps 4923 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 496 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 111 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini index 508240960..5fbc0ed64 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -359,7 +359,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/power/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 4c710c177..3ef273e4f 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 13202840. This will break if not /dev/zero. +warn: allowing mmap of file @ fd 15924344. This will break if not /dev/zero. For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index 85fc6bc9f..9691f5f7c 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:13:07 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 24 2010 23:13:11 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:43:42 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:43:45 +M5 executing on zizzer command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11960500 because target called exit() +Exiting @ tick 11864500 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 4d658aa1d..1e1223443 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 51828 # Simulator instruction rate (inst/s) -host_mem_usage 189300 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -host_tick_rate 106468871 # Simulator tick rate (ticks/s) +host_inst_rate 50476 # Simulator instruction rate (inst/s) +host_mem_usage 202684 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 102996710 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5800 # Number of instructions simulated sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11960500 # Number of ticks simulated +sim_ticks 11864500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 734 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1942 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 389 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1971 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2303 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 188 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.condIncorrect 387 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1757 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2100 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1038 # Number of branches committed system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 10831 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.535500 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.248160 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 10785 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.537784 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.251292 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 8265 76.31% 76.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 1142 10.54% 86.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 659 6.08% 92.94% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 268 2.47% 95.41% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 226 2.09% 97.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 118 1.09% 98.59% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 80 0.74% 99.33% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 22 0.20% 99.53% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 8225 76.26% 76.26% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1129 10.47% 86.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 673 6.24% 92.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 258 2.39% 95.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 226 2.10% 97.46% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 120 1.11% 98.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 82 0.76% 99.33% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 21 0.19% 99.53% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 10831 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 10785 # Number of insts commited each cycle system.cpu.commit.COM:count 5800 # Number of instructions committed system.cpu.commit.COM:loads 962 # Number of loads committed system.cpu.commit.COM:membars 7 # Number of memory barriers committed system.cpu.commit.COM:refs 2008 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 243 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 240 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3801 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.124483 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.124483 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1436 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33320.224719 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34437.500000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1347 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2965500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061978 # miss rate for ReadReq accesses +system.cpu.cpi 4.091379 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.091379 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33612.359551 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1355 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 2991500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.061634 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1928500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.038997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33497.150997 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35861.538462 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33542.735043 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36053.846154 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 11757500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11773500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2331000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2343500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.048077 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2482 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33461.363636 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2042 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 14723000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.177276 # miss rate for demand accesses +system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 33556.818182 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2050 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14765000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.176707 # miss rate for demand accesses system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4259500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.048751 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 4273500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.048594 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.016127 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 66.056188 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2482 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33461.363636 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35202.479339 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.016240 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 66.517345 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 33556.818182 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2042 # number of overall hits -system.cpu.dcache.overall_miss_latency 14723000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.177276 # miss rate for overall accesses +system.cpu.dcache.overall_hits 2050 # number of overall hits +system.cpu.dcache.overall_miss_latency 14765000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.176707 # miss rate for overall accesses system.cpu.dcache.overall_misses 440 # number of overall misses system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4259500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.048751 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 4273500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.048594 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.056188 # Cycle average of tags in use -system.cpu.dcache.total_refs 2085 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 66.517345 # Cycle average of tags in use +system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1201 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 148 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 256 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 10901 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7556 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2000 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 615 # Number of cycles decode is squashing +system.cpu.decode.DECODE:BlockedCycles 1153 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7618 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 1941 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu.decode.DECODE:UnblockCycles 73 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses @@ -134,190 +134,190 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2303 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1463 # Number of cache lines fetched -system.cpu.fetch.Cycles 3604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 216 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12241 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 411 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.096271 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1463 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 922 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.511705 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.069457 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458316 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2100 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1490 # Number of cache lines fetched +system.cpu.fetch.Cycles 3561 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.088496 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.492499 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.029238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.423250 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 9306 81.30% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 148 1.29% 82.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 183 1.60% 84.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 143 1.25% 85.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 197 1.72% 87.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 135 1.18% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 371 3.24% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 95 0.83% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 868 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 9285 81.77% 81.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 161 1.42% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 189 1.66% 84.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 155 1.37% 86.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 202 1.78% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 136 1.20% 89.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 272 2.40% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 77 0.68% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 878 7.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11446 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 1463 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36616.094987 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34771.212121 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1084 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13877500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.259057 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 379 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11474500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.225564 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 11355 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36423.575130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34778.614458 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 14059500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11546500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.284848 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.325301 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1463 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36616.094987 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency -system.cpu.icache.demand_hits 1084 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13877500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.259057 # miss rate for demand accesses -system.cpu.icache.demand_misses 379 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 49 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11474500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.225564 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36423.575130 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency +system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 14059500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses +system.cpu.icache.demand_misses 386 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11546500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.077734 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 159.198376 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1463 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36616.094987 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34771.212121 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.078771 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 161.323458 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36423.575130 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1084 # number of overall hits -system.cpu.icache.overall_miss_latency 13877500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.259057 # miss rate for overall accesses -system.cpu.icache.overall_misses 379 # number of overall misses -system.cpu.icache.overall_mshr_hits 49 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11474500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.225564 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses +system.cpu.icache.overall_hits 1104 # number of overall hits +system.cpu.icache.overall_miss_latency 14059500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses +system.cpu.icache.overall_misses 386 # number of overall misses +system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11546500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 159.198376 # Cycle average of tags in use -system.cpu.icache.total_refs 1084 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.323458 # Cycle average of tags in use +system.cpu.icache.total_refs 1104 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12476 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1260 # Number of branches executed +system.cpu.idleCycles 12375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1261 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.324680 # Inst execution rate -system.cpu.iew.EXEC:refs 2768 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1280 # Number of stores executed +system.cpu.iew.EXEC:rate 0.328319 # Inst execution rate +system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1315 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5977 # num instructions consuming a value -system.cpu.iew.WB:count 7563 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.643801 # average fanout of values written-back +system.cpu.iew.WB:consumers 5889 # num instructions consuming a value +system.cpu.iew.WB:count 7582 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.646290 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3848 # num instructions producing a value -system.cpu.iew.WB:rate 0.316152 # insts written-back per cycle -system.cpu.iew.WB:sent 7622 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 141 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1815 # Number of dispatched load instructions +system.cpu.iew.WB:producers 3806 # num instructions producing a value +system.cpu.iew.WB:rate 0.319511 # insts written-back per cycle +system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 117 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1394 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9586 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1488 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 320 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7767 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1450 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9185 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7791 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 615 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 40 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 42 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 853 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 348 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 64 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.242455 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.242455 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 719 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 404 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.244416 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.244416 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5153 63.72% 63.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.72% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.74% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1611 19.92% 83.67% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1321 16.33% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.39% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1593 19.69% 83.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1368 16.91% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8087 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 141 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017435 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 8089 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 153 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018915 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.80% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 67 47.52% 55.32% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 63 44.68% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 11 7.19% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.19% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 73 47.71% 54.90% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11446 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.706535 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384911 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 11355 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.712373 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.391316 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 8157 71.27% 71.27% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 1172 10.24% 81.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 822 7.18% 88.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 530 4.63% 93.32% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 377 3.29% 96.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 216 1.89% 98.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 120 1.05% 99.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 43 0.38% 99.92% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 9 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 8066 71.03% 71.03% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 1182 10.41% 81.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 820 7.22% 88.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 507 4.46% 93.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 388 3.42% 96.55% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 218 1.92% 98.47% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 121 1.07% 99.53% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 46 0.41% 99.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11446 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.338057 # Inst issue rate -system.cpu.iq.iqInstsAdded 9564 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8087 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 11355 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.340877 # Inst issue rate +system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3408 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2985 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 3586 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 2761 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -328,28 +328,28 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34697.916667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1665500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34927.083333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31750 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1676500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1512000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1524000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 386 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31156.084656 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34327.631579 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31150 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12978000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.979275 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 378 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11777000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979275 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 13044500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34235.294118 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34264.705882 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 582000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 582500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles @@ -357,69 +357,69 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.022161 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.022039 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34374.413146 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14643500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981567 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 426 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14721000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13289000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13361000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.981651 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005513 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 180.652204 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34374.413146 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31194.835681 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005582 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 182.925254 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34394.859813 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14643500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981567 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 426 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14721000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 428 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13289000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 426 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13361000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.981651 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 428 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 361 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 363 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 180.652204 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 182.925254 # Cycle average of tags in use system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 67 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1815 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1394 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23922 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 356 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 23730 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7745 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 222 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 17199 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10376 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 9321 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1877 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 615 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 273 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4314 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 580 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:IdleCycles 7801 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 213 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 1823 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 263 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 575 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 571 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 494 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 9 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index dcbe2d23b..5b9e4a123 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -377,7 +377,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 660b124b5..356c9b63f 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:20:32 -M5 executing on SC2B0619 +M5 compiled May 12 2010 01:43:39 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 01:54:47 +M5 executing on zizzer command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 14251500 because target called exit() +Exiting @ tick 14406500 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 016b2b2d7..113c3ed26 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 95914 # Simulator instruction rate (inst/s) -host_mem_usage 191488 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 106648956 # Simulator tick rate (ticks/s) +host_inst_rate 76100 # Simulator instruction rate (inst/s) +host_mem_usage 204896 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 85690748 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 12773 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14251500 # Number of ticks simulated +sim_ticks 14406500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 4733 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 175 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1595 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 3153 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5548 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 681 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 801 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 4845 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 174 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1651 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 3171 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 5637 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 690 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches::0 1051 # Number of branches committed system.cpu.commit.COM:branches::1 1051 # Number of branches committed system.cpu.commit.COM:branches::total 2102 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 122 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 135 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 22838 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.560776 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.272228 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 23178 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.552550 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.284564 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 16881 73.92% 73.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 3016 13.21% 87.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 1386 6.07% 93.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 576 2.52% 95.71% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 326 1.43% 97.14% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 268 1.17% 98.31% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 170 0.74% 99.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 93 0.41% 99.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 122 0.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 17373 74.95% 74.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 2862 12.35% 87.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1369 5.91% 93.21% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 536 2.31% 95.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 355 1.53% 97.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 284 1.23% 98.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 169 0.73% 99.01% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 95 0.41% 99.42% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 135 0.58% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 22838 # Number of insts commited each cycle -system.cpu.commit.COM:count::0 6403 # Number of instructions committed -system.cpu.commit.COM:count::1 6404 # Number of instructions committed +system.cpu.commit.COM:committed_per_cycle::total 23178 # Number of insts commited each cycle +system.cpu.commit.COM:count::0 6404 # Number of instructions committed +system.cpu.commit.COM:count::1 6403 # Number of instructions committed system.cpu.commit.COM:count::total 12807 # Number of instructions committed system.cpu.commit.COM:loads::0 1185 # Number of loads committed system.cpu.commit.COM:loads::1 1185 # Number of loads committed @@ -55,118 +55,118 @@ system.cpu.commit.COM:refs::total 4100 # Nu system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1166 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1214 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 10895 # The number of squashed insts skipped by commit -system.cpu.committedInsts::0 6386 # Number of Instructions Simulated -system.cpu.committedInsts::1 6387 # Number of Instructions Simulated +system.cpu.commit.commitSquashedInsts 11211 # The number of squashed insts skipped by commit +system.cpu.committedInsts::0 6387 # Number of Instructions Simulated +system.cpu.committedInsts::1 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.463514 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.462815 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.231582 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3925 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 35473.913043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35473.913043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36849.514563 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3580 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::0 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12238500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.087898 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::0 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::0 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.052484 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052484 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::0 206 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 206 # number of ReadReq MSHR misses +system.cpu.cpi::0 4.511351 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.512058 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.255852 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3953 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 35613.003096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35613.003096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36812.195122 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3630 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::0 11503000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11503000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081710 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 323 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::0 118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7546500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.051859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::0 205 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 33703.947368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33703.947368 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36103.448276 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33528.289474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33528.289474 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36083.333333 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::0 25615000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25615000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::0 25481500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25481500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::0 6282000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6282000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::0 6278500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6278500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.100578 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13.102273 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.282051 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5655 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 34256.561086 # average overall miss latency +system.cpu.dcache.demand_accesses 5683 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 34150.046168 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34256.561086 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34150.046168 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 4550 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::0 37853500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_hits 4600 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::0 36984500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 37853500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.195402 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1105 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::0 725 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_miss_latency::total 36984500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.190568 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1083 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::0 704 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 725 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::0 13873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::total 704 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::0 13825000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.067197 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency::total 13825000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.066690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067197 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::0 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066690 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::0 379 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 379 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.054614 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 223.700041 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 5655 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 34256.561086 # average overall miss latency +system.cpu.dcache.occ_%::0 0.054473 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 223.120996 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 5683 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 34150.046168 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34256.561086 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36507.894737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34150.046168 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4550 # number of overall hits -system.cpu.dcache.overall_miss_latency::0 37853500 # number of overall miss cycles +system.cpu.dcache.overall_hits 4600 # number of overall hits +system.cpu.dcache.overall_miss_latency::0 36984500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 37853500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.195402 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1105 # number of overall misses -system.cpu.dcache.overall_mshr_hits::0 725 # number of overall MSHR hits +system.cpu.dcache.overall_miss_latency::total 36984500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.190568 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1083 # number of overall misses +system.cpu.dcache.overall_mshr_hits::0 704 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 725 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::0 13873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_hits::total 704 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::0 13825000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13873000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.067197 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency::total 13825000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.066690 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067197 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::0 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066690 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::0 379 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 380 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 379 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -176,153 +176,153 @@ system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 223.700041 # Cycle average of tags in use -system.cpu.dcache.total_refs 4612 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 223.120996 # Cycle average of tags in use +system.cpu.dcache.total_refs 4662 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks::0 0 # number of writebacks system.cpu.dcache.writebacks::1 0 # number of writebacks system.cpu.dcache.writebacks::total 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 5063 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 441 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 602 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 27492 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 33392 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 4878 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2128 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 668 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 186 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 6300 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 451 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 595 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 27842 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 34006 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4930 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 2198 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 677 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 6328 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 6155 # DTB hits -system.cpu.dtb.data_misses 145 # DTB misses +system.cpu.dtb.data_hits 6178 # DTB hits +system.cpu.dtb.data_misses 150 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 4144 # DTB read accesses +system.cpu.dtb.read_accesses 4160 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 4056 # DTB read hits +system.cpu.dtb.read_hits 4072 # DTB read hits system.cpu.dtb.read_misses 88 # DTB read misses -system.cpu.dtb.write_accesses 2156 # DTB write accesses +system.cpu.dtb.write_accesses 2168 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2099 # DTB write hits -system.cpu.dtb.write_misses 57 # DTB write misses -system.cpu.fetch.Branches 5548 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4113 # Number of cache lines fetched -system.cpu.fetch.Cycles 9444 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 613 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 30949 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.194639 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4113 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1597 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.085777 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 22904 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.351249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.742840 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 2106 # DTB write hits +system.cpu.dtb.write_misses 62 # DTB write misses +system.cpu.fetch.Branches 5637 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 4152 # Number of cache lines fetched +system.cpu.fetch.Cycles 9523 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 615 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 31429 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1766 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.195634 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 4152 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1491 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.090754 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 23259 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.351262 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.751825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 17622 76.94% 76.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 416 1.82% 78.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 353 1.54% 80.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 477 2.08% 82.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 425 1.86% 84.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 349 1.52% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 442 1.93% 87.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 261 1.14% 88.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2559 11.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 17946 77.16% 77.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 425 1.83% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 330 1.42% 80.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 452 1.94% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 406 1.75% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 353 1.52% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 452 1.94% 87.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 273 1.17% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2622 11.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 22904 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 4113 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 35793.697979 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35793.697979 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35516.155089 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3272 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::0 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30102500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.204474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 841 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits::0 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency::0 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.150498 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150498 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::0 619 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 619 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 23259 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 4152 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 35658.767773 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35658.767773 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35482.171799 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 3308 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::0 30096000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30096000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.203276 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 844 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits::0 227 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency::0 21892500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21892500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.148603 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148603 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::0 617 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 617 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.285945 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.361426 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4113 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 35793.697979 # average overall miss latency +system.cpu.icache.demand_accesses 4152 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 35658.767773 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35793.697979 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency::total 35658.767773 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35482.171799 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 3272 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::0 30102500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_hits 3308 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::0 30096000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30102500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.204474 # miss rate for demand accesses -system.cpu.icache.demand_misses 841 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits::0 222 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_miss_latency::total 30096000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.203276 # miss rate for demand accesses +system.cpu.icache.demand_misses 844 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits::0 227 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 222 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency::0 21984500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency::0 21892500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.150498 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency::total 21892500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.148603 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.150498 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_rate::total 0.148603 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::0 617 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 617 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.156877 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 321.284131 # Average occupied blocks per context -system.cpu.icache.overall_accesses 4113 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 35793.697979 # average overall miss latency +system.cpu.icache.occ_%::0 0.156062 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 319.614812 # Average occupied blocks per context +system.cpu.icache.overall_accesses 4152 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 35658.767773 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35793.697979 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::0 35516.155089 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency::total 35658.767773 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35482.171799 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3272 # number of overall hits -system.cpu.icache.overall_miss_latency::0 30102500 # number of overall miss cycles +system.cpu.icache.overall_hits 3308 # number of overall hits +system.cpu.icache.overall_miss_latency::0 30096000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30102500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.204474 # miss rate for overall accesses -system.cpu.icache.overall_misses 841 # number of overall misses -system.cpu.icache.overall_mshr_hits::0 222 # number of overall MSHR hits +system.cpu.icache.overall_miss_latency::total 30096000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.203276 # miss rate for overall accesses +system.cpu.icache.overall_misses 844 # number of overall misses +system.cpu.icache.overall_mshr_hits::0 227 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 222 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency::0 21984500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_hits::total 227 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency::0 21892500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.150498 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency::total 21892500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.148603 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.150498 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_rate::total 0.148603 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::0 617 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 617 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -332,198 +332,198 @@ system.cpu.icache.overall_mshr_uncacheable_misses::total 0 system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 617 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 321.284131 # Cycle average of tags in use -system.cpu.icache.total_refs 3272 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 319.614812 # Cycle average of tags in use +system.cpu.icache.total_refs 3308 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks::0 0 # number of writebacks system.cpu.icache.writebacks::1 0 # number of writebacks system.cpu.icache.writebacks::total 0 # number of writebacks -system.cpu.idleCycles 5600 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches::0 1573 # Number of branches executed -system.cpu.iew.EXEC:branches::1 1587 # Number of branches executed -system.cpu.iew.EXEC:branches::total 3160 # Number of branches executed -system.cpu.iew.EXEC:nop::0 70 # number of nop insts executed -system.cpu.iew.EXEC:nop::1 65 # number of nop insts executed +system.cpu.idleCycles 5555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches::0 1592 # Number of branches executed +system.cpu.iew.EXEC:branches::1 1585 # Number of branches executed +system.cpu.iew.EXEC:branches::total 3177 # Number of branches executed +system.cpu.iew.EXEC:nop::0 69 # number of nop insts executed +system.cpu.iew.EXEC:nop::1 66 # number of nop insts executed system.cpu.iew.EXEC:nop::total 135 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.673940 # Inst execution rate -system.cpu.iew.EXEC:refs::0 3132 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::1 3189 # number of memory reference insts executed -system.cpu.iew.EXEC:refs::total 6321 # number of memory reference insts executed -system.cpu.iew.EXEC:stores::0 1090 # Number of stores executed -system.cpu.iew.EXEC:stores::1 1085 # Number of stores executed -system.cpu.iew.EXEC:stores::total 2175 # Number of stores executed +system.cpu.iew.EXEC:rate 0.670750 # Inst execution rate +system.cpu.iew.EXEC:refs::0 3218 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::1 3132 # number of memory reference insts executed +system.cpu.iew.EXEC:refs::total 6350 # number of memory reference insts executed +system.cpu.iew.EXEC:stores::0 1105 # Number of stores executed +system.cpu.iew.EXEC:stores::1 1082 # Number of stores executed +system.cpu.iew.EXEC:stores::total 2187 # Number of stores executed system.cpu.iew.EXEC:swp::0 0 # number of swp insts executed system.cpu.iew.EXEC:swp::1 0 # number of swp insts executed system.cpu.iew.EXEC:swp::total 0 # number of swp insts executed -system.cpu.iew.WB:consumers::0 5984 # num instructions consuming a value -system.cpu.iew.WB:consumers::1 5917 # num instructions consuming a value -system.cpu.iew.WB:consumers::total 11901 # num instructions consuming a value -system.cpu.iew.WB:count::0 9221 # cumulative count of insts written-back -system.cpu.iew.WB:count::1 9205 # cumulative count of insts written-back -system.cpu.iew.WB:count::total 18426 # cumulative count of insts written-back -system.cpu.iew.WB:fanout::0 0.776404 # average fanout of values written-back -system.cpu.iew.WB:fanout::1 0.776407 # average fanout of values written-back -system.cpu.iew.WB:fanout::total 1.552811 # average fanout of values written-back +system.cpu.iew.WB:consumers::0 6017 # num instructions consuming a value +system.cpu.iew.WB:consumers::1 5962 # num instructions consuming a value +system.cpu.iew.WB:consumers::total 11979 # num instructions consuming a value +system.cpu.iew.WB:count::0 9293 # cumulative count of insts written-back +system.cpu.iew.WB:count::1 9238 # cumulative count of insts written-back +system.cpu.iew.WB:count::total 18531 # cumulative count of insts written-back +system.cpu.iew.WB:fanout::0 0.773143 # average fanout of values written-back +system.cpu.iew.WB:fanout::1 0.773398 # average fanout of values written-back +system.cpu.iew.WB:fanout::total 1.546541 # average fanout of values written-back system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers::0 4646 # num instructions producing a value -system.cpu.iew.WB:producers::1 4594 # num instructions producing a value -system.cpu.iew.WB:producers::total 9240 # num instructions producing a value -system.cpu.iew.WB:rate::0 0.323498 # insts written-back per cycle -system.cpu.iew.WB:rate::1 0.322937 # insts written-back per cycle -system.cpu.iew.WB:rate::total 0.646436 # insts written-back per cycle -system.cpu.iew.WB:sent::0 9324 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::1 9340 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent::total 18664 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1342 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1080 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4951 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 727 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2585 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 23775 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts::0 2042 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2104 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4146 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1180 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 19210 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers::0 4652 # num instructions producing a value +system.cpu.iew.WB:producers::1 4611 # num instructions producing a value +system.cpu.iew.WB:producers::total 9263 # num instructions producing a value +system.cpu.iew.WB:rate::0 0.322517 # insts written-back per cycle +system.cpu.iew.WB:rate::1 0.320608 # insts written-back per cycle +system.cpu.iew.WB:rate::total 0.643125 # insts written-back per cycle +system.cpu.iew.WB:sent::0 9430 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::1 9343 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent::total 18773 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1399 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1055 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 5029 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 731 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2605 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 24098 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts::0 2113 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2050 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1224 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 19327 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2128 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 2198 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 57 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 71 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1246 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 417 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1385 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 471 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 72 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 64 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1335 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 438 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 136 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1080 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 262 # Number of branches that were predicted taken incorrectly -system.cpu.ipc::0 0.224039 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.224074 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.448113 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.1.squashedLoads 1274 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 404 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 135 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1143 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 256 # Number of branches that were predicted taken incorrectly +system.cpu.ipc::0 0.221663 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.221628 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.443291 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 6830 67.10% 67.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.15% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2173 21.35% 88.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1171 11.50% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 6901 66.76% 66.78% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 66.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.81% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2273 21.99% 88.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1158 11.20% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 10179 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::total 10337 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntAlu 6842 67.01% 67.03% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.04% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemRead 2230 21.84% 88.89% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::MemWrite 1134 11.11% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntAlu 6867 67.23% 67.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntMult 1 0.01% 67.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::IntDiv 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatAdd 2 0.02% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCmp 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatCvt 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatDiv 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.28% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemRead 2182 21.36% 88.64% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::MemWrite 1160 11.36% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_1::total 10211 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1::total 10214 # Type of FU issued system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntAlu 13672 67.05% 67.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemRead 4403 21.59% 88.70% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::MemWrite 2305 11.30% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntAlu 13768 66.99% 67.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntMult 2 0.01% 67.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::IntDiv 0 0.00% 67.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatAdd 4 0.02% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCmp 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatCvt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatMult 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatDiv 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::FloatSqrt 0 0.00% 67.04% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemRead 4455 21.68% 88.72% # Type of FU issued +system.cpu.iq.ISSUE:FU_type::MemWrite 2318 11.28% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type::total 20390 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt::0 87 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::1 85 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt::total 172 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::1 0.004169 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate::total 0.008436 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type::total 20551 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt::0 79 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::1 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt::total 167 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate::0 0.003844 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::1 0.004282 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate::total 0.008126 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 13 7.56% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 7.56% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 96 55.81% 63.37% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 63 36.63% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 9 5.39% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.39% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 95 56.89% 62.28% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 63 37.72% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 22904 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.890238 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.446450 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 23259 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.883572 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.458526 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 14156 61.81% 61.81% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 3289 14.36% 76.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 2351 10.26% 86.43% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 1373 5.99% 92.42% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 854 3.73% 96.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 535 2.34% 98.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 261 1.14% 99.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 57 0.25% 99.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 28 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 14576 62.67% 62.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 3197 13.75% 76.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 2342 10.07% 86.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 1327 5.71% 92.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 883 3.80% 95.98% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 568 2.44% 98.43% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 270 1.16% 99.59% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 71 0.31% 99.89% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 25 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 22904 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.715338 # Inst issue rate -system.cpu.iq.iqInstsAdded 23596 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 20390 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9662 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5422 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 23259 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.713230 # Inst issue rate +system.cpu.iq.iqInstsAdded 23917 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 20551 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 9939 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 5669 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4162 # ITB accesses +system.cpu.itb.fetch_accesses 4210 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 4113 # ITB hits -system.cpu.itb.fetch_misses 49 # ITB misses +system.cpu.itb.fetch_hits 4152 # ITB hits +system.cpu.itb.fetch_misses 58 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -533,116 +533,116 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31589.041096 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency::0 5058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5058000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34623.287671 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34623.287671 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31544.520548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency::0 5055000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5055000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4612000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4612000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4605500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4605500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 825 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34555.285541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34555.285541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31414.337789 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 822 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34548.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34548.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31393.902439 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::0 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28439000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997576 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25854000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997576 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::0 823 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency::0 28329500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28329500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997567 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 820 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25743000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25743000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997567 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997567 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::0 820 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34482.142857 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31357.142857 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency::0 965500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 965500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31392.857143 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency::0 966000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 966000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 28 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 878000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 878000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 879000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 879000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002516 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002525 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::0 34568.627451 # average overall miss latency +system.cpu.l2cache.demand_accesses 968 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::0 34559.523810 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34568.627451 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34559.523810 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::0 33497000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::0 33384500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997940 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 969 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency::total 33384500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997934 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 966 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::0 30466000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::0 30348500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::0 0.997940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_latency::total 30348500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::0 0.997934 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::0 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997934 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::0 966 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 969 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.013297 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 435.713880 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::0 34568.627451 # average overall miss latency +system.cpu.l2cache.occ_%::0 0.013217 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 433.083390 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 968 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::0 34559.523810 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34568.627451 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31440.660475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34559.523810 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency::0 33497000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::0 33384500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33497000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997940 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 969 # number of overall misses +system.cpu.l2cache.overall_miss_latency::total 33384500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997934 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 966 # number of overall misses system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::0 30466000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::0 30348500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::0 0.997940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency::total 30348500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::0 0.997934 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::0 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997934 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::0 966 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 969 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 966 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles @@ -652,42 +652,43 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.sampled_refs 795 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 792 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 435.713880 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 433.083390 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks::0 0 # number of writebacks system.cpu.l2cache.writebacks::1 0 # number of writebacks system.cpu.l2cache.writebacks::total 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2431 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1282 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 58 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 32 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1303 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 28504 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 2835 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2570 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 27 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 5 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2459 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1269 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 28814 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 2841 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 33866 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1399 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 34469 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1383 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 32685 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 26128 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 19538 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 4546 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2128 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1422 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 10372 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 850 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 3399 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 33146 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 26493 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19854 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4562 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 2198 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1440 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10688 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 847 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3428 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 0cc32d77e..927a68251 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -358,7 +358,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index a6f645c41..8a865dd25 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:00 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:45:56 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:47:29 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 27756500 because target called exit() +Exiting @ tick 27640500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index d92dfc078..bf26975cc 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,336 +1,336 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 72869 # Simulator instruction rate (inst/s) -host_mem_usage 190800 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host -host_tick_rate 139786869 # Simulator tick rate (ticks/s) +host_inst_rate 58626 # Simulator instruction rate (inst/s) +host_mem_usage 204232 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +host_tick_rate 112030496 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 14449 # Number of instructions simulated sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27756500 # Number of ticks simulated +sim_ticks 27640500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 4398 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 9844 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 4205 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 9185 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11413 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 11413 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 2913 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11479 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 11479 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 3359 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 42766 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.354838 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 0.957636 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 42520 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.356891 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 0.964493 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0-1 34594 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1-2 4804 11.23% 92.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2-3 1741 4.07% 96.20% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3-4 720 1.68% 97.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4-5 413 0.97% 98.84% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5-6 144 0.34% 99.18% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6-7 196 0.46% 99.64% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7-8 51 0.12% 99.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 103 0.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 34367 80.83% 80.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 4806 11.30% 92.13% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 1719 4.04% 96.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 713 1.68% 97.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 414 0.97% 98.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 146 0.34% 99.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 193 0.45% 99.62% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 48 0.11% 99.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 114 0.27% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 42766 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 42520 # Number of insts commited each cycle system.cpu.commit.COM:count 15175 # Number of instructions committed system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 3674 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 2913 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 19910 # The number of squashed insts skipped by commit system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses +system.cpu.cpi 3.826009 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.826009 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3842 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 35228.070175 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35561.538462 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3728 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4016000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.029672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2311500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.016918 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 31248.306998 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35612.745098 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 13843000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3632500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 32.222973 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency -system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses -system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 5284 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32062.836625 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4727 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 17859000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.105413 # miss rate for demand accesses +system.cpu.dcache.demand_misses 557 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 390 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5944000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.031605 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.026530 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 108.665251 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.026503 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 108.555093 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 5284 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32062.836625 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4728 # number of overall hits -system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses -system.cpu.dcache.overall_misses 558 # number of overall misses -system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 4727 # number of overall hits +system.cpu.dcache.overall_miss_latency 17859000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.105413 # miss rate for overall accesses +system.cpu.dcache.overall_misses 557 # number of overall misses +system.cpu.dcache.overall_mshr_hits 390 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5944000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.031605 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use -system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 108.555093 # Cycle average of tags in use +system.cpu.dcache.total_refs 4769 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched -system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 3018 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 47090 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.236929 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.372442 # Number of instructions fetched each cycle (Total) +system.cpu.decode.DECODE:BlockedCycles 7141 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 51862 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 20451 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 14795 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4325 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 11479 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7330 # Number of cache lines fetched +system.cpu.fetch.Cycles 23798 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 830 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 58419 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.207644 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 7330 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4205 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.056745 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 46845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.247070 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.396969 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0-1 30448 64.66% 64.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1-2 7532 15.99% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2-3 1217 2.58% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3-4 1059 2.25% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4-5 1060 2.25% 87.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5-6 1193 2.53% 90.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6-7 711 1.51% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7-8 327 0.69% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3543 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 30399 64.89% 64.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 7442 15.89% 80.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 1110 2.37% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 985 2.10% 85.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 1044 2.23% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 1211 2.59% 90.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 663 1.42% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 335 0.72% 92.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3656 7.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47090 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses +system.cpu.fetch.rateDist::total 46845 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 7330 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 33618.691589 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34870.473538 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6795 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 17986000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.072988 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_latency 12518500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.048977 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.980447 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency -system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses +system.cpu.icache.demand_accesses 7330 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 33618.691589 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency +system.cpu.icache.demand_hits 6795 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 17986000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.072988 # miss rate for demand accesses system.cpu.icache.demand_misses 535 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 12518500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.048977 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.110760 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 226.836007 # Average occupied blocks per context -system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.110625 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 226.560324 # Average occupied blocks per context +system.cpu.icache.overall_accesses 7330 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 33618.691589 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6821 # number of overall hits -system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses +system.cpu.icache.overall_hits 6795 # number of overall hits +system.cpu.icache.overall_miss_latency 17986000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.072988 # miss rate for overall accesses system.cpu.icache.overall_misses 535 # number of overall misses system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 12518500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.048977 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use -system.cpu.icache.total_refs 6821 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 226.560324 # Cycle average of tags in use +system.cpu.icache.total_refs 6795 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 4842 # Number of branches executed -system.cpu.iew.EXEC:nop 2091 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate -system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2454 # Number of stores executed +system.cpu.idleCycles 8437 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 4838 # Number of branches executed +system.cpu.iew.EXEC:nop 2088 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.449477 # Inst execution rate +system.cpu.iew.EXEC:refs 6429 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2469 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 13039 # num instructions consuming a value +system.cpu.iew.WB:consumers 13103 # num instructions consuming a value system.cpu.iew.WB:count 23891 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back +system.cpu.iew.WB:fanout 0.824239 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 10787 # num instructions producing a value -system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle -system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 10800 # num instructions producing a value +system.cpu.iew.WB:rate 0.432166 # insts written-back per cycle +system.cpu.iew.WB:sent 24095 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3199 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 4967 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions +system.cpu.iew.iewDispSquashedInsts 3043 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 3406 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewExecLoadInsts 3960 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4355 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 24848 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 4325 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 36 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 2741 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1958 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads +system.cpu.iew.predictedNotTakenIncorrect 814 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2385 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.261369 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.261369 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 21395 73.22% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.22% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 4720 16.15% 89.37% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 3105 10.63% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 21370 73.18% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 73.18% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 4722 16.17% 89.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 3111 10.65% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 29220 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 29203 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 177 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006061 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 40 23.12% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 20 11.56% 34.68% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 113 65.32% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 44 24.86% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 24.86% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 20 11.30% 36.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 113 63.84% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 47090 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.620514 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.275912 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 46845 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.623396 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.283288 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0-1 34112 72.44% 72.44% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1-2 5516 11.71% 84.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2-3 3070 6.52% 90.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3-4 2146 4.56% 95.23% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4-5 997 2.12% 97.35% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5-6 653 1.39% 98.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6-7 342 0.73% 99.46% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7-8 211 0.45% 99.91% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0-1 33954 72.48% 72.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1-2 5459 11.65% 84.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2-3 3016 6.44% 90.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3-4 2133 4.55% 95.13% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4-5 995 2.12% 97.25% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5-6 695 1.48% 98.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6-7 336 0.72% 99.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7-8 214 0.46% 99.91% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 47090 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate -system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 46845 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.528255 # Inst issue rate +system.cpu.iq.iqInstsAdded 32305 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 29203 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15689 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 12321 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34397.590361 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31313.253012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2855000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2599000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34219.047619 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.761905 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 14372000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 13022000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency 34342.105263 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency 652500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles @@ -345,31 +345,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 34248.508946 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 17227000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15621000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.007680 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 251.642612 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.007671 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 251.347828 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 34248.508946 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 17227000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses system.cpu.l2cache.overall_misses 503 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15621000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -377,31 +377,31 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 251.347828 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 26 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 4960 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 3415 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 55514 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking +system.cpu.memDep0.insertedLoads 4967 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 3406 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 55282 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 31 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle +system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 22239 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenameLookups 74814 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 42611 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:RunCycles 13163 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4325 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 313 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializeStallCycles 6774 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5153 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 824 # count of temporary serializing insts renamed system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 2fffc58e2..e7279bca8 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -317,7 +317,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 1d66e4129..e80cf75e8 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,34 +5,34 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:02 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:45:56 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:45:58 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 1, Thread 3] Got lock [Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 @@ -41,26 +41,26 @@ Iteration 3 completed [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 Iteration 4 completed -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 Iteration 5 completed -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 7, Thread 2] Got lock [Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 Iteration 7 completed [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 @@ -69,19 +69,19 @@ Iteration 7 completed [Iteration 8, Thread 3] Got lock [Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 220484500 because target called exit() +Exiting @ tick 217002500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 75d6c02bb..a59d4f21a 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,943 +1,942 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 38759 # Simulator instruction rate (inst/s) -host_mem_usage 200852 # Number of bytes of host memory used -host_seconds 11.32 # Real time elapsed on the host -host_tick_rate 19469095 # Simulator tick rate (ticks/s) +host_inst_rate 71817 # Simulator instruction rate (inst/s) +host_mem_usage 214292 # Number of bytes of host memory used +host_seconds 6.05 # Real time elapsed on the host +host_tick_rate 35890036 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 438923 # Number of instructions simulated -sim_seconds 0.000220 # Number of seconds simulated -sim_ticks 220484500 # Number of ticks simulated +sim_insts 434213 # Number of instructions simulated +sim_seconds 0.000217 # Number of seconds simulated +sim_ticks 217002500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 54549 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 70955 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 52073 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 66680 # Number of BTB lookups system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 31037 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 79925 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 79925 # Number of BP lookups +system.cpu0.BPredUnit.condIncorrect 30422 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 81408 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 81408 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 25657 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 567 # number cycles where commit BW limit reached +system.cpu0.commit.COM:branches 25190 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 578 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 355685 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.364783 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 0.822342 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 347008 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.368821 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 0.833965 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0-1 269749 75.84% 75.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1-2 56588 15.91% 91.75% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2-3 24519 6.89% 98.64% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3-4 1287 0.36% 99.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4-5 786 0.22% 99.23% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5-6 567 0.16% 99.38% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6-7 1608 0.45% 99.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7-8 14 0.00% 99.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 567 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0-1 262750 75.72% 75.72% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1-2 55494 15.99% 91.71% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2-3 23803 6.86% 98.57% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3-4 1293 0.37% 98.94% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4-5 820 0.24% 99.18% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5-6 559 0.16% 99.34% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6-7 1671 0.48% 99.82% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7-8 40 0.01% 99.83% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 578 0.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 355685 # Number of insts commited each cycle -system.cpu0.commit.COM:count 129748 # Number of instructions committed -system.cpu0.commit.COM:loads 30551 # Number of loads committed -system.cpu0.commit.COM:membars 8310 # Number of memory barriers committed -system.cpu0.commit.COM:refs 41937 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 347008 # Number of insts commited each cycle +system.cpu0.commit.COM:count 127984 # Number of instructions committed +system.cpu0.commit.COM:loads 30137 # Number of loads committed +system.cpu0.commit.COM:membars 7796 # Number of memory barriers committed +system.cpu0.commit.COM:refs 41570 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 31037 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 129748 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 9029 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 140741 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 104996 # Number of Instructions Simulated -system.cpu0.committedInsts_total 104996 # Number of Instructions Simulated -system.cpu0.cpi 3.832270 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.832270 # CPI: Total CPI of All Threads -system.cpu0.dcache.ReadReq_accesses 29224 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 18192.118227 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 15806.818182 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 29021 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 3693000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.006946 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 203 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 2782000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.006022 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 176 # number of ReadReq MSHR misses -system.cpu0.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_avg_miss_latency 21093.220339 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 22239.583333 # average SwapReq mshr miss latency +system.cpu0.commit.branchMispredicts 30422 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 127984 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 8513 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 104211 # Number of Instructions Simulated +system.cpu0.committedInsts_total 104211 # Number of Instructions Simulated +system.cpu0.cpi 3.794734 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.794734 # CPI: Total CPI of All Threads +system.cpu0.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 28373 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 4031500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.007312 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 209 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 3023000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.006088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses +system.cpu0.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_avg_miss_latency 21973.684211 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 23510.869565 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu0.dcache.SwapReq_miss_latency 1244500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_rate 0.808219 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_misses 59 # number of SwapReq misses +system.cpu0.dcache.SwapReq_miss_latency 1252500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_misses 57 # number of SwapReq misses system.cpu0.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits -system.cpu0.dcache.SwapReq_mshr_miss_latency 1067500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.657534 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_misses 48 # number of SwapReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 11313 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 23258.064516 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 14768.867925 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 11189 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 2884000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.010961 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 124 # number of WriteReq misses +system.cpu0.dcache.SwapReq_mshr_miss_latency 1081500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_rate 0.647887 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 11362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 24003.906250 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 15831.818182 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 11234 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 3072500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.011266 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 128 # number of WriteReq misses system.cpu0.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 1565500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 1741500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009681 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 110 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 735.966667 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 708.483871 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 40537 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 20113.149847 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 15416.666667 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 40210 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 6577000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.008067 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 327 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 4347500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.006957 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 282 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_accesses 39944 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 21080.118694 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 39607 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 7104000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.008437 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 337 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 4764500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.007110 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 284 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.055235 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 28.280349 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 40537 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 20113.149847 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 15416.666667 # average overall mshr miss latency +system.cpu0.dcache.occ_%::0 0.056939 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 29.152957 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 39944 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 40210 # number of overall hits -system.cpu0.dcache.overall_miss_latency 6577000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.008067 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 327 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 4347500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.006957 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 282 # number of overall MSHR misses +system.cpu0.dcache.overall_hits 39607 # number of overall hits +system.cpu0.dcache.overall_miss_latency 7104000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.008437 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 337 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 53 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 4764500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.007110 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 284 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu0.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 28.280349 # Cycle average of tags in use -system.cpu0.dcache.total_refs 22079 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 29.152957 # Cycle average of tags in use +system.cpu0.dcache.total_refs 21963 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 1 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 31385 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:DecodedInsts 367055 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 175688 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 148454 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 34938 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:UnblockCycles 158 # Number of cycles decode is unblocking -system.cpu0.fetch.Branches 79925 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 83600 # Number of cache lines fetched -system.cpu0.fetch.Cycles 244044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 9987 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 413648 # Number of instructions fetch has processed -system.cpu0.fetch.SquashCycles 31188 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.198634 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 83600 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 54549 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 1.028021 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 399788 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.034668 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.929402 # Number of instructions fetched each cycle (Total) +system.cpu0.decode.DECODE:BlockedCycles 31861 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:DecodedInsts 361505 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 170760 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 144226 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 34255 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking +system.cpu0.fetch.Branches 81408 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 81347 # Number of cache lines fetched +system.cpu0.fetch.Cycles 236913 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 412447 # Number of instructions fetch has processed +system.cpu0.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.205860 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 1.042974 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 390306 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.056727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.974128 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0-1 239369 59.87% 59.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1-2 86666 21.68% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2-3 18970 4.75% 86.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3-4 18363 4.59% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4-5 2993 0.75% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5-6 13233 3.31% 94.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6-7 1665 0.42% 95.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7-8 2406 0.60% 95.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 16123 4.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0-1 234764 60.15% 60.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1-2 83865 21.49% 81.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2-3 17837 4.57% 86.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3-4 14411 3.69% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4-5 2742 0.70% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5-6 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6-7 1358 0.35% 95.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7-8 2423 0.62% 95.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 16356 4.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 399788 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses 83600 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14035.763411 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11552.755906 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 82873 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 10204000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.008696 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 727 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 92 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7336000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.007596 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 635 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.fetch.rateDist::total 390306 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 80599 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 14184500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.009195 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 748 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 116 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 10114500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.007769 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 632 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 130.508661 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.avg_refs 127.530063 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 83600 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14035.763411 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11552.755906 # average overall mshr miss latency -system.cpu0.icache.demand_hits 82873 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 10204000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.008696 # miss rate for demand accesses -system.cpu0.icache.demand_misses 727 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7336000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.007596 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_accesses 81347 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 18963.235294 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency +system.cpu0.icache.demand_hits 80599 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 14184500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.009195 # miss rate for demand accesses +system.cpu0.icache.demand_misses 748 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 116 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 10114500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.007769 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 632 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.187347 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 95.921890 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 83600 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14035.763411 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11552.755906 # average overall mshr miss latency +system.cpu0.icache.occ_%::0 0.191179 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 97.883584 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 81347 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 82873 # number of overall hits -system.cpu0.icache.overall_miss_latency 10204000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.008696 # miss rate for overall accesses -system.cpu0.icache.overall_misses 727 # number of overall misses -system.cpu0.icache.overall_mshr_hits 92 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7336000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.007596 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu0.icache.overall_hits 80599 # number of overall hits +system.cpu0.icache.overall_miss_latency 14184500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.009195 # miss rate for overall accesses +system.cpu0.icache.overall_misses 748 # number of overall misses +system.cpu0.icache.overall_mshr_hits 116 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 10114500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.007769 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 632 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 524 # number of replacements -system.cpu0.icache.sampled_refs 635 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 522 # number of replacements +system.cpu0.icache.sampled_refs 632 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 95.921890 # Cycle average of tags in use -system.cpu0.icache.total_refs 82873 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 97.883584 # Cycle average of tags in use +system.cpu0.icache.total_refs 80599 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 2585 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 37656 # Number of branches executed -system.cpu0.iew.EXEC:nop 48476 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.417965 # Inst execution rate -system.cpu0.iew.EXEC:refs 49837 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 13176 # Number of stores executed +system.cpu0.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 37149 # Number of branches executed +system.cpu0.iew.EXEC:nop 47058 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.419532 # Inst execution rate +system.cpu0.iew.EXEC:refs 49104 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 13043 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 81944 # num instructions consuming a value -system.cpu0.iew.WB:count 164449 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.932149 # average fanout of values written-back +system.cpu0.iew.WB:consumers 81150 # num instructions consuming a value +system.cpu0.iew.WB:count 162295 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.931855 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 76384 # num instructions producing a value -system.cpu0.iew.WB:rate 0.408698 # insts written-back per cycle -system.cpu0.iew.WB:sent 164672 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 31697 # Number of branch mispredicts detected at execute +system.cpu0.iew.WB:producers 75620 # num instructions producing a value +system.cpu0.iew.WB:rate 0.410403 # insts written-back per cycle +system.cpu0.iew.WB:sent 162544 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute system.cpu0.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 41051 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 9374 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 4077 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 22447 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 270509 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 36661 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 34703 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 168178 # Number of executed instructions +system.cpu0.iew.iewDispLoadInsts 40176 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 9384 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 3614 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 22433 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 266034 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 36061 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 34221 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 165905 # Number of executed instructions system.cpu0.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 34938 # Number of cycles IEW is squashing +system.cpu0.iew.iewSquashCycles 34255 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 7417 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.forwLoads 7459 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 646 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.memOrderViolation 698 # Number of memory ordering violations system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 10500 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 11061 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 646 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 856 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 30841 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.260942 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.260942 # IPC: Total IPC of All Threads +system.cpu0.iew.lsq.thread.0.squashedLoads 10039 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 11000 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 698 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.263523 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.263523 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 142871 70.42% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 46166 22.76% 93.18% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 13844 6.82% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 45052 22.51% 93.14% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 13735 6.86% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 202881 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.000853 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 200126 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.000904 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 23 13.29% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 11 6.36% 19.65% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 139 80.35% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 19 10.50% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 17 9.39% 19.89% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 399788 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.507471 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.960639 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 390306 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.512741 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.969063 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 279763 69.98% 69.98% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 72065 18.03% 88.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 24983 6.25% 94.25% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 14756 3.69% 97.94% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 5406 1.35% 99.30% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 2153 0.54% 99.83% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 473 0.12% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 157 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 32 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 272942 69.93% 69.93% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 69416 17.79% 87.72% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 25173 6.45% 94.16% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 14490 3.71% 97.88% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 5424 1.39% 99.27% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 2186 0.56% 99.83% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 485 0.12% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 162 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 28 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 399788 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.504211 # Inst issue rate -system.cpu0.iq.iqInstsAdded 204299 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 202881 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 17734 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 79448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.ISSUE:issued_per_cycle::total 390306 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.506068 # Inst issue rate +system.cpu0.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 200126 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 77302 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 8705 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 34402 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.memDep0.conflictingLoads 7616 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 83 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 41051 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 22447 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 402373 # number of cpu cycles simulated -system.cpu0.rename.RENAME:CommittedMaps 87918 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IdleCycles 188663 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:RenameLookups 464430 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 298607 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 213629 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 135723 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 34938 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 563 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 125711 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 30736 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 9619 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 36235 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 9747 # count of temporary serializing insts renamed -system.cpu0.timesIdled 284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.iq.iqSquashedNonSpecRemoved 8735 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 33615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.memDep0.conflictingLoads 7669 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 92 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 395453 # number of cpu cycles simulated +system.cpu0.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle +system.cpu0.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 293451 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 211386 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 131636 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 34255 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 645 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 123786 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 31130 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 9653 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 36749 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 9784 # count of temporary serializing insts renamed +system.cpu0.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 53615 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 73516 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 48405 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 65841 # Number of BTB lookups system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 30904 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 87311 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 87311 # Number of BP lookups +system.cpu1.BPredUnit.condIncorrect 32660 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 82266 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 82266 # Number of BP lookups system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 25648 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 570 # number cycles where commit BW limit reached +system.cpu1.commit.COM:branches 25082 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 576 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 355192 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.364749 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 0.823293 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 346536 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.381828 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 0.836481 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0-1 269483 75.87% 75.87% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1-2 56385 15.87% 91.74% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2-3 24471 6.89% 98.63% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3-4 1296 0.36% 99.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4-5 793 0.22% 99.22% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5-6 569 0.16% 99.38% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6-7 1611 0.45% 99.84% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7-8 14 0.00% 99.84% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 570 0.16% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0-1 257870 74.41% 74.41% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1-2 60023 17.32% 91.73% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2-3 23680 6.83% 98.57% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3-4 1288 0.37% 98.94% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4-5 802 0.23% 99.17% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5-6 567 0.16% 99.33% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6-7 1691 0.49% 99.82% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7-8 39 0.01% 99.83% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 576 0.17% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 355192 # Number of insts commited each cycle -system.cpu1.commit.COM:count 129556 # Number of instructions committed -system.cpu1.commit.COM:loads 30466 # Number of loads committed -system.cpu1.commit.COM:membars 8390 # Number of memory barriers committed -system.cpu1.commit.COM:refs 41763 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 346536 # Number of insts commited each cycle +system.cpu1.commit.COM:count 132317 # Number of instructions committed +system.cpu1.commit.COM:loads 32415 # Number of loads committed +system.cpu1.commit.COM:membars 5314 # Number of memory barriers committed +system.cpu1.commit.COM:refs 46218 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 30904 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 129556 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 9104 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 142883 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 104728 # Number of Instructions Simulated -system.cpu1.committedInsts_total 104728 # Number of Instructions Simulated -system.cpu1.cpi 3.839040 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 3.839040 # CPI: Total CPI of All Threads -system.cpu1.dcache.ReadReq_accesses 29199 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 17894.736842 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 15858.433735 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 29009 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 3400000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.006507 # miss rate for ReadReq accesses +system.cpu1.commit.branchMispredicts 32660 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 132317 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 6025 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 111128 # Number of Instructions Simulated +system.cpu1.committedInsts_total 111128 # Number of Instructions Simulated +system.cpu1.cpi 3.555675 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 3.555675 # CPI: Total CPI of All Threads +system.cpu1.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 28295 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 3169000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.006670 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_misses 190 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 24 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 2632500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.005685 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 166 # number of ReadReq MSHR misses -system.cpu1.dcache.SwapReq_accesses 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_avg_miss_latency 22592.592593 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 24604.651163 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_miss_latency 1220000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_rate 0.794118 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_misses 54 # number of SwapReq misses -system.cpu1.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_miss_latency 1058000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.632353 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_misses 43 # number of SwapReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 11229 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 23876.984127 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15889.908257 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 11103 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 3008500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.011221 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 126 # number of WriteReq misses +system.cpu1.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 2299000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.005441 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses +system.cpu1.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_avg_miss_latency 22773.584906 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22782.608696 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_miss_latency 1207000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_rate 0.815385 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_misses 53 # number of SwapReq misses +system.cpu1.dcache.SwapReq_mshr_hits 7 # number of SwapReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_miss_latency 1048000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.707692 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 13738 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 22585.271318 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 14535.714286 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 13609 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 2913500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.009390 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 129 # number of WriteReq misses system.cpu1.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1732000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.009707 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1628000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.008153 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 112 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 709.516129 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 810.166667 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 40428 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 20280.063291 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 15870.909091 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 40112 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 6408500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.007816 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 316 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 4364500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.006802 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 275 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_accesses 42223 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 19067.398119 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 41904 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 6082500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.007555 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 319 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 3927000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.006324 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.053563 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 27.424102 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 40428 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 20280.063291 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 15870.909091 # average overall mshr miss latency +system.cpu1.dcache.occ_%::0 0.054820 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 28.067737 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 42223 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 40112 # number of overall hits -system.cpu1.dcache.overall_miss_latency 6408500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.007816 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 316 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 41 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 4364500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.006802 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 275 # number of overall MSHR misses +system.cpu1.dcache.overall_hits 41904 # number of overall hits +system.cpu1.dcache.overall_miss_latency 6082500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.007555 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 319 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 52 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 3927000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.006324 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 27.424102 # Cycle average of tags in use -system.cpu1.dcache.total_refs 21995 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 28.067737 # Cycle average of tags in use +system.cpu1.dcache.total_refs 24305 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 31080 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:DecodedInsts 370792 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 175773 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 148188 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 35250 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:BlockedCycles 35593 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:DecodedInsts 394229 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 164873 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 145919 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 36967 # Number of cycles decode is squashing system.cpu1.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking -system.cpu1.fetch.Branches 87311 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 83559 # Number of cache lines fetched -system.cpu1.fetch.Cycles 243794 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 9908 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 428254 # Number of instructions fetch has processed -system.cpu1.fetch.SquashCycles 31054 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.217162 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 83559 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 53615 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 1.065163 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 399545 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.071854 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.991830 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.Branches 82266 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 80954 # Number of cache lines fetched +system.cpu1.fetch.Cycles 235714 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 435938 # Number of instructions fetch has processed +system.cpu1.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.208197 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 1.103263 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 392614 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.110348 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.081451 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0-1 239335 59.90% 59.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1-2 86108 21.55% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2-3 18621 4.66% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3-4 13625 3.41% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4-5 2965 0.74% 90.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5-6 17436 4.36% 94.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6-7 2130 0.53% 95.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7-8 2391 0.60% 95.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 16934 4.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0-1 237879 60.59% 60.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1-2 82939 21.12% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2-3 12394 3.16% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3-4 15941 4.06% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4-5 2706 0.69% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5-6 16830 4.29% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6-7 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7-8 2412 0.61% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 19726 5.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 399545 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses 83559 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 13800.273598 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11301.412873 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 82828 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 10088000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.008748 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 731 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 7199000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.007623 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 637 # number of ReadReq MSHR misses +system.cpu1.fetch.rateDist::total 392614 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 80218 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 10255000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.009092 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 736 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 7339500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.007893 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 639 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 130.028257 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 125.536776 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 83559 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 13800.273598 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11301.412873 # average overall mshr miss latency -system.cpu1.icache.demand_hits 82828 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 10088000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.008748 # miss rate for demand accesses -system.cpu1.icache.demand_misses 731 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 94 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 7199000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.007623 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 637 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_accesses 80954 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 13933.423913 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency +system.cpu1.icache.demand_hits 80218 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 10255000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.009092 # miss rate for demand accesses +system.cpu1.icache.demand_misses 736 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 7339500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.007893 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 639 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.183643 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 94.025224 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 83559 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 13800.273598 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11301.412873 # average overall mshr miss latency +system.cpu1.icache.occ_%::0 0.188794 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 96.662446 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 80954 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 82828 # number of overall hits -system.cpu1.icache.overall_miss_latency 10088000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.008748 # miss rate for overall accesses -system.cpu1.icache.overall_misses 731 # number of overall misses -system.cpu1.icache.overall_mshr_hits 94 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 7199000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.007623 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 637 # number of overall MSHR misses +system.cpu1.icache.overall_hits 80218 # number of overall hits +system.cpu1.icache.overall_miss_latency 10255000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.009092 # miss rate for overall accesses +system.cpu1.icache.overall_misses 736 # number of overall misses +system.cpu1.icache.overall_mshr_hits 97 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 7339500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.007893 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 639 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 525 # number of replacements -system.cpu1.icache.sampled_refs 637 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 527 # number of replacements +system.cpu1.icache.sampled_refs 639 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 94.025224 # Cycle average of tags in use -system.cpu1.icache.total_refs 82828 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 96.662446 # Cycle average of tags in use +system.cpu1.icache.total_refs 80218 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 2510 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 37542 # Number of branches executed -system.cpu1.iew.EXEC:nop 48922 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.416853 # Inst execution rate -system.cpu1.iew.EXEC:refs 49631 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 13081 # Number of stores executed +system.cpu1.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 39408 # Number of branches executed +system.cpu1.iew.EXEC:nop 47237 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.449348 # Inst execution rate +system.cpu1.iew.EXEC:refs 53769 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 15425 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 81643 # num instructions consuming a value -system.cpu1.iew.WB:count 163892 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.931911 # average fanout of values written-back +system.cpu1.iew.WB:consumers 88234 # num instructions consuming a value +system.cpu1.iew.WB:count 173934 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.937246 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 76084 # num instructions producing a value -system.cpu1.iew.WB:rate 0.407636 # insts written-back per cycle -system.cpu1.iew.WB:sent 164117 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 31560 # Number of branch mispredicts detected at execute +system.cpu1.iew.WB:producers 82697 # num instructions producing a value +system.cpu1.iew.WB:rate 0.440189 # insts written-back per cycle +system.cpu1.iew.WB:sent 174194 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute system.cpu1.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 41822 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 9263 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 4013 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 22260 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 272458 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 36550 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 35100 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 167598 # Number of executed instructions +system.cpu1.iew.iewDispLoadInsts 43341 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 11749 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 3545 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 27172 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 284714 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 38344 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 36975 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 177553 # Number of executed instructions system.cpu1.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 35250 # Number of cycles IEW is squashing +system.cpu1.iew.iewSquashCycles 36967 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 7331 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.forwLoads 9839 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 641 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 701 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 11356 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 10963 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 641 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 844 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 30716 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.260482 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.260482 # IPC: Total IPC of All Threads +system.cpu1.iew.lsq.thread.0.squashedLoads 10926 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 13369 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 701 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.281241 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.281241 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 142808 70.45% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 46141 22.76% 93.22% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 13749 6.78% 100.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 44868 20.91% 92.48% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 16122 7.52% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 202698 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.000853 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 214528 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.000867 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 23 13.29% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 11 6.36% 19.65% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 139 80.35% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 399545 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.507322 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.960841 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 392614 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.546409 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.998842 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 279804 70.03% 70.03% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 71581 17.92% 87.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 25282 6.33% 94.27% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 14650 3.67% 97.94% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 5420 1.36% 99.30% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 2146 0.54% 99.83% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 473 0.12% 99.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 157 0.04% 99.99% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 32 0.01% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 270914 69.00% 69.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 66150 16.85% 85.85% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 30383 7.74% 93.59% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 16859 4.29% 97.88% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 5420 1.38% 99.26% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 2202 0.56% 99.83% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 491 0.13% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 161 0.04% 99.99% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 399545 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.504155 # Inst issue rate -system.cpu1.iq.iqInstsAdded 205352 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 202698 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 18184 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 81269 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 9080 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 37464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.memDep0.conflictingLoads 8438 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 93 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 41822 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 22260 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 402055 # number of cpu cycles simulated -system.cpu1.rename.RENAME:CommittedMaps 87658 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IdleCycles 188598 # Number of cycles rename is idle +system.cpu1.iq.ISSUE:issued_per_cycle::total 392614 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.542923 # Inst issue rate +system.cpu1.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 214528 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 86635 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 11566 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 36678 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.memDep0.conflictingLoads 10938 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 96 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 395135 # number of cpu cycles simulated +system.cpu1.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle system.cpu1.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:RenameLookups 466261 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 302877 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 213560 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 135600 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 35250 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 564 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 125902 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 30430 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 9493 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 36017 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 9618 # count of temporary serializing insts renamed -system.cpu1.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.rename.RENAME:RenameLookups 494732 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 312015 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 231166 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 130989 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 36967 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 619 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 136540 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 34885 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 11999 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 46061 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 12120 # count of temporary serializing insts renamed +system.cpu1.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.BTBHits 44906 # Number of BTB hits -system.cpu2.BPredUnit.BTBLookups 70035 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 44089 # Number of BTB hits +system.cpu2.BPredUnit.BTBLookups 68672 # Number of BTB lookups system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu2.BPredUnit.condIncorrect 43027 # Number of conditional branches incorrect -system.cpu2.BPredUnit.condPredicted 71789 # Number of conditional branches predicted -system.cpu2.BPredUnit.lookups 71789 # Number of BP lookups +system.cpu2.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect +system.cpu2.BPredUnit.condPredicted 70853 # Number of conditional branches predicted +system.cpu2.BPredUnit.lookups 70853 # Number of BP lookups system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu2.commit.COM:branches 23667 # Number of branches committed -system.cpu2.commit.COM:bw_lim_events 171 # number cycles where commit BW limit reached +system.cpu2.commit.COM:branches 23275 # Number of branches committed +system.cpu2.commit.COM:bw_lim_events 181 # number cycles where commit BW limit reached system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.commit.COM:committed_per_cycle::samples 377940 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::mean 0.368394 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::stdev 0.672472 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::samples 371561 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::mean 0.368389 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::stdev 0.674594 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::0-1 268475 71.04% 71.04% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::1-2 84750 22.42% 93.46% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::2-3 22813 6.04% 99.50% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::3-4 683 0.18% 99.68% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::4-5 329 0.09% 99.76% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::5-6 229 0.06% 99.83% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::6-7 453 0.12% 99.94% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::7-8 37 0.01% 99.95% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::8 171 0.05% 100.00% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::0-1 264099 71.08% 71.08% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::1-2 83154 22.38% 93.46% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::2-3 22390 6.03% 99.48% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::3-4 687 0.18% 99.67% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::4-5 334 0.09% 99.76% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::5-6 230 0.06% 99.82% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::6-7 452 0.12% 99.94% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::7-8 34 0.01% 99.95% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::8 181 0.05% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::total 377940 # Number of insts commited each cycle -system.cpu2.commit.COM:count 139231 # Number of instructions committed -system.cpu2.commit.COM:loads 42546 # Number of loads committed +system.cpu2.commit.COM:committed_per_cycle::total 371561 # Number of insts commited each cycle +system.cpu2.commit.COM:count 136879 # Number of instructions committed +system.cpu2.commit.COM:loads 41762 # Number of loads committed system.cpu2.commit.COM:membars 84 # Number of memory barriers committed -system.cpu2.commit.COM:refs 64325 # Number of memory references committed +system.cpu2.commit.COM:refs 63149 # Number of memory references committed system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.branchMispredicts 43027 # The number of times a branch was mispredicted -system.cpu2.commit.commitCommittedInsts 139231 # The number of committed instructions +system.cpu2.commit.branchMispredicts 42322 # The number of times a branch was mispredicted +system.cpu2.commit.commitCommittedInsts 136879 # The number of committed instructions system.cpu2.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.commitSquashedInsts 182418 # The number of squashed insts skipped by commit -system.cpu2.committedInsts 118749 # Number of Instructions Simulated -system.cpu2.committedInsts_total 118749 # Number of Instructions Simulated -system.cpu2.cpi 3.713463 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 3.713463 # CPI: Total CPI of All Threads -system.cpu2.dcache.ReadReq_accesses 24971 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 30599.025974 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 23979.820628 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 24663 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 9424500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.012334 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 308 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_hits 85 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_miss_latency 5347500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.008930 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 223 # number of ReadReq MSHR misses +system.cpu2.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit +system.cpu2.committedInsts 116789 # Number of Instructions Simulated +system.cpu2.committedInsts_total 116789 # Number of Instructions Simulated +system.cpu2.cpi 3.716155 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 3.716155 # CPI: Total CPI of All Threads +system.cpu2.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 30305.031447 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 24347 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 9637000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.012893 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 318 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses system.cpu2.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_avg_miss_latency 15538.461538 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 12538.461538 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency 15653.846154 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 12653.846154 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu2.dcache.SwapReq_miss_latency 404000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency 407000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu2.dcache.SwapReq_mshr_miss_latency 326000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency 329000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 21737 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 45735.701906 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 39151.515152 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 21160 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 26389500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.026545 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 45805.892548 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 38962.500000 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 20768 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 26430000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.027032 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_misses 577 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_hits 379 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_miss_latency 7752000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009109 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 198 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_hits 377 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_miss_latency 7792500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs 22000 # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 168.806818 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 162.931818 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 66000 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 46708 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 40467.796610 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 31115.201900 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 45823 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 35814000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.018948 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 885 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 464 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 13099500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.009013 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 421 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_accesses 46010 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 40298.324022 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 45115 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 36067000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.019452 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 895 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 467 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 13280500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.009302 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.285109 # Average percentage of cache occupancy -system.cpu2.dcache.occ_%::1 -0.006965 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 145.975885 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -3.566137 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 46708 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 40467.796610 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 31115.201900 # average overall mshr miss latency +system.cpu2.dcache.occ_%::0 0.284939 # Average percentage of cache occupancy +system.cpu2.dcache.occ_%::1 -0.008000 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 145.888773 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -4.096255 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 46010 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 40298.324022 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 45823 # number of overall hits -system.cpu2.dcache.overall_miss_latency 35814000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.018948 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 885 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 464 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 13099500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.009013 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 421 # number of overall MSHR misses +system.cpu2.dcache.overall_hits 45115 # number of overall hits +system.cpu2.dcache.overall_miss_latency 36067000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.019452 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 895 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 467 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 13280500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.009302 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 428 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.dcache.replacements 10 # number of replacements system.cpu2.dcache.sampled_refs 176 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 142.409748 # Cycle average of tags in use -system.cpu2.dcache.total_refs 29710 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 141.792519 # Cycle average of tags in use +system.cpu2.dcache.total_refs 28676 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 6 # number of writebacks -system.cpu2.decode.DECODE:BlockedCycles 54269 # Number of cycles decode is blocked -system.cpu2.decode.DECODE:DecodedInsts 458617 # Number of instructions handled by decode -system.cpu2.decode.DECODE:IdleCycles 166605 # Number of cycles decode is idle -system.cpu2.decode.DECODE:RunCycles 156987 # Number of cycles decode is running -system.cpu2.decode.DECODE:SquashCycles 44866 # Number of cycles decode is squashing -system.cpu2.decode.DECODE:UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu2.fetch.Branches 71789 # Number of branches that fetch encountered -system.cpu2.fetch.CacheLines 88443 # Number of cache lines fetched -system.cpu2.fetch.Cycles 246728 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.IcacheSquashes 21058 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.Insts 464576 # Number of instructions fetch has processed -system.cpu2.fetch.SquashCycles 43179 # Number of cycles fetch has spent squashing -system.cpu2.fetch.branchRate 0.162798 # Number of branch fetches per cycle -system.cpu2.fetch.icacheStallCycles 88443 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.predictedBranches 44906 # Number of branches that fetch has predicted taken -system.cpu2.fetch.rate 1.053532 # Number of inst fetches per cycle -system.cpu2.fetch.rateDist::samples 422806 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.098792 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.122739 # Number of instructions fetched each cycle (Total) +system.cpu2.decode.DECODE:BlockedCycles 52836 # Number of cycles decode is blocked +system.cpu2.decode.DECODE:DecodedInsts 451840 # Number of instructions handled by decode +system.cpu2.decode.DECODE:IdleCycles 164219 # Number of cycles decode is idle +system.cpu2.decode.DECODE:RunCycles 154431 # Number of cycles decode is running +system.cpu2.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing +system.cpu2.decode.DECODE:UnblockCycles 75 # Number of cycles decode is unblocking +system.cpu2.fetch.Branches 70853 # Number of branches that fetch encountered +system.cpu2.fetch.CacheLines 87025 # Number of cache lines fetched +system.cpu2.fetch.Cycles 242792 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.IcacheSquashes 20665 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.Insts 457882 # Number of instructions fetch has processed +system.cpu2.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing +system.cpu2.fetch.branchRate 0.163254 # Number of branch fetches per cycle +system.cpu2.fetch.icacheStallCycles 87025 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken +system.cpu2.fetch.rate 1.055013 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::samples 415853 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.101067 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.125993 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0-1 264558 62.57% 62.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1-2 88255 20.87% 83.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2-3 1011 0.24% 83.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3-4 21518 5.09% 88.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4-5 1067 0.25% 89.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5-6 21230 5.02% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6-7 652 0.15% 94.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7-8 705 0.17% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 23810 5.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0-1 260123 62.55% 62.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1-2 86799 20.87% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2-3 1004 0.24% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3-4 21052 5.06% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4-5 1074 0.26% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5-6 20905 5.03% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6-7 680 0.16% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7-8 710 0.17% 94.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 23506 5.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 422806 # Number of instructions fetched each cycle (Total) -system.cpu2.icache.ReadReq_accesses 88443 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 37054.535017 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 35099.253731 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 87572 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 32274500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.009848 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 871 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_hits 201 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_miss_latency 23516500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.007576 # mshr miss rate for ReadReq accesses +system.cpu2.fetch.rateDist::total 415853 # Number of instructions fetched each cycle (Total) +system.cpu2.icache.ReadReq_accesses 87025 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 37067.241379 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 35094.029851 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 86155 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 32248500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 870 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_hits 200 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_miss_latency 23513000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.007699 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_misses 670 # number of ReadReq MSHR misses system.cpu2.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 130.899851 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 128.781764 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 88443 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 37054.535017 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 35099.253731 # average overall mshr miss latency -system.cpu2.icache.demand_hits 87572 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 32274500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.009848 # miss rate for demand accesses -system.cpu2.icache.demand_misses 871 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 201 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 23516500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.007576 # mshr miss rate for demand accesses +system.cpu2.icache.demand_accesses 87025 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 37067.241379 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency +system.cpu2.icache.demand_hits 86155 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 32248500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.009997 # miss rate for demand accesses +system.cpu2.icache.demand_misses 870 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 200 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 23513000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.007699 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_misses 670 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.526897 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 269.771036 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 88443 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 37054.535017 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 35099.253731 # average overall mshr miss latency +system.cpu2.icache.occ_%::0 0.526442 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 269.538121 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 87025 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 37067.241379 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 87572 # number of overall hits -system.cpu2.icache.overall_miss_latency 32274500 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.009848 # miss rate for overall accesses -system.cpu2.icache.overall_misses 871 # number of overall misses -system.cpu2.icache.overall_mshr_hits 201 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 23516500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.007576 # mshr miss rate for overall accesses +system.cpu2.icache.overall_hits 86155 # number of overall hits +system.cpu2.icache.overall_miss_latency 32248500 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.009997 # miss rate for overall accesses +system.cpu2.icache.overall_misses 870 # number of overall misses +system.cpu2.icache.overall_mshr_hits 200 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 23513000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.007699 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_misses 670 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.icache.replacements 363 # number of replacements system.cpu2.icache.sampled_refs 669 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 269.771036 # Cycle average of tags in use -system.cpu2.icache.total_refs 87572 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 269.538121 # Cycle average of tags in use +system.cpu2.icache.total_refs 86155 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idleCycles 18164 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.iew.EXEC:branches 45174 # Number of branches executed -system.cpu2.iew.EXEC:nop 60963 # number of nop insts executed -system.cpu2.iew.EXEC:rate 0.434102 # Inst execution rate -system.cpu2.iew.EXEC:refs 67735 # number of memory reference insts executed -system.cpu2.iew.EXEC:stores 22705 # Number of stores executed +system.cpu2.idleCycles 18153 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.iew.EXEC:branches 44503 # Number of branches executed +system.cpu2.iew.EXEC:nop 59775 # number of nop insts executed +system.cpu2.iew.EXEC:rate 0.434987 # Inst execution rate +system.cpu2.iew.EXEC:refs 66647 # number of memory reference insts executed +system.cpu2.iew.EXEC:stores 22312 # Number of stores executed system.cpu2.iew.EXEC:swp 0 # number of swp insts executed -system.cpu2.iew.WB:consumers 96501 # num instructions consuming a value -system.cpu2.iew.WB:count 189859 # cumulative count of insts written-back -system.cpu2.iew.WB:fanout 0.973959 # average fanout of values written-back +system.cpu2.iew.WB:consumers 95172 # num instructions consuming a value +system.cpu2.iew.WB:count 187212 # cumulative count of insts written-back +system.cpu2.iew.WB:fanout 0.972912 # average fanout of values written-back system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.iew.WB:producers 93988 # num instructions producing a value -system.cpu2.iew.WB:rate 0.430549 # insts written-back per cycle -system.cpu2.iew.WB:sent 190138 # cumulative count of insts sent to commit -system.cpu2.iew.branchMispredicts 43334 # Number of branch mispredicts detected at execute +system.cpu2.iew.WB:producers 92594 # num instructions producing a value +system.cpu2.iew.WB:rate 0.431358 # insts written-back per cycle +system.cpu2.iew.WB:sent 187507 # cumulative count of insts sent to commit +system.cpu2.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute system.cpu2.iew.iewBlockCycles 24 # Number of cycles IEW is blocking -system.cpu2.iew.iewDispLoadInsts 46475 # Number of dispatched load instructions -system.cpu2.iew.iewDispNonSpecInsts 21048 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewDispSquashedInsts 2818 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispStoreInsts 43788 # Number of dispatched store instructions -system.cpu2.iew.iewDispatchedInsts 321686 # Number of instructions dispatched to IQ -system.cpu2.iew.iewExecLoadInsts 45030 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 43684 # Number of squashed instructions skipped in execute -system.cpu2.iew.iewExecutedInsts 191426 # Number of executed instructions +system.cpu2.iew.iewDispLoadInsts 45739 # Number of dispatched load instructions +system.cpu2.iew.iewDispNonSpecInsts 20652 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewDispSquashedInsts 2935 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispStoreInsts 43021 # Number of dispatched store instructions +system.cpu2.iew.iewDispatchedInsts 316777 # Number of instructions dispatched to IQ +system.cpu2.iew.iewExecLoadInsts 44335 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 42979 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecutedInsts 188787 # Number of executed instructions system.cpu2.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.iewSquashCycles 44866 # Number of cycles IEW is squashing +system.cpu2.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing system.cpu2.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.lsq.thread.0.forwLoads 19969 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.memOrderViolation 186 # Number of memory ordering violations +system.cpu2.iew.lsq.thread.0.memOrderViolation 197 # Number of memory ordering violations system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread.0.squashedLoads 3929 # Number of loads squashed -system.cpu2.iew.lsq.thread.0.squashedStores 22009 # Number of stores squashed -system.cpu2.iew.memOrderViolationEvents 186 # Number of memory order violations -system.cpu2.iew.predictedNotTakenIncorrect 868 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.predictedTakenIncorrect 42466 # Number of branches that were predicted taken incorrectly -system.cpu2.ipc 0.269290 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.269290 # IPC: Total IPC of All Threads +system.cpu2.iew.lsq.thread.0.squashedLoads 3977 # Number of loads squashed +system.cpu2.iew.lsq.thread.0.squashedStores 21634 # Number of stores squashed +system.cpu2.iew.memOrderViolationEvents 197 # Number of memory order violations +system.cpu2.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly +system.cpu2.ipc 0.269095 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.269095 # IPC: Total IPC of All Threads system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntAlu 166509 70.82% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemRead 45663 19.42% 90.24% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemWrite 22938 9.76% 100.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemRead 44972 19.40% 90.27% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemWrite 22555 9.73% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::total 235110 # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::total 231766 # Type of FU issued system.cpu2.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested -system.cpu2.iq.ISSUE:fu_busy_rate 0.000566 # FU busy rate (busy events/executed inst) +system.cpu2.iq.ISSUE:fu_busy_rate 0.000574 # FU busy rate (busy events/executed inst) system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IntAlu 38 28.57% 28.57% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 28.57% # attempts to use FU when none available @@ -952,576 +951,577 @@ system.cpu2.iq.ISSUE:fu_full::MemRead 27 20.30% 48.87% # at system.cpu2.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:issued_per_cycle::samples 422806 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.556071 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.945329 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::samples 415853 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.557327 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.948090 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::0-1 286677 67.80% 67.80% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::1-2 67298 15.92% 83.72% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::2-3 43645 10.32% 94.04% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::3-4 22116 5.23% 99.27% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::4-5 1740 0.41% 99.69% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::5-6 920 0.22% 99.90% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::6-7 282 0.07% 99.97% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::7-8 102 0.02% 99.99% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::0-1 281858 67.78% 67.78% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::1-2 66212 15.92% 83.70% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::2-3 42876 10.31% 94.01% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::3-4 21783 5.24% 99.25% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::4-5 1770 0.43% 99.67% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::5-6 926 0.22% 99.90% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::6-7 279 0.07% 99.96% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::7-8 123 0.03% 99.99% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::total 422806 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:rate 0.533166 # Inst issue rate -system.cpu2.iq.iqInstsAdded 239551 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqInstsIssued 235110 # Number of instructions issued -system.cpu2.iq.iqNonSpecInstsAdded 21172 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqSquashedInstsExamined 99184 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedNonSpecRemoved 20613 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.iqSquashedOperandsExamined 15669 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.memDep0.conflictingLoads 20136 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 109 # Number of conflicting stores. -system.cpu2.memDep0.insertedLoads 46475 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 43788 # Number of stores inserted to the mem dependence unit. -system.cpu2.numCycles 440970 # number of cpu cycles simulated +system.cpu2.iq.ISSUE:issued_per_cycle::total 415853 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:rate 0.534016 # Inst issue rate +system.cpu2.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqInstsIssued 231766 # Number of instructions issued +system.cpu2.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqSquashedInstsExamined 98225 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.memDep0.conflictingLoads 19721 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 107 # Number of conflicting stores. +system.cpu2.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit. +system.cpu2.numCycles 434006 # number of cpu cycles simulated system.cpu2.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking -system.cpu2.rename.RENAME:CommittedMaps 97924 # Number of HB maps that are committed -system.cpu2.rename.RENAME:IdleCycles 188399 # Number of cycles rename is idle +system.cpu2.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed +system.cpu2.rename.RENAME:IdleCycles 185616 # Number of cycles rename is idle system.cpu2.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RENAME:RenameLookups 512581 # Number of register rename lookups that rename has made -system.cpu2.rename.RENAME:RenamedInsts 328892 # Number of instructions processed by rename -system.cpu2.rename.RENAME:RenamedOperands 245007 # Number of destination operands rename has renamed -system.cpu2.rename.RENAME:RunCycles 135302 # Number of cycles rename is running -system.cpu2.rename.RENAME:SquashCycles 44866 # Number of cycles rename is squashing -system.cpu2.rename.RENAME:UnblockCycles 350 # Number of cycles rename is unblocking -system.cpu2.rename.RENAME:UndoneMaps 147083 # Number of HB maps that are undone due to squashing -system.cpu2.rename.RENAME:serializeStallCycles 53857 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RENAME:serializingInsts 21162 # count of serializing insts renamed -system.cpu2.rename.RENAME:skidInsts 84753 # count of insts added to the skid buffer -system.cpu2.rename.RENAME:tempSerializingInsts 21158 # count of temporary serializing insts renamed +system.cpu2.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made +system.cpu2.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename +system.cpu2.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed +system.cpu2.rename.RENAME:RunCycles 133139 # Number of cycles rename is running +system.cpu2.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing +system.cpu2.rename.RENAME:UnblockCycles 355 # Number of cycles rename is unblocking +system.cpu2.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing +system.cpu2.rename.RENAME:serializeStallCycles 52419 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed +system.cpu2.rename.RENAME:skidInsts 83231 # count of insts added to the skid buffer +system.cpu2.rename.RENAME:tempSerializingInsts 20770 # count of temporary serializing insts renamed system.cpu2.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.BTBHits 51243 # Number of BTB hits -system.cpu3.BPredUnit.BTBLookups 69683 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 53713 # Number of BTB hits +system.cpu3.BPredUnit.BTBLookups 65870 # Number of BTB lookups system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu3.BPredUnit.condIncorrect 32692 # Number of conditional branches incorrect -system.cpu3.BPredUnit.condPredicted 78569 # Number of conditional branches predicted -system.cpu3.BPredUnit.lookups 78569 # Number of BP lookups +system.cpu3.BPredUnit.condIncorrect 29792 # Number of conditional branches incorrect +system.cpu3.BPredUnit.condPredicted 83669 # Number of conditional branches predicted +system.cpu3.BPredUnit.lookups 83669 # Number of BP lookups system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu3.commit.COM:branches 25257 # Number of branches committed -system.cpu3.commit.COM:bw_lim_events 568 # number cycles where commit BW limit reached +system.cpu3.commit.COM:branches 25470 # Number of branches committed +system.cpu3.commit.COM:bw_lim_events 577 # number cycles where commit BW limit reached system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.commit.COM:committed_per_cycle::samples 351415 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::mean 0.376558 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::stdev 0.826419 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::samples 350132 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::mean 0.363609 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::stdev 0.831936 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::0-1 262526 74.71% 74.71% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::1-2 59947 17.06% 91.76% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::2-3 24097 6.86% 98.62% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::3-4 1297 0.37% 98.99% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::4-5 787 0.22% 99.21% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::5-6 568 0.16% 99.38% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::6-7 1611 0.46% 99.83% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::7-8 14 0.00% 99.84% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::8 568 0.16% 100.00% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::0-1 266836 76.21% 76.21% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::1-2 54270 15.50% 91.71% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::2-3 24066 6.87% 98.58% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::3-4 1288 0.37% 98.95% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::4-5 810 0.23% 99.18% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::5-6 561 0.16% 99.34% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::6-7 1684 0.48% 99.82% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::7-8 40 0.01% 99.84% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::8 577 0.16% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::total 351415 # Number of insts commited each cycle -system.cpu3.commit.COM:count 132328 # Number of instructions committed -system.cpu3.commit.COM:loads 32245 # Number of loads committed -system.cpu3.commit.COM:membars 5830 # Number of memory barriers committed -system.cpu3.commit.COM:refs 45707 # Number of memory references committed +system.cpu3.commit.COM:committed_per_cycle::total 350132 # Number of insts commited each cycle +system.cpu3.commit.COM:count 127311 # Number of instructions committed +system.cpu3.commit.COM:loads 29520 # Number of loads committed +system.cpu3.commit.COM:membars 8970 # Number of memory barriers committed +system.cpu3.commit.COM:refs 40059 # Number of memory references committed system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.branchMispredicts 32692 # The number of times a branch was mispredicted -system.cpu3.commit.commitCommittedInsts 132328 # The number of committed instructions -system.cpu3.commit.commitNonSpecStalls 6543 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.commitSquashedInsts 149632 # The number of squashed insts skipped by commit -system.cpu3.committedInsts 110450 # Number of Instructions Simulated -system.cpu3.committedInsts_total 110450 # Number of Instructions Simulated -system.cpu3.cpi 3.645957 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 3.645957 # CPI: Total CPI of All Threads -system.cpu3.dcache.ReadReq_accesses 28797 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 19788.770053 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 16721.212121 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 28610 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 3700500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.006494 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 187 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_miss_latency 2759000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.005730 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses -system.cpu3.dcache.SwapReq_accesses 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_avg_miss_latency 21918.181818 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22138.297872 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_miss_latency 1205500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_rate 0.820896 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_misses 55 # number of SwapReq misses -system.cpu3.dcache.SwapReq_mshr_hits 8 # number of SwapReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_miss_latency 1040500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.701493 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_misses 47 # number of SwapReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 13395 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 23007.751938 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14729.729730 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 13266 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 2968000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.009630 # miss rate for WriteReq accesses +system.cpu3.commit.branchMispredicts 29792 # The number of times a branch was mispredicted +system.cpu3.commit.commitCommittedInsts 127311 # The number of committed instructions +system.cpu3.commit.commitNonSpecStalls 9688 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit +system.cpu3.committedInsts 102085 # Number of Instructions Simulated +system.cpu3.committedInsts_total 102085 # Number of Instructions Simulated +system.cpu3.cpi 3.876926 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 3.876926 # CPI: Total CPI of All Threads +system.cpu3.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 28662 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 3852000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.007067 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 204 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_miss_latency 2921500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.006062 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_avg_miss_latency 22155.172414 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 24152.173913 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_miss_latency 1285000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_mshr_hits 12 # number of SwapReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_miss_latency 1111000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.638889 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 10467 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 23593.023256 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15414.414414 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 10338 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 3043500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.012324 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_misses 129 # number of WriteReq misses system.cpu3.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_miss_latency 1635000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.008287 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_latency 1711000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.010605 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_misses 111 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 804.066667 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 701.333333 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 42192 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 21102.848101 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 15920.289855 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 41876 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 6668500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.007490 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 316 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 4394000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.006542 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 276 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_accesses 39333 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 20707.207207 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 39000 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 6895500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.008466 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 333 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 4632500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.007271 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 286 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.056978 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 29.172631 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 42192 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 21102.848101 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 15920.289855 # average overall mshr miss latency +system.cpu3.dcache.occ_%::0 0.053188 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 27.232391 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 39333 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 41876 # number of overall hits -system.cpu3.dcache.overall_miss_latency 6668500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.007490 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 316 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 40 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 4394000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.006542 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 276 # number of overall MSHR misses +system.cpu3.dcache.overall_hits 39000 # number of overall hits +system.cpu3.dcache.overall_miss_latency 6895500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.008466 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 333 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 47 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 4632500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.007271 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 286 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 29.172631 # Cycle average of tags in use -system.cpu3.dcache.total_refs 24122 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 27.232391 # Cycle average of tags in use +system.cpu3.dcache.total_refs 21040 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.decode.DECODE:BlockedCycles 35128 # Number of cycles decode is blocked -system.cpu3.decode.DECODE:DecodedInsts 388171 # Number of instructions handled by decode -system.cpu3.decode.DECODE:IdleCycles 168108 # Number of cycles decode is idle -system.cpu3.decode.DECODE:RunCycles 148027 # Number of cycles decode is running -system.cpu3.decode.DECODE:SquashCycles 36551 # Number of cycles decode is squashing -system.cpu3.decode.DECODE:UnblockCycles 152 # Number of cycles decode is unblocking -system.cpu3.fetch.Branches 78569 # Number of branches that fetch encountered -system.cpu3.fetch.CacheLines 81998 # Number of cache lines fetched -system.cpu3.fetch.Cycles 239499 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.IcacheSquashes 12083 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.Insts 427102 # Number of instructions fetch has processed -system.cpu3.fetch.SquashCycles 32841 # Number of cycles fetch has spent squashing -system.cpu3.fetch.branchRate 0.195107 # Number of branch fetches per cycle -system.cpu3.fetch.icacheStallCycles 81998 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.predictedBranches 51243 # Number of branches that fetch has predicted taken -system.cpu3.fetch.rate 1.060607 # Number of inst fetches per cycle -system.cpu3.fetch.rateDist::samples 397135 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.075458 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.013935 # Number of instructions fetched each cycle (Total) +system.cpu3.decode.DECODE:BlockedCycles 30059 # Number of cycles decode is blocked +system.cpu3.decode.DECODE:DecodedInsts 353088 # Number of instructions handled by decode +system.cpu3.decode.DECODE:IdleCycles 174967 # Number of cycles decode is idle +system.cpu3.decode.DECODE:RunCycles 144955 # Number of cycles decode is running +system.cpu3.decode.DECODE:SquashCycles 33628 # Number of cycles decode is squashing +system.cpu3.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking +system.cpu3.fetch.Branches 83669 # Number of branches that fetch encountered +system.cpu3.fetch.CacheLines 82467 # Number of cache lines fetched +system.cpu3.fetch.Cycles 239936 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.Insts 410532 # Number of instructions fetch has processed +system.cpu3.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing +system.cpu3.fetch.branchRate 0.211405 # Number of branch fetches per cycle +system.cpu3.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken +system.cpu3.fetch.rate 1.037284 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::samples 392867 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.044964 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 1.945559 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0-1 239656 60.35% 60.35% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1-2 85048 21.42% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2-3 14012 3.53% 85.29% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3-4 17951 4.52% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4-5 2990 0.75% 90.56% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5-6 15291 3.85% 94.41% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6-7 1676 0.42% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7-8 2382 0.60% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 18129 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0-1 235421 59.92% 59.92% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1-2 84908 21.61% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2-3 20175 5.14% 86.67% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3-4 13313 3.39% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4-5 2697 0.69% 90.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5-6 17066 4.34% 95.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6-7 1329 0.34% 95.43% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7-8 2421 0.62% 96.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 15537 3.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 397135 # Number of instructions fetched each cycle (Total) -system.cpu3.icache.ReadReq_accesses 81998 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 19529.880478 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 16592.417062 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 81245 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 14706000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.009183 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 753 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_miss_latency 10503000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.007720 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_misses 633 # number of ReadReq MSHR misses -system.cpu3.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked +system.cpu3.fetch.rateDist::total 392867 # Number of instructions fetched each cycle (Total) +system.cpu3.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 81734 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 10621000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.008888 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 733 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.007712 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 636 # number of ReadReq MSHR misses +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 128.349131 # Average number of references to valid blocks. -system.cpu3.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu3.icache.avg_refs 128.512579 # Average number of references to valid blocks. +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 81998 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 19529.880478 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 16592.417062 # average overall mshr miss latency -system.cpu3.icache.demand_hits 81245 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 14706000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.009183 # miss rate for demand accesses -system.cpu3.icache.demand_misses 753 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 10503000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.007720 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 633 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_accesses 82467 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 14489.768076 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency +system.cpu3.icache.demand_hits 81734 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 10621000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.008888 # miss rate for demand accesses +system.cpu3.icache.demand_misses 733 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 7591000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.007712 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 636 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.192956 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 98.793514 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 81998 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 19529.880478 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 16592.417062 # average overall mshr miss latency +system.cpu3.icache.occ_%::0 0.182938 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 93.664377 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 82467 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 81245 # number of overall hits -system.cpu3.icache.overall_miss_latency 14706000 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.009183 # miss rate for overall accesses -system.cpu3.icache.overall_misses 753 # number of overall misses -system.cpu3.icache.overall_mshr_hits 120 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 10503000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.007720 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 633 # number of overall MSHR misses +system.cpu3.icache.overall_hits 81734 # number of overall hits +system.cpu3.icache.overall_miss_latency 10621000 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.008888 # miss rate for overall accesses +system.cpu3.icache.overall_misses 733 # number of overall misses +system.cpu3.icache.overall_mshr_hits 97 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 7591000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.007712 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 636 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 522 # number of replacements -system.cpu3.icache.sampled_refs 633 # Sample count of references to valid blocks. +system.cpu3.icache.replacements 524 # number of replacements +system.cpu3.icache.sampled_refs 636 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 98.793514 # Cycle average of tags in use -system.cpu3.icache.total_refs 81245 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 93.664377 # Cycle average of tags in use +system.cpu3.icache.total_refs 81734 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idleCycles 5561 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.iew.EXEC:branches 39289 # Number of branches executed -system.cpu3.iew.EXEC:nop 47300 # number of nop insts executed -system.cpu3.iew.EXEC:rate 0.440007 # Inst execution rate -system.cpu3.iew.EXEC:refs 53548 # number of memory reference insts executed -system.cpu3.iew.EXEC:stores 15235 # Number of stores executed +system.cpu3.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.iew.EXEC:branches 36547 # Number of branches executed +system.cpu3.iew.EXEC:nop 47873 # number of nop insts executed +system.cpu3.iew.EXEC:rate 0.410224 # Inst execution rate +system.cpu3.iew.EXEC:refs 47615 # number of memory reference insts executed +system.cpu3.iew.EXEC:stores 12164 # Number of stores executed system.cpu3.iew.EXEC:swp 0 # number of swp insts executed -system.cpu3.iew.WB:consumers 87751 # num instructions consuming a value -system.cpu3.iew.WB:count 173492 # cumulative count of insts written-back -system.cpu3.iew.WB:fanout 0.936696 # average fanout of values written-back +system.cpu3.iew.WB:consumers 78764 # num instructions consuming a value +system.cpu3.iew.WB:count 158732 # cumulative count of insts written-back +system.cpu3.iew.WB:fanout 0.929676 # average fanout of values written-back system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.iew.WB:producers 82196 # num instructions producing a value -system.cpu3.iew.WB:rate 0.430826 # insts written-back per cycle -system.cpu3.iew.WB:sent 173712 # cumulative count of insts sent to commit -system.cpu3.iew.branchMispredicts 33345 # Number of branch mispredicts detected at execute +system.cpu3.iew.WB:producers 73225 # num instructions producing a value +system.cpu3.iew.WB:rate 0.401065 # insts written-back per cycle +system.cpu3.iew.WB:sent 158983 # cumulative count of insts sent to commit +system.cpu3.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute system.cpu3.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu3.iew.iewDispLoadInsts 42639 # Number of dispatched load instructions -system.cpu3.iew.iewDispNonSpecInsts 11434 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewDispSquashedInsts 4085 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispStoreInsts 26562 # Number of dispatched store instructions -system.cpu3.iew.iewDispatchedInsts 281979 # Number of instructions dispatched to IQ -system.cpu3.iew.iewExecLoadInsts 38313 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 36396 # Number of squashed instructions skipped in execute -system.cpu3.iew.iewExecutedInsts 177189 # Number of executed instructions +system.cpu3.iew.iewDispLoadInsts 39543 # Number of dispatched load instructions +system.cpu3.iew.iewDispNonSpecInsts 8501 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewDispSquashedInsts 3508 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispStoreInsts 20654 # Number of dispatched store instructions +system.cpu3.iew.iewDispatchedInsts 261662 # Number of instructions dispatched to IQ +system.cpu3.iew.iewExecLoadInsts 35451 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 33572 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecutedInsts 162357 # Number of executed instructions system.cpu3.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.iewSquashCycles 36551 # Number of cycles IEW is squashing +system.cpu3.iew.iewSquashCycles 33628 # Number of cycles IEW is squashing system.cpu3.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.lsq.thread.0.forwLoads 9499 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread.0.forwLoads 6568 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.memOrderViolation 639 # Number of memory ordering violations +system.cpu3.iew.lsq.thread.0.memOrderViolation 694 # Number of memory ordering violations system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread.0.squashedLoads 10394 # Number of loads squashed -system.cpu3.iew.lsq.thread.0.squashedStores 13100 # Number of stores squashed -system.cpu3.iew.memOrderViolationEvents 639 # Number of memory order violations -system.cpu3.iew.predictedNotTakenIncorrect 830 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.predictedTakenIncorrect 32515 # Number of branches that were predicted taken incorrectly -system.cpu3.ipc 0.274276 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.274276 # IPC: Total IPC of All Threads +system.cpu3.iew.lsq.thread.0.squashedLoads 10023 # Number of loads squashed +system.cpu3.iew.lsq.thread.0.squashedStores 10115 # Number of stores squashed +system.cpu3.iew.memOrderViolationEvents 694 # Number of memory order violations +system.cpu3.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly +system.cpu3.ipc 0.257936 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.257936 # IPC: Total IPC of All Threads system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntAlu 152352 71.33% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemRead 45332 21.22% 92.56% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemWrite 15901 7.44% 100.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemRead 45623 23.29% 93.43% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemWrite 12865 6.57% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::total 213585 # Type of FU issued -system.cpu3.iq.ISSUE:fu_busy_cnt 168 # FU busy when requested -system.cpu3.iq.ISSUE:fu_busy_rate 0.000787 # FU busy rate (busy events/executed inst) +system.cpu3.iq.ISSUE:FU_type_0::total 195929 # Type of FU issued +system.cpu3.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested +system.cpu3.iq.ISSUE:fu_busy_rate 0.000949 # FU busy rate (busy events/executed inst) system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntAlu 18 10.71% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemRead 11 6.55% 17.26% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemWrite 139 82.74% 100.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:issued_per_cycle::samples 397135 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.537815 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.988033 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::samples 392867 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.498716 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.955880 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::0-1 274584 69.14% 69.14% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::1-2 68377 17.22% 86.36% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::2-3 29162 7.34% 93.70% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::3-4 16815 4.23% 97.94% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::4-5 5405 1.36% 99.30% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::5-6 2141 0.54% 99.84% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::6-7 468 0.12% 99.95% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::7-8 158 0.04% 99.99% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::8 25 0.01% 100.00% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::0-1 276221 70.31% 70.31% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::1-2 71375 18.17% 88.48% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::2-3 23368 5.95% 94.42% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::3-4 13587 3.46% 97.88% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::4-5 5437 1.38% 99.27% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::5-6 2194 0.56% 99.83% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::6-7 490 0.12% 99.95% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::7-8 161 0.04% 99.99% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::total 397135 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:rate 0.530388 # Inst issue rate -system.cpu3.iq.iqInstsAdded 217367 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqInstsIssued 213585 # Number of instructions issued -system.cpu3.iq.iqNonSpecInstsAdded 17312 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqSquashedInstsExamined 84893 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedNonSpecRemoved 10769 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.iqSquashedOperandsExamined 34030 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.memDep0.conflictingLoads 9667 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 80 # Number of conflicting stores. -system.cpu3.memDep0.insertedLoads 42639 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 26562 # Number of stores inserted to the mem dependence unit. -system.cpu3.numCycles 402696 # number of cpu cycles simulated -system.cpu3.rename.RENAME:CommittedMaps 93774 # Number of HB maps that are committed -system.cpu3.rename.RENAME:IdleCycles 183092 # Number of cycles rename is idle -system.cpu3.rename.RENAME:RenameLookups 489966 # Number of register rename lookups that rename has made -system.cpu3.rename.RENAME:RenamedInsts 307555 # Number of instructions processed by rename -system.cpu3.rename.RENAME:RenamedOperands 229124 # Number of destination operands rename has renamed -system.cpu3.rename.RENAME:RunCycles 133281 # Number of cycles rename is running -system.cpu3.rename.RENAME:SquashCycles 36551 # Number of cycles rename is squashing -system.cpu3.rename.RENAME:UnblockCycles 561 # Number of cycles rename is unblocking -system.cpu3.rename.RENAME:UndoneMaps 135350 # Number of HB maps that are undone due to squashing -system.cpu3.rename.RENAME:serializeStallCycles 34481 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RENAME:serializingInsts 11653 # count of serializing insts renamed -system.cpu3.rename.RENAME:skidInsts 44534 # count of insts added to the skid buffer -system.cpu3.rename.RENAME:tempSerializingInsts 11782 # count of temporary serializing insts renamed -system.cpu3.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses) +system.cpu3.iq.ISSUE:issued_per_cycle::total 392867 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:rate 0.495050 # Inst issue rate +system.cpu3.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqInstsIssued 195929 # Number of instructions issued +system.cpu3.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqSquashedInstsExamined 74909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedNonSpecRemoved 7843 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.iqSquashedOperandsExamined 33478 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.memDep0.conflictingLoads 6760 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 87 # Number of conflicting stores. +system.cpu3.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit. +system.cpu3.numCycles 395776 # number of cpu cycles simulated +system.cpu3.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed +system.cpu3.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle +system.cpu3.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RENAME:RenameLookups 447878 # Number of register rename lookups that rename has made +system.cpu3.rename.RENAME:RenamedInsts 290237 # Number of instructions processed by rename +system.cpu3.rename.RENAME:RenamedOperands 204758 # Number of destination operands rename has renamed +system.cpu3.rename.RENAME:RunCycles 133245 # Number of cycles rename is running +system.cpu3.rename.RENAME:SquashCycles 33628 # Number of cycles rename is squashing +system.cpu3.rename.RENAME:UnblockCycles 630 # Number of cycles rename is unblocking +system.cpu3.rename.RENAME:UndoneMaps 119564 # Number of HB maps that are undone due to squashing +system.cpu3.rename.RENAME:serializeStallCycles 29341 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RENAME:serializingInsts 8772 # count of serializing insts renamed +system.cpu3.rename.RENAME:skidInsts 33179 # count of insts added to the skid buffer +system.cpu3.rename.RENAME:tempSerializingInsts 8900 # count of temporary serializing insts renamed +system.cpu3.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.l2c.ReadExReq_accesses::0 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 572875 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 572875 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 73132.978723 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 528807.692308 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1747690.671031 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40316.793893 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 6874500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_miss_latency::0 528730.769231 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 572791.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 73122.340426 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 572791.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1747436.442990 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40312.977099 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 6873500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::0 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::2 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5281500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 10.916667 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_latency 5281000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 10.076923 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 1.393617 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 10.076923 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 649 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::0 646 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 653 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::2 752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 647 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2699 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 4142500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 7249375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 63451.859956 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 325814.606742 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 11781141.466698 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39997.282609 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits::0 642 # number of ReadReq hits +system.l2c.ReadReq_accesses::3 650 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2701 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 362318.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 4830916.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 63425.601751 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 2229653.846154 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 7486314.864571 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits::0 566 # number of ReadReq hits system.l2c.ReadReq_hits::1 647 # number of ReadReq hits system.l2c.ReadReq_hits::2 295 # number of ReadReq hits -system.l2c.ReadReq_hits::3 558 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2142 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 28997500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.010786 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.006144 # miss rate for ReadReq accesses +system.l2c.ReadReq_hits::3 637 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2145 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 28985500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.123839 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.009188 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::2 0.607713 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.137558 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.762201 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 7 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::3 0.020000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.760740 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 80 # number of ReadReq misses +system.l2c.ReadReq_misses::1 6 # number of ReadReq misses system.l2c.ReadReq_misses::2 457 # number of ReadReq misses -system.l2c.ReadReq_misses::3 89 # number of ReadReq misses -system.l2c.ReadReq_misses::total 557 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 22078500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.850539 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.847926 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_misses::3 13 # number of ReadReq misses +system.l2c.ReadReq_misses::total 556 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 22080000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.854489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.845329 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 0.734043 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 0.853168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.285677 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 0.849231 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.283092 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 552 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses::0 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 52 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 53 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::3 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 114 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 68894.736842 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::total 117 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 62333.333333 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 59500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 25173.076923 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 24698.113208 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::3 62333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 215901.147099 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40039.473684 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 208864.779874 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40038.461538 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 1309000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::0 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 52 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 53 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::3 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 114 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 4564500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 6 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 5.181818 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 2.192308 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 5.428571 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 18.802697 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 114 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses::total 117 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 4684500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 5.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 5.318182 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 2.207547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 5.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 18.668586 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 3.998131 # Average number of references to valid blocks. +system.l2c.avg_refs 4.003738 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 661 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 663 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 659 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 665 # number of demand (read+write) accesses system.l2c.demand_accesses::2 846 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 660 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2830 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 1888000 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 2242000 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 65103.448276 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 351686.274510 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 4546789.722786 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40058.565154 # average overall mshr miss latency -system.l2c.demand_hits::0 642 # number of demand (read+write) hits +system.l2c.demand_accesses::3 662 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2832 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 385580.645161 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1992166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 65079.854809 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1434360 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3877187.166637 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency +system.l2c.demand_hits::0 566 # number of demand (read+write) hits system.l2c.demand_hits::1 647 # number of demand (read+write) hits system.l2c.demand_hits::2 295 # number of demand (read+write) hits -system.l2c.demand_hits::3 558 # number of demand (read+write) hits -system.l2c.demand_hits::total 2142 # number of demand (read+write) hits -system.l2c.demand_miss_latency 35872000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.028744 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.024133 # miss rate for demand accesses +system.l2c.demand_hits::3 637 # number of demand (read+write) hits +system.l2c.demand_hits::total 2145 # number of demand (read+write) hits +system.l2c.demand_miss_latency 35859000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.141123 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.027068 # miss rate for demand accesses system.l2c.demand_miss_rate::2 0.651300 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.154545 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.858723 # miss rate for demand accesses -system.l2c.demand_misses::0 19 # number of demand (read+write) misses -system.l2c.demand_misses::1 16 # number of demand (read+write) misses +system.l2c.demand_miss_rate::3 0.037764 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.857255 # miss rate for demand accesses +system.l2c.demand_misses::0 93 # number of demand (read+write) misses +system.l2c.demand_misses::1 18 # number of demand (read+write) misses system.l2c.demand_misses::2 551 # number of demand (read+write) misses -system.l2c.demand_misses::3 102 # number of demand (read+write) misses -system.l2c.demand_misses::total 688 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 27360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 1.033283 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.030166 # mshr miss rate for demand accesses +system.l2c.demand_misses::3 25 # number of demand (read+write) misses +system.l2c.demand_misses::total 687 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 27361000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 1.036419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.027068 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 0.807329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.034848 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 3.905626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.031722 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 3.902537 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 683 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.000042 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.000041 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.005574 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.001194 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.000088 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 2.720574 # Average occupied blocks per context -system.l2c.occ_blocks::1 2.658049 # Average occupied blocks per context -system.l2c.occ_blocks::2 365.307630 # Average occupied blocks per context -system.l2c.occ_blocks::3 78.263554 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.734616 # Average occupied blocks per context -system.l2c.overall_accesses::0 661 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 663 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.001067 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000056 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.005570 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000152 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000091 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 69.921003 # Average occupied blocks per context +system.l2c.occ_blocks::1 3.643564 # Average occupied blocks per context +system.l2c.occ_blocks::2 365.031703 # Average occupied blocks per context +system.l2c.occ_blocks::3 9.942146 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.939892 # Average occupied blocks per context +system.l2c.overall_accesses::0 659 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 665 # number of overall (read+write) accesses system.l2c.overall_accesses::2 846 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 660 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2830 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 1888000 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 2242000 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 65103.448276 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 351686.274510 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 4546789.722786 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40058.565154 # average overall mshr miss latency +system.l2c.overall_accesses::3 662 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2832 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 385580.645161 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1992166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 65079.854809 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1434360 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3877187.166637 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 642 # number of overall hits +system.l2c.overall_hits::0 566 # number of overall hits system.l2c.overall_hits::1 647 # number of overall hits system.l2c.overall_hits::2 295 # number of overall hits -system.l2c.overall_hits::3 558 # number of overall hits -system.l2c.overall_hits::total 2142 # number of overall hits -system.l2c.overall_miss_latency 35872000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.028744 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.024133 # miss rate for overall accesses +system.l2c.overall_hits::3 637 # number of overall hits +system.l2c.overall_hits::total 2145 # number of overall hits +system.l2c.overall_miss_latency 35859000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.141123 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.027068 # miss rate for overall accesses system.l2c.overall_miss_rate::2 0.651300 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.154545 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.858723 # miss rate for overall accesses -system.l2c.overall_misses::0 19 # number of overall misses -system.l2c.overall_misses::1 16 # number of overall misses +system.l2c.overall_miss_rate::3 0.037764 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.857255 # miss rate for overall accesses +system.l2c.overall_misses::0 93 # number of overall misses +system.l2c.overall_misses::1 18 # number of overall misses system.l2c.overall_misses::2 551 # number of overall misses -system.l2c.overall_misses::3 102 # number of overall misses -system.l2c.overall_misses::total 688 # number of overall misses -system.l2c.overall_mshr_hits 5 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 27360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 1.033283 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.030166 # mshr miss rate for overall accesses +system.l2c.overall_misses::3 25 # number of overall misses +system.l2c.overall_misses::total 687 # number of overall misses +system.l2c.overall_mshr_hits 4 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 27361000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 1.036419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.027068 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 0.807329 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.034848 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 3.905626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.031722 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 3.902537 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 683 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements system.l2c.sampled_refs 535 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 454.684423 # Cycle average of tags in use -system.l2c.total_refs 2139 # Total number of references to valid blocks. +system.l2c.tagsinuse 454.478308 # Cycle average of tags in use +system.l2c.total_refs 2142 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks |