13 files changed, 9 insertions, 13 deletions

diff --git a/src/arch/SConscript b/src/arch/SConscript
index 4f731880f..70a8de7fb 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -43,7 +43,6 @@ Import('*')
 
 # List of headers to generate
 isa_switch_hdrs = Split('''
-        faults.hh
         interrupts.hh
         isa.hh
         isa_traits.hh
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 2b0e26cd2..027e3f573 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -50,7 +50,6 @@
 #include <string>
 #include <queue>
 
-#include "arch/faults.hh"
 #include "arch/utility.hh"
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
@@ -64,6 +63,7 @@
 #include "cpu/translation.hh"
 #include "mem/packet.hh"
 #include "sim/byteswap.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/system.hh"
 #include "sim/tlb.hh"
 
diff --git a/src/cpu/inorder/comm.hh b/src/cpu/inorder/comm.hh
index 02a7e9fa4..c2c97cd83 100644
--- a/src/cpu/inorder/comm.hh
+++ b/src/cpu/inorder/comm.hh
@@ -34,7 +34,6 @@
 
 #include <vector>
 
-#include "arch/faults.hh"
 #include "arch/isa_traits.hh"
 #include "base/types.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index b61beece2..702442478 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -34,7 +34,6 @@
 #include <sstream>
 #include <string>
 
-#include "arch/faults.hh"
 #include "base/bigint.hh"
 #include "base/cp_annotate.hh"
 #include "base/cprintf.hh"
@@ -45,6 +44,7 @@
 #include "cpu/exetrace.hh"
 #include "debug/InOrderDynInst.hh"
 #include "mem/request.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/full_system.hh"
 
 using namespace std;
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index b49dd7594..d61a42480 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -37,7 +37,6 @@
 #include <list>
 #include <string>
 
-#include "arch/faults.hh"
 #include "arch/isa_traits.hh"
 #include "arch/mt.hh"
 #include "arch/types.hh"
@@ -58,6 +57,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/InOrderDynInst.hh"
 #include "mem/packet.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/system.hh"
 
 #if THE_ISA == ALPHA_ISA
diff --git a/src/cpu/inorder/thread_state.hh b/src/cpu/inorder/thread_state.hh
index 1ffc59f65..34c146b42 100644
--- a/src/cpu/inorder/thread_state.hh
+++ b/src/cpu/inorder/thread_state.hh
@@ -31,7 +31,6 @@
 #ifndef __CPU_INORDER_THREAD_STATE_HH__
 #define __CPU_INORDER_THREAD_STATE_HH__
 
-#include "arch/faults.hh"
 #include "arch/isa_traits.hh"
 #include "base/callback.hh"
 #include "base/output.hh"
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 4247c3796..702606d39 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -37,7 +37,6 @@
 #include <map>
 #include <queue>
 
-#include "arch/faults.hh"
 #include "arch/generic/debugfaults.hh"
 #include "arch/isa_traits.hh"
 #include "arch/locked_mem.hh"
@@ -50,6 +49,7 @@
 #include "debug/LSQUnit.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
+#include "sim/fault_fwd.hh"
 
 struct DerivO3CPUParams;
 
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index f532078fe..65545b6aa 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -30,7 +30,6 @@
  */
 
 #include "arch/alpha/osfpal.hh"
-#include "arch/faults.hh"
 #include "arch/isa_traits.hh" // For MachInst
 #include "arch/kernel_stats.hh"
 #include "arch/tlb.hh"
diff --git a/src/cpu/ozone/lsq_unit.hh b/src/cpu/ozone/lsq_unit.hh
index c812a10a2..8a8e2ccd5 100644
--- a/src/cpu/ozone/lsq_unit.hh
+++ b/src/cpu/ozone/lsq_unit.hh
@@ -35,13 +35,13 @@
 #include <map>
 #include <queue>
 
-#include "arch/faults.hh"
 #include "arch/types.hh"
 #include "base/hashmap.hh"
 #include "config/the_isa.hh"
 #include "cpu/inst_seq.hh"
 #include "mem/mem_interface.hh"
 //#include "mem/page_table.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/sim_object.hh"
 
 class PageTable;
diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh
index f36b870d8..3ee96585a 100644
--- a/src/cpu/ozone/lsq_unit_impl.hh
+++ b/src/cpu/ozone/lsq_unit_impl.hh
@@ -28,10 +28,10 @@
  * Authors: Kevin Lim
  */
 
-#include "arch/faults.hh"
 #include "base/str.hh"
 #include "config/the_isa.hh"
 #include "cpu/ozone/lsq_unit.hh"
+#include "sim/fault_fwd.hh"
 
 template <class Impl>
 OzoneLSQ<Impl>::StoreCompletionEvent::StoreCompletionEvent(int store_idx,
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index dd573e5e0..809725c0d 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -36,7 +36,6 @@
 #include <map>
 #include <queue>
 
-#include "arch/faults.hh"
 #include "arch/types.hh"
 #include "base/fast_alloc.hh"
 #include "base/hashmap.hh"
@@ -46,6 +45,7 @@
 #include "mem/port.hh"
 //#include "mem/page_table.hh"
 #include "sim/debug.hh"
+#include "sim/fault_fwd.hh"
 #include "sim/sim_object.hh"
 
 class MemObject;
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index 811d66567..d80cdcf8c 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -28,12 +28,12 @@
  * Authors: Kevin Lim
  */
 
-#include "arch/faults.hh"
 #include "base/str.hh"
 #include "config/the_isa.hh"
 #include "config/use_checker.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/ozone/lw_lsq.hh"
+#include "sim/fault_fwd.hh"
 
 template<class Impl>
 OzoneLWLSQ<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 97ce3264a..945c40b79 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -40,7 +40,6 @@
  * Authors: Steve Reinhardt
  */
 
-#include "arch/faults.hh"
 #include "arch/kernel_stats.hh"
 #include "arch/stacktrace.hh"
 #include "arch/tlb.hh"
@@ -74,6 +73,7 @@
 #include "params/BaseSimpleCPU.hh"
 #include "sim/byteswap.hh"
 #include "sim/debug.hh"
+#include "sim/faults.hh"
 #include "sim/full_system.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_object.hh"