diff options
Diffstat (limited to 'src/arch/arm/isa.cc')
| -rw-r--r-- | src/arch/arm/isa.cc | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index a4e9c7975..aaf209e30 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1595,16 +1595,20 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) // can't be an atomic translation because that causes problems // with unexpected atomic snoop requests. warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); - Request req(0, val, 0, flags, Request::funcMasterId, - tc->pcState().pc(), tc->contextId()); + + auto req = std::make_shared<Request>( + 0, val, 0, flags, Request::funcMasterId, + tc->pcState().pc(), tc->contextId()); + fault = getDTBPtr(tc)->translateFunctional( - &req, tc, mode, tranType); + req, tc, mode, tranType); + TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); HCR hcr = readMiscRegNoEffect(MISCREG_HCR); MiscReg newVal; if (fault == NoFault) { - Addr paddr = req.getPaddr(); + Addr paddr = req->getPaddr(); if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { newVal = (paddr & mask(39, 12)) | @@ -1774,7 +1778,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_AT_S1E3R_Xt: case MISCREG_AT_S1E3W_Xt: { - RequestPtr req = new Request; + RequestPtr req = std::make_shared<Request>(); Request::Flags flags = 0; BaseTLB::Mode mode = BaseTLB::Read; TLB::ArmTranslationType tranType = TLB::NormalTran; @@ -1893,7 +1897,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", val, fsr, newVal); } - delete req; setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); return; } |